1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/radeon_drm.h> 28 #include "radeon.h" 29 30 #define CURSOR_WIDTH 64 31 #define CURSOR_HEIGHT 64 32 33 static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock) 34 { 35 struct radeon_device *rdev = crtc->dev->dev_private; 36 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 37 uint32_t cur_lock; 38 39 if (ASIC_IS_DCE4(rdev)) { 40 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset); 41 if (lock) 42 cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK; 43 else 44 cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK; 45 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); 46 } else if (ASIC_IS_AVIVO(rdev)) { 47 cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); 48 if (lock) 49 cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK; 50 else 51 cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK; 52 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); 53 } else { 54 cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset); 55 if (lock) 56 cur_lock |= RADEON_CUR_LOCK; 57 else 58 cur_lock &= ~RADEON_CUR_LOCK; 59 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); 60 } 61 } 62 63 static void radeon_hide_cursor(struct drm_crtc *crtc) 64 { 65 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 66 struct radeon_device *rdev = crtc->dev->dev_private; 67 68 if (ASIC_IS_DCE4(rdev)) { 69 WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset, 70 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) | 71 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2)); 72 } else if (ASIC_IS_AVIVO(rdev)) { 73 WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, 74 (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); 75 } else { 76 u32 reg; 77 switch (radeon_crtc->crtc_id) { 78 case 0: 79 reg = RADEON_CRTC_GEN_CNTL; 80 break; 81 case 1: 82 reg = RADEON_CRTC2_GEN_CNTL; 83 break; 84 default: 85 return; 86 } 87 WREG32_IDX(reg, RREG32_IDX(reg) & ~RADEON_CRTC_CUR_EN); 88 } 89 } 90 91 static void radeon_show_cursor(struct drm_crtc *crtc) 92 { 93 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 94 struct radeon_device *rdev = crtc->dev->dev_private; 95 96 if (ASIC_IS_DCE4(rdev)) { 97 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); 98 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN | 99 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) | 100 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2)); 101 } else if (ASIC_IS_AVIVO(rdev)) { 102 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); 103 WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | 104 (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); 105 } else { 106 switch (radeon_crtc->crtc_id) { 107 case 0: 108 WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); 109 break; 110 case 1: 111 WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); 112 break; 113 default: 114 return; 115 } 116 117 WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN | 118 (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)), 119 ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); 120 } 121 } 122 123 static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj, 124 uint64_t gpu_addr) 125 { 126 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 127 struct radeon_device *rdev = crtc->dev->dev_private; 128 129 if (ASIC_IS_DCE4(rdev)) { 130 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 131 upper_32_bits(gpu_addr)); 132 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 133 gpu_addr & 0xffffffff); 134 } else if (ASIC_IS_AVIVO(rdev)) { 135 if (rdev->family >= CHIP_RV770) { 136 if (radeon_crtc->crtc_id) 137 WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr)); 138 else 139 WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr)); 140 } 141 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 142 gpu_addr & 0xffffffff); 143 } else { 144 radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr; 145 /* offset is from DISP(2)_BASE_ADDRESS */ 146 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset); 147 } 148 } 149 150 int radeon_crtc_cursor_set(struct drm_crtc *crtc, 151 struct drm_file *file_priv, 152 uint32_t handle, 153 uint32_t width, 154 uint32_t height) 155 { 156 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 157 struct radeon_device *rdev = crtc->dev->dev_private; 158 struct drm_gem_object *obj; 159 struct radeon_bo *robj; 160 uint64_t gpu_addr; 161 int ret; 162 163 if (!handle) { 164 /* turn off cursor */ 165 radeon_hide_cursor(crtc); 166 obj = NULL; 167 goto unpin; 168 } 169 170 if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) { 171 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 172 return -EINVAL; 173 } 174 175 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); 176 if (!obj) { 177 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id); 178 return -ENOENT; 179 } 180 181 robj = gem_to_radeon_bo(obj); 182 ret = radeon_bo_reserve(robj, false); 183 if (unlikely(ret != 0)) 184 goto fail; 185 /* Only 27 bit offset for legacy cursor */ 186 ret = radeon_bo_pin_restricted(robj, RADEON_GEM_DOMAIN_VRAM, 187 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, 188 &gpu_addr); 189 radeon_bo_unreserve(robj); 190 if (ret) 191 goto fail; 192 193 radeon_crtc->cursor_width = width; 194 radeon_crtc->cursor_height = height; 195 196 radeon_lock_cursor(crtc, true); 197 radeon_set_cursor(crtc, obj, gpu_addr); 198 radeon_show_cursor(crtc); 199 radeon_lock_cursor(crtc, false); 200 201 unpin: 202 if (radeon_crtc->cursor_bo) { 203 robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); 204 ret = radeon_bo_reserve(robj, false); 205 if (likely(ret == 0)) { 206 radeon_bo_unpin(robj); 207 radeon_bo_unreserve(robj); 208 } 209 drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo); 210 } 211 212 radeon_crtc->cursor_bo = obj; 213 return 0; 214 fail: 215 drm_gem_object_unreference_unlocked(obj); 216 217 return ret; 218 } 219 220 int radeon_crtc_cursor_move(struct drm_crtc *crtc, 221 int x, int y) 222 { 223 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 224 struct radeon_device *rdev = crtc->dev->dev_private; 225 int xorigin = 0, yorigin = 0; 226 int w = radeon_crtc->cursor_width; 227 228 if (ASIC_IS_AVIVO(rdev)) { 229 /* avivo cursor are offset into the total surface */ 230 x += crtc->x; 231 y += crtc->y; 232 } 233 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 234 235 if (x < 0) { 236 xorigin = min(-x, CURSOR_WIDTH - 1); 237 x = 0; 238 } 239 if (y < 0) { 240 yorigin = min(-y, CURSOR_HEIGHT - 1); 241 y = 0; 242 } 243 244 /* fixed on DCE6 and newer */ 245 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE6(rdev)) { 246 int i = 0; 247 struct drm_crtc *crtc_p; 248 249 /* avivo cursor image can't end on 128 pixel boundary or 250 * go past the end of the frame if both crtcs are enabled 251 */ 252 list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) { 253 if (crtc_p->enabled) 254 i++; 255 } 256 if (i > 1) { 257 int cursor_end, frame_end; 258 259 cursor_end = x - xorigin + w; 260 frame_end = crtc->x + crtc->mode.crtc_hdisplay; 261 if (cursor_end >= frame_end) { 262 w = w - (cursor_end - frame_end); 263 if (!(frame_end & 0x7f)) 264 w--; 265 } else { 266 if (!(cursor_end & 0x7f)) 267 w--; 268 } 269 if (w <= 0) { 270 w = 1; 271 cursor_end = x - xorigin + w; 272 if (!(cursor_end & 0x7f)) { 273 x--; 274 WARN_ON_ONCE(x < 0); 275 } 276 } 277 } 278 } 279 280 radeon_lock_cursor(crtc, true); 281 if (ASIC_IS_DCE4(rdev)) { 282 WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y); 283 WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); 284 WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset, 285 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1)); 286 } else if (ASIC_IS_AVIVO(rdev)) { 287 WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y); 288 WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); 289 WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, 290 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1)); 291 } else { 292 if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN) 293 y *= 2; 294 295 WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset, 296 (RADEON_CUR_LOCK 297 | (xorigin << 16) 298 | yorigin)); 299 WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset, 300 (RADEON_CUR_LOCK 301 | (x << 16) 302 | y)); 303 /* offset is from DISP(2)_BASE_ADDRESS */ 304 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset + 305 (yorigin * 256))); 306 } 307 radeon_lock_cursor(crtc, false); 308 309 return 0; 310 } 311