1 /* 2 * Copyright 2008 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Jerome Glisse <glisse@freedesktop.org> 26 */ 27 #include "drmP.h" 28 #include "radeon_drm.h" 29 #include "radeon_reg.h" 30 #include "radeon.h" 31 32 void r100_cs_dump_packet(struct radeon_cs_parser *p, 33 struct radeon_cs_packet *pkt); 34 35 int radeon_cs_parser_relocs(struct radeon_cs_parser *p) 36 { 37 struct drm_device *ddev = p->rdev->ddev; 38 struct radeon_cs_chunk *chunk; 39 unsigned i, j; 40 bool duplicate; 41 42 if (p->chunk_relocs_idx == -1) { 43 return 0; 44 } 45 chunk = &p->chunks[p->chunk_relocs_idx]; 46 /* FIXME: we assume that each relocs use 4 dwords */ 47 p->nrelocs = chunk->length_dw / 4; 48 p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL); 49 if (p->relocs_ptr == NULL) { 50 return -ENOMEM; 51 } 52 p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL); 53 if (p->relocs == NULL) { 54 return -ENOMEM; 55 } 56 for (i = 0; i < p->nrelocs; i++) { 57 struct drm_radeon_cs_reloc *r; 58 59 duplicate = false; 60 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4]; 61 for (j = 0; j < i; j++) { 62 if (r->handle == p->relocs[j].handle) { 63 p->relocs_ptr[i] = &p->relocs[j]; 64 duplicate = true; 65 break; 66 } 67 } 68 if (!duplicate) { 69 p->relocs[i].gobj = drm_gem_object_lookup(ddev, 70 p->filp, 71 r->handle); 72 if (p->relocs[i].gobj == NULL) { 73 DRM_ERROR("gem object lookup failed 0x%x\n", 74 r->handle); 75 return -ENOENT; 76 } 77 p->relocs_ptr[i] = &p->relocs[i]; 78 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj); 79 p->relocs[i].lobj.bo = p->relocs[i].robj; 80 p->relocs[i].lobj.wdomain = r->write_domain; 81 p->relocs[i].lobj.rdomain = r->read_domains; 82 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo; 83 p->relocs[i].handle = r->handle; 84 p->relocs[i].flags = r->flags; 85 radeon_bo_list_add_object(&p->relocs[i].lobj, 86 &p->validated); 87 88 } else 89 p->relocs[i].handle = 0; 90 } 91 return radeon_bo_list_validate(&p->validated); 92 } 93 94 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority) 95 { 96 p->priority = priority; 97 98 switch (ring) { 99 default: 100 DRM_ERROR("unknown ring id: %d\n", ring); 101 return -EINVAL; 102 case RADEON_CS_RING_GFX: 103 p->ring = RADEON_RING_TYPE_GFX_INDEX; 104 break; 105 case RADEON_CS_RING_COMPUTE: 106 if (p->rdev->family >= CHIP_TAHITI) { 107 if (p->priority > 0) 108 p->ring = CAYMAN_RING_TYPE_CP1_INDEX; 109 else 110 p->ring = CAYMAN_RING_TYPE_CP2_INDEX; 111 } else 112 p->ring = RADEON_RING_TYPE_GFX_INDEX; 113 break; 114 } 115 return 0; 116 } 117 118 static int radeon_cs_sync_rings(struct radeon_cs_parser *p) 119 { 120 bool sync_to_ring[RADEON_NUM_RINGS] = { }; 121 int i, r; 122 123 for (i = 0; i < p->nrelocs; i++) { 124 if (!p->relocs[i].robj || !p->relocs[i].robj->tbo.sync_obj) 125 continue; 126 127 if (!(p->relocs[i].flags & RADEON_RELOC_DONT_SYNC)) { 128 struct radeon_fence *fence = p->relocs[i].robj->tbo.sync_obj; 129 if (!radeon_fence_signaled(fence)) { 130 sync_to_ring[fence->ring] = true; 131 } 132 } 133 } 134 135 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 136 /* no need to sync to our own or unused rings */ 137 if (i == p->ring || !sync_to_ring[i] || !p->rdev->ring[i].ready) 138 continue; 139 140 if (!p->ib->fence->semaphore) { 141 r = radeon_semaphore_create(p->rdev, &p->ib->fence->semaphore); 142 if (r) 143 return r; 144 } 145 146 r = radeon_ring_lock(p->rdev, &p->rdev->ring[i], 3); 147 if (r) 148 return r; 149 radeon_semaphore_emit_signal(p->rdev, i, p->ib->fence->semaphore); 150 radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[i]); 151 152 r = radeon_ring_lock(p->rdev, &p->rdev->ring[p->ring], 3); 153 if (r) 154 return r; 155 radeon_semaphore_emit_wait(p->rdev, p->ring, p->ib->fence->semaphore); 156 radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[p->ring]); 157 } 158 return 0; 159 } 160 161 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) 162 { 163 struct drm_radeon_cs *cs = data; 164 uint64_t *chunk_array_ptr; 165 unsigned size, i; 166 u32 ring = RADEON_CS_RING_GFX; 167 s32 priority = 0; 168 169 if (!cs->num_chunks) { 170 return 0; 171 } 172 /* get chunks */ 173 INIT_LIST_HEAD(&p->validated); 174 p->idx = 0; 175 p->chunk_ib_idx = -1; 176 p->chunk_relocs_idx = -1; 177 p->chunk_flags_idx = -1; 178 p->chunk_const_ib_idx = -1; 179 p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL); 180 if (p->chunks_array == NULL) { 181 return -ENOMEM; 182 } 183 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks); 184 if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr, 185 sizeof(uint64_t)*cs->num_chunks)) { 186 return -EFAULT; 187 } 188 p->cs_flags = 0; 189 p->nchunks = cs->num_chunks; 190 p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL); 191 if (p->chunks == NULL) { 192 return -ENOMEM; 193 } 194 for (i = 0; i < p->nchunks; i++) { 195 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL; 196 struct drm_radeon_cs_chunk user_chunk; 197 uint32_t __user *cdata; 198 199 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i]; 200 if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr, 201 sizeof(struct drm_radeon_cs_chunk))) { 202 return -EFAULT; 203 } 204 p->chunks[i].length_dw = user_chunk.length_dw; 205 p->chunks[i].kdata = NULL; 206 p->chunks[i].chunk_id = user_chunk.chunk_id; 207 208 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) { 209 p->chunk_relocs_idx = i; 210 } 211 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) { 212 p->chunk_ib_idx = i; 213 /* zero length IB isn't useful */ 214 if (p->chunks[i].length_dw == 0) 215 return -EINVAL; 216 } 217 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) { 218 p->chunk_const_ib_idx = i; 219 /* zero length CONST IB isn't useful */ 220 if (p->chunks[i].length_dw == 0) 221 return -EINVAL; 222 } 223 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) { 224 p->chunk_flags_idx = i; 225 /* zero length flags aren't useful */ 226 if (p->chunks[i].length_dw == 0) 227 return -EINVAL; 228 } 229 230 p->chunks[i].length_dw = user_chunk.length_dw; 231 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data; 232 233 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data; 234 if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) || 235 (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) { 236 size = p->chunks[i].length_dw * sizeof(uint32_t); 237 p->chunks[i].kdata = kmalloc(size, GFP_KERNEL); 238 if (p->chunks[i].kdata == NULL) { 239 return -ENOMEM; 240 } 241 if (DRM_COPY_FROM_USER(p->chunks[i].kdata, 242 p->chunks[i].user_ptr, size)) { 243 return -EFAULT; 244 } 245 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) { 246 p->cs_flags = p->chunks[i].kdata[0]; 247 if (p->chunks[i].length_dw > 1) 248 ring = p->chunks[i].kdata[1]; 249 if (p->chunks[i].length_dw > 2) 250 priority = (s32)p->chunks[i].kdata[2]; 251 } 252 } 253 } 254 255 if ((p->cs_flags & RADEON_CS_USE_VM) && 256 !p->rdev->vm_manager.enabled) { 257 DRM_ERROR("VM not active on asic!\n"); 258 return -EINVAL; 259 } 260 261 /* we only support VM on SI+ */ 262 if ((p->rdev->family >= CHIP_TAHITI) && 263 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) { 264 DRM_ERROR("VM required on SI+!\n"); 265 return -EINVAL; 266 } 267 268 if (radeon_cs_get_ring(p, ring, priority)) 269 return -EINVAL; 270 271 272 /* deal with non-vm */ 273 if ((p->chunk_ib_idx != -1) && 274 ((p->cs_flags & RADEON_CS_USE_VM) == 0) && 275 (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) { 276 if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) { 277 DRM_ERROR("cs IB too big: %d\n", 278 p->chunks[p->chunk_ib_idx].length_dw); 279 return -EINVAL; 280 } 281 p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL); 282 p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL); 283 if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL || 284 p->chunks[p->chunk_ib_idx].kpage[1] == NULL) 285 return -ENOMEM; 286 p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1; 287 p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1; 288 p->chunks[p->chunk_ib_idx].last_copied_page = -1; 289 p->chunks[p->chunk_ib_idx].last_page_index = 290 ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE; 291 } 292 293 return 0; 294 } 295 296 /** 297 * cs_parser_fini() - clean parser states 298 * @parser: parser structure holding parsing context. 299 * @error: error number 300 * 301 * If error is set than unvalidate buffer, otherwise just free memory 302 * used by parsing context. 303 **/ 304 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error) 305 { 306 unsigned i; 307 308 309 if (!error && parser->ib) 310 ttm_eu_fence_buffer_objects(&parser->validated, 311 parser->ib->fence); 312 else 313 ttm_eu_backoff_reservation(&parser->validated); 314 315 if (parser->relocs != NULL) { 316 for (i = 0; i < parser->nrelocs; i++) { 317 if (parser->relocs[i].gobj) 318 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj); 319 } 320 } 321 kfree(parser->track); 322 kfree(parser->relocs); 323 kfree(parser->relocs_ptr); 324 for (i = 0; i < parser->nchunks; i++) { 325 kfree(parser->chunks[i].kdata); 326 kfree(parser->chunks[i].kpage[0]); 327 kfree(parser->chunks[i].kpage[1]); 328 } 329 kfree(parser->chunks); 330 kfree(parser->chunks_array); 331 radeon_ib_free(parser->rdev, &parser->ib); 332 } 333 334 static int radeon_cs_ib_chunk(struct radeon_device *rdev, 335 struct radeon_cs_parser *parser) 336 { 337 struct radeon_cs_chunk *ib_chunk; 338 int r; 339 340 if (parser->chunk_ib_idx == -1) 341 return 0; 342 343 if (parser->cs_flags & RADEON_CS_USE_VM) 344 return 0; 345 346 ib_chunk = &parser->chunks[parser->chunk_ib_idx]; 347 /* Copy the packet into the IB, the parser will read from the 348 * input memory (cached) and write to the IB (which can be 349 * uncached). 350 */ 351 r = radeon_ib_get(rdev, parser->ring, &parser->ib, 352 ib_chunk->length_dw * 4); 353 if (r) { 354 DRM_ERROR("Failed to get ib !\n"); 355 return r; 356 } 357 parser->ib->length_dw = ib_chunk->length_dw; 358 r = radeon_cs_parse(rdev, parser->ring, parser); 359 if (r || parser->parser_error) { 360 DRM_ERROR("Invalid command stream !\n"); 361 return r; 362 } 363 r = radeon_cs_finish_pages(parser); 364 if (r) { 365 DRM_ERROR("Invalid command stream !\n"); 366 return r; 367 } 368 r = radeon_cs_sync_rings(parser); 369 if (r) { 370 DRM_ERROR("Failed to synchronize rings !\n"); 371 } 372 parser->ib->vm_id = 0; 373 r = radeon_ib_schedule(rdev, parser->ib); 374 if (r) { 375 DRM_ERROR("Failed to schedule IB !\n"); 376 } 377 return 0; 378 } 379 380 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser, 381 struct radeon_vm *vm) 382 { 383 struct radeon_bo_list *lobj; 384 struct radeon_bo *bo; 385 int r; 386 387 list_for_each_entry(lobj, &parser->validated, tv.head) { 388 bo = lobj->bo; 389 r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem); 390 if (r) { 391 return r; 392 } 393 } 394 return 0; 395 } 396 397 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev, 398 struct radeon_cs_parser *parser) 399 { 400 struct radeon_cs_chunk *ib_chunk; 401 struct radeon_fpriv *fpriv = parser->filp->driver_priv; 402 struct radeon_vm *vm = &fpriv->vm; 403 int r; 404 405 if (parser->chunk_ib_idx == -1) 406 return 0; 407 408 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0) 409 return 0; 410 411 if ((rdev->family >= CHIP_TAHITI) && 412 (parser->chunk_const_ib_idx != -1)) { 413 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx]; 414 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { 415 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw); 416 return -EINVAL; 417 } 418 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib, 419 ib_chunk->length_dw * 4); 420 if (r) { 421 DRM_ERROR("Failed to get const ib !\n"); 422 return r; 423 } 424 parser->const_ib->is_const_ib = true; 425 parser->const_ib->length_dw = ib_chunk->length_dw; 426 /* Copy the packet into the IB */ 427 if (DRM_COPY_FROM_USER(parser->const_ib->ptr, ib_chunk->user_ptr, 428 ib_chunk->length_dw * 4)) { 429 return -EFAULT; 430 } 431 r = radeon_ring_ib_parse(rdev, parser->ring, parser->const_ib); 432 if (r) { 433 return r; 434 } 435 } 436 437 ib_chunk = &parser->chunks[parser->chunk_ib_idx]; 438 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { 439 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw); 440 return -EINVAL; 441 } 442 r = radeon_ib_get(rdev, parser->ring, &parser->ib, 443 ib_chunk->length_dw * 4); 444 if (r) { 445 DRM_ERROR("Failed to get ib !\n"); 446 return r; 447 } 448 parser->ib->length_dw = ib_chunk->length_dw; 449 /* Copy the packet into the IB */ 450 if (DRM_COPY_FROM_USER(parser->ib->ptr, ib_chunk->user_ptr, 451 ib_chunk->length_dw * 4)) { 452 return -EFAULT; 453 } 454 r = radeon_ring_ib_parse(rdev, parser->ring, parser->ib); 455 if (r) { 456 return r; 457 } 458 459 mutex_lock(&vm->mutex); 460 r = radeon_vm_bind(rdev, vm); 461 if (r) { 462 goto out; 463 } 464 r = radeon_bo_vm_update_pte(parser, vm); 465 if (r) { 466 goto out; 467 } 468 r = radeon_cs_sync_rings(parser); 469 if (r) { 470 DRM_ERROR("Failed to synchronize rings !\n"); 471 } 472 473 if ((rdev->family >= CHIP_TAHITI) && 474 (parser->chunk_const_ib_idx != -1)) { 475 parser->const_ib->vm_id = vm->id; 476 /* ib pool is bind at 0 in virtual address space to gpu_addr is the 477 * offset inside the pool bo 478 */ 479 parser->const_ib->gpu_addr = parser->const_ib->sa_bo.offset; 480 r = radeon_ib_schedule(rdev, parser->const_ib); 481 if (r) 482 goto out; 483 } 484 485 parser->ib->vm_id = vm->id; 486 /* ib pool is bind at 0 in virtual address space to gpu_addr is the 487 * offset inside the pool bo 488 */ 489 parser->ib->gpu_addr = parser->ib->sa_bo.offset; 490 parser->ib->is_const_ib = false; 491 r = radeon_ib_schedule(rdev, parser->ib); 492 out: 493 if (!r) { 494 if (vm->fence) { 495 radeon_fence_unref(&vm->fence); 496 } 497 vm->fence = radeon_fence_ref(parser->ib->fence); 498 } 499 mutex_unlock(&fpriv->vm.mutex); 500 return r; 501 } 502 503 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 504 { 505 struct radeon_device *rdev = dev->dev_private; 506 struct radeon_cs_parser parser; 507 int r; 508 509 radeon_mutex_lock(&rdev->cs_mutex); 510 if (!rdev->accel_working) { 511 radeon_mutex_unlock(&rdev->cs_mutex); 512 return -EBUSY; 513 } 514 /* initialize parser */ 515 memset(&parser, 0, sizeof(struct radeon_cs_parser)); 516 parser.filp = filp; 517 parser.rdev = rdev; 518 parser.dev = rdev->dev; 519 parser.family = rdev->family; 520 r = radeon_cs_parser_init(&parser, data); 521 if (r) { 522 DRM_ERROR("Failed to initialize parser !\n"); 523 radeon_cs_parser_fini(&parser, r); 524 radeon_mutex_unlock(&rdev->cs_mutex); 525 return r; 526 } 527 r = radeon_cs_parser_relocs(&parser); 528 if (r) { 529 if (r != -ERESTARTSYS) 530 DRM_ERROR("Failed to parse relocation %d!\n", r); 531 radeon_cs_parser_fini(&parser, r); 532 radeon_mutex_unlock(&rdev->cs_mutex); 533 return r; 534 } 535 r = radeon_cs_ib_chunk(rdev, &parser); 536 if (r) { 537 goto out; 538 } 539 r = radeon_cs_ib_vm_chunk(rdev, &parser); 540 if (r) { 541 goto out; 542 } 543 out: 544 radeon_cs_parser_fini(&parser, r); 545 radeon_mutex_unlock(&rdev->cs_mutex); 546 return r; 547 } 548 549 int radeon_cs_finish_pages(struct radeon_cs_parser *p) 550 { 551 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 552 int i; 553 int size = PAGE_SIZE; 554 555 for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) { 556 if (i == ibc->last_page_index) { 557 size = (ibc->length_dw * 4) % PAGE_SIZE; 558 if (size == 0) 559 size = PAGE_SIZE; 560 } 561 562 if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)), 563 ibc->user_ptr + (i * PAGE_SIZE), 564 size)) 565 return -EFAULT; 566 } 567 return 0; 568 } 569 570 int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx) 571 { 572 int new_page; 573 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 574 int i; 575 int size = PAGE_SIZE; 576 577 for (i = ibc->last_copied_page + 1; i < pg_idx; i++) { 578 if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)), 579 ibc->user_ptr + (i * PAGE_SIZE), 580 PAGE_SIZE)) { 581 p->parser_error = -EFAULT; 582 return 0; 583 } 584 } 585 586 new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1; 587 588 if (pg_idx == ibc->last_page_index) { 589 size = (ibc->length_dw * 4) % PAGE_SIZE; 590 if (size == 0) 591 size = PAGE_SIZE; 592 } 593 594 if (DRM_COPY_FROM_USER(ibc->kpage[new_page], 595 ibc->user_ptr + (pg_idx * PAGE_SIZE), 596 size)) { 597 p->parser_error = -EFAULT; 598 return 0; 599 } 600 601 /* copy to IB here */ 602 memcpy((void *)(p->ib->ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size); 603 604 ibc->last_copied_page = pg_idx; 605 ibc->kpage_idx[new_page] = pg_idx; 606 607 return new_page; 608 } 609