1 /* 2 * Copyright 2008 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Jerome Glisse <glisse@freedesktop.org> 26 */ 27 #include <linux/list_sort.h> 28 #include <drm/drmP.h> 29 #include <drm/radeon_drm.h> 30 #include "radeon_reg.h" 31 #include "radeon.h" 32 #include "radeon_trace.h" 33 34 #define RADEON_CS_MAX_PRIORITY 32u 35 #define RADEON_CS_NUM_BUCKETS (RADEON_CS_MAX_PRIORITY + 1) 36 37 /* This is based on the bucket sort with O(n) time complexity. 38 * An item with priority "i" is added to bucket[i]. The lists are then 39 * concatenated in descending order. 40 */ 41 struct radeon_cs_buckets { 42 struct list_head bucket[RADEON_CS_NUM_BUCKETS]; 43 }; 44 45 static void radeon_cs_buckets_init(struct radeon_cs_buckets *b) 46 { 47 unsigned i; 48 49 for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++) 50 INIT_LIST_HEAD(&b->bucket[i]); 51 } 52 53 static void radeon_cs_buckets_add(struct radeon_cs_buckets *b, 54 struct list_head *item, unsigned priority) 55 { 56 /* Since buffers which appear sooner in the relocation list are 57 * likely to be used more often than buffers which appear later 58 * in the list, the sort mustn't change the ordering of buffers 59 * with the same priority, i.e. it must be stable. 60 */ 61 list_add_tail(item, &b->bucket[min(priority, RADEON_CS_MAX_PRIORITY)]); 62 } 63 64 static void radeon_cs_buckets_get_list(struct radeon_cs_buckets *b, 65 struct list_head *out_list) 66 { 67 unsigned i; 68 69 /* Connect the sorted buckets in the output list. */ 70 for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++) { 71 list_splice(&b->bucket[i], out_list); 72 } 73 } 74 75 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) 76 { 77 struct drm_device *ddev = p->rdev->ddev; 78 struct radeon_cs_chunk *chunk; 79 struct radeon_cs_buckets buckets; 80 unsigned i, j; 81 bool duplicate; 82 83 if (p->chunk_relocs_idx == -1) { 84 return 0; 85 } 86 chunk = &p->chunks[p->chunk_relocs_idx]; 87 p->dma_reloc_idx = 0; 88 /* FIXME: we assume that each relocs use 4 dwords */ 89 p->nrelocs = chunk->length_dw / 4; 90 p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL); 91 if (p->relocs_ptr == NULL) { 92 return -ENOMEM; 93 } 94 p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL); 95 if (p->relocs == NULL) { 96 return -ENOMEM; 97 } 98 99 radeon_cs_buckets_init(&buckets); 100 101 for (i = 0; i < p->nrelocs; i++) { 102 struct drm_radeon_cs_reloc *r; 103 unsigned priority; 104 105 duplicate = false; 106 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4]; 107 for (j = 0; j < i; j++) { 108 if (r->handle == p->relocs[j].handle) { 109 p->relocs_ptr[i] = &p->relocs[j]; 110 duplicate = true; 111 break; 112 } 113 } 114 if (duplicate) { 115 p->relocs[i].handle = 0; 116 continue; 117 } 118 119 p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp, 120 r->handle); 121 if (p->relocs[i].gobj == NULL) { 122 DRM_ERROR("gem object lookup failed 0x%x\n", 123 r->handle); 124 return -ENOENT; 125 } 126 p->relocs_ptr[i] = &p->relocs[i]; 127 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj); 128 129 /* The userspace buffer priorities are from 0 to 15. A higher 130 * number means the buffer is more important. 131 * Also, the buffers used for write have a higher priority than 132 * the buffers used for read only, which doubles the range 133 * to 0 to 31. 32 is reserved for the kernel driver. 134 */ 135 priority = (r->flags & 0xf) * 2 + !!r->write_domain; 136 137 /* the first reloc of an UVD job is the msg and that must be in 138 VRAM, also but everything into VRAM on AGP cards to avoid 139 image corruptions */ 140 if (p->ring == R600_RING_TYPE_UVD_INDEX && 141 (i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) { 142 /* TODO: is this still needed for NI+ ? */ 143 p->relocs[i].prefered_domains = 144 RADEON_GEM_DOMAIN_VRAM; 145 146 p->relocs[i].allowed_domains = 147 RADEON_GEM_DOMAIN_VRAM; 148 149 /* prioritize this over any other relocation */ 150 priority = RADEON_CS_MAX_PRIORITY; 151 } else { 152 uint32_t domain = r->write_domain ? 153 r->write_domain : r->read_domains; 154 155 if (domain & RADEON_GEM_DOMAIN_CPU) { 156 DRM_ERROR("RADEON_GEM_DOMAIN_CPU is not valid " 157 "for command submission\n"); 158 return -EINVAL; 159 } 160 161 p->relocs[i].prefered_domains = domain; 162 if (domain == RADEON_GEM_DOMAIN_VRAM) 163 domain |= RADEON_GEM_DOMAIN_GTT; 164 p->relocs[i].allowed_domains = domain; 165 } 166 167 p->relocs[i].tv.bo = &p->relocs[i].robj->tbo; 168 p->relocs[i].handle = r->handle; 169 170 radeon_cs_buckets_add(&buckets, &p->relocs[i].tv.head, 171 priority); 172 } 173 174 radeon_cs_buckets_get_list(&buckets, &p->validated); 175 176 if (p->cs_flags & RADEON_CS_USE_VM) 177 p->vm_bos = radeon_vm_get_bos(p->rdev, p->ib.vm, 178 &p->validated); 179 180 return radeon_bo_list_validate(p->rdev, &p->ticket, &p->validated, p->ring); 181 } 182 183 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority) 184 { 185 p->priority = priority; 186 187 switch (ring) { 188 default: 189 DRM_ERROR("unknown ring id: %d\n", ring); 190 return -EINVAL; 191 case RADEON_CS_RING_GFX: 192 p->ring = RADEON_RING_TYPE_GFX_INDEX; 193 break; 194 case RADEON_CS_RING_COMPUTE: 195 if (p->rdev->family >= CHIP_TAHITI) { 196 if (p->priority > 0) 197 p->ring = CAYMAN_RING_TYPE_CP1_INDEX; 198 else 199 p->ring = CAYMAN_RING_TYPE_CP2_INDEX; 200 } else 201 p->ring = RADEON_RING_TYPE_GFX_INDEX; 202 break; 203 case RADEON_CS_RING_DMA: 204 if (p->rdev->family >= CHIP_CAYMAN) { 205 if (p->priority > 0) 206 p->ring = R600_RING_TYPE_DMA_INDEX; 207 else 208 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX; 209 } else if (p->rdev->family >= CHIP_RV770) { 210 p->ring = R600_RING_TYPE_DMA_INDEX; 211 } else { 212 return -EINVAL; 213 } 214 break; 215 case RADEON_CS_RING_UVD: 216 p->ring = R600_RING_TYPE_UVD_INDEX; 217 break; 218 case RADEON_CS_RING_VCE: 219 /* TODO: only use the low priority ring for now */ 220 p->ring = TN_RING_TYPE_VCE1_INDEX; 221 break; 222 } 223 return 0; 224 } 225 226 static void radeon_cs_sync_rings(struct radeon_cs_parser *p) 227 { 228 int i; 229 230 for (i = 0; i < p->nrelocs; i++) { 231 if (!p->relocs[i].robj) 232 continue; 233 234 radeon_semaphore_sync_to(p->ib.semaphore, 235 p->relocs[i].robj->tbo.sync_obj); 236 } 237 } 238 239 /* XXX: note that this is called from the legacy UMS CS ioctl as well */ 240 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) 241 { 242 struct drm_radeon_cs *cs = data; 243 uint64_t *chunk_array_ptr; 244 unsigned size, i; 245 u32 ring = RADEON_CS_RING_GFX; 246 s32 priority = 0; 247 248 if (!cs->num_chunks) { 249 return 0; 250 } 251 /* get chunks */ 252 INIT_LIST_HEAD(&p->validated); 253 p->idx = 0; 254 p->ib.sa_bo = NULL; 255 p->ib.semaphore = NULL; 256 p->const_ib.sa_bo = NULL; 257 p->const_ib.semaphore = NULL; 258 p->chunk_ib_idx = -1; 259 p->chunk_relocs_idx = -1; 260 p->chunk_flags_idx = -1; 261 p->chunk_const_ib_idx = -1; 262 p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL); 263 if (p->chunks_array == NULL) { 264 return -ENOMEM; 265 } 266 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks); 267 if (copy_from_user(p->chunks_array, chunk_array_ptr, 268 sizeof(uint64_t)*cs->num_chunks)) { 269 return -EFAULT; 270 } 271 p->cs_flags = 0; 272 p->nchunks = cs->num_chunks; 273 p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL); 274 if (p->chunks == NULL) { 275 return -ENOMEM; 276 } 277 for (i = 0; i < p->nchunks; i++) { 278 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL; 279 struct drm_radeon_cs_chunk user_chunk; 280 uint32_t __user *cdata; 281 282 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i]; 283 if (copy_from_user(&user_chunk, chunk_ptr, 284 sizeof(struct drm_radeon_cs_chunk))) { 285 return -EFAULT; 286 } 287 p->chunks[i].length_dw = user_chunk.length_dw; 288 p->chunks[i].chunk_id = user_chunk.chunk_id; 289 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) { 290 p->chunk_relocs_idx = i; 291 } 292 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) { 293 p->chunk_ib_idx = i; 294 /* zero length IB isn't useful */ 295 if (p->chunks[i].length_dw == 0) 296 return -EINVAL; 297 } 298 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) { 299 p->chunk_const_ib_idx = i; 300 /* zero length CONST IB isn't useful */ 301 if (p->chunks[i].length_dw == 0) 302 return -EINVAL; 303 } 304 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) { 305 p->chunk_flags_idx = i; 306 /* zero length flags aren't useful */ 307 if (p->chunks[i].length_dw == 0) 308 return -EINVAL; 309 } 310 311 size = p->chunks[i].length_dw; 312 cdata = (void __user *)(unsigned long)user_chunk.chunk_data; 313 p->chunks[i].user_ptr = cdata; 314 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) 315 continue; 316 317 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) { 318 if (!p->rdev || !(p->rdev->flags & RADEON_IS_AGP)) 319 continue; 320 } 321 322 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t)); 323 size *= sizeof(uint32_t); 324 if (p->chunks[i].kdata == NULL) { 325 return -ENOMEM; 326 } 327 if (copy_from_user(p->chunks[i].kdata, cdata, size)) { 328 return -EFAULT; 329 } 330 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) { 331 p->cs_flags = p->chunks[i].kdata[0]; 332 if (p->chunks[i].length_dw > 1) 333 ring = p->chunks[i].kdata[1]; 334 if (p->chunks[i].length_dw > 2) 335 priority = (s32)p->chunks[i].kdata[2]; 336 } 337 } 338 339 /* these are KMS only */ 340 if (p->rdev) { 341 if ((p->cs_flags & RADEON_CS_USE_VM) && 342 !p->rdev->vm_manager.enabled) { 343 DRM_ERROR("VM not active on asic!\n"); 344 return -EINVAL; 345 } 346 347 if (radeon_cs_get_ring(p, ring, priority)) 348 return -EINVAL; 349 350 /* we only support VM on some SI+ rings */ 351 if ((p->cs_flags & RADEON_CS_USE_VM) == 0) { 352 if (p->rdev->asic->ring[p->ring]->cs_parse == NULL) { 353 DRM_ERROR("Ring %d requires VM!\n", p->ring); 354 return -EINVAL; 355 } 356 } else { 357 if (p->rdev->asic->ring[p->ring]->ib_parse == NULL) { 358 DRM_ERROR("VM not supported on ring %d!\n", 359 p->ring); 360 return -EINVAL; 361 } 362 } 363 } 364 365 return 0; 366 } 367 368 static int cmp_size_smaller_first(void *priv, struct list_head *a, 369 struct list_head *b) 370 { 371 struct radeon_cs_reloc *la = list_entry(a, struct radeon_cs_reloc, tv.head); 372 struct radeon_cs_reloc *lb = list_entry(b, struct radeon_cs_reloc, tv.head); 373 374 /* Sort A before B if A is smaller. */ 375 return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages; 376 } 377 378 /** 379 * cs_parser_fini() - clean parser states 380 * @parser: parser structure holding parsing context. 381 * @error: error number 382 * 383 * If error is set than unvalidate buffer, otherwise just free memory 384 * used by parsing context. 385 **/ 386 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error, bool backoff) 387 { 388 unsigned i; 389 390 if (!error) { 391 /* Sort the buffer list from the smallest to largest buffer, 392 * which affects the order of buffers in the LRU list. 393 * This assures that the smallest buffers are added first 394 * to the LRU list, so they are likely to be later evicted 395 * first, instead of large buffers whose eviction is more 396 * expensive. 397 * 398 * This slightly lowers the number of bytes moved by TTM 399 * per frame under memory pressure. 400 */ 401 list_sort(NULL, &parser->validated, cmp_size_smaller_first); 402 403 ttm_eu_fence_buffer_objects(&parser->ticket, 404 &parser->validated, 405 parser->ib.fence); 406 } else if (backoff) { 407 ttm_eu_backoff_reservation(&parser->ticket, 408 &parser->validated); 409 } 410 411 if (parser->relocs != NULL) { 412 for (i = 0; i < parser->nrelocs; i++) { 413 if (parser->relocs[i].gobj) 414 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj); 415 } 416 } 417 kfree(parser->track); 418 kfree(parser->relocs); 419 kfree(parser->relocs_ptr); 420 kfree(parser->vm_bos); 421 for (i = 0; i < parser->nchunks; i++) 422 drm_free_large(parser->chunks[i].kdata); 423 kfree(parser->chunks); 424 kfree(parser->chunks_array); 425 radeon_ib_free(parser->rdev, &parser->ib); 426 radeon_ib_free(parser->rdev, &parser->const_ib); 427 } 428 429 static int radeon_cs_ib_chunk(struct radeon_device *rdev, 430 struct radeon_cs_parser *parser) 431 { 432 int r; 433 434 if (parser->chunk_ib_idx == -1) 435 return 0; 436 437 if (parser->cs_flags & RADEON_CS_USE_VM) 438 return 0; 439 440 r = radeon_cs_parse(rdev, parser->ring, parser); 441 if (r || parser->parser_error) { 442 DRM_ERROR("Invalid command stream !\n"); 443 return r; 444 } 445 446 if (parser->ring == R600_RING_TYPE_UVD_INDEX) 447 radeon_uvd_note_usage(rdev); 448 else if ((parser->ring == TN_RING_TYPE_VCE1_INDEX) || 449 (parser->ring == TN_RING_TYPE_VCE2_INDEX)) 450 radeon_vce_note_usage(rdev); 451 452 radeon_cs_sync_rings(parser); 453 r = radeon_ib_schedule(rdev, &parser->ib, NULL); 454 if (r) { 455 DRM_ERROR("Failed to schedule IB !\n"); 456 } 457 return r; 458 } 459 460 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *p, 461 struct radeon_vm *vm) 462 { 463 struct radeon_device *rdev = p->rdev; 464 struct radeon_bo_va *bo_va; 465 int i, r; 466 467 r = radeon_vm_update_page_directory(rdev, vm); 468 if (r) 469 return r; 470 471 r = radeon_vm_clear_freed(rdev, vm); 472 if (r) 473 return r; 474 475 if (vm->ib_bo_va == NULL) { 476 DRM_ERROR("Tmp BO not in VM!\n"); 477 return -EINVAL; 478 } 479 480 r = radeon_vm_bo_update(rdev, vm->ib_bo_va, 481 &rdev->ring_tmp_bo.bo->tbo.mem); 482 if (r) 483 return r; 484 485 for (i = 0; i < p->nrelocs; i++) { 486 struct radeon_bo *bo; 487 488 /* ignore duplicates */ 489 if (p->relocs_ptr[i] != &p->relocs[i]) 490 continue; 491 492 bo = p->relocs[i].robj; 493 bo_va = radeon_vm_bo_find(vm, bo); 494 if (bo_va == NULL) { 495 dev_err(rdev->dev, "bo %p not in vm %p\n", bo, vm); 496 return -EINVAL; 497 } 498 499 r = radeon_vm_bo_update(rdev, bo_va, &bo->tbo.mem); 500 if (r) 501 return r; 502 } 503 504 return radeon_vm_clear_invalids(rdev, vm); 505 } 506 507 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev, 508 struct radeon_cs_parser *parser) 509 { 510 struct radeon_fpriv *fpriv = parser->filp->driver_priv; 511 struct radeon_vm *vm = &fpriv->vm; 512 int r; 513 514 if (parser->chunk_ib_idx == -1) 515 return 0; 516 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0) 517 return 0; 518 519 if (parser->const_ib.length_dw) { 520 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib); 521 if (r) { 522 return r; 523 } 524 } 525 526 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib); 527 if (r) { 528 return r; 529 } 530 531 if (parser->ring == R600_RING_TYPE_UVD_INDEX) 532 radeon_uvd_note_usage(rdev); 533 534 mutex_lock(&vm->mutex); 535 r = radeon_bo_vm_update_pte(parser, vm); 536 if (r) { 537 goto out; 538 } 539 radeon_cs_sync_rings(parser); 540 radeon_semaphore_sync_to(parser->ib.semaphore, vm->fence); 541 542 if ((rdev->family >= CHIP_TAHITI) && 543 (parser->chunk_const_ib_idx != -1)) { 544 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib); 545 } else { 546 r = radeon_ib_schedule(rdev, &parser->ib, NULL); 547 } 548 549 out: 550 mutex_unlock(&vm->mutex); 551 return r; 552 } 553 554 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r) 555 { 556 if (r == -EDEADLK) { 557 r = radeon_gpu_reset(rdev); 558 if (!r) 559 r = -EAGAIN; 560 } 561 return r; 562 } 563 564 static int radeon_cs_ib_fill(struct radeon_device *rdev, struct radeon_cs_parser *parser) 565 { 566 struct radeon_cs_chunk *ib_chunk; 567 struct radeon_vm *vm = NULL; 568 int r; 569 570 if (parser->chunk_ib_idx == -1) 571 return 0; 572 573 if (parser->cs_flags & RADEON_CS_USE_VM) { 574 struct radeon_fpriv *fpriv = parser->filp->driver_priv; 575 vm = &fpriv->vm; 576 577 if ((rdev->family >= CHIP_TAHITI) && 578 (parser->chunk_const_ib_idx != -1)) { 579 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx]; 580 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { 581 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw); 582 return -EINVAL; 583 } 584 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib, 585 vm, ib_chunk->length_dw * 4); 586 if (r) { 587 DRM_ERROR("Failed to get const ib !\n"); 588 return r; 589 } 590 parser->const_ib.is_const_ib = true; 591 parser->const_ib.length_dw = ib_chunk->length_dw; 592 if (copy_from_user(parser->const_ib.ptr, 593 ib_chunk->user_ptr, 594 ib_chunk->length_dw * 4)) 595 return -EFAULT; 596 } 597 598 ib_chunk = &parser->chunks[parser->chunk_ib_idx]; 599 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { 600 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw); 601 return -EINVAL; 602 } 603 } 604 ib_chunk = &parser->chunks[parser->chunk_ib_idx]; 605 606 r = radeon_ib_get(rdev, parser->ring, &parser->ib, 607 vm, ib_chunk->length_dw * 4); 608 if (r) { 609 DRM_ERROR("Failed to get ib !\n"); 610 return r; 611 } 612 parser->ib.length_dw = ib_chunk->length_dw; 613 if (ib_chunk->kdata) 614 memcpy(parser->ib.ptr, ib_chunk->kdata, ib_chunk->length_dw * 4); 615 else if (copy_from_user(parser->ib.ptr, ib_chunk->user_ptr, ib_chunk->length_dw * 4)) 616 return -EFAULT; 617 return 0; 618 } 619 620 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 621 { 622 struct radeon_device *rdev = dev->dev_private; 623 struct radeon_cs_parser parser; 624 int r; 625 626 down_read(&rdev->exclusive_lock); 627 if (!rdev->accel_working) { 628 up_read(&rdev->exclusive_lock); 629 return -EBUSY; 630 } 631 /* initialize parser */ 632 memset(&parser, 0, sizeof(struct radeon_cs_parser)); 633 parser.filp = filp; 634 parser.rdev = rdev; 635 parser.dev = rdev->dev; 636 parser.family = rdev->family; 637 r = radeon_cs_parser_init(&parser, data); 638 if (r) { 639 DRM_ERROR("Failed to initialize parser !\n"); 640 radeon_cs_parser_fini(&parser, r, false); 641 up_read(&rdev->exclusive_lock); 642 r = radeon_cs_handle_lockup(rdev, r); 643 return r; 644 } 645 646 r = radeon_cs_ib_fill(rdev, &parser); 647 if (!r) { 648 r = radeon_cs_parser_relocs(&parser); 649 if (r && r != -ERESTARTSYS) 650 DRM_ERROR("Failed to parse relocation %d!\n", r); 651 } 652 653 if (r) { 654 radeon_cs_parser_fini(&parser, r, false); 655 up_read(&rdev->exclusive_lock); 656 r = radeon_cs_handle_lockup(rdev, r); 657 return r; 658 } 659 660 trace_radeon_cs(&parser); 661 662 r = radeon_cs_ib_chunk(rdev, &parser); 663 if (r) { 664 goto out; 665 } 666 r = radeon_cs_ib_vm_chunk(rdev, &parser); 667 if (r) { 668 goto out; 669 } 670 out: 671 radeon_cs_parser_fini(&parser, r, true); 672 up_read(&rdev->exclusive_lock); 673 r = radeon_cs_handle_lockup(rdev, r); 674 return r; 675 } 676 677 /** 678 * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet 679 * @parser: parser structure holding parsing context. 680 * @pkt: where to store packet information 681 * 682 * Assume that chunk_ib_index is properly set. Will return -EINVAL 683 * if packet is bigger than remaining ib size. or if packets is unknown. 684 **/ 685 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 686 struct radeon_cs_packet *pkt, 687 unsigned idx) 688 { 689 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; 690 struct radeon_device *rdev = p->rdev; 691 uint32_t header; 692 693 if (idx >= ib_chunk->length_dw) { 694 DRM_ERROR("Can not parse packet at %d after CS end %d !\n", 695 idx, ib_chunk->length_dw); 696 return -EINVAL; 697 } 698 header = radeon_get_ib_value(p, idx); 699 pkt->idx = idx; 700 pkt->type = RADEON_CP_PACKET_GET_TYPE(header); 701 pkt->count = RADEON_CP_PACKET_GET_COUNT(header); 702 pkt->one_reg_wr = 0; 703 switch (pkt->type) { 704 case RADEON_PACKET_TYPE0: 705 if (rdev->family < CHIP_R600) { 706 pkt->reg = R100_CP_PACKET0_GET_REG(header); 707 pkt->one_reg_wr = 708 RADEON_CP_PACKET0_GET_ONE_REG_WR(header); 709 } else 710 pkt->reg = R600_CP_PACKET0_GET_REG(header); 711 break; 712 case RADEON_PACKET_TYPE3: 713 pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header); 714 break; 715 case RADEON_PACKET_TYPE2: 716 pkt->count = -1; 717 break; 718 default: 719 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); 720 return -EINVAL; 721 } 722 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { 723 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", 724 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); 725 return -EINVAL; 726 } 727 return 0; 728 } 729 730 /** 731 * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP 732 * @p: structure holding the parser context. 733 * 734 * Check if the next packet is NOP relocation packet3. 735 **/ 736 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p) 737 { 738 struct radeon_cs_packet p3reloc; 739 int r; 740 741 r = radeon_cs_packet_parse(p, &p3reloc, p->idx); 742 if (r) 743 return false; 744 if (p3reloc.type != RADEON_PACKET_TYPE3) 745 return false; 746 if (p3reloc.opcode != RADEON_PACKET3_NOP) 747 return false; 748 return true; 749 } 750 751 /** 752 * radeon_cs_dump_packet() - dump raw packet context 753 * @p: structure holding the parser context. 754 * @pkt: structure holding the packet. 755 * 756 * Used mostly for debugging and error reporting. 757 **/ 758 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 759 struct radeon_cs_packet *pkt) 760 { 761 volatile uint32_t *ib; 762 unsigned i; 763 unsigned idx; 764 765 ib = p->ib.ptr; 766 idx = pkt->idx; 767 for (i = 0; i <= (pkt->count + 1); i++, idx++) 768 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); 769 } 770 771 /** 772 * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet 773 * @parser: parser structure holding parsing context. 774 * @data: pointer to relocation data 775 * @offset_start: starting offset 776 * @offset_mask: offset mask (to align start offset on) 777 * @reloc: reloc informations 778 * 779 * Check if next packet is relocation packet3, do bo validation and compute 780 * GPU offset using the provided start. 781 **/ 782 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 783 struct radeon_cs_reloc **cs_reloc, 784 int nomm) 785 { 786 struct radeon_cs_chunk *relocs_chunk; 787 struct radeon_cs_packet p3reloc; 788 unsigned idx; 789 int r; 790 791 if (p->chunk_relocs_idx == -1) { 792 DRM_ERROR("No relocation chunk !\n"); 793 return -EINVAL; 794 } 795 *cs_reloc = NULL; 796 relocs_chunk = &p->chunks[p->chunk_relocs_idx]; 797 r = radeon_cs_packet_parse(p, &p3reloc, p->idx); 798 if (r) 799 return r; 800 p->idx += p3reloc.count + 2; 801 if (p3reloc.type != RADEON_PACKET_TYPE3 || 802 p3reloc.opcode != RADEON_PACKET3_NOP) { 803 DRM_ERROR("No packet3 for relocation for packet at %d.\n", 804 p3reloc.idx); 805 radeon_cs_dump_packet(p, &p3reloc); 806 return -EINVAL; 807 } 808 idx = radeon_get_ib_value(p, p3reloc.idx + 1); 809 if (idx >= relocs_chunk->length_dw) { 810 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 811 idx, relocs_chunk->length_dw); 812 radeon_cs_dump_packet(p, &p3reloc); 813 return -EINVAL; 814 } 815 /* FIXME: we assume reloc size is 4 dwords */ 816 if (nomm) { 817 *cs_reloc = p->relocs; 818 (*cs_reloc)->gpu_offset = 819 (u64)relocs_chunk->kdata[idx + 3] << 32; 820 (*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0]; 821 } else 822 *cs_reloc = p->relocs_ptr[(idx / 4)]; 823 return 0; 824 } 825