1 /* 2 * Copyright 2008 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Jerome Glisse <glisse@freedesktop.org> 26 */ 27 #include <drm/drmP.h> 28 #include <drm/radeon_drm.h> 29 #include "radeon_reg.h" 30 #include "radeon.h" 31 32 void r100_cs_dump_packet(struct radeon_cs_parser *p, 33 struct radeon_cs_packet *pkt); 34 35 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) 36 { 37 struct drm_device *ddev = p->rdev->ddev; 38 struct radeon_cs_chunk *chunk; 39 unsigned i, j; 40 bool duplicate; 41 42 if (p->chunk_relocs_idx == -1) { 43 return 0; 44 } 45 chunk = &p->chunks[p->chunk_relocs_idx]; 46 /* FIXME: we assume that each relocs use 4 dwords */ 47 p->nrelocs = chunk->length_dw / 4; 48 p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL); 49 if (p->relocs_ptr == NULL) { 50 return -ENOMEM; 51 } 52 p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL); 53 if (p->relocs == NULL) { 54 return -ENOMEM; 55 } 56 for (i = 0; i < p->nrelocs; i++) { 57 struct drm_radeon_cs_reloc *r; 58 59 duplicate = false; 60 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4]; 61 for (j = 0; j < i; j++) { 62 if (r->handle == p->relocs[j].handle) { 63 p->relocs_ptr[i] = &p->relocs[j]; 64 duplicate = true; 65 break; 66 } 67 } 68 if (!duplicate) { 69 p->relocs[i].gobj = drm_gem_object_lookup(ddev, 70 p->filp, 71 r->handle); 72 if (p->relocs[i].gobj == NULL) { 73 DRM_ERROR("gem object lookup failed 0x%x\n", 74 r->handle); 75 return -ENOENT; 76 } 77 p->relocs_ptr[i] = &p->relocs[i]; 78 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj); 79 p->relocs[i].lobj.bo = p->relocs[i].robj; 80 p->relocs[i].lobj.wdomain = r->write_domain; 81 p->relocs[i].lobj.rdomain = r->read_domains; 82 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo; 83 p->relocs[i].handle = r->handle; 84 p->relocs[i].flags = r->flags; 85 radeon_bo_list_add_object(&p->relocs[i].lobj, 86 &p->validated); 87 88 } else 89 p->relocs[i].handle = 0; 90 } 91 return radeon_bo_list_validate(&p->validated); 92 } 93 94 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority) 95 { 96 p->priority = priority; 97 98 switch (ring) { 99 default: 100 DRM_ERROR("unknown ring id: %d\n", ring); 101 return -EINVAL; 102 case RADEON_CS_RING_GFX: 103 p->ring = RADEON_RING_TYPE_GFX_INDEX; 104 break; 105 case RADEON_CS_RING_COMPUTE: 106 if (p->rdev->family >= CHIP_TAHITI) { 107 if (p->priority > 0) 108 p->ring = CAYMAN_RING_TYPE_CP1_INDEX; 109 else 110 p->ring = CAYMAN_RING_TYPE_CP2_INDEX; 111 } else 112 p->ring = RADEON_RING_TYPE_GFX_INDEX; 113 break; 114 } 115 return 0; 116 } 117 118 static void radeon_cs_sync_to(struct radeon_cs_parser *p, 119 struct radeon_fence *fence) 120 { 121 struct radeon_fence *other; 122 123 if (!fence) 124 return; 125 126 other = p->ib.sync_to[fence->ring]; 127 p->ib.sync_to[fence->ring] = radeon_fence_later(fence, other); 128 } 129 130 static void radeon_cs_sync_rings(struct radeon_cs_parser *p) 131 { 132 int i; 133 134 for (i = 0; i < p->nrelocs; i++) { 135 if (!p->relocs[i].robj) 136 continue; 137 138 radeon_cs_sync_to(p, p->relocs[i].robj->tbo.sync_obj); 139 } 140 } 141 142 /* XXX: note that this is called from the legacy UMS CS ioctl as well */ 143 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) 144 { 145 struct drm_radeon_cs *cs = data; 146 uint64_t *chunk_array_ptr; 147 unsigned size, i; 148 u32 ring = RADEON_CS_RING_GFX; 149 s32 priority = 0; 150 151 if (!cs->num_chunks) { 152 return 0; 153 } 154 /* get chunks */ 155 INIT_LIST_HEAD(&p->validated); 156 p->idx = 0; 157 p->ib.sa_bo = NULL; 158 p->ib.semaphore = NULL; 159 p->const_ib.sa_bo = NULL; 160 p->const_ib.semaphore = NULL; 161 p->chunk_ib_idx = -1; 162 p->chunk_relocs_idx = -1; 163 p->chunk_flags_idx = -1; 164 p->chunk_const_ib_idx = -1; 165 p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL); 166 if (p->chunks_array == NULL) { 167 return -ENOMEM; 168 } 169 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks); 170 if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr, 171 sizeof(uint64_t)*cs->num_chunks)) { 172 return -EFAULT; 173 } 174 p->cs_flags = 0; 175 p->nchunks = cs->num_chunks; 176 p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL); 177 if (p->chunks == NULL) { 178 return -ENOMEM; 179 } 180 for (i = 0; i < p->nchunks; i++) { 181 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL; 182 struct drm_radeon_cs_chunk user_chunk; 183 uint32_t __user *cdata; 184 185 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i]; 186 if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr, 187 sizeof(struct drm_radeon_cs_chunk))) { 188 return -EFAULT; 189 } 190 p->chunks[i].length_dw = user_chunk.length_dw; 191 p->chunks[i].kdata = NULL; 192 p->chunks[i].chunk_id = user_chunk.chunk_id; 193 194 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) { 195 p->chunk_relocs_idx = i; 196 } 197 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) { 198 p->chunk_ib_idx = i; 199 /* zero length IB isn't useful */ 200 if (p->chunks[i].length_dw == 0) 201 return -EINVAL; 202 } 203 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) { 204 p->chunk_const_ib_idx = i; 205 /* zero length CONST IB isn't useful */ 206 if (p->chunks[i].length_dw == 0) 207 return -EINVAL; 208 } 209 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) { 210 p->chunk_flags_idx = i; 211 /* zero length flags aren't useful */ 212 if (p->chunks[i].length_dw == 0) 213 return -EINVAL; 214 } 215 216 p->chunks[i].length_dw = user_chunk.length_dw; 217 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data; 218 219 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data; 220 if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) || 221 (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) { 222 size = p->chunks[i].length_dw * sizeof(uint32_t); 223 p->chunks[i].kdata = kmalloc(size, GFP_KERNEL); 224 if (p->chunks[i].kdata == NULL) { 225 return -ENOMEM; 226 } 227 if (DRM_COPY_FROM_USER(p->chunks[i].kdata, 228 p->chunks[i].user_ptr, size)) { 229 return -EFAULT; 230 } 231 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) { 232 p->cs_flags = p->chunks[i].kdata[0]; 233 if (p->chunks[i].length_dw > 1) 234 ring = p->chunks[i].kdata[1]; 235 if (p->chunks[i].length_dw > 2) 236 priority = (s32)p->chunks[i].kdata[2]; 237 } 238 } 239 } 240 241 /* these are KMS only */ 242 if (p->rdev) { 243 if ((p->cs_flags & RADEON_CS_USE_VM) && 244 !p->rdev->vm_manager.enabled) { 245 DRM_ERROR("VM not active on asic!\n"); 246 return -EINVAL; 247 } 248 249 /* we only support VM on SI+ */ 250 if ((p->rdev->family >= CHIP_TAHITI) && 251 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) { 252 DRM_ERROR("VM required on SI+!\n"); 253 return -EINVAL; 254 } 255 256 if (radeon_cs_get_ring(p, ring, priority)) 257 return -EINVAL; 258 } 259 260 /* deal with non-vm */ 261 if ((p->chunk_ib_idx != -1) && 262 ((p->cs_flags & RADEON_CS_USE_VM) == 0) && 263 (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) { 264 if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) { 265 DRM_ERROR("cs IB too big: %d\n", 266 p->chunks[p->chunk_ib_idx].length_dw); 267 return -EINVAL; 268 } 269 if ((p->rdev->flags & RADEON_IS_AGP)) { 270 p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL); 271 p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL); 272 if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL || 273 p->chunks[p->chunk_ib_idx].kpage[1] == NULL) { 274 kfree(p->chunks[i].kpage[0]); 275 kfree(p->chunks[i].kpage[1]); 276 return -ENOMEM; 277 } 278 } 279 p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1; 280 p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1; 281 p->chunks[p->chunk_ib_idx].last_copied_page = -1; 282 p->chunks[p->chunk_ib_idx].last_page_index = 283 ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE; 284 } 285 286 return 0; 287 } 288 289 /** 290 * cs_parser_fini() - clean parser states 291 * @parser: parser structure holding parsing context. 292 * @error: error number 293 * 294 * If error is set than unvalidate buffer, otherwise just free memory 295 * used by parsing context. 296 **/ 297 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error) 298 { 299 unsigned i; 300 301 if (!error) { 302 ttm_eu_fence_buffer_objects(&parser->validated, 303 parser->ib.fence); 304 } else { 305 ttm_eu_backoff_reservation(&parser->validated); 306 } 307 308 if (parser->relocs != NULL) { 309 for (i = 0; i < parser->nrelocs; i++) { 310 if (parser->relocs[i].gobj) 311 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj); 312 } 313 } 314 kfree(parser->track); 315 kfree(parser->relocs); 316 kfree(parser->relocs_ptr); 317 for (i = 0; i < parser->nchunks; i++) { 318 kfree(parser->chunks[i].kdata); 319 if ((parser->rdev->flags & RADEON_IS_AGP)) { 320 kfree(parser->chunks[i].kpage[0]); 321 kfree(parser->chunks[i].kpage[1]); 322 } 323 } 324 kfree(parser->chunks); 325 kfree(parser->chunks_array); 326 radeon_ib_free(parser->rdev, &parser->ib); 327 radeon_ib_free(parser->rdev, &parser->const_ib); 328 } 329 330 static int radeon_cs_ib_chunk(struct radeon_device *rdev, 331 struct radeon_cs_parser *parser) 332 { 333 struct radeon_cs_chunk *ib_chunk; 334 int r; 335 336 if (parser->chunk_ib_idx == -1) 337 return 0; 338 339 if (parser->cs_flags & RADEON_CS_USE_VM) 340 return 0; 341 342 ib_chunk = &parser->chunks[parser->chunk_ib_idx]; 343 /* Copy the packet into the IB, the parser will read from the 344 * input memory (cached) and write to the IB (which can be 345 * uncached). 346 */ 347 r = radeon_ib_get(rdev, parser->ring, &parser->ib, 348 NULL, ib_chunk->length_dw * 4); 349 if (r) { 350 DRM_ERROR("Failed to get ib !\n"); 351 return r; 352 } 353 parser->ib.length_dw = ib_chunk->length_dw; 354 r = radeon_cs_parse(rdev, parser->ring, parser); 355 if (r || parser->parser_error) { 356 DRM_ERROR("Invalid command stream !\n"); 357 return r; 358 } 359 r = radeon_cs_finish_pages(parser); 360 if (r) { 361 DRM_ERROR("Invalid command stream !\n"); 362 return r; 363 } 364 radeon_cs_sync_rings(parser); 365 r = radeon_ib_schedule(rdev, &parser->ib, NULL); 366 if (r) { 367 DRM_ERROR("Failed to schedule IB !\n"); 368 } 369 return r; 370 } 371 372 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser, 373 struct radeon_vm *vm) 374 { 375 struct radeon_device *rdev = parser->rdev; 376 struct radeon_bo_list *lobj; 377 struct radeon_bo *bo; 378 int r; 379 380 r = radeon_vm_bo_update_pte(rdev, vm, rdev->ring_tmp_bo.bo, &rdev->ring_tmp_bo.bo->tbo.mem); 381 if (r) { 382 return r; 383 } 384 list_for_each_entry(lobj, &parser->validated, tv.head) { 385 bo = lobj->bo; 386 r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem); 387 if (r) { 388 return r; 389 } 390 } 391 return 0; 392 } 393 394 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev, 395 struct radeon_cs_parser *parser) 396 { 397 struct radeon_cs_chunk *ib_chunk; 398 struct radeon_fpriv *fpriv = parser->filp->driver_priv; 399 struct radeon_vm *vm = &fpriv->vm; 400 int r; 401 402 if (parser->chunk_ib_idx == -1) 403 return 0; 404 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0) 405 return 0; 406 407 if ((rdev->family >= CHIP_TAHITI) && 408 (parser->chunk_const_ib_idx != -1)) { 409 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx]; 410 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { 411 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw); 412 return -EINVAL; 413 } 414 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib, 415 vm, ib_chunk->length_dw * 4); 416 if (r) { 417 DRM_ERROR("Failed to get const ib !\n"); 418 return r; 419 } 420 parser->const_ib.is_const_ib = true; 421 parser->const_ib.length_dw = ib_chunk->length_dw; 422 /* Copy the packet into the IB */ 423 if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr, 424 ib_chunk->length_dw * 4)) { 425 return -EFAULT; 426 } 427 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib); 428 if (r) { 429 return r; 430 } 431 } 432 433 ib_chunk = &parser->chunks[parser->chunk_ib_idx]; 434 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { 435 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw); 436 return -EINVAL; 437 } 438 r = radeon_ib_get(rdev, parser->ring, &parser->ib, 439 vm, ib_chunk->length_dw * 4); 440 if (r) { 441 DRM_ERROR("Failed to get ib !\n"); 442 return r; 443 } 444 parser->ib.length_dw = ib_chunk->length_dw; 445 /* Copy the packet into the IB */ 446 if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr, 447 ib_chunk->length_dw * 4)) { 448 return -EFAULT; 449 } 450 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib); 451 if (r) { 452 return r; 453 } 454 455 mutex_lock(&rdev->vm_manager.lock); 456 mutex_lock(&vm->mutex); 457 r = radeon_vm_alloc_pt(rdev, vm); 458 if (r) { 459 goto out; 460 } 461 r = radeon_bo_vm_update_pte(parser, vm); 462 if (r) { 463 goto out; 464 } 465 radeon_cs_sync_rings(parser); 466 radeon_cs_sync_to(parser, vm->fence); 467 radeon_cs_sync_to(parser, radeon_vm_grab_id(rdev, vm, parser->ring)); 468 469 if ((rdev->family >= CHIP_TAHITI) && 470 (parser->chunk_const_ib_idx != -1)) { 471 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib); 472 } else { 473 r = radeon_ib_schedule(rdev, &parser->ib, NULL); 474 } 475 476 if (!r) { 477 radeon_vm_fence(rdev, vm, parser->ib.fence); 478 } 479 480 out: 481 radeon_vm_add_to_lru(rdev, vm); 482 mutex_unlock(&vm->mutex); 483 mutex_unlock(&rdev->vm_manager.lock); 484 return r; 485 } 486 487 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r) 488 { 489 if (r == -EDEADLK) { 490 r = radeon_gpu_reset(rdev); 491 if (!r) 492 r = -EAGAIN; 493 } 494 return r; 495 } 496 497 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 498 { 499 struct radeon_device *rdev = dev->dev_private; 500 struct radeon_cs_parser parser; 501 int r; 502 503 down_read(&rdev->exclusive_lock); 504 if (!rdev->accel_working) { 505 up_read(&rdev->exclusive_lock); 506 return -EBUSY; 507 } 508 /* initialize parser */ 509 memset(&parser, 0, sizeof(struct radeon_cs_parser)); 510 parser.filp = filp; 511 parser.rdev = rdev; 512 parser.dev = rdev->dev; 513 parser.family = rdev->family; 514 r = radeon_cs_parser_init(&parser, data); 515 if (r) { 516 DRM_ERROR("Failed to initialize parser !\n"); 517 radeon_cs_parser_fini(&parser, r); 518 up_read(&rdev->exclusive_lock); 519 r = radeon_cs_handle_lockup(rdev, r); 520 return r; 521 } 522 r = radeon_cs_parser_relocs(&parser); 523 if (r) { 524 if (r != -ERESTARTSYS) 525 DRM_ERROR("Failed to parse relocation %d!\n", r); 526 radeon_cs_parser_fini(&parser, r); 527 up_read(&rdev->exclusive_lock); 528 r = radeon_cs_handle_lockup(rdev, r); 529 return r; 530 } 531 r = radeon_cs_ib_chunk(rdev, &parser); 532 if (r) { 533 goto out; 534 } 535 r = radeon_cs_ib_vm_chunk(rdev, &parser); 536 if (r) { 537 goto out; 538 } 539 out: 540 radeon_cs_parser_fini(&parser, r); 541 up_read(&rdev->exclusive_lock); 542 r = radeon_cs_handle_lockup(rdev, r); 543 return r; 544 } 545 546 int radeon_cs_finish_pages(struct radeon_cs_parser *p) 547 { 548 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 549 int i; 550 int size = PAGE_SIZE; 551 552 for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) { 553 if (i == ibc->last_page_index) { 554 size = (ibc->length_dw * 4) % PAGE_SIZE; 555 if (size == 0) 556 size = PAGE_SIZE; 557 } 558 559 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)), 560 ibc->user_ptr + (i * PAGE_SIZE), 561 size)) 562 return -EFAULT; 563 } 564 return 0; 565 } 566 567 static int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx) 568 { 569 int new_page; 570 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 571 int i; 572 int size = PAGE_SIZE; 573 bool copy1 = (p->rdev->flags & RADEON_IS_AGP) ? false : true; 574 575 for (i = ibc->last_copied_page + 1; i < pg_idx; i++) { 576 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)), 577 ibc->user_ptr + (i * PAGE_SIZE), 578 PAGE_SIZE)) { 579 p->parser_error = -EFAULT; 580 return 0; 581 } 582 } 583 584 if (pg_idx == ibc->last_page_index) { 585 size = (ibc->length_dw * 4) % PAGE_SIZE; 586 if (size == 0) 587 size = PAGE_SIZE; 588 } 589 590 new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1; 591 if (copy1) 592 ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4)); 593 594 if (DRM_COPY_FROM_USER(ibc->kpage[new_page], 595 ibc->user_ptr + (pg_idx * PAGE_SIZE), 596 size)) { 597 p->parser_error = -EFAULT; 598 return 0; 599 } 600 601 /* copy to IB for non single case */ 602 if (!copy1) 603 memcpy((void *)(p->ib.ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size); 604 605 ibc->last_copied_page = pg_idx; 606 ibc->kpage_idx[new_page] = pg_idx; 607 608 return new_page; 609 } 610 611 u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 612 { 613 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 614 u32 pg_idx, pg_offset; 615 u32 idx_value = 0; 616 int new_page; 617 618 pg_idx = (idx * 4) / PAGE_SIZE; 619 pg_offset = (idx * 4) % PAGE_SIZE; 620 621 if (ibc->kpage_idx[0] == pg_idx) 622 return ibc->kpage[0][pg_offset/4]; 623 if (ibc->kpage_idx[1] == pg_idx) 624 return ibc->kpage[1][pg_offset/4]; 625 626 new_page = radeon_cs_update_pages(p, pg_idx); 627 if (new_page < 0) { 628 p->parser_error = new_page; 629 return 0; 630 } 631 632 idx_value = ibc->kpage[new_page][pg_offset/4]; 633 return idx_value; 634 } 635