1 /* 2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario 3 * Copyright 2007-8 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 */ 27 #include "drmP.h" 28 #include "radeon_drm.h" 29 #include "radeon.h" 30 #include "atom.h" 31 32 #ifdef CONFIG_PPC_PMAC 33 /* not sure which of these are needed */ 34 #include <asm/machdep.h> 35 #include <asm/pmac_feature.h> 36 #include <asm/prom.h> 37 #include <asm/pci-bridge.h> 38 #endif /* CONFIG_PPC_PMAC */ 39 40 /* from radeon_encoder.c */ 41 extern uint32_t 42 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, 43 uint8_t dac); 44 extern void radeon_link_encoder_connector(struct drm_device *dev); 45 46 /* from radeon_connector.c */ 47 extern void 48 radeon_add_legacy_connector(struct drm_device *dev, 49 uint32_t connector_id, 50 uint32_t supported_device, 51 int connector_type, 52 struct radeon_i2c_bus_rec *i2c_bus, 53 uint16_t connector_object_id, 54 struct radeon_hpd *hpd); 55 56 /* from radeon_legacy_encoder.c */ 57 extern void 58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, 59 uint32_t supported_device); 60 61 /* old legacy ATI BIOS routines */ 62 63 /* COMBIOS table offsets */ 64 enum radeon_combios_table_offset { 65 /* absolute offset tables */ 66 COMBIOS_ASIC_INIT_1_TABLE, 67 COMBIOS_BIOS_SUPPORT_TABLE, 68 COMBIOS_DAC_PROGRAMMING_TABLE, 69 COMBIOS_MAX_COLOR_DEPTH_TABLE, 70 COMBIOS_CRTC_INFO_TABLE, 71 COMBIOS_PLL_INFO_TABLE, 72 COMBIOS_TV_INFO_TABLE, 73 COMBIOS_DFP_INFO_TABLE, 74 COMBIOS_HW_CONFIG_INFO_TABLE, 75 COMBIOS_MULTIMEDIA_INFO_TABLE, 76 COMBIOS_TV_STD_PATCH_TABLE, 77 COMBIOS_LCD_INFO_TABLE, 78 COMBIOS_MOBILE_INFO_TABLE, 79 COMBIOS_PLL_INIT_TABLE, 80 COMBIOS_MEM_CONFIG_TABLE, 81 COMBIOS_SAVE_MASK_TABLE, 82 COMBIOS_HARDCODED_EDID_TABLE, 83 COMBIOS_ASIC_INIT_2_TABLE, 84 COMBIOS_CONNECTOR_INFO_TABLE, 85 COMBIOS_DYN_CLK_1_TABLE, 86 COMBIOS_RESERVED_MEM_TABLE, 87 COMBIOS_EXT_TMDS_INFO_TABLE, 88 COMBIOS_MEM_CLK_INFO_TABLE, 89 COMBIOS_EXT_DAC_INFO_TABLE, 90 COMBIOS_MISC_INFO_TABLE, 91 COMBIOS_CRT_INFO_TABLE, 92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE, 93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE, 94 COMBIOS_FAN_SPEED_INFO_TABLE, 95 COMBIOS_OVERDRIVE_INFO_TABLE, 96 COMBIOS_OEM_INFO_TABLE, 97 COMBIOS_DYN_CLK_2_TABLE, 98 COMBIOS_POWER_CONNECTOR_INFO_TABLE, 99 COMBIOS_I2C_INFO_TABLE, 100 /* relative offset tables */ 101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */ 102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */ 103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */ 104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */ 105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */ 106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */ 107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */ 108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */ 109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */ 110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */ 111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */ 112 }; 113 114 enum radeon_combios_ddc { 115 DDC_NONE_DETECTED, 116 DDC_MONID, 117 DDC_DVI, 118 DDC_VGA, 119 DDC_CRT2, 120 DDC_LCD, 121 DDC_GPIO, 122 }; 123 124 enum radeon_combios_connector { 125 CONNECTOR_NONE_LEGACY, 126 CONNECTOR_PROPRIETARY_LEGACY, 127 CONNECTOR_CRT_LEGACY, 128 CONNECTOR_DVI_I_LEGACY, 129 CONNECTOR_DVI_D_LEGACY, 130 CONNECTOR_CTV_LEGACY, 131 CONNECTOR_STV_LEGACY, 132 CONNECTOR_UNSUPPORTED_LEGACY 133 }; 134 135 const int legacy_connector_convert[] = { 136 DRM_MODE_CONNECTOR_Unknown, 137 DRM_MODE_CONNECTOR_DVID, 138 DRM_MODE_CONNECTOR_VGA, 139 DRM_MODE_CONNECTOR_DVII, 140 DRM_MODE_CONNECTOR_DVID, 141 DRM_MODE_CONNECTOR_Composite, 142 DRM_MODE_CONNECTOR_SVIDEO, 143 DRM_MODE_CONNECTOR_Unknown, 144 }; 145 146 static uint16_t combios_get_table_offset(struct drm_device *dev, 147 enum radeon_combios_table_offset table) 148 { 149 struct radeon_device *rdev = dev->dev_private; 150 int rev; 151 uint16_t offset = 0, check_offset; 152 153 switch (table) { 154 /* absolute offset tables */ 155 case COMBIOS_ASIC_INIT_1_TABLE: 156 check_offset = RBIOS16(rdev->bios_header_start + 0xc); 157 if (check_offset) 158 offset = check_offset; 159 break; 160 case COMBIOS_BIOS_SUPPORT_TABLE: 161 check_offset = RBIOS16(rdev->bios_header_start + 0x14); 162 if (check_offset) 163 offset = check_offset; 164 break; 165 case COMBIOS_DAC_PROGRAMMING_TABLE: 166 check_offset = RBIOS16(rdev->bios_header_start + 0x2a); 167 if (check_offset) 168 offset = check_offset; 169 break; 170 case COMBIOS_MAX_COLOR_DEPTH_TABLE: 171 check_offset = RBIOS16(rdev->bios_header_start + 0x2c); 172 if (check_offset) 173 offset = check_offset; 174 break; 175 case COMBIOS_CRTC_INFO_TABLE: 176 check_offset = RBIOS16(rdev->bios_header_start + 0x2e); 177 if (check_offset) 178 offset = check_offset; 179 break; 180 case COMBIOS_PLL_INFO_TABLE: 181 check_offset = RBIOS16(rdev->bios_header_start + 0x30); 182 if (check_offset) 183 offset = check_offset; 184 break; 185 case COMBIOS_TV_INFO_TABLE: 186 check_offset = RBIOS16(rdev->bios_header_start + 0x32); 187 if (check_offset) 188 offset = check_offset; 189 break; 190 case COMBIOS_DFP_INFO_TABLE: 191 check_offset = RBIOS16(rdev->bios_header_start + 0x34); 192 if (check_offset) 193 offset = check_offset; 194 break; 195 case COMBIOS_HW_CONFIG_INFO_TABLE: 196 check_offset = RBIOS16(rdev->bios_header_start + 0x36); 197 if (check_offset) 198 offset = check_offset; 199 break; 200 case COMBIOS_MULTIMEDIA_INFO_TABLE: 201 check_offset = RBIOS16(rdev->bios_header_start + 0x38); 202 if (check_offset) 203 offset = check_offset; 204 break; 205 case COMBIOS_TV_STD_PATCH_TABLE: 206 check_offset = RBIOS16(rdev->bios_header_start + 0x3e); 207 if (check_offset) 208 offset = check_offset; 209 break; 210 case COMBIOS_LCD_INFO_TABLE: 211 check_offset = RBIOS16(rdev->bios_header_start + 0x40); 212 if (check_offset) 213 offset = check_offset; 214 break; 215 case COMBIOS_MOBILE_INFO_TABLE: 216 check_offset = RBIOS16(rdev->bios_header_start + 0x42); 217 if (check_offset) 218 offset = check_offset; 219 break; 220 case COMBIOS_PLL_INIT_TABLE: 221 check_offset = RBIOS16(rdev->bios_header_start + 0x46); 222 if (check_offset) 223 offset = check_offset; 224 break; 225 case COMBIOS_MEM_CONFIG_TABLE: 226 check_offset = RBIOS16(rdev->bios_header_start + 0x48); 227 if (check_offset) 228 offset = check_offset; 229 break; 230 case COMBIOS_SAVE_MASK_TABLE: 231 check_offset = RBIOS16(rdev->bios_header_start + 0x4a); 232 if (check_offset) 233 offset = check_offset; 234 break; 235 case COMBIOS_HARDCODED_EDID_TABLE: 236 check_offset = RBIOS16(rdev->bios_header_start + 0x4c); 237 if (check_offset) 238 offset = check_offset; 239 break; 240 case COMBIOS_ASIC_INIT_2_TABLE: 241 check_offset = RBIOS16(rdev->bios_header_start + 0x4e); 242 if (check_offset) 243 offset = check_offset; 244 break; 245 case COMBIOS_CONNECTOR_INFO_TABLE: 246 check_offset = RBIOS16(rdev->bios_header_start + 0x50); 247 if (check_offset) 248 offset = check_offset; 249 break; 250 case COMBIOS_DYN_CLK_1_TABLE: 251 check_offset = RBIOS16(rdev->bios_header_start + 0x52); 252 if (check_offset) 253 offset = check_offset; 254 break; 255 case COMBIOS_RESERVED_MEM_TABLE: 256 check_offset = RBIOS16(rdev->bios_header_start + 0x54); 257 if (check_offset) 258 offset = check_offset; 259 break; 260 case COMBIOS_EXT_TMDS_INFO_TABLE: 261 check_offset = RBIOS16(rdev->bios_header_start + 0x58); 262 if (check_offset) 263 offset = check_offset; 264 break; 265 case COMBIOS_MEM_CLK_INFO_TABLE: 266 check_offset = RBIOS16(rdev->bios_header_start + 0x5a); 267 if (check_offset) 268 offset = check_offset; 269 break; 270 case COMBIOS_EXT_DAC_INFO_TABLE: 271 check_offset = RBIOS16(rdev->bios_header_start + 0x5c); 272 if (check_offset) 273 offset = check_offset; 274 break; 275 case COMBIOS_MISC_INFO_TABLE: 276 check_offset = RBIOS16(rdev->bios_header_start + 0x5e); 277 if (check_offset) 278 offset = check_offset; 279 break; 280 case COMBIOS_CRT_INFO_TABLE: 281 check_offset = RBIOS16(rdev->bios_header_start + 0x60); 282 if (check_offset) 283 offset = check_offset; 284 break; 285 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE: 286 check_offset = RBIOS16(rdev->bios_header_start + 0x62); 287 if (check_offset) 288 offset = check_offset; 289 break; 290 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE: 291 check_offset = RBIOS16(rdev->bios_header_start + 0x64); 292 if (check_offset) 293 offset = check_offset; 294 break; 295 case COMBIOS_FAN_SPEED_INFO_TABLE: 296 check_offset = RBIOS16(rdev->bios_header_start + 0x66); 297 if (check_offset) 298 offset = check_offset; 299 break; 300 case COMBIOS_OVERDRIVE_INFO_TABLE: 301 check_offset = RBIOS16(rdev->bios_header_start + 0x68); 302 if (check_offset) 303 offset = check_offset; 304 break; 305 case COMBIOS_OEM_INFO_TABLE: 306 check_offset = RBIOS16(rdev->bios_header_start + 0x6a); 307 if (check_offset) 308 offset = check_offset; 309 break; 310 case COMBIOS_DYN_CLK_2_TABLE: 311 check_offset = RBIOS16(rdev->bios_header_start + 0x6c); 312 if (check_offset) 313 offset = check_offset; 314 break; 315 case COMBIOS_POWER_CONNECTOR_INFO_TABLE: 316 check_offset = RBIOS16(rdev->bios_header_start + 0x6e); 317 if (check_offset) 318 offset = check_offset; 319 break; 320 case COMBIOS_I2C_INFO_TABLE: 321 check_offset = RBIOS16(rdev->bios_header_start + 0x70); 322 if (check_offset) 323 offset = check_offset; 324 break; 325 /* relative offset tables */ 326 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */ 327 check_offset = 328 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 329 if (check_offset) { 330 rev = RBIOS8(check_offset); 331 if (rev > 0) { 332 check_offset = RBIOS16(check_offset + 0x3); 333 if (check_offset) 334 offset = check_offset; 335 } 336 } 337 break; 338 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */ 339 check_offset = 340 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 341 if (check_offset) { 342 rev = RBIOS8(check_offset); 343 if (rev > 0) { 344 check_offset = RBIOS16(check_offset + 0x5); 345 if (check_offset) 346 offset = check_offset; 347 } 348 } 349 break; 350 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */ 351 check_offset = 352 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 353 if (check_offset) { 354 rev = RBIOS8(check_offset); 355 if (rev > 0) { 356 check_offset = RBIOS16(check_offset + 0x7); 357 if (check_offset) 358 offset = check_offset; 359 } 360 } 361 break; 362 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */ 363 check_offset = 364 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 365 if (check_offset) { 366 rev = RBIOS8(check_offset); 367 if (rev == 2) { 368 check_offset = RBIOS16(check_offset + 0x9); 369 if (check_offset) 370 offset = check_offset; 371 } 372 } 373 break; 374 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */ 375 check_offset = 376 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 377 if (check_offset) { 378 while (RBIOS8(check_offset++)); 379 check_offset += 2; 380 if (check_offset) 381 offset = check_offset; 382 } 383 break; 384 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */ 385 check_offset = 386 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 387 if (check_offset) { 388 check_offset = RBIOS16(check_offset + 0x11); 389 if (check_offset) 390 offset = check_offset; 391 } 392 break; 393 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */ 394 check_offset = 395 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 396 if (check_offset) { 397 check_offset = RBIOS16(check_offset + 0x13); 398 if (check_offset) 399 offset = check_offset; 400 } 401 break; 402 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */ 403 check_offset = 404 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 405 if (check_offset) { 406 check_offset = RBIOS16(check_offset + 0x15); 407 if (check_offset) 408 offset = check_offset; 409 } 410 break; 411 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */ 412 check_offset = 413 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 414 if (check_offset) { 415 check_offset = RBIOS16(check_offset + 0x17); 416 if (check_offset) 417 offset = check_offset; 418 } 419 break; 420 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */ 421 check_offset = 422 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 423 if (check_offset) { 424 check_offset = RBIOS16(check_offset + 0x2); 425 if (check_offset) 426 offset = check_offset; 427 } 428 break; 429 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */ 430 check_offset = 431 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 432 if (check_offset) { 433 check_offset = RBIOS16(check_offset + 0x4); 434 if (check_offset) 435 offset = check_offset; 436 } 437 break; 438 default: 439 break; 440 } 441 442 return offset; 443 444 } 445 446 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, 447 int ddc_line) 448 { 449 struct radeon_i2c_bus_rec i2c; 450 451 if (ddc_line == RADEON_GPIOPAD_MASK) { 452 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; 453 i2c.mask_data_reg = RADEON_GPIOPAD_MASK; 454 i2c.a_clk_reg = RADEON_GPIOPAD_A; 455 i2c.a_data_reg = RADEON_GPIOPAD_A; 456 i2c.en_clk_reg = RADEON_GPIOPAD_EN; 457 i2c.en_data_reg = RADEON_GPIOPAD_EN; 458 i2c.y_clk_reg = RADEON_GPIOPAD_Y; 459 i2c.y_data_reg = RADEON_GPIOPAD_Y; 460 } else if (ddc_line == RADEON_MDGPIO_MASK) { 461 i2c.mask_clk_reg = RADEON_MDGPIO_MASK; 462 i2c.mask_data_reg = RADEON_MDGPIO_MASK; 463 i2c.a_clk_reg = RADEON_MDGPIO_A; 464 i2c.a_data_reg = RADEON_MDGPIO_A; 465 i2c.en_clk_reg = RADEON_MDGPIO_EN; 466 i2c.en_data_reg = RADEON_MDGPIO_EN; 467 i2c.y_clk_reg = RADEON_MDGPIO_Y; 468 i2c.y_data_reg = RADEON_MDGPIO_Y; 469 } else { 470 i2c.mask_clk_mask = RADEON_GPIO_EN_1; 471 i2c.mask_data_mask = RADEON_GPIO_EN_0; 472 i2c.a_clk_mask = RADEON_GPIO_A_1; 473 i2c.a_data_mask = RADEON_GPIO_A_0; 474 i2c.en_clk_mask = RADEON_GPIO_EN_1; 475 i2c.en_data_mask = RADEON_GPIO_EN_0; 476 i2c.y_clk_mask = RADEON_GPIO_Y_1; 477 i2c.y_data_mask = RADEON_GPIO_Y_0; 478 479 i2c.mask_clk_reg = ddc_line; 480 i2c.mask_data_reg = ddc_line; 481 i2c.a_clk_reg = ddc_line; 482 i2c.a_data_reg = ddc_line; 483 i2c.en_clk_reg = ddc_line; 484 i2c.en_data_reg = ddc_line; 485 i2c.y_clk_reg = ddc_line; 486 i2c.y_data_reg = ddc_line; 487 } 488 489 if (rdev->family < CHIP_R200) 490 i2c.hw_capable = false; 491 else { 492 switch (ddc_line) { 493 case RADEON_GPIO_VGA_DDC: 494 case RADEON_GPIO_DVI_DDC: 495 i2c.hw_capable = true; 496 break; 497 case RADEON_GPIO_MONID: 498 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work 499 * reliably on some pre-r4xx hardware; not sure why. 500 */ 501 i2c.hw_capable = false; 502 break; 503 default: 504 i2c.hw_capable = false; 505 break; 506 } 507 } 508 i2c.mm_i2c = false; 509 i2c.i2c_id = 0; 510 511 if (ddc_line) 512 i2c.valid = true; 513 else 514 i2c.valid = false; 515 516 return i2c; 517 } 518 519 bool radeon_combios_get_clock_info(struct drm_device *dev) 520 { 521 struct radeon_device *rdev = dev->dev_private; 522 uint16_t pll_info; 523 struct radeon_pll *p1pll = &rdev->clock.p1pll; 524 struct radeon_pll *p2pll = &rdev->clock.p2pll; 525 struct radeon_pll *spll = &rdev->clock.spll; 526 struct radeon_pll *mpll = &rdev->clock.mpll; 527 int8_t rev; 528 uint16_t sclk, mclk; 529 530 if (rdev->bios == NULL) 531 return false; 532 533 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); 534 if (pll_info) { 535 rev = RBIOS8(pll_info); 536 537 /* pixel clocks */ 538 p1pll->reference_freq = RBIOS16(pll_info + 0xe); 539 p1pll->reference_div = RBIOS16(pll_info + 0x10); 540 p1pll->pll_out_min = RBIOS32(pll_info + 0x12); 541 p1pll->pll_out_max = RBIOS32(pll_info + 0x16); 542 543 if (rev > 9) { 544 p1pll->pll_in_min = RBIOS32(pll_info + 0x36); 545 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); 546 } else { 547 p1pll->pll_in_min = 40; 548 p1pll->pll_in_max = 500; 549 } 550 *p2pll = *p1pll; 551 552 /* system clock */ 553 spll->reference_freq = RBIOS16(pll_info + 0x1a); 554 spll->reference_div = RBIOS16(pll_info + 0x1c); 555 spll->pll_out_min = RBIOS32(pll_info + 0x1e); 556 spll->pll_out_max = RBIOS32(pll_info + 0x22); 557 558 if (rev > 10) { 559 spll->pll_in_min = RBIOS32(pll_info + 0x48); 560 spll->pll_in_max = RBIOS32(pll_info + 0x4c); 561 } else { 562 /* ??? */ 563 spll->pll_in_min = 40; 564 spll->pll_in_max = 500; 565 } 566 567 /* memory clock */ 568 mpll->reference_freq = RBIOS16(pll_info + 0x26); 569 mpll->reference_div = RBIOS16(pll_info + 0x28); 570 mpll->pll_out_min = RBIOS32(pll_info + 0x2a); 571 mpll->pll_out_max = RBIOS32(pll_info + 0x2e); 572 573 if (rev > 10) { 574 mpll->pll_in_min = RBIOS32(pll_info + 0x5a); 575 mpll->pll_in_max = RBIOS32(pll_info + 0x5e); 576 } else { 577 /* ??? */ 578 mpll->pll_in_min = 40; 579 mpll->pll_in_max = 500; 580 } 581 582 /* default sclk/mclk */ 583 sclk = RBIOS16(pll_info + 0xa); 584 mclk = RBIOS16(pll_info + 0x8); 585 if (sclk == 0) 586 sclk = 200 * 100; 587 if (mclk == 0) 588 mclk = 200 * 100; 589 590 rdev->clock.default_sclk = sclk; 591 rdev->clock.default_mclk = mclk; 592 593 return true; 594 } 595 return false; 596 } 597 598 bool radeon_combios_sideport_present(struct radeon_device *rdev) 599 { 600 struct drm_device *dev = rdev->ddev; 601 u16 igp_info; 602 603 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE); 604 605 if (igp_info) { 606 if (RBIOS16(igp_info + 0x4)) 607 return true; 608 } 609 return false; 610 } 611 612 static const uint32_t default_primarydac_adj[CHIP_LAST] = { 613 0x00000808, /* r100 */ 614 0x00000808, /* rv100 */ 615 0x00000808, /* rs100 */ 616 0x00000808, /* rv200 */ 617 0x00000808, /* rs200 */ 618 0x00000808, /* r200 */ 619 0x00000808, /* rv250 */ 620 0x00000000, /* rs300 */ 621 0x00000808, /* rv280 */ 622 0x00000808, /* r300 */ 623 0x00000808, /* r350 */ 624 0x00000808, /* rv350 */ 625 0x00000808, /* rv380 */ 626 0x00000808, /* r420 */ 627 0x00000808, /* r423 */ 628 0x00000808, /* rv410 */ 629 0x00000000, /* rs400 */ 630 0x00000000, /* rs480 */ 631 }; 632 633 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev, 634 struct radeon_encoder_primary_dac *p_dac) 635 { 636 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family]; 637 return; 638 } 639 640 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct 641 radeon_encoder 642 *encoder) 643 { 644 struct drm_device *dev = encoder->base.dev; 645 struct radeon_device *rdev = dev->dev_private; 646 uint16_t dac_info; 647 uint8_t rev, bg, dac; 648 struct radeon_encoder_primary_dac *p_dac = NULL; 649 int found = 0; 650 651 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), 652 GFP_KERNEL); 653 654 if (!p_dac) 655 return NULL; 656 657 if (rdev->bios == NULL) 658 goto out; 659 660 /* check CRT table */ 661 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 662 if (dac_info) { 663 rev = RBIOS8(dac_info) & 0x3; 664 if (rev < 2) { 665 bg = RBIOS8(dac_info + 0x2) & 0xf; 666 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf; 667 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 668 } else { 669 bg = RBIOS8(dac_info + 0x2) & 0xf; 670 dac = RBIOS8(dac_info + 0x3) & 0xf; 671 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 672 } 673 found = 1; 674 } 675 676 out: 677 if (!found) /* fallback to defaults */ 678 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac); 679 680 return p_dac; 681 } 682 683 enum radeon_tv_std 684 radeon_combios_get_tv_info(struct radeon_device *rdev) 685 { 686 struct drm_device *dev = rdev->ddev; 687 uint16_t tv_info; 688 enum radeon_tv_std tv_std = TV_STD_NTSC; 689 690 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 691 if (tv_info) { 692 if (RBIOS8(tv_info + 6) == 'T') { 693 switch (RBIOS8(tv_info + 7) & 0xf) { 694 case 1: 695 tv_std = TV_STD_NTSC; 696 DRM_INFO("Default TV standard: NTSC\n"); 697 break; 698 case 2: 699 tv_std = TV_STD_PAL; 700 DRM_INFO("Default TV standard: PAL\n"); 701 break; 702 case 3: 703 tv_std = TV_STD_PAL_M; 704 DRM_INFO("Default TV standard: PAL-M\n"); 705 break; 706 case 4: 707 tv_std = TV_STD_PAL_60; 708 DRM_INFO("Default TV standard: PAL-60\n"); 709 break; 710 case 5: 711 tv_std = TV_STD_NTSC_J; 712 DRM_INFO("Default TV standard: NTSC-J\n"); 713 break; 714 case 6: 715 tv_std = TV_STD_SCART_PAL; 716 DRM_INFO("Default TV standard: SCART-PAL\n"); 717 break; 718 default: 719 tv_std = TV_STD_NTSC; 720 DRM_INFO 721 ("Unknown TV standard; defaulting to NTSC\n"); 722 break; 723 } 724 725 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { 726 case 0: 727 DRM_INFO("29.498928713 MHz TV ref clk\n"); 728 break; 729 case 1: 730 DRM_INFO("28.636360000 MHz TV ref clk\n"); 731 break; 732 case 2: 733 DRM_INFO("14.318180000 MHz TV ref clk\n"); 734 break; 735 case 3: 736 DRM_INFO("27.000000000 MHz TV ref clk\n"); 737 break; 738 default: 739 break; 740 } 741 } 742 } 743 return tv_std; 744 } 745 746 static const uint32_t default_tvdac_adj[CHIP_LAST] = { 747 0x00000000, /* r100 */ 748 0x00280000, /* rv100 */ 749 0x00000000, /* rs100 */ 750 0x00880000, /* rv200 */ 751 0x00000000, /* rs200 */ 752 0x00000000, /* r200 */ 753 0x00770000, /* rv250 */ 754 0x00290000, /* rs300 */ 755 0x00560000, /* rv280 */ 756 0x00780000, /* r300 */ 757 0x00770000, /* r350 */ 758 0x00780000, /* rv350 */ 759 0x00780000, /* rv380 */ 760 0x01080000, /* r420 */ 761 0x01080000, /* r423 */ 762 0x01080000, /* rv410 */ 763 0x00780000, /* rs400 */ 764 0x00780000, /* rs480 */ 765 }; 766 767 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev, 768 struct radeon_encoder_tv_dac *tv_dac) 769 { 770 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family]; 771 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250)) 772 tv_dac->ps2_tvdac_adj = 0x00880000; 773 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 774 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 775 return; 776 } 777 778 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct 779 radeon_encoder 780 *encoder) 781 { 782 struct drm_device *dev = encoder->base.dev; 783 struct radeon_device *rdev = dev->dev_private; 784 uint16_t dac_info; 785 uint8_t rev, bg, dac; 786 struct radeon_encoder_tv_dac *tv_dac = NULL; 787 int found = 0; 788 789 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 790 if (!tv_dac) 791 return NULL; 792 793 if (rdev->bios == NULL) 794 goto out; 795 796 /* first check TV table */ 797 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 798 if (dac_info) { 799 rev = RBIOS8(dac_info + 0x3); 800 if (rev > 4) { 801 bg = RBIOS8(dac_info + 0xc) & 0xf; 802 dac = RBIOS8(dac_info + 0xd) & 0xf; 803 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 804 805 bg = RBIOS8(dac_info + 0xe) & 0xf; 806 dac = RBIOS8(dac_info + 0xf) & 0xf; 807 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 808 809 bg = RBIOS8(dac_info + 0x10) & 0xf; 810 dac = RBIOS8(dac_info + 0x11) & 0xf; 811 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 812 found = 1; 813 } else if (rev > 1) { 814 bg = RBIOS8(dac_info + 0xc) & 0xf; 815 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf; 816 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 817 818 bg = RBIOS8(dac_info + 0xd) & 0xf; 819 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf; 820 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 821 822 bg = RBIOS8(dac_info + 0xe) & 0xf; 823 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf; 824 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 825 found = 1; 826 } 827 tv_dac->tv_std = radeon_combios_get_tv_info(rdev); 828 } 829 if (!found) { 830 /* then check CRT table */ 831 dac_info = 832 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 833 if (dac_info) { 834 rev = RBIOS8(dac_info) & 0x3; 835 if (rev < 2) { 836 bg = RBIOS8(dac_info + 0x3) & 0xf; 837 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf; 838 tv_dac->ps2_tvdac_adj = 839 (bg << 16) | (dac << 20); 840 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 841 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 842 found = 1; 843 } else { 844 bg = RBIOS8(dac_info + 0x4) & 0xf; 845 dac = RBIOS8(dac_info + 0x5) & 0xf; 846 tv_dac->ps2_tvdac_adj = 847 (bg << 16) | (dac << 20); 848 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 849 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 850 found = 1; 851 } 852 } else { 853 DRM_INFO("No TV DAC info found in BIOS\n"); 854 } 855 } 856 857 out: 858 if (!found) /* fallback to defaults */ 859 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac); 860 861 return tv_dac; 862 } 863 864 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct 865 radeon_device 866 *rdev) 867 { 868 struct radeon_encoder_lvds *lvds = NULL; 869 uint32_t fp_vert_stretch, fp_horz_stretch; 870 uint32_t ppll_div_sel, ppll_val; 871 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); 872 873 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 874 875 if (!lvds) 876 return NULL; 877 878 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH); 879 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH); 880 881 /* These should be fail-safe defaults, fingers crossed */ 882 lvds->panel_pwr_delay = 200; 883 lvds->panel_vcc_delay = 2000; 884 885 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 886 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; 887 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; 888 889 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) 890 lvds->native_mode.vdisplay = 891 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >> 892 RADEON_VERT_PANEL_SHIFT) + 1; 893 else 894 lvds->native_mode.vdisplay = 895 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1; 896 897 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) 898 lvds->native_mode.hdisplay = 899 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >> 900 RADEON_HORZ_PANEL_SHIFT) + 1) * 8; 901 else 902 lvds->native_mode.hdisplay = 903 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8; 904 905 if ((lvds->native_mode.hdisplay < 640) || 906 (lvds->native_mode.vdisplay < 480)) { 907 lvds->native_mode.hdisplay = 640; 908 lvds->native_mode.vdisplay = 480; 909 } 910 911 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; 912 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel); 913 if ((ppll_val & 0x000707ff) == 0x1bb) 914 lvds->use_bios_dividers = false; 915 else { 916 lvds->panel_ref_divider = 917 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; 918 lvds->panel_post_divider = (ppll_val >> 16) & 0x7; 919 lvds->panel_fb_divider = ppll_val & 0x7ff; 920 921 if ((lvds->panel_ref_divider != 0) && 922 (lvds->panel_fb_divider > 3)) 923 lvds->use_bios_dividers = true; 924 } 925 lvds->panel_vcc_delay = 200; 926 927 DRM_INFO("Panel info derived from registers\n"); 928 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 929 lvds->native_mode.vdisplay); 930 931 return lvds; 932 } 933 934 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder 935 *encoder) 936 { 937 struct drm_device *dev = encoder->base.dev; 938 struct radeon_device *rdev = dev->dev_private; 939 uint16_t lcd_info; 940 uint32_t panel_setup; 941 char stmp[30]; 942 int tmp, i; 943 struct radeon_encoder_lvds *lvds = NULL; 944 945 if (rdev->bios == NULL) { 946 lvds = radeon_legacy_get_lvds_info_from_regs(rdev); 947 goto out; 948 } 949 950 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 951 952 if (lcd_info) { 953 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 954 955 if (!lvds) 956 return NULL; 957 958 for (i = 0; i < 24; i++) 959 stmp[i] = RBIOS8(lcd_info + i + 1); 960 stmp[24] = 0; 961 962 DRM_INFO("Panel ID String: %s\n", stmp); 963 964 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19); 965 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b); 966 967 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 968 lvds->native_mode.vdisplay); 969 970 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); 971 if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0) 972 lvds->panel_vcc_delay = 2000; 973 974 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24); 975 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf; 976 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf; 977 978 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e); 979 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30); 980 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31); 981 if ((lvds->panel_ref_divider != 0) && 982 (lvds->panel_fb_divider > 3)) 983 lvds->use_bios_dividers = true; 984 985 panel_setup = RBIOS32(lcd_info + 0x39); 986 lvds->lvds_gen_cntl = 0xff00; 987 if (panel_setup & 0x1) 988 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT; 989 990 if ((panel_setup >> 4) & 0x1) 991 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE; 992 993 switch ((panel_setup >> 8) & 0x7) { 994 case 0: 995 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM; 996 break; 997 case 1: 998 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY; 999 break; 1000 case 2: 1001 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY; 1002 break; 1003 default: 1004 break; 1005 } 1006 1007 if ((panel_setup >> 16) & 0x1) 1008 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW; 1009 1010 if ((panel_setup >> 17) & 0x1) 1011 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW; 1012 1013 if ((panel_setup >> 18) & 0x1) 1014 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW; 1015 1016 if ((panel_setup >> 23) & 0x1) 1017 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL; 1018 1019 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000); 1020 1021 for (i = 0; i < 32; i++) { 1022 tmp = RBIOS16(lcd_info + 64 + i * 2); 1023 if (tmp == 0) 1024 break; 1025 1026 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) && 1027 (RBIOS16(tmp + 2) == 1028 lvds->native_mode.vdisplay)) { 1029 lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8; 1030 lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8; 1031 lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) + 1032 RBIOS16(tmp + 21)) * 8; 1033 1034 lvds->native_mode.vtotal = RBIOS16(tmp + 24); 1035 lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff; 1036 lvds->native_mode.vsync_end = 1037 ((RBIOS16(tmp + 28) & 0xf800) >> 11) + 1038 (RBIOS16(tmp + 28) & 0x7ff); 1039 1040 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10; 1041 lvds->native_mode.flags = 0; 1042 /* set crtc values */ 1043 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1044 1045 } 1046 } 1047 } else { 1048 DRM_INFO("No panel info found in BIOS\n"); 1049 lvds = radeon_legacy_get_lvds_info_from_regs(rdev); 1050 } 1051 out: 1052 if (lvds) 1053 encoder->native_mode = lvds->native_mode; 1054 return lvds; 1055 } 1056 1057 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = { 1058 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */ 1059 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */ 1060 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */ 1061 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */ 1062 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */ 1063 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */ 1064 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */ 1065 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */ 1066 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */ 1067 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */ 1068 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */ 1069 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */ 1070 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */ 1071 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */ 1072 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */ 1073 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */ 1074 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */ 1075 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */ 1076 }; 1077 1078 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 1079 struct radeon_encoder_int_tmds *tmds) 1080 { 1081 struct drm_device *dev = encoder->base.dev; 1082 struct radeon_device *rdev = dev->dev_private; 1083 int i; 1084 1085 for (i = 0; i < 4; i++) { 1086 tmds->tmds_pll[i].value = 1087 default_tmds_pll[rdev->family][i].value; 1088 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; 1089 } 1090 1091 return true; 1092 } 1093 1094 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 1095 struct radeon_encoder_int_tmds *tmds) 1096 { 1097 struct drm_device *dev = encoder->base.dev; 1098 struct radeon_device *rdev = dev->dev_private; 1099 uint16_t tmds_info; 1100 int i, n; 1101 uint8_t ver; 1102 1103 if (rdev->bios == NULL) 1104 return false; 1105 1106 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 1107 1108 if (tmds_info) { 1109 ver = RBIOS8(tmds_info); 1110 DRM_INFO("DFP table revision: %d\n", ver); 1111 if (ver == 3) { 1112 n = RBIOS8(tmds_info + 5) + 1; 1113 if (n > 4) 1114 n = 4; 1115 for (i = 0; i < n; i++) { 1116 tmds->tmds_pll[i].value = 1117 RBIOS32(tmds_info + i * 10 + 0x08); 1118 tmds->tmds_pll[i].freq = 1119 RBIOS16(tmds_info + i * 10 + 0x10); 1120 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n", 1121 tmds->tmds_pll[i].freq, 1122 tmds->tmds_pll[i].value); 1123 } 1124 } else if (ver == 4) { 1125 int stride = 0; 1126 n = RBIOS8(tmds_info + 5) + 1; 1127 if (n > 4) 1128 n = 4; 1129 for (i = 0; i < n; i++) { 1130 tmds->tmds_pll[i].value = 1131 RBIOS32(tmds_info + stride + 0x08); 1132 tmds->tmds_pll[i].freq = 1133 RBIOS16(tmds_info + stride + 0x10); 1134 if (i == 0) 1135 stride += 10; 1136 else 1137 stride += 6; 1138 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n", 1139 tmds->tmds_pll[i].freq, 1140 tmds->tmds_pll[i].value); 1141 } 1142 } 1143 } else { 1144 DRM_INFO("No TMDS info found in BIOS\n"); 1145 return false; 1146 } 1147 return true; 1148 } 1149 1150 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 1151 struct radeon_encoder_ext_tmds *tmds) 1152 { 1153 struct drm_device *dev = encoder->base.dev; 1154 struct radeon_device *rdev = dev->dev_private; 1155 struct radeon_i2c_bus_rec i2c_bus; 1156 1157 /* default for macs */ 1158 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1159 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1160 1161 /* XXX some macs have duallink chips */ 1162 switch (rdev->mode_info.connector_table) { 1163 case CT_POWERBOOK_EXTERNAL: 1164 case CT_MINI_EXTERNAL: 1165 default: 1166 tmds->dvo_chip = DVO_SIL164; 1167 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1168 break; 1169 } 1170 1171 return true; 1172 } 1173 1174 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 1175 struct radeon_encoder_ext_tmds *tmds) 1176 { 1177 struct drm_device *dev = encoder->base.dev; 1178 struct radeon_device *rdev = dev->dev_private; 1179 uint16_t offset; 1180 uint8_t ver, id, blocks, clk, data; 1181 int i; 1182 enum radeon_combios_ddc gpio; 1183 struct radeon_i2c_bus_rec i2c_bus; 1184 1185 if (rdev->bios == NULL) 1186 return false; 1187 1188 tmds->i2c_bus = NULL; 1189 if (rdev->flags & RADEON_IS_IGP) { 1190 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); 1191 if (offset) { 1192 ver = RBIOS8(offset); 1193 DRM_INFO("GPIO Table revision: %d\n", ver); 1194 blocks = RBIOS8(offset + 2); 1195 for (i = 0; i < blocks; i++) { 1196 id = RBIOS8(offset + 3 + (i * 5) + 0); 1197 if (id == 136) { 1198 clk = RBIOS8(offset + 3 + (i * 5) + 3); 1199 data = RBIOS8(offset + 3 + (i * 5) + 4); 1200 i2c_bus.valid = true; 1201 i2c_bus.mask_clk_mask = (1 << clk); 1202 i2c_bus.mask_data_mask = (1 << data); 1203 i2c_bus.a_clk_mask = (1 << clk); 1204 i2c_bus.a_data_mask = (1 << data); 1205 i2c_bus.en_clk_mask = (1 << clk); 1206 i2c_bus.en_data_mask = (1 << data); 1207 i2c_bus.y_clk_mask = (1 << clk); 1208 i2c_bus.y_data_mask = (1 << data); 1209 i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK; 1210 i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK; 1211 i2c_bus.a_clk_reg = RADEON_GPIOPAD_A; 1212 i2c_bus.a_data_reg = RADEON_GPIOPAD_A; 1213 i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN; 1214 i2c_bus.en_data_reg = RADEON_GPIOPAD_EN; 1215 i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y; 1216 i2c_bus.y_data_reg = RADEON_GPIOPAD_Y; 1217 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1218 tmds->dvo_chip = DVO_SIL164; 1219 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1220 break; 1221 } 1222 } 1223 } 1224 } else { 1225 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1226 if (offset) { 1227 ver = RBIOS8(offset); 1228 DRM_INFO("External TMDS Table revision: %d\n", ver); 1229 tmds->slave_addr = RBIOS8(offset + 4 + 2); 1230 tmds->slave_addr >>= 1; /* 7 bit addressing */ 1231 gpio = RBIOS8(offset + 4 + 3); 1232 switch (gpio) { 1233 case DDC_MONID: 1234 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1235 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1236 break; 1237 case DDC_DVI: 1238 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1239 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1240 break; 1241 case DDC_VGA: 1242 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1243 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1244 break; 1245 case DDC_CRT2: 1246 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */ 1247 if (rdev->family >= CHIP_R300) 1248 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1249 else 1250 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1251 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1252 break; 1253 case DDC_LCD: /* MM i2c */ 1254 DRM_ERROR("MM i2c requires hw i2c engine\n"); 1255 break; 1256 default: 1257 DRM_ERROR("Unsupported gpio %d\n", gpio); 1258 break; 1259 } 1260 } 1261 } 1262 1263 if (!tmds->i2c_bus) { 1264 DRM_INFO("No valid Ext TMDS info found in BIOS\n"); 1265 return false; 1266 } 1267 1268 return true; 1269 } 1270 1271 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) 1272 { 1273 struct radeon_device *rdev = dev->dev_private; 1274 struct radeon_i2c_bus_rec ddc_i2c; 1275 struct radeon_hpd hpd; 1276 1277 rdev->mode_info.connector_table = radeon_connector_table; 1278 if (rdev->mode_info.connector_table == CT_NONE) { 1279 #ifdef CONFIG_PPC_PMAC 1280 if (machine_is_compatible("PowerBook3,3")) { 1281 /* powerbook with VGA */ 1282 rdev->mode_info.connector_table = CT_POWERBOOK_VGA; 1283 } else if (machine_is_compatible("PowerBook3,4") || 1284 machine_is_compatible("PowerBook3,5")) { 1285 /* powerbook with internal tmds */ 1286 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL; 1287 } else if (machine_is_compatible("PowerBook5,1") || 1288 machine_is_compatible("PowerBook5,2") || 1289 machine_is_compatible("PowerBook5,3") || 1290 machine_is_compatible("PowerBook5,4") || 1291 machine_is_compatible("PowerBook5,5")) { 1292 /* powerbook with external single link tmds (sil164) */ 1293 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1294 } else if (machine_is_compatible("PowerBook5,6")) { 1295 /* powerbook with external dual or single link tmds */ 1296 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1297 } else if (machine_is_compatible("PowerBook5,7") || 1298 machine_is_compatible("PowerBook5,8") || 1299 machine_is_compatible("PowerBook5,9")) { 1300 /* PowerBook6,2 ? */ 1301 /* powerbook with external dual link tmds (sil1178?) */ 1302 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1303 } else if (machine_is_compatible("PowerBook4,1") || 1304 machine_is_compatible("PowerBook4,2") || 1305 machine_is_compatible("PowerBook4,3") || 1306 machine_is_compatible("PowerBook6,3") || 1307 machine_is_compatible("PowerBook6,5") || 1308 machine_is_compatible("PowerBook6,7")) { 1309 /* ibook */ 1310 rdev->mode_info.connector_table = CT_IBOOK; 1311 } else if (machine_is_compatible("PowerMac4,4")) { 1312 /* emac */ 1313 rdev->mode_info.connector_table = CT_EMAC; 1314 } else if (machine_is_compatible("PowerMac10,1")) { 1315 /* mini with internal tmds */ 1316 rdev->mode_info.connector_table = CT_MINI_INTERNAL; 1317 } else if (machine_is_compatible("PowerMac10,2")) { 1318 /* mini with external tmds */ 1319 rdev->mode_info.connector_table = CT_MINI_EXTERNAL; 1320 } else if (machine_is_compatible("PowerMac12,1")) { 1321 /* PowerMac8,1 ? */ 1322 /* imac g5 isight */ 1323 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; 1324 } else 1325 #endif /* CONFIG_PPC_PMAC */ 1326 rdev->mode_info.connector_table = CT_GENERIC; 1327 } 1328 1329 switch (rdev->mode_info.connector_table) { 1330 case CT_GENERIC: 1331 DRM_INFO("Connector Table: %d (generic)\n", 1332 rdev->mode_info.connector_table); 1333 /* these are the most common settings */ 1334 if (rdev->flags & RADEON_SINGLE_CRTC) { 1335 /* VGA - primary dac */ 1336 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1337 hpd.hpd = RADEON_HPD_NONE; 1338 radeon_add_legacy_encoder(dev, 1339 radeon_get_encoder_id(dev, 1340 ATOM_DEVICE_CRT1_SUPPORT, 1341 1), 1342 ATOM_DEVICE_CRT1_SUPPORT); 1343 radeon_add_legacy_connector(dev, 0, 1344 ATOM_DEVICE_CRT1_SUPPORT, 1345 DRM_MODE_CONNECTOR_VGA, 1346 &ddc_i2c, 1347 CONNECTOR_OBJECT_ID_VGA, 1348 &hpd); 1349 } else if (rdev->flags & RADEON_IS_MOBILITY) { 1350 /* LVDS */ 1351 ddc_i2c = combios_setup_i2c_bus(rdev, 0); 1352 hpd.hpd = RADEON_HPD_NONE; 1353 radeon_add_legacy_encoder(dev, 1354 radeon_get_encoder_id(dev, 1355 ATOM_DEVICE_LCD1_SUPPORT, 1356 0), 1357 ATOM_DEVICE_LCD1_SUPPORT); 1358 radeon_add_legacy_connector(dev, 0, 1359 ATOM_DEVICE_LCD1_SUPPORT, 1360 DRM_MODE_CONNECTOR_LVDS, 1361 &ddc_i2c, 1362 CONNECTOR_OBJECT_ID_LVDS, 1363 &hpd); 1364 1365 /* VGA - primary dac */ 1366 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1367 hpd.hpd = RADEON_HPD_NONE; 1368 radeon_add_legacy_encoder(dev, 1369 radeon_get_encoder_id(dev, 1370 ATOM_DEVICE_CRT1_SUPPORT, 1371 1), 1372 ATOM_DEVICE_CRT1_SUPPORT); 1373 radeon_add_legacy_connector(dev, 1, 1374 ATOM_DEVICE_CRT1_SUPPORT, 1375 DRM_MODE_CONNECTOR_VGA, 1376 &ddc_i2c, 1377 CONNECTOR_OBJECT_ID_VGA, 1378 &hpd); 1379 } else { 1380 /* DVI-I - tv dac, int tmds */ 1381 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1382 hpd.hpd = RADEON_HPD_1; 1383 radeon_add_legacy_encoder(dev, 1384 radeon_get_encoder_id(dev, 1385 ATOM_DEVICE_DFP1_SUPPORT, 1386 0), 1387 ATOM_DEVICE_DFP1_SUPPORT); 1388 radeon_add_legacy_encoder(dev, 1389 radeon_get_encoder_id(dev, 1390 ATOM_DEVICE_CRT2_SUPPORT, 1391 2), 1392 ATOM_DEVICE_CRT2_SUPPORT); 1393 radeon_add_legacy_connector(dev, 0, 1394 ATOM_DEVICE_DFP1_SUPPORT | 1395 ATOM_DEVICE_CRT2_SUPPORT, 1396 DRM_MODE_CONNECTOR_DVII, 1397 &ddc_i2c, 1398 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1399 &hpd); 1400 1401 /* VGA - primary dac */ 1402 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1403 hpd.hpd = RADEON_HPD_NONE; 1404 radeon_add_legacy_encoder(dev, 1405 radeon_get_encoder_id(dev, 1406 ATOM_DEVICE_CRT1_SUPPORT, 1407 1), 1408 ATOM_DEVICE_CRT1_SUPPORT); 1409 radeon_add_legacy_connector(dev, 1, 1410 ATOM_DEVICE_CRT1_SUPPORT, 1411 DRM_MODE_CONNECTOR_VGA, 1412 &ddc_i2c, 1413 CONNECTOR_OBJECT_ID_VGA, 1414 &hpd); 1415 } 1416 1417 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 1418 /* TV - tv dac */ 1419 ddc_i2c.valid = false; 1420 hpd.hpd = RADEON_HPD_NONE; 1421 radeon_add_legacy_encoder(dev, 1422 radeon_get_encoder_id(dev, 1423 ATOM_DEVICE_TV1_SUPPORT, 1424 2), 1425 ATOM_DEVICE_TV1_SUPPORT); 1426 radeon_add_legacy_connector(dev, 2, 1427 ATOM_DEVICE_TV1_SUPPORT, 1428 DRM_MODE_CONNECTOR_SVIDEO, 1429 &ddc_i2c, 1430 CONNECTOR_OBJECT_ID_SVIDEO, 1431 &hpd); 1432 } 1433 break; 1434 case CT_IBOOK: 1435 DRM_INFO("Connector Table: %d (ibook)\n", 1436 rdev->mode_info.connector_table); 1437 /* LVDS */ 1438 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1439 hpd.hpd = RADEON_HPD_NONE; 1440 radeon_add_legacy_encoder(dev, 1441 radeon_get_encoder_id(dev, 1442 ATOM_DEVICE_LCD1_SUPPORT, 1443 0), 1444 ATOM_DEVICE_LCD1_SUPPORT); 1445 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1446 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1447 CONNECTOR_OBJECT_ID_LVDS, 1448 &hpd); 1449 /* VGA - TV DAC */ 1450 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1451 hpd.hpd = RADEON_HPD_NONE; 1452 radeon_add_legacy_encoder(dev, 1453 radeon_get_encoder_id(dev, 1454 ATOM_DEVICE_CRT2_SUPPORT, 1455 2), 1456 ATOM_DEVICE_CRT2_SUPPORT); 1457 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1458 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1459 CONNECTOR_OBJECT_ID_VGA, 1460 &hpd); 1461 /* TV - TV DAC */ 1462 ddc_i2c.valid = false; 1463 hpd.hpd = RADEON_HPD_NONE; 1464 radeon_add_legacy_encoder(dev, 1465 radeon_get_encoder_id(dev, 1466 ATOM_DEVICE_TV1_SUPPORT, 1467 2), 1468 ATOM_DEVICE_TV1_SUPPORT); 1469 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1470 DRM_MODE_CONNECTOR_SVIDEO, 1471 &ddc_i2c, 1472 CONNECTOR_OBJECT_ID_SVIDEO, 1473 &hpd); 1474 break; 1475 case CT_POWERBOOK_EXTERNAL: 1476 DRM_INFO("Connector Table: %d (powerbook external tmds)\n", 1477 rdev->mode_info.connector_table); 1478 /* LVDS */ 1479 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1480 hpd.hpd = RADEON_HPD_NONE; 1481 radeon_add_legacy_encoder(dev, 1482 radeon_get_encoder_id(dev, 1483 ATOM_DEVICE_LCD1_SUPPORT, 1484 0), 1485 ATOM_DEVICE_LCD1_SUPPORT); 1486 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1487 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1488 CONNECTOR_OBJECT_ID_LVDS, 1489 &hpd); 1490 /* DVI-I - primary dac, ext tmds */ 1491 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1492 hpd.hpd = RADEON_HPD_2; /* ??? */ 1493 radeon_add_legacy_encoder(dev, 1494 radeon_get_encoder_id(dev, 1495 ATOM_DEVICE_DFP2_SUPPORT, 1496 0), 1497 ATOM_DEVICE_DFP2_SUPPORT); 1498 radeon_add_legacy_encoder(dev, 1499 radeon_get_encoder_id(dev, 1500 ATOM_DEVICE_CRT1_SUPPORT, 1501 1), 1502 ATOM_DEVICE_CRT1_SUPPORT); 1503 /* XXX some are SL */ 1504 radeon_add_legacy_connector(dev, 1, 1505 ATOM_DEVICE_DFP2_SUPPORT | 1506 ATOM_DEVICE_CRT1_SUPPORT, 1507 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1508 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 1509 &hpd); 1510 /* TV - TV DAC */ 1511 ddc_i2c.valid = false; 1512 hpd.hpd = RADEON_HPD_NONE; 1513 radeon_add_legacy_encoder(dev, 1514 radeon_get_encoder_id(dev, 1515 ATOM_DEVICE_TV1_SUPPORT, 1516 2), 1517 ATOM_DEVICE_TV1_SUPPORT); 1518 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1519 DRM_MODE_CONNECTOR_SVIDEO, 1520 &ddc_i2c, 1521 CONNECTOR_OBJECT_ID_SVIDEO, 1522 &hpd); 1523 break; 1524 case CT_POWERBOOK_INTERNAL: 1525 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", 1526 rdev->mode_info.connector_table); 1527 /* LVDS */ 1528 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1529 hpd.hpd = RADEON_HPD_NONE; 1530 radeon_add_legacy_encoder(dev, 1531 radeon_get_encoder_id(dev, 1532 ATOM_DEVICE_LCD1_SUPPORT, 1533 0), 1534 ATOM_DEVICE_LCD1_SUPPORT); 1535 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1536 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1537 CONNECTOR_OBJECT_ID_LVDS, 1538 &hpd); 1539 /* DVI-I - primary dac, int tmds */ 1540 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1541 hpd.hpd = RADEON_HPD_1; /* ??? */ 1542 radeon_add_legacy_encoder(dev, 1543 radeon_get_encoder_id(dev, 1544 ATOM_DEVICE_DFP1_SUPPORT, 1545 0), 1546 ATOM_DEVICE_DFP1_SUPPORT); 1547 radeon_add_legacy_encoder(dev, 1548 radeon_get_encoder_id(dev, 1549 ATOM_DEVICE_CRT1_SUPPORT, 1550 1), 1551 ATOM_DEVICE_CRT1_SUPPORT); 1552 radeon_add_legacy_connector(dev, 1, 1553 ATOM_DEVICE_DFP1_SUPPORT | 1554 ATOM_DEVICE_CRT1_SUPPORT, 1555 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1556 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1557 &hpd); 1558 /* TV - TV DAC */ 1559 ddc_i2c.valid = false; 1560 hpd.hpd = RADEON_HPD_NONE; 1561 radeon_add_legacy_encoder(dev, 1562 radeon_get_encoder_id(dev, 1563 ATOM_DEVICE_TV1_SUPPORT, 1564 2), 1565 ATOM_DEVICE_TV1_SUPPORT); 1566 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1567 DRM_MODE_CONNECTOR_SVIDEO, 1568 &ddc_i2c, 1569 CONNECTOR_OBJECT_ID_SVIDEO, 1570 &hpd); 1571 break; 1572 case CT_POWERBOOK_VGA: 1573 DRM_INFO("Connector Table: %d (powerbook vga)\n", 1574 rdev->mode_info.connector_table); 1575 /* LVDS */ 1576 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1577 hpd.hpd = RADEON_HPD_NONE; 1578 radeon_add_legacy_encoder(dev, 1579 radeon_get_encoder_id(dev, 1580 ATOM_DEVICE_LCD1_SUPPORT, 1581 0), 1582 ATOM_DEVICE_LCD1_SUPPORT); 1583 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1584 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1585 CONNECTOR_OBJECT_ID_LVDS, 1586 &hpd); 1587 /* VGA - primary dac */ 1588 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1589 hpd.hpd = RADEON_HPD_NONE; 1590 radeon_add_legacy_encoder(dev, 1591 radeon_get_encoder_id(dev, 1592 ATOM_DEVICE_CRT1_SUPPORT, 1593 1), 1594 ATOM_DEVICE_CRT1_SUPPORT); 1595 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 1596 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1597 CONNECTOR_OBJECT_ID_VGA, 1598 &hpd); 1599 /* TV - TV DAC */ 1600 ddc_i2c.valid = false; 1601 hpd.hpd = RADEON_HPD_NONE; 1602 radeon_add_legacy_encoder(dev, 1603 radeon_get_encoder_id(dev, 1604 ATOM_DEVICE_TV1_SUPPORT, 1605 2), 1606 ATOM_DEVICE_TV1_SUPPORT); 1607 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1608 DRM_MODE_CONNECTOR_SVIDEO, 1609 &ddc_i2c, 1610 CONNECTOR_OBJECT_ID_SVIDEO, 1611 &hpd); 1612 break; 1613 case CT_MINI_EXTERNAL: 1614 DRM_INFO("Connector Table: %d (mini external tmds)\n", 1615 rdev->mode_info.connector_table); 1616 /* DVI-I - tv dac, ext tmds */ 1617 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1618 hpd.hpd = RADEON_HPD_2; /* ??? */ 1619 radeon_add_legacy_encoder(dev, 1620 radeon_get_encoder_id(dev, 1621 ATOM_DEVICE_DFP2_SUPPORT, 1622 0), 1623 ATOM_DEVICE_DFP2_SUPPORT); 1624 radeon_add_legacy_encoder(dev, 1625 radeon_get_encoder_id(dev, 1626 ATOM_DEVICE_CRT2_SUPPORT, 1627 2), 1628 ATOM_DEVICE_CRT2_SUPPORT); 1629 /* XXX are any DL? */ 1630 radeon_add_legacy_connector(dev, 0, 1631 ATOM_DEVICE_DFP2_SUPPORT | 1632 ATOM_DEVICE_CRT2_SUPPORT, 1633 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1634 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1635 &hpd); 1636 /* TV - TV DAC */ 1637 ddc_i2c.valid = false; 1638 hpd.hpd = RADEON_HPD_NONE; 1639 radeon_add_legacy_encoder(dev, 1640 radeon_get_encoder_id(dev, 1641 ATOM_DEVICE_TV1_SUPPORT, 1642 2), 1643 ATOM_DEVICE_TV1_SUPPORT); 1644 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1645 DRM_MODE_CONNECTOR_SVIDEO, 1646 &ddc_i2c, 1647 CONNECTOR_OBJECT_ID_SVIDEO, 1648 &hpd); 1649 break; 1650 case CT_MINI_INTERNAL: 1651 DRM_INFO("Connector Table: %d (mini internal tmds)\n", 1652 rdev->mode_info.connector_table); 1653 /* DVI-I - tv dac, int tmds */ 1654 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1655 hpd.hpd = RADEON_HPD_1; /* ??? */ 1656 radeon_add_legacy_encoder(dev, 1657 radeon_get_encoder_id(dev, 1658 ATOM_DEVICE_DFP1_SUPPORT, 1659 0), 1660 ATOM_DEVICE_DFP1_SUPPORT); 1661 radeon_add_legacy_encoder(dev, 1662 radeon_get_encoder_id(dev, 1663 ATOM_DEVICE_CRT2_SUPPORT, 1664 2), 1665 ATOM_DEVICE_CRT2_SUPPORT); 1666 radeon_add_legacy_connector(dev, 0, 1667 ATOM_DEVICE_DFP1_SUPPORT | 1668 ATOM_DEVICE_CRT2_SUPPORT, 1669 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1670 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1671 &hpd); 1672 /* TV - TV DAC */ 1673 ddc_i2c.valid = false; 1674 hpd.hpd = RADEON_HPD_NONE; 1675 radeon_add_legacy_encoder(dev, 1676 radeon_get_encoder_id(dev, 1677 ATOM_DEVICE_TV1_SUPPORT, 1678 2), 1679 ATOM_DEVICE_TV1_SUPPORT); 1680 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1681 DRM_MODE_CONNECTOR_SVIDEO, 1682 &ddc_i2c, 1683 CONNECTOR_OBJECT_ID_SVIDEO, 1684 &hpd); 1685 break; 1686 case CT_IMAC_G5_ISIGHT: 1687 DRM_INFO("Connector Table: %d (imac g5 isight)\n", 1688 rdev->mode_info.connector_table); 1689 /* DVI-D - int tmds */ 1690 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1691 hpd.hpd = RADEON_HPD_1; /* ??? */ 1692 radeon_add_legacy_encoder(dev, 1693 radeon_get_encoder_id(dev, 1694 ATOM_DEVICE_DFP1_SUPPORT, 1695 0), 1696 ATOM_DEVICE_DFP1_SUPPORT); 1697 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT, 1698 DRM_MODE_CONNECTOR_DVID, &ddc_i2c, 1699 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 1700 &hpd); 1701 /* VGA - tv dac */ 1702 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1703 hpd.hpd = RADEON_HPD_NONE; 1704 radeon_add_legacy_encoder(dev, 1705 radeon_get_encoder_id(dev, 1706 ATOM_DEVICE_CRT2_SUPPORT, 1707 2), 1708 ATOM_DEVICE_CRT2_SUPPORT); 1709 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1710 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1711 CONNECTOR_OBJECT_ID_VGA, 1712 &hpd); 1713 /* TV - TV DAC */ 1714 ddc_i2c.valid = false; 1715 hpd.hpd = RADEON_HPD_NONE; 1716 radeon_add_legacy_encoder(dev, 1717 radeon_get_encoder_id(dev, 1718 ATOM_DEVICE_TV1_SUPPORT, 1719 2), 1720 ATOM_DEVICE_TV1_SUPPORT); 1721 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1722 DRM_MODE_CONNECTOR_SVIDEO, 1723 &ddc_i2c, 1724 CONNECTOR_OBJECT_ID_SVIDEO, 1725 &hpd); 1726 break; 1727 case CT_EMAC: 1728 DRM_INFO("Connector Table: %d (emac)\n", 1729 rdev->mode_info.connector_table); 1730 /* VGA - primary dac */ 1731 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1732 hpd.hpd = RADEON_HPD_NONE; 1733 radeon_add_legacy_encoder(dev, 1734 radeon_get_encoder_id(dev, 1735 ATOM_DEVICE_CRT1_SUPPORT, 1736 1), 1737 ATOM_DEVICE_CRT1_SUPPORT); 1738 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1739 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1740 CONNECTOR_OBJECT_ID_VGA, 1741 &hpd); 1742 /* VGA - tv dac */ 1743 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1744 hpd.hpd = RADEON_HPD_NONE; 1745 radeon_add_legacy_encoder(dev, 1746 radeon_get_encoder_id(dev, 1747 ATOM_DEVICE_CRT2_SUPPORT, 1748 2), 1749 ATOM_DEVICE_CRT2_SUPPORT); 1750 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1751 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1752 CONNECTOR_OBJECT_ID_VGA, 1753 &hpd); 1754 /* TV - TV DAC */ 1755 ddc_i2c.valid = false; 1756 hpd.hpd = RADEON_HPD_NONE; 1757 radeon_add_legacy_encoder(dev, 1758 radeon_get_encoder_id(dev, 1759 ATOM_DEVICE_TV1_SUPPORT, 1760 2), 1761 ATOM_DEVICE_TV1_SUPPORT); 1762 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1763 DRM_MODE_CONNECTOR_SVIDEO, 1764 &ddc_i2c, 1765 CONNECTOR_OBJECT_ID_SVIDEO, 1766 &hpd); 1767 break; 1768 default: 1769 DRM_INFO("Connector table: %d (invalid)\n", 1770 rdev->mode_info.connector_table); 1771 return false; 1772 } 1773 1774 radeon_link_encoder_connector(dev); 1775 1776 return true; 1777 } 1778 1779 static bool radeon_apply_legacy_quirks(struct drm_device *dev, 1780 int bios_index, 1781 enum radeon_combios_connector 1782 *legacy_connector, 1783 struct radeon_i2c_bus_rec *ddc_i2c, 1784 struct radeon_hpd *hpd) 1785 { 1786 struct radeon_device *rdev = dev->dev_private; 1787 1788 /* XPRESS DDC quirks */ 1789 if ((rdev->family == CHIP_RS400 || 1790 rdev->family == CHIP_RS480) && 1791 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 1792 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1793 else if ((rdev->family == CHIP_RS400 || 1794 rdev->family == CHIP_RS480) && 1795 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) { 1796 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK); 1797 ddc_i2c->mask_clk_mask = (0x20 << 8); 1798 ddc_i2c->mask_data_mask = 0x80; 1799 ddc_i2c->a_clk_mask = (0x20 << 8); 1800 ddc_i2c->a_data_mask = 0x80; 1801 ddc_i2c->en_clk_mask = (0x20 << 8); 1802 ddc_i2c->en_data_mask = 0x80; 1803 ddc_i2c->y_clk_mask = (0x20 << 8); 1804 ddc_i2c->y_data_mask = 0x80; 1805 } 1806 1807 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */ 1808 if ((rdev->family >= CHIP_R300) && 1809 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 1810 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1811 1812 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, 1813 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ 1814 if (dev->pdev->device == 0x515e && 1815 dev->pdev->subsystem_vendor == 0x1014) { 1816 if (*legacy_connector == CONNECTOR_CRT_LEGACY && 1817 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 1818 return false; 1819 } 1820 1821 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */ 1822 if (dev->pdev->device == 0x5159 && 1823 dev->pdev->subsystem_vendor == 0x1002 && 1824 dev->pdev->subsystem_device == 0x013a) { 1825 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) 1826 *legacy_connector = CONNECTOR_CRT_LEGACY; 1827 1828 } 1829 1830 /* X300 card with extra non-existent DVI port */ 1831 if (dev->pdev->device == 0x5B60 && 1832 dev->pdev->subsystem_vendor == 0x17af && 1833 dev->pdev->subsystem_device == 0x201e && bios_index == 2) { 1834 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) 1835 return false; 1836 } 1837 1838 return true; 1839 } 1840 1841 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev) 1842 { 1843 /* Acer 5102 has non-existent TV port */ 1844 if (dev->pdev->device == 0x5975 && 1845 dev->pdev->subsystem_vendor == 0x1025 && 1846 dev->pdev->subsystem_device == 0x009f) 1847 return false; 1848 1849 /* HP dc5750 has non-existent TV port */ 1850 if (dev->pdev->device == 0x5974 && 1851 dev->pdev->subsystem_vendor == 0x103c && 1852 dev->pdev->subsystem_device == 0x280a) 1853 return false; 1854 1855 /* MSI S270 has non-existent TV port */ 1856 if (dev->pdev->device == 0x5955 && 1857 dev->pdev->subsystem_vendor == 0x1462 && 1858 dev->pdev->subsystem_device == 0x0131) 1859 return false; 1860 1861 return true; 1862 } 1863 1864 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d) 1865 { 1866 struct radeon_device *rdev = dev->dev_private; 1867 uint32_t ext_tmds_info; 1868 1869 if (rdev->flags & RADEON_IS_IGP) { 1870 if (is_dvi_d) 1871 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 1872 else 1873 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 1874 } 1875 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1876 if (ext_tmds_info) { 1877 uint8_t rev = RBIOS8(ext_tmds_info); 1878 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5); 1879 if (rev >= 3) { 1880 if (is_dvi_d) 1881 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 1882 else 1883 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 1884 } else { 1885 if (flags & 1) { 1886 if (is_dvi_d) 1887 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 1888 else 1889 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 1890 } 1891 } 1892 } 1893 if (is_dvi_d) 1894 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 1895 else 1896 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 1897 } 1898 1899 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) 1900 { 1901 struct radeon_device *rdev = dev->dev_private; 1902 uint32_t conn_info, entry, devices; 1903 uint16_t tmp, connector_object_id; 1904 enum radeon_combios_ddc ddc_type; 1905 enum radeon_combios_connector connector; 1906 int i = 0; 1907 struct radeon_i2c_bus_rec ddc_i2c; 1908 struct radeon_hpd hpd; 1909 1910 if (rdev->bios == NULL) 1911 return false; 1912 1913 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE); 1914 if (conn_info) { 1915 for (i = 0; i < 4; i++) { 1916 entry = conn_info + 2 + i * 2; 1917 1918 if (!RBIOS16(entry)) 1919 break; 1920 1921 tmp = RBIOS16(entry); 1922 1923 connector = (tmp >> 12) & 0xf; 1924 1925 ddc_type = (tmp >> 8) & 0xf; 1926 switch (ddc_type) { 1927 case DDC_MONID: 1928 ddc_i2c = 1929 combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1930 break; 1931 case DDC_DVI: 1932 ddc_i2c = 1933 combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1934 break; 1935 case DDC_VGA: 1936 ddc_i2c = 1937 combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1938 break; 1939 case DDC_CRT2: 1940 ddc_i2c = 1941 combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1942 break; 1943 default: 1944 break; 1945 } 1946 1947 switch (connector) { 1948 case CONNECTOR_PROPRIETARY_LEGACY: 1949 case CONNECTOR_DVI_I_LEGACY: 1950 case CONNECTOR_DVI_D_LEGACY: 1951 if ((tmp >> 4) & 0x1) 1952 hpd.hpd = RADEON_HPD_2; 1953 else 1954 hpd.hpd = RADEON_HPD_1; 1955 break; 1956 default: 1957 hpd.hpd = RADEON_HPD_NONE; 1958 break; 1959 } 1960 1961 if (!radeon_apply_legacy_quirks(dev, i, &connector, 1962 &ddc_i2c, &hpd)) 1963 continue; 1964 1965 switch (connector) { 1966 case CONNECTOR_PROPRIETARY_LEGACY: 1967 if ((tmp >> 4) & 0x1) 1968 devices = ATOM_DEVICE_DFP2_SUPPORT; 1969 else 1970 devices = ATOM_DEVICE_DFP1_SUPPORT; 1971 radeon_add_legacy_encoder(dev, 1972 radeon_get_encoder_id 1973 (dev, devices, 0), 1974 devices); 1975 radeon_add_legacy_connector(dev, i, devices, 1976 legacy_connector_convert 1977 [connector], 1978 &ddc_i2c, 1979 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 1980 &hpd); 1981 break; 1982 case CONNECTOR_CRT_LEGACY: 1983 if (tmp & 0x1) { 1984 devices = ATOM_DEVICE_CRT2_SUPPORT; 1985 radeon_add_legacy_encoder(dev, 1986 radeon_get_encoder_id 1987 (dev, 1988 ATOM_DEVICE_CRT2_SUPPORT, 1989 2), 1990 ATOM_DEVICE_CRT2_SUPPORT); 1991 } else { 1992 devices = ATOM_DEVICE_CRT1_SUPPORT; 1993 radeon_add_legacy_encoder(dev, 1994 radeon_get_encoder_id 1995 (dev, 1996 ATOM_DEVICE_CRT1_SUPPORT, 1997 1), 1998 ATOM_DEVICE_CRT1_SUPPORT); 1999 } 2000 radeon_add_legacy_connector(dev, 2001 i, 2002 devices, 2003 legacy_connector_convert 2004 [connector], 2005 &ddc_i2c, 2006 CONNECTOR_OBJECT_ID_VGA, 2007 &hpd); 2008 break; 2009 case CONNECTOR_DVI_I_LEGACY: 2010 devices = 0; 2011 if (tmp & 0x1) { 2012 devices |= ATOM_DEVICE_CRT2_SUPPORT; 2013 radeon_add_legacy_encoder(dev, 2014 radeon_get_encoder_id 2015 (dev, 2016 ATOM_DEVICE_CRT2_SUPPORT, 2017 2), 2018 ATOM_DEVICE_CRT2_SUPPORT); 2019 } else { 2020 devices |= ATOM_DEVICE_CRT1_SUPPORT; 2021 radeon_add_legacy_encoder(dev, 2022 radeon_get_encoder_id 2023 (dev, 2024 ATOM_DEVICE_CRT1_SUPPORT, 2025 1), 2026 ATOM_DEVICE_CRT1_SUPPORT); 2027 } 2028 if ((tmp >> 4) & 0x1) { 2029 devices |= ATOM_DEVICE_DFP2_SUPPORT; 2030 radeon_add_legacy_encoder(dev, 2031 radeon_get_encoder_id 2032 (dev, 2033 ATOM_DEVICE_DFP2_SUPPORT, 2034 0), 2035 ATOM_DEVICE_DFP2_SUPPORT); 2036 connector_object_id = combios_check_dl_dvi(dev, 0); 2037 } else { 2038 devices |= ATOM_DEVICE_DFP1_SUPPORT; 2039 radeon_add_legacy_encoder(dev, 2040 radeon_get_encoder_id 2041 (dev, 2042 ATOM_DEVICE_DFP1_SUPPORT, 2043 0), 2044 ATOM_DEVICE_DFP1_SUPPORT); 2045 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2046 } 2047 radeon_add_legacy_connector(dev, 2048 i, 2049 devices, 2050 legacy_connector_convert 2051 [connector], 2052 &ddc_i2c, 2053 connector_object_id, 2054 &hpd); 2055 break; 2056 case CONNECTOR_DVI_D_LEGACY: 2057 if ((tmp >> 4) & 0x1) { 2058 devices = ATOM_DEVICE_DFP2_SUPPORT; 2059 connector_object_id = combios_check_dl_dvi(dev, 1); 2060 } else { 2061 devices = ATOM_DEVICE_DFP1_SUPPORT; 2062 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2063 } 2064 radeon_add_legacy_encoder(dev, 2065 radeon_get_encoder_id 2066 (dev, devices, 0), 2067 devices); 2068 radeon_add_legacy_connector(dev, i, devices, 2069 legacy_connector_convert 2070 [connector], 2071 &ddc_i2c, 2072 connector_object_id, 2073 &hpd); 2074 break; 2075 case CONNECTOR_CTV_LEGACY: 2076 case CONNECTOR_STV_LEGACY: 2077 radeon_add_legacy_encoder(dev, 2078 radeon_get_encoder_id 2079 (dev, 2080 ATOM_DEVICE_TV1_SUPPORT, 2081 2), 2082 ATOM_DEVICE_TV1_SUPPORT); 2083 radeon_add_legacy_connector(dev, i, 2084 ATOM_DEVICE_TV1_SUPPORT, 2085 legacy_connector_convert 2086 [connector], 2087 &ddc_i2c, 2088 CONNECTOR_OBJECT_ID_SVIDEO, 2089 &hpd); 2090 break; 2091 default: 2092 DRM_ERROR("Unknown connector type: %d\n", 2093 connector); 2094 continue; 2095 } 2096 2097 } 2098 } else { 2099 uint16_t tmds_info = 2100 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 2101 if (tmds_info) { 2102 DRM_DEBUG("Found DFP table, assuming DVI connector\n"); 2103 2104 radeon_add_legacy_encoder(dev, 2105 radeon_get_encoder_id(dev, 2106 ATOM_DEVICE_CRT1_SUPPORT, 2107 1), 2108 ATOM_DEVICE_CRT1_SUPPORT); 2109 radeon_add_legacy_encoder(dev, 2110 radeon_get_encoder_id(dev, 2111 ATOM_DEVICE_DFP1_SUPPORT, 2112 0), 2113 ATOM_DEVICE_DFP1_SUPPORT); 2114 2115 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 2116 hpd.hpd = RADEON_HPD_NONE; 2117 radeon_add_legacy_connector(dev, 2118 0, 2119 ATOM_DEVICE_CRT1_SUPPORT | 2120 ATOM_DEVICE_DFP1_SUPPORT, 2121 DRM_MODE_CONNECTOR_DVII, 2122 &ddc_i2c, 2123 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2124 &hpd); 2125 } else { 2126 uint16_t crt_info = 2127 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 2128 DRM_DEBUG("Found CRT table, assuming VGA connector\n"); 2129 if (crt_info) { 2130 radeon_add_legacy_encoder(dev, 2131 radeon_get_encoder_id(dev, 2132 ATOM_DEVICE_CRT1_SUPPORT, 2133 1), 2134 ATOM_DEVICE_CRT1_SUPPORT); 2135 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 2136 hpd.hpd = RADEON_HPD_NONE; 2137 radeon_add_legacy_connector(dev, 2138 0, 2139 ATOM_DEVICE_CRT1_SUPPORT, 2140 DRM_MODE_CONNECTOR_VGA, 2141 &ddc_i2c, 2142 CONNECTOR_OBJECT_ID_VGA, 2143 &hpd); 2144 } else { 2145 DRM_DEBUG("No connector info found\n"); 2146 return false; 2147 } 2148 } 2149 } 2150 2151 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) { 2152 uint16_t lcd_info = 2153 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 2154 if (lcd_info) { 2155 uint16_t lcd_ddc_info = 2156 combios_get_table_offset(dev, 2157 COMBIOS_LCD_DDC_INFO_TABLE); 2158 2159 radeon_add_legacy_encoder(dev, 2160 radeon_get_encoder_id(dev, 2161 ATOM_DEVICE_LCD1_SUPPORT, 2162 0), 2163 ATOM_DEVICE_LCD1_SUPPORT); 2164 2165 if (lcd_ddc_info) { 2166 ddc_type = RBIOS8(lcd_ddc_info + 2); 2167 switch (ddc_type) { 2168 case DDC_MONID: 2169 ddc_i2c = 2170 combios_setup_i2c_bus 2171 (rdev, RADEON_GPIO_MONID); 2172 break; 2173 case DDC_DVI: 2174 ddc_i2c = 2175 combios_setup_i2c_bus 2176 (rdev, RADEON_GPIO_DVI_DDC); 2177 break; 2178 case DDC_VGA: 2179 ddc_i2c = 2180 combios_setup_i2c_bus 2181 (rdev, RADEON_GPIO_VGA_DDC); 2182 break; 2183 case DDC_CRT2: 2184 ddc_i2c = 2185 combios_setup_i2c_bus 2186 (rdev, RADEON_GPIO_CRT2_DDC); 2187 break; 2188 case DDC_LCD: 2189 ddc_i2c = 2190 combios_setup_i2c_bus 2191 (rdev, RADEON_GPIOPAD_MASK); 2192 ddc_i2c.mask_clk_mask = 2193 RBIOS32(lcd_ddc_info + 3); 2194 ddc_i2c.mask_data_mask = 2195 RBIOS32(lcd_ddc_info + 7); 2196 ddc_i2c.a_clk_mask = 2197 RBIOS32(lcd_ddc_info + 3); 2198 ddc_i2c.a_data_mask = 2199 RBIOS32(lcd_ddc_info + 7); 2200 ddc_i2c.en_clk_mask = 2201 RBIOS32(lcd_ddc_info + 3); 2202 ddc_i2c.en_data_mask = 2203 RBIOS32(lcd_ddc_info + 7); 2204 ddc_i2c.y_clk_mask = 2205 RBIOS32(lcd_ddc_info + 3); 2206 ddc_i2c.y_data_mask = 2207 RBIOS32(lcd_ddc_info + 7); 2208 break; 2209 case DDC_GPIO: 2210 ddc_i2c = 2211 combios_setup_i2c_bus 2212 (rdev, RADEON_MDGPIO_MASK); 2213 ddc_i2c.mask_clk_mask = 2214 RBIOS32(lcd_ddc_info + 3); 2215 ddc_i2c.mask_data_mask = 2216 RBIOS32(lcd_ddc_info + 7); 2217 ddc_i2c.a_clk_mask = 2218 RBIOS32(lcd_ddc_info + 3); 2219 ddc_i2c.a_data_mask = 2220 RBIOS32(lcd_ddc_info + 7); 2221 ddc_i2c.en_clk_mask = 2222 RBIOS32(lcd_ddc_info + 3); 2223 ddc_i2c.en_data_mask = 2224 RBIOS32(lcd_ddc_info + 7); 2225 ddc_i2c.y_clk_mask = 2226 RBIOS32(lcd_ddc_info + 3); 2227 ddc_i2c.y_data_mask = 2228 RBIOS32(lcd_ddc_info + 7); 2229 break; 2230 default: 2231 ddc_i2c.valid = false; 2232 break; 2233 } 2234 DRM_DEBUG("LCD DDC Info Table found!\n"); 2235 } else 2236 ddc_i2c.valid = false; 2237 2238 hpd.hpd = RADEON_HPD_NONE; 2239 radeon_add_legacy_connector(dev, 2240 5, 2241 ATOM_DEVICE_LCD1_SUPPORT, 2242 DRM_MODE_CONNECTOR_LVDS, 2243 &ddc_i2c, 2244 CONNECTOR_OBJECT_ID_LVDS, 2245 &hpd); 2246 } 2247 } 2248 2249 /* check TV table */ 2250 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 2251 uint32_t tv_info = 2252 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 2253 if (tv_info) { 2254 if (RBIOS8(tv_info + 6) == 'T') { 2255 if (radeon_apply_legacy_tv_quirks(dev)) { 2256 hpd.hpd = RADEON_HPD_NONE; 2257 radeon_add_legacy_encoder(dev, 2258 radeon_get_encoder_id 2259 (dev, 2260 ATOM_DEVICE_TV1_SUPPORT, 2261 2), 2262 ATOM_DEVICE_TV1_SUPPORT); 2263 radeon_add_legacy_connector(dev, 6, 2264 ATOM_DEVICE_TV1_SUPPORT, 2265 DRM_MODE_CONNECTOR_SVIDEO, 2266 &ddc_i2c, 2267 CONNECTOR_OBJECT_ID_SVIDEO, 2268 &hpd); 2269 } 2270 } 2271 } 2272 } 2273 2274 radeon_link_encoder_connector(dev); 2275 2276 return true; 2277 } 2278 2279 void radeon_external_tmds_setup(struct drm_encoder *encoder) 2280 { 2281 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2282 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2283 2284 if (!tmds) 2285 return; 2286 2287 switch (tmds->dvo_chip) { 2288 case DVO_SIL164: 2289 /* sil 164 */ 2290 radeon_i2c_do_lock(tmds->i2c_bus, 1); 2291 radeon_i2c_sw_put_byte(tmds->i2c_bus, 2292 tmds->slave_addr, 2293 0x08, 0x30); 2294 radeon_i2c_sw_put_byte(tmds->i2c_bus, 2295 tmds->slave_addr, 2296 0x09, 0x00); 2297 radeon_i2c_sw_put_byte(tmds->i2c_bus, 2298 tmds->slave_addr, 2299 0x0a, 0x90); 2300 radeon_i2c_sw_put_byte(tmds->i2c_bus, 2301 tmds->slave_addr, 2302 0x0c, 0x89); 2303 radeon_i2c_sw_put_byte(tmds->i2c_bus, 2304 tmds->slave_addr, 2305 0x08, 0x3b); 2306 radeon_i2c_do_lock(tmds->i2c_bus, 0); 2307 break; 2308 case DVO_SIL1178: 2309 /* sil 1178 - untested */ 2310 /* 2311 * 0x0f, 0x44 2312 * 0x0f, 0x4c 2313 * 0x0e, 0x01 2314 * 0x0a, 0x80 2315 * 0x09, 0x30 2316 * 0x0c, 0xc9 2317 * 0x0d, 0x70 2318 * 0x08, 0x32 2319 * 0x08, 0x33 2320 */ 2321 break; 2322 default: 2323 break; 2324 } 2325 2326 } 2327 2328 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) 2329 { 2330 struct drm_device *dev = encoder->dev; 2331 struct radeon_device *rdev = dev->dev_private; 2332 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2333 uint16_t offset; 2334 uint8_t blocks, slave_addr, rev; 2335 uint32_t index, id; 2336 uint32_t reg, val, and_mask, or_mask; 2337 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2338 2339 if (rdev->bios == NULL) 2340 return false; 2341 2342 if (!tmds) 2343 return false; 2344 2345 if (rdev->flags & RADEON_IS_IGP) { 2346 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE); 2347 rev = RBIOS8(offset); 2348 if (offset) { 2349 rev = RBIOS8(offset); 2350 if (rev > 1) { 2351 blocks = RBIOS8(offset + 3); 2352 index = offset + 4; 2353 while (blocks > 0) { 2354 id = RBIOS16(index); 2355 index += 2; 2356 switch (id >> 13) { 2357 case 0: 2358 reg = (id & 0x1fff) * 4; 2359 val = RBIOS32(index); 2360 index += 4; 2361 WREG32(reg, val); 2362 break; 2363 case 2: 2364 reg = (id & 0x1fff) * 4; 2365 and_mask = RBIOS32(index); 2366 index += 4; 2367 or_mask = RBIOS32(index); 2368 index += 4; 2369 val = RREG32(reg); 2370 val = (val & and_mask) | or_mask; 2371 WREG32(reg, val); 2372 break; 2373 case 3: 2374 val = RBIOS16(index); 2375 index += 2; 2376 udelay(val); 2377 break; 2378 case 4: 2379 val = RBIOS16(index); 2380 index += 2; 2381 udelay(val * 1000); 2382 break; 2383 case 6: 2384 slave_addr = id & 0xff; 2385 slave_addr >>= 1; /* 7 bit addressing */ 2386 index++; 2387 reg = RBIOS8(index); 2388 index++; 2389 val = RBIOS8(index); 2390 index++; 2391 radeon_i2c_do_lock(tmds->i2c_bus, 1); 2392 radeon_i2c_sw_put_byte(tmds->i2c_bus, 2393 slave_addr, 2394 reg, val); 2395 radeon_i2c_do_lock(tmds->i2c_bus, 0); 2396 break; 2397 default: 2398 DRM_ERROR("Unknown id %d\n", id >> 13); 2399 break; 2400 } 2401 blocks--; 2402 } 2403 return true; 2404 } 2405 } 2406 } else { 2407 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 2408 if (offset) { 2409 index = offset + 10; 2410 id = RBIOS16(index); 2411 while (id != 0xffff) { 2412 index += 2; 2413 switch (id >> 13) { 2414 case 0: 2415 reg = (id & 0x1fff) * 4; 2416 val = RBIOS32(index); 2417 WREG32(reg, val); 2418 break; 2419 case 2: 2420 reg = (id & 0x1fff) * 4; 2421 and_mask = RBIOS32(index); 2422 index += 4; 2423 or_mask = RBIOS32(index); 2424 index += 4; 2425 val = RREG32(reg); 2426 val = (val & and_mask) | or_mask; 2427 WREG32(reg, val); 2428 break; 2429 case 4: 2430 val = RBIOS16(index); 2431 index += 2; 2432 udelay(val); 2433 break; 2434 case 5: 2435 reg = id & 0x1fff; 2436 and_mask = RBIOS32(index); 2437 index += 4; 2438 or_mask = RBIOS32(index); 2439 index += 4; 2440 val = RREG32_PLL(reg); 2441 val = (val & and_mask) | or_mask; 2442 WREG32_PLL(reg, val); 2443 break; 2444 case 6: 2445 reg = id & 0x1fff; 2446 val = RBIOS8(index); 2447 index += 1; 2448 radeon_i2c_do_lock(tmds->i2c_bus, 1); 2449 radeon_i2c_sw_put_byte(tmds->i2c_bus, 2450 tmds->slave_addr, 2451 reg, val); 2452 radeon_i2c_do_lock(tmds->i2c_bus, 0); 2453 break; 2454 default: 2455 DRM_ERROR("Unknown id %d\n", id >> 13); 2456 break; 2457 } 2458 id = RBIOS16(index); 2459 } 2460 return true; 2461 } 2462 } 2463 return false; 2464 } 2465 2466 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset) 2467 { 2468 struct radeon_device *rdev = dev->dev_private; 2469 2470 if (offset) { 2471 while (RBIOS16(offset)) { 2472 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13); 2473 uint32_t addr = (RBIOS16(offset) & 0x1fff); 2474 uint32_t val, and_mask, or_mask; 2475 uint32_t tmp; 2476 2477 offset += 2; 2478 switch (cmd) { 2479 case 0: 2480 val = RBIOS32(offset); 2481 offset += 4; 2482 WREG32(addr, val); 2483 break; 2484 case 1: 2485 val = RBIOS32(offset); 2486 offset += 4; 2487 WREG32(addr, val); 2488 break; 2489 case 2: 2490 and_mask = RBIOS32(offset); 2491 offset += 4; 2492 or_mask = RBIOS32(offset); 2493 offset += 4; 2494 tmp = RREG32(addr); 2495 tmp &= and_mask; 2496 tmp |= or_mask; 2497 WREG32(addr, tmp); 2498 break; 2499 case 3: 2500 and_mask = RBIOS32(offset); 2501 offset += 4; 2502 or_mask = RBIOS32(offset); 2503 offset += 4; 2504 tmp = RREG32(addr); 2505 tmp &= and_mask; 2506 tmp |= or_mask; 2507 WREG32(addr, tmp); 2508 break; 2509 case 4: 2510 val = RBIOS16(offset); 2511 offset += 2; 2512 udelay(val); 2513 break; 2514 case 5: 2515 val = RBIOS16(offset); 2516 offset += 2; 2517 switch (addr) { 2518 case 8: 2519 while (val--) { 2520 if (! 2521 (RREG32_PLL 2522 (RADEON_CLK_PWRMGT_CNTL) & 2523 RADEON_MC_BUSY)) 2524 break; 2525 } 2526 break; 2527 case 9: 2528 while (val--) { 2529 if ((RREG32(RADEON_MC_STATUS) & 2530 RADEON_MC_IDLE)) 2531 break; 2532 } 2533 break; 2534 default: 2535 break; 2536 } 2537 break; 2538 default: 2539 break; 2540 } 2541 } 2542 } 2543 } 2544 2545 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset) 2546 { 2547 struct radeon_device *rdev = dev->dev_private; 2548 2549 if (offset) { 2550 while (RBIOS8(offset)) { 2551 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6); 2552 uint8_t addr = (RBIOS8(offset) & 0x3f); 2553 uint32_t val, shift, tmp; 2554 uint32_t and_mask, or_mask; 2555 2556 offset++; 2557 switch (cmd) { 2558 case 0: 2559 val = RBIOS32(offset); 2560 offset += 4; 2561 WREG32_PLL(addr, val); 2562 break; 2563 case 1: 2564 shift = RBIOS8(offset) * 8; 2565 offset++; 2566 and_mask = RBIOS8(offset) << shift; 2567 and_mask |= ~(0xff << shift); 2568 offset++; 2569 or_mask = RBIOS8(offset) << shift; 2570 offset++; 2571 tmp = RREG32_PLL(addr); 2572 tmp &= and_mask; 2573 tmp |= or_mask; 2574 WREG32_PLL(addr, tmp); 2575 break; 2576 case 2: 2577 case 3: 2578 tmp = 1000; 2579 switch (addr) { 2580 case 1: 2581 udelay(150); 2582 break; 2583 case 2: 2584 udelay(1000); 2585 break; 2586 case 3: 2587 while (tmp--) { 2588 if (! 2589 (RREG32_PLL 2590 (RADEON_CLK_PWRMGT_CNTL) & 2591 RADEON_MC_BUSY)) 2592 break; 2593 } 2594 break; 2595 case 4: 2596 while (tmp--) { 2597 if (RREG32_PLL 2598 (RADEON_CLK_PWRMGT_CNTL) & 2599 RADEON_DLL_READY) 2600 break; 2601 } 2602 break; 2603 case 5: 2604 tmp = 2605 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); 2606 if (tmp & RADEON_CG_NO1_DEBUG_0) { 2607 #if 0 2608 uint32_t mclk_cntl = 2609 RREG32_PLL 2610 (RADEON_MCLK_CNTL); 2611 mclk_cntl &= 0xffff0000; 2612 /*mclk_cntl |= 0x00001111;*//* ??? */ 2613 WREG32_PLL(RADEON_MCLK_CNTL, 2614 mclk_cntl); 2615 udelay(10000); 2616 #endif 2617 WREG32_PLL 2618 (RADEON_CLK_PWRMGT_CNTL, 2619 tmp & 2620 ~RADEON_CG_NO1_DEBUG_0); 2621 udelay(10000); 2622 } 2623 break; 2624 default: 2625 break; 2626 } 2627 break; 2628 default: 2629 break; 2630 } 2631 } 2632 } 2633 } 2634 2635 static void combios_parse_ram_reset_table(struct drm_device *dev, 2636 uint16_t offset) 2637 { 2638 struct radeon_device *rdev = dev->dev_private; 2639 uint32_t tmp; 2640 2641 if (offset) { 2642 uint8_t val = RBIOS8(offset); 2643 while (val != 0xff) { 2644 offset++; 2645 2646 if (val == 0x0f) { 2647 uint32_t channel_complete_mask; 2648 2649 if (ASIC_IS_R300(rdev)) 2650 channel_complete_mask = 2651 R300_MEM_PWRUP_COMPLETE; 2652 else 2653 channel_complete_mask = 2654 RADEON_MEM_PWRUP_COMPLETE; 2655 tmp = 20000; 2656 while (tmp--) { 2657 if ((RREG32(RADEON_MEM_STR_CNTL) & 2658 channel_complete_mask) == 2659 channel_complete_mask) 2660 break; 2661 } 2662 } else { 2663 uint32_t or_mask = RBIOS16(offset); 2664 offset += 2; 2665 2666 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 2667 tmp &= RADEON_SDRAM_MODE_MASK; 2668 tmp |= or_mask; 2669 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 2670 2671 or_mask = val << 24; 2672 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 2673 tmp &= RADEON_B3MEM_RESET_MASK; 2674 tmp |= or_mask; 2675 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 2676 } 2677 val = RBIOS8(offset); 2678 } 2679 } 2680 } 2681 2682 static uint32_t combios_detect_ram(struct drm_device *dev, int ram, 2683 int mem_addr_mapping) 2684 { 2685 struct radeon_device *rdev = dev->dev_private; 2686 uint32_t mem_cntl; 2687 uint32_t mem_size; 2688 uint32_t addr = 0; 2689 2690 mem_cntl = RREG32(RADEON_MEM_CNTL); 2691 if (mem_cntl & RV100_HALF_MODE) 2692 ram /= 2; 2693 mem_size = ram; 2694 mem_cntl &= ~(0xff << 8); 2695 mem_cntl |= (mem_addr_mapping & 0xff) << 8; 2696 WREG32(RADEON_MEM_CNTL, mem_cntl); 2697 RREG32(RADEON_MEM_CNTL); 2698 2699 /* sdram reset ? */ 2700 2701 /* something like this???? */ 2702 while (ram--) { 2703 addr = ram * 1024 * 1024; 2704 /* write to each page */ 2705 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER); 2706 WREG32(RADEON_MM_DATA, 0xdeadbeef); 2707 /* read back and verify */ 2708 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER); 2709 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef) 2710 return 0; 2711 } 2712 2713 return mem_size; 2714 } 2715 2716 static void combios_write_ram_size(struct drm_device *dev) 2717 { 2718 struct radeon_device *rdev = dev->dev_private; 2719 uint8_t rev; 2720 uint16_t offset; 2721 uint32_t mem_size = 0; 2722 uint32_t mem_cntl = 0; 2723 2724 /* should do something smarter here I guess... */ 2725 if (rdev->flags & RADEON_IS_IGP) 2726 return; 2727 2728 /* first check detected mem table */ 2729 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE); 2730 if (offset) { 2731 rev = RBIOS8(offset); 2732 if (rev < 3) { 2733 mem_cntl = RBIOS32(offset + 1); 2734 mem_size = RBIOS16(offset + 5); 2735 if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) && 2736 ((dev->pdev->device != 0x515e) 2737 && (dev->pdev->device != 0x5969))) 2738 WREG32(RADEON_MEM_CNTL, mem_cntl); 2739 } 2740 } 2741 2742 if (!mem_size) { 2743 offset = 2744 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 2745 if (offset) { 2746 rev = RBIOS8(offset - 1); 2747 if (rev < 1) { 2748 if (((rdev->flags & RADEON_FAMILY_MASK) < 2749 CHIP_R200) 2750 && ((dev->pdev->device != 0x515e) 2751 && (dev->pdev->device != 0x5969))) { 2752 int ram = 0; 2753 int mem_addr_mapping = 0; 2754 2755 while (RBIOS8(offset)) { 2756 ram = RBIOS8(offset); 2757 mem_addr_mapping = 2758 RBIOS8(offset + 1); 2759 if (mem_addr_mapping != 0x25) 2760 ram *= 2; 2761 mem_size = 2762 combios_detect_ram(dev, ram, 2763 mem_addr_mapping); 2764 if (mem_size) 2765 break; 2766 offset += 2; 2767 } 2768 } else 2769 mem_size = RBIOS8(offset); 2770 } else { 2771 mem_size = RBIOS8(offset); 2772 mem_size *= 2; /* convert to MB */ 2773 } 2774 } 2775 } 2776 2777 mem_size *= (1024 * 1024); /* convert to bytes */ 2778 WREG32(RADEON_CONFIG_MEMSIZE, mem_size); 2779 } 2780 2781 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable) 2782 { 2783 uint16_t dyn_clk_info = 2784 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); 2785 2786 if (dyn_clk_info) 2787 combios_parse_pll_table(dev, dyn_clk_info); 2788 } 2789 2790 void radeon_combios_asic_init(struct drm_device *dev) 2791 { 2792 struct radeon_device *rdev = dev->dev_private; 2793 uint16_t table; 2794 2795 /* port hardcoded mac stuff from radeonfb */ 2796 if (rdev->bios == NULL) 2797 return; 2798 2799 /* ASIC INIT 1 */ 2800 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE); 2801 if (table) 2802 combios_parse_mmio_table(dev, table); 2803 2804 /* PLL INIT */ 2805 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE); 2806 if (table) 2807 combios_parse_pll_table(dev, table); 2808 2809 /* ASIC INIT 2 */ 2810 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE); 2811 if (table) 2812 combios_parse_mmio_table(dev, table); 2813 2814 if (!(rdev->flags & RADEON_IS_IGP)) { 2815 /* ASIC INIT 4 */ 2816 table = 2817 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE); 2818 if (table) 2819 combios_parse_mmio_table(dev, table); 2820 2821 /* RAM RESET */ 2822 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE); 2823 if (table) 2824 combios_parse_ram_reset_table(dev, table); 2825 2826 /* ASIC INIT 3 */ 2827 table = 2828 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE); 2829 if (table) 2830 combios_parse_mmio_table(dev, table); 2831 2832 /* write CONFIG_MEMSIZE */ 2833 combios_write_ram_size(dev); 2834 } 2835 2836 /* DYN CLK 1 */ 2837 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); 2838 if (table) 2839 combios_parse_pll_table(dev, table); 2840 2841 } 2842 2843 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev) 2844 { 2845 struct radeon_device *rdev = dev->dev_private; 2846 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch; 2847 2848 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 2849 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 2850 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH); 2851 2852 /* let the bios control the backlight */ 2853 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; 2854 2855 /* tell the bios not to handle mode switching */ 2856 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | 2857 RADEON_ACC_MODE_CHANGE); 2858 2859 /* tell the bios a driver is loaded */ 2860 bios_7_scratch |= RADEON_DRV_LOADED; 2861 2862 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 2863 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 2864 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch); 2865 } 2866 2867 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock) 2868 { 2869 struct drm_device *dev = encoder->dev; 2870 struct radeon_device *rdev = dev->dev_private; 2871 uint32_t bios_6_scratch; 2872 2873 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 2874 2875 if (lock) 2876 bios_6_scratch |= RADEON_DRIVER_CRITICAL; 2877 else 2878 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL; 2879 2880 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 2881 } 2882 2883 void 2884 radeon_combios_connected_scratch_regs(struct drm_connector *connector, 2885 struct drm_encoder *encoder, 2886 bool connected) 2887 { 2888 struct drm_device *dev = connector->dev; 2889 struct radeon_device *rdev = dev->dev_private; 2890 struct radeon_connector *radeon_connector = 2891 to_radeon_connector(connector); 2892 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2893 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH); 2894 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 2895 2896 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 2897 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 2898 if (connected) { 2899 DRM_DEBUG("TV1 connected\n"); 2900 /* fix me */ 2901 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; 2902 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ 2903 bios_5_scratch |= RADEON_TV1_ON; 2904 bios_5_scratch |= RADEON_ACC_REQ_TV1; 2905 } else { 2906 DRM_DEBUG("TV1 disconnected\n"); 2907 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; 2908 bios_5_scratch &= ~RADEON_TV1_ON; 2909 bios_5_scratch &= ~RADEON_ACC_REQ_TV1; 2910 } 2911 } 2912 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 2913 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 2914 if (connected) { 2915 DRM_DEBUG("LCD1 connected\n"); 2916 bios_4_scratch |= RADEON_LCD1_ATTACHED; 2917 bios_5_scratch |= RADEON_LCD1_ON; 2918 bios_5_scratch |= RADEON_ACC_REQ_LCD1; 2919 } else { 2920 DRM_DEBUG("LCD1 disconnected\n"); 2921 bios_4_scratch &= ~RADEON_LCD1_ATTACHED; 2922 bios_5_scratch &= ~RADEON_LCD1_ON; 2923 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; 2924 } 2925 } 2926 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 2927 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 2928 if (connected) { 2929 DRM_DEBUG("CRT1 connected\n"); 2930 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; 2931 bios_5_scratch |= RADEON_CRT1_ON; 2932 bios_5_scratch |= RADEON_ACC_REQ_CRT1; 2933 } else { 2934 DRM_DEBUG("CRT1 disconnected\n"); 2935 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; 2936 bios_5_scratch &= ~RADEON_CRT1_ON; 2937 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; 2938 } 2939 } 2940 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 2941 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 2942 if (connected) { 2943 DRM_DEBUG("CRT2 connected\n"); 2944 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; 2945 bios_5_scratch |= RADEON_CRT2_ON; 2946 bios_5_scratch |= RADEON_ACC_REQ_CRT2; 2947 } else { 2948 DRM_DEBUG("CRT2 disconnected\n"); 2949 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; 2950 bios_5_scratch &= ~RADEON_CRT2_ON; 2951 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; 2952 } 2953 } 2954 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 2955 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 2956 if (connected) { 2957 DRM_DEBUG("DFP1 connected\n"); 2958 bios_4_scratch |= RADEON_DFP1_ATTACHED; 2959 bios_5_scratch |= RADEON_DFP1_ON; 2960 bios_5_scratch |= RADEON_ACC_REQ_DFP1; 2961 } else { 2962 DRM_DEBUG("DFP1 disconnected\n"); 2963 bios_4_scratch &= ~RADEON_DFP1_ATTACHED; 2964 bios_5_scratch &= ~RADEON_DFP1_ON; 2965 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; 2966 } 2967 } 2968 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 2969 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 2970 if (connected) { 2971 DRM_DEBUG("DFP2 connected\n"); 2972 bios_4_scratch |= RADEON_DFP2_ATTACHED; 2973 bios_5_scratch |= RADEON_DFP2_ON; 2974 bios_5_scratch |= RADEON_ACC_REQ_DFP2; 2975 } else { 2976 DRM_DEBUG("DFP2 disconnected\n"); 2977 bios_4_scratch &= ~RADEON_DFP2_ATTACHED; 2978 bios_5_scratch &= ~RADEON_DFP2_ON; 2979 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; 2980 } 2981 } 2982 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch); 2983 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 2984 } 2985 2986 void 2987 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 2988 { 2989 struct drm_device *dev = encoder->dev; 2990 struct radeon_device *rdev = dev->dev_private; 2991 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2992 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 2993 2994 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 2995 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK; 2996 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT); 2997 } 2998 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2999 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK; 3000 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT); 3001 } 3002 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 3003 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK; 3004 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT); 3005 } 3006 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 3007 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK; 3008 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT); 3009 } 3010 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 3011 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK; 3012 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT); 3013 } 3014 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 3015 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK; 3016 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT); 3017 } 3018 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3019 } 3020 3021 void 3022 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 3023 { 3024 struct drm_device *dev = encoder->dev; 3025 struct radeon_device *rdev = dev->dev_private; 3026 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3027 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3028 3029 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 3030 if (on) 3031 bios_6_scratch |= RADEON_TV_DPMS_ON; 3032 else 3033 bios_6_scratch &= ~RADEON_TV_DPMS_ON; 3034 } 3035 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3036 if (on) 3037 bios_6_scratch |= RADEON_CRT_DPMS_ON; 3038 else 3039 bios_6_scratch &= ~RADEON_CRT_DPMS_ON; 3040 } 3041 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3042 if (on) 3043 bios_6_scratch |= RADEON_LCD_DPMS_ON; 3044 else 3045 bios_6_scratch &= ~RADEON_LCD_DPMS_ON; 3046 } 3047 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 3048 if (on) 3049 bios_6_scratch |= RADEON_DFP_DPMS_ON; 3050 else 3051 bios_6_scratch &= ~RADEON_DFP_DPMS_ON; 3052 } 3053 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3054 } 3055