1 /* 2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario 3 * Copyright 2007-8 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 */ 27 28 #include <drm/drm_device.h> 29 #include <drm/drm_pci.h> 30 #include <drm/radeon_drm.h> 31 32 #include "radeon.h" 33 #include "atom.h" 34 35 #ifdef CONFIG_PPC_PMAC 36 /* not sure which of these are needed */ 37 #include <asm/machdep.h> 38 #include <asm/pmac_feature.h> 39 #include <asm/prom.h> 40 #endif /* CONFIG_PPC_PMAC */ 41 42 /* from radeon_legacy_encoder.c */ 43 extern void 44 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, 45 uint32_t supported_device); 46 47 /* old legacy ATI BIOS routines */ 48 49 /* COMBIOS table offsets */ 50 enum radeon_combios_table_offset { 51 /* absolute offset tables */ 52 COMBIOS_ASIC_INIT_1_TABLE, 53 COMBIOS_BIOS_SUPPORT_TABLE, 54 COMBIOS_DAC_PROGRAMMING_TABLE, 55 COMBIOS_MAX_COLOR_DEPTH_TABLE, 56 COMBIOS_CRTC_INFO_TABLE, 57 COMBIOS_PLL_INFO_TABLE, 58 COMBIOS_TV_INFO_TABLE, 59 COMBIOS_DFP_INFO_TABLE, 60 COMBIOS_HW_CONFIG_INFO_TABLE, 61 COMBIOS_MULTIMEDIA_INFO_TABLE, 62 COMBIOS_TV_STD_PATCH_TABLE, 63 COMBIOS_LCD_INFO_TABLE, 64 COMBIOS_MOBILE_INFO_TABLE, 65 COMBIOS_PLL_INIT_TABLE, 66 COMBIOS_MEM_CONFIG_TABLE, 67 COMBIOS_SAVE_MASK_TABLE, 68 COMBIOS_HARDCODED_EDID_TABLE, 69 COMBIOS_ASIC_INIT_2_TABLE, 70 COMBIOS_CONNECTOR_INFO_TABLE, 71 COMBIOS_DYN_CLK_1_TABLE, 72 COMBIOS_RESERVED_MEM_TABLE, 73 COMBIOS_EXT_TMDS_INFO_TABLE, 74 COMBIOS_MEM_CLK_INFO_TABLE, 75 COMBIOS_EXT_DAC_INFO_TABLE, 76 COMBIOS_MISC_INFO_TABLE, 77 COMBIOS_CRT_INFO_TABLE, 78 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE, 79 COMBIOS_COMPONENT_VIDEO_INFO_TABLE, 80 COMBIOS_FAN_SPEED_INFO_TABLE, 81 COMBIOS_OVERDRIVE_INFO_TABLE, 82 COMBIOS_OEM_INFO_TABLE, 83 COMBIOS_DYN_CLK_2_TABLE, 84 COMBIOS_POWER_CONNECTOR_INFO_TABLE, 85 COMBIOS_I2C_INFO_TABLE, 86 /* relative offset tables */ 87 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */ 88 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */ 89 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */ 90 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */ 91 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */ 92 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */ 93 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */ 94 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */ 95 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */ 96 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */ 97 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */ 98 }; 99 100 enum radeon_combios_ddc { 101 DDC_NONE_DETECTED, 102 DDC_MONID, 103 DDC_DVI, 104 DDC_VGA, 105 DDC_CRT2, 106 DDC_LCD, 107 DDC_GPIO, 108 }; 109 110 enum radeon_combios_connector { 111 CONNECTOR_NONE_LEGACY, 112 CONNECTOR_PROPRIETARY_LEGACY, 113 CONNECTOR_CRT_LEGACY, 114 CONNECTOR_DVI_I_LEGACY, 115 CONNECTOR_DVI_D_LEGACY, 116 CONNECTOR_CTV_LEGACY, 117 CONNECTOR_STV_LEGACY, 118 CONNECTOR_UNSUPPORTED_LEGACY 119 }; 120 121 static const int legacy_connector_convert[] = { 122 DRM_MODE_CONNECTOR_Unknown, 123 DRM_MODE_CONNECTOR_DVID, 124 DRM_MODE_CONNECTOR_VGA, 125 DRM_MODE_CONNECTOR_DVII, 126 DRM_MODE_CONNECTOR_DVID, 127 DRM_MODE_CONNECTOR_Composite, 128 DRM_MODE_CONNECTOR_SVIDEO, 129 DRM_MODE_CONNECTOR_Unknown, 130 }; 131 132 static uint16_t combios_get_table_offset(struct drm_device *dev, 133 enum radeon_combios_table_offset table) 134 { 135 struct radeon_device *rdev = dev->dev_private; 136 int rev, size; 137 uint16_t offset = 0, check_offset; 138 139 if (!rdev->bios) 140 return 0; 141 142 switch (table) { 143 /* absolute offset tables */ 144 case COMBIOS_ASIC_INIT_1_TABLE: 145 check_offset = 0xc; 146 break; 147 case COMBIOS_BIOS_SUPPORT_TABLE: 148 check_offset = 0x14; 149 break; 150 case COMBIOS_DAC_PROGRAMMING_TABLE: 151 check_offset = 0x2a; 152 break; 153 case COMBIOS_MAX_COLOR_DEPTH_TABLE: 154 check_offset = 0x2c; 155 break; 156 case COMBIOS_CRTC_INFO_TABLE: 157 check_offset = 0x2e; 158 break; 159 case COMBIOS_PLL_INFO_TABLE: 160 check_offset = 0x30; 161 break; 162 case COMBIOS_TV_INFO_TABLE: 163 check_offset = 0x32; 164 break; 165 case COMBIOS_DFP_INFO_TABLE: 166 check_offset = 0x34; 167 break; 168 case COMBIOS_HW_CONFIG_INFO_TABLE: 169 check_offset = 0x36; 170 break; 171 case COMBIOS_MULTIMEDIA_INFO_TABLE: 172 check_offset = 0x38; 173 break; 174 case COMBIOS_TV_STD_PATCH_TABLE: 175 check_offset = 0x3e; 176 break; 177 case COMBIOS_LCD_INFO_TABLE: 178 check_offset = 0x40; 179 break; 180 case COMBIOS_MOBILE_INFO_TABLE: 181 check_offset = 0x42; 182 break; 183 case COMBIOS_PLL_INIT_TABLE: 184 check_offset = 0x46; 185 break; 186 case COMBIOS_MEM_CONFIG_TABLE: 187 check_offset = 0x48; 188 break; 189 case COMBIOS_SAVE_MASK_TABLE: 190 check_offset = 0x4a; 191 break; 192 case COMBIOS_HARDCODED_EDID_TABLE: 193 check_offset = 0x4c; 194 break; 195 case COMBIOS_ASIC_INIT_2_TABLE: 196 check_offset = 0x4e; 197 break; 198 case COMBIOS_CONNECTOR_INFO_TABLE: 199 check_offset = 0x50; 200 break; 201 case COMBIOS_DYN_CLK_1_TABLE: 202 check_offset = 0x52; 203 break; 204 case COMBIOS_RESERVED_MEM_TABLE: 205 check_offset = 0x54; 206 break; 207 case COMBIOS_EXT_TMDS_INFO_TABLE: 208 check_offset = 0x58; 209 break; 210 case COMBIOS_MEM_CLK_INFO_TABLE: 211 check_offset = 0x5a; 212 break; 213 case COMBIOS_EXT_DAC_INFO_TABLE: 214 check_offset = 0x5c; 215 break; 216 case COMBIOS_MISC_INFO_TABLE: 217 check_offset = 0x5e; 218 break; 219 case COMBIOS_CRT_INFO_TABLE: 220 check_offset = 0x60; 221 break; 222 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE: 223 check_offset = 0x62; 224 break; 225 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE: 226 check_offset = 0x64; 227 break; 228 case COMBIOS_FAN_SPEED_INFO_TABLE: 229 check_offset = 0x66; 230 break; 231 case COMBIOS_OVERDRIVE_INFO_TABLE: 232 check_offset = 0x68; 233 break; 234 case COMBIOS_OEM_INFO_TABLE: 235 check_offset = 0x6a; 236 break; 237 case COMBIOS_DYN_CLK_2_TABLE: 238 check_offset = 0x6c; 239 break; 240 case COMBIOS_POWER_CONNECTOR_INFO_TABLE: 241 check_offset = 0x6e; 242 break; 243 case COMBIOS_I2C_INFO_TABLE: 244 check_offset = 0x70; 245 break; 246 /* relative offset tables */ 247 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */ 248 check_offset = 249 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 250 if (check_offset) { 251 rev = RBIOS8(check_offset); 252 if (rev > 0) { 253 check_offset = RBIOS16(check_offset + 0x3); 254 if (check_offset) 255 offset = check_offset; 256 } 257 } 258 break; 259 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */ 260 check_offset = 261 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 262 if (check_offset) { 263 rev = RBIOS8(check_offset); 264 if (rev > 0) { 265 check_offset = RBIOS16(check_offset + 0x5); 266 if (check_offset) 267 offset = check_offset; 268 } 269 } 270 break; 271 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */ 272 check_offset = 273 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 274 if (check_offset) { 275 rev = RBIOS8(check_offset); 276 if (rev > 0) { 277 check_offset = RBIOS16(check_offset + 0x7); 278 if (check_offset) 279 offset = check_offset; 280 } 281 } 282 break; 283 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */ 284 check_offset = 285 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 286 if (check_offset) { 287 rev = RBIOS8(check_offset); 288 if (rev == 2) { 289 check_offset = RBIOS16(check_offset + 0x9); 290 if (check_offset) 291 offset = check_offset; 292 } 293 } 294 break; 295 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */ 296 check_offset = 297 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 298 if (check_offset) { 299 while (RBIOS8(check_offset++)); 300 check_offset += 2; 301 if (check_offset) 302 offset = check_offset; 303 } 304 break; 305 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */ 306 check_offset = 307 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 308 if (check_offset) { 309 check_offset = RBIOS16(check_offset + 0x11); 310 if (check_offset) 311 offset = check_offset; 312 } 313 break; 314 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */ 315 check_offset = 316 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 317 if (check_offset) { 318 check_offset = RBIOS16(check_offset + 0x13); 319 if (check_offset) 320 offset = check_offset; 321 } 322 break; 323 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */ 324 check_offset = 325 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 326 if (check_offset) { 327 check_offset = RBIOS16(check_offset + 0x15); 328 if (check_offset) 329 offset = check_offset; 330 } 331 break; 332 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */ 333 check_offset = 334 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 335 if (check_offset) { 336 check_offset = RBIOS16(check_offset + 0x17); 337 if (check_offset) 338 offset = check_offset; 339 } 340 break; 341 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */ 342 check_offset = 343 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 344 if (check_offset) { 345 check_offset = RBIOS16(check_offset + 0x2); 346 if (check_offset) 347 offset = check_offset; 348 } 349 break; 350 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */ 351 check_offset = 352 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 353 if (check_offset) { 354 check_offset = RBIOS16(check_offset + 0x4); 355 if (check_offset) 356 offset = check_offset; 357 } 358 break; 359 default: 360 check_offset = 0; 361 break; 362 } 363 364 size = RBIOS8(rdev->bios_header_start + 0x6); 365 /* check absolute offset tables */ 366 if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size) 367 offset = RBIOS16(rdev->bios_header_start + check_offset); 368 369 return offset; 370 } 371 372 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev) 373 { 374 int edid_info, size; 375 struct edid *edid; 376 unsigned char *raw; 377 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE); 378 if (!edid_info) 379 return false; 380 381 raw = rdev->bios + edid_info; 382 size = EDID_LENGTH * (raw[0x7e] + 1); 383 edid = kmalloc(size, GFP_KERNEL); 384 if (edid == NULL) 385 return false; 386 387 memcpy((unsigned char *)edid, raw, size); 388 389 if (!drm_edid_is_valid(edid)) { 390 kfree(edid); 391 return false; 392 } 393 394 rdev->mode_info.bios_hardcoded_edid = edid; 395 rdev->mode_info.bios_hardcoded_edid_size = size; 396 return true; 397 } 398 399 /* this is used for atom LCDs as well */ 400 struct edid * 401 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev) 402 { 403 struct edid *edid; 404 405 if (rdev->mode_info.bios_hardcoded_edid) { 406 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 407 if (edid) { 408 memcpy((unsigned char *)edid, 409 (unsigned char *)rdev->mode_info.bios_hardcoded_edid, 410 rdev->mode_info.bios_hardcoded_edid_size); 411 return edid; 412 } 413 } 414 return NULL; 415 } 416 417 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, 418 enum radeon_combios_ddc ddc, 419 u32 clk_mask, 420 u32 data_mask) 421 { 422 struct radeon_i2c_bus_rec i2c; 423 int ddc_line = 0; 424 425 /* ddc id = mask reg 426 * DDC_NONE_DETECTED = none 427 * DDC_DVI = RADEON_GPIO_DVI_DDC 428 * DDC_VGA = RADEON_GPIO_VGA_DDC 429 * DDC_LCD = RADEON_GPIOPAD_MASK 430 * DDC_GPIO = RADEON_MDGPIO_MASK 431 * r1xx 432 * DDC_MONID = RADEON_GPIO_MONID 433 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC 434 * r200 435 * DDC_MONID = RADEON_GPIO_MONID 436 * DDC_CRT2 = RADEON_GPIO_DVI_DDC 437 * r300/r350 438 * DDC_MONID = RADEON_GPIO_DVI_DDC 439 * DDC_CRT2 = RADEON_GPIO_DVI_DDC 440 * rv2xx/rv3xx 441 * DDC_MONID = RADEON_GPIO_MONID 442 * DDC_CRT2 = RADEON_GPIO_MONID 443 * rs3xx/rs4xx 444 * DDC_MONID = RADEON_GPIOPAD_MASK 445 * DDC_CRT2 = RADEON_GPIO_MONID 446 */ 447 switch (ddc) { 448 case DDC_NONE_DETECTED: 449 default: 450 ddc_line = 0; 451 break; 452 case DDC_DVI: 453 ddc_line = RADEON_GPIO_DVI_DDC; 454 break; 455 case DDC_VGA: 456 ddc_line = RADEON_GPIO_VGA_DDC; 457 break; 458 case DDC_LCD: 459 ddc_line = RADEON_GPIOPAD_MASK; 460 break; 461 case DDC_GPIO: 462 ddc_line = RADEON_MDGPIO_MASK; 463 break; 464 case DDC_MONID: 465 if (rdev->family == CHIP_RS300 || 466 rdev->family == CHIP_RS400 || 467 rdev->family == CHIP_RS480) 468 ddc_line = RADEON_GPIOPAD_MASK; 469 else if (rdev->family == CHIP_R300 || 470 rdev->family == CHIP_R350) { 471 ddc_line = RADEON_GPIO_DVI_DDC; 472 ddc = DDC_DVI; 473 } else 474 ddc_line = RADEON_GPIO_MONID; 475 break; 476 case DDC_CRT2: 477 if (rdev->family == CHIP_R200 || 478 rdev->family == CHIP_R300 || 479 rdev->family == CHIP_R350) { 480 ddc_line = RADEON_GPIO_DVI_DDC; 481 ddc = DDC_DVI; 482 } else if (rdev->family == CHIP_RS300 || 483 rdev->family == CHIP_RS400 || 484 rdev->family == CHIP_RS480) 485 ddc_line = RADEON_GPIO_MONID; 486 else if (rdev->family >= CHIP_RV350) { 487 ddc_line = RADEON_GPIO_MONID; 488 ddc = DDC_MONID; 489 } else 490 ddc_line = RADEON_GPIO_CRT2_DDC; 491 break; 492 } 493 494 if (ddc_line == RADEON_GPIOPAD_MASK) { 495 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; 496 i2c.mask_data_reg = RADEON_GPIOPAD_MASK; 497 i2c.a_clk_reg = RADEON_GPIOPAD_A; 498 i2c.a_data_reg = RADEON_GPIOPAD_A; 499 i2c.en_clk_reg = RADEON_GPIOPAD_EN; 500 i2c.en_data_reg = RADEON_GPIOPAD_EN; 501 i2c.y_clk_reg = RADEON_GPIOPAD_Y; 502 i2c.y_data_reg = RADEON_GPIOPAD_Y; 503 } else if (ddc_line == RADEON_MDGPIO_MASK) { 504 i2c.mask_clk_reg = RADEON_MDGPIO_MASK; 505 i2c.mask_data_reg = RADEON_MDGPIO_MASK; 506 i2c.a_clk_reg = RADEON_MDGPIO_A; 507 i2c.a_data_reg = RADEON_MDGPIO_A; 508 i2c.en_clk_reg = RADEON_MDGPIO_EN; 509 i2c.en_data_reg = RADEON_MDGPIO_EN; 510 i2c.y_clk_reg = RADEON_MDGPIO_Y; 511 i2c.y_data_reg = RADEON_MDGPIO_Y; 512 } else { 513 i2c.mask_clk_reg = ddc_line; 514 i2c.mask_data_reg = ddc_line; 515 i2c.a_clk_reg = ddc_line; 516 i2c.a_data_reg = ddc_line; 517 i2c.en_clk_reg = ddc_line; 518 i2c.en_data_reg = ddc_line; 519 i2c.y_clk_reg = ddc_line; 520 i2c.y_data_reg = ddc_line; 521 } 522 523 if (clk_mask && data_mask) { 524 /* system specific masks */ 525 i2c.mask_clk_mask = clk_mask; 526 i2c.mask_data_mask = data_mask; 527 i2c.a_clk_mask = clk_mask; 528 i2c.a_data_mask = data_mask; 529 i2c.en_clk_mask = clk_mask; 530 i2c.en_data_mask = data_mask; 531 i2c.y_clk_mask = clk_mask; 532 i2c.y_data_mask = data_mask; 533 } else if ((ddc_line == RADEON_GPIOPAD_MASK) || 534 (ddc_line == RADEON_MDGPIO_MASK)) { 535 /* default gpiopad masks */ 536 i2c.mask_clk_mask = (0x20 << 8); 537 i2c.mask_data_mask = 0x80; 538 i2c.a_clk_mask = (0x20 << 8); 539 i2c.a_data_mask = 0x80; 540 i2c.en_clk_mask = (0x20 << 8); 541 i2c.en_data_mask = 0x80; 542 i2c.y_clk_mask = (0x20 << 8); 543 i2c.y_data_mask = 0x80; 544 } else { 545 /* default masks for ddc pads */ 546 i2c.mask_clk_mask = RADEON_GPIO_MASK_1; 547 i2c.mask_data_mask = RADEON_GPIO_MASK_0; 548 i2c.a_clk_mask = RADEON_GPIO_A_1; 549 i2c.a_data_mask = RADEON_GPIO_A_0; 550 i2c.en_clk_mask = RADEON_GPIO_EN_1; 551 i2c.en_data_mask = RADEON_GPIO_EN_0; 552 i2c.y_clk_mask = RADEON_GPIO_Y_1; 553 i2c.y_data_mask = RADEON_GPIO_Y_0; 554 } 555 556 switch (rdev->family) { 557 case CHIP_R100: 558 case CHIP_RV100: 559 case CHIP_RS100: 560 case CHIP_RV200: 561 case CHIP_RS200: 562 case CHIP_RS300: 563 switch (ddc_line) { 564 case RADEON_GPIO_DVI_DDC: 565 i2c.hw_capable = true; 566 break; 567 default: 568 i2c.hw_capable = false; 569 break; 570 } 571 break; 572 case CHIP_R200: 573 switch (ddc_line) { 574 case RADEON_GPIO_DVI_DDC: 575 case RADEON_GPIO_MONID: 576 i2c.hw_capable = true; 577 break; 578 default: 579 i2c.hw_capable = false; 580 break; 581 } 582 break; 583 case CHIP_RV250: 584 case CHIP_RV280: 585 switch (ddc_line) { 586 case RADEON_GPIO_VGA_DDC: 587 case RADEON_GPIO_DVI_DDC: 588 case RADEON_GPIO_CRT2_DDC: 589 i2c.hw_capable = true; 590 break; 591 default: 592 i2c.hw_capable = false; 593 break; 594 } 595 break; 596 case CHIP_R300: 597 case CHIP_R350: 598 switch (ddc_line) { 599 case RADEON_GPIO_VGA_DDC: 600 case RADEON_GPIO_DVI_DDC: 601 i2c.hw_capable = true; 602 break; 603 default: 604 i2c.hw_capable = false; 605 break; 606 } 607 break; 608 case CHIP_RV350: 609 case CHIP_RV380: 610 case CHIP_RS400: 611 case CHIP_RS480: 612 switch (ddc_line) { 613 case RADEON_GPIO_VGA_DDC: 614 case RADEON_GPIO_DVI_DDC: 615 i2c.hw_capable = true; 616 break; 617 case RADEON_GPIO_MONID: 618 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work 619 * reliably on some pre-r4xx hardware; not sure why. 620 */ 621 i2c.hw_capable = false; 622 break; 623 default: 624 i2c.hw_capable = false; 625 break; 626 } 627 break; 628 default: 629 i2c.hw_capable = false; 630 break; 631 } 632 i2c.mm_i2c = false; 633 634 i2c.i2c_id = ddc; 635 i2c.hpd = RADEON_HPD_NONE; 636 637 if (ddc_line) 638 i2c.valid = true; 639 else 640 i2c.valid = false; 641 642 return i2c; 643 } 644 645 static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev) 646 { 647 struct drm_device *dev = rdev->ddev; 648 struct radeon_i2c_bus_rec i2c; 649 u16 offset; 650 u8 id, blocks, clk, data; 651 int i; 652 653 i2c.valid = false; 654 655 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); 656 if (offset) { 657 blocks = RBIOS8(offset + 2); 658 for (i = 0; i < blocks; i++) { 659 id = RBIOS8(offset + 3 + (i * 5) + 0); 660 if (id == 136) { 661 clk = RBIOS8(offset + 3 + (i * 5) + 3); 662 data = RBIOS8(offset + 3 + (i * 5) + 4); 663 /* gpiopad */ 664 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 665 (1 << clk), (1 << data)); 666 break; 667 } 668 } 669 } 670 return i2c; 671 } 672 673 void radeon_combios_i2c_init(struct radeon_device *rdev) 674 { 675 struct drm_device *dev = rdev->ddev; 676 struct radeon_i2c_bus_rec i2c; 677 678 /* actual hw pads 679 * r1xx/rs2xx/rs3xx 680 * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm 681 * r200 682 * 0x60, 0x64, 0x68, mm 683 * r300/r350 684 * 0x60, 0x64, mm 685 * rv2xx/rv3xx/rs4xx 686 * 0x60, 0x64, 0x68, gpiopads, mm 687 */ 688 689 /* 0x60 */ 690 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 691 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC"); 692 /* 0x64 */ 693 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 694 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC"); 695 696 /* mm i2c */ 697 i2c.valid = true; 698 i2c.hw_capable = true; 699 i2c.mm_i2c = true; 700 i2c.i2c_id = 0xa0; 701 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C"); 702 703 if (rdev->family == CHIP_R300 || 704 rdev->family == CHIP_R350) { 705 /* only 2 sw i2c pads */ 706 } else if (rdev->family == CHIP_RS300 || 707 rdev->family == CHIP_RS400 || 708 rdev->family == CHIP_RS480) { 709 /* 0x68 */ 710 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 711 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 712 713 /* gpiopad */ 714 i2c = radeon_combios_get_i2c_info_from_table(rdev); 715 if (i2c.valid) 716 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK"); 717 } else if ((rdev->family == CHIP_R200) || 718 (rdev->family >= CHIP_R300)) { 719 /* 0x68 */ 720 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 721 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 722 } else { 723 /* 0x68 */ 724 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 725 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 726 /* 0x6c */ 727 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 728 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC"); 729 } 730 } 731 732 bool radeon_combios_get_clock_info(struct drm_device *dev) 733 { 734 struct radeon_device *rdev = dev->dev_private; 735 uint16_t pll_info; 736 struct radeon_pll *p1pll = &rdev->clock.p1pll; 737 struct radeon_pll *p2pll = &rdev->clock.p2pll; 738 struct radeon_pll *spll = &rdev->clock.spll; 739 struct radeon_pll *mpll = &rdev->clock.mpll; 740 int8_t rev; 741 uint16_t sclk, mclk; 742 743 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); 744 if (pll_info) { 745 rev = RBIOS8(pll_info); 746 747 /* pixel clocks */ 748 p1pll->reference_freq = RBIOS16(pll_info + 0xe); 749 p1pll->reference_div = RBIOS16(pll_info + 0x10); 750 p1pll->pll_out_min = RBIOS32(pll_info + 0x12); 751 p1pll->pll_out_max = RBIOS32(pll_info + 0x16); 752 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 753 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 754 755 if (rev > 9) { 756 p1pll->pll_in_min = RBIOS32(pll_info + 0x36); 757 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); 758 } else { 759 p1pll->pll_in_min = 40; 760 p1pll->pll_in_max = 500; 761 } 762 *p2pll = *p1pll; 763 764 /* system clock */ 765 spll->reference_freq = RBIOS16(pll_info + 0x1a); 766 spll->reference_div = RBIOS16(pll_info + 0x1c); 767 spll->pll_out_min = RBIOS32(pll_info + 0x1e); 768 spll->pll_out_max = RBIOS32(pll_info + 0x22); 769 770 if (rev > 10) { 771 spll->pll_in_min = RBIOS32(pll_info + 0x48); 772 spll->pll_in_max = RBIOS32(pll_info + 0x4c); 773 } else { 774 /* ??? */ 775 spll->pll_in_min = 40; 776 spll->pll_in_max = 500; 777 } 778 779 /* memory clock */ 780 mpll->reference_freq = RBIOS16(pll_info + 0x26); 781 mpll->reference_div = RBIOS16(pll_info + 0x28); 782 mpll->pll_out_min = RBIOS32(pll_info + 0x2a); 783 mpll->pll_out_max = RBIOS32(pll_info + 0x2e); 784 785 if (rev > 10) { 786 mpll->pll_in_min = RBIOS32(pll_info + 0x5a); 787 mpll->pll_in_max = RBIOS32(pll_info + 0x5e); 788 } else { 789 /* ??? */ 790 mpll->pll_in_min = 40; 791 mpll->pll_in_max = 500; 792 } 793 794 /* default sclk/mclk */ 795 sclk = RBIOS16(pll_info + 0xa); 796 mclk = RBIOS16(pll_info + 0x8); 797 if (sclk == 0) 798 sclk = 200 * 100; 799 if (mclk == 0) 800 mclk = 200 * 100; 801 802 rdev->clock.default_sclk = sclk; 803 rdev->clock.default_mclk = mclk; 804 805 if (RBIOS32(pll_info + 0x16)) 806 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16); 807 else 808 rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */ 809 810 return true; 811 } 812 return false; 813 } 814 815 bool radeon_combios_sideport_present(struct radeon_device *rdev) 816 { 817 struct drm_device *dev = rdev->ddev; 818 u16 igp_info; 819 820 /* sideport is AMD only */ 821 if (rdev->family == CHIP_RS400) 822 return false; 823 824 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE); 825 826 if (igp_info) { 827 if (RBIOS16(igp_info + 0x4)) 828 return true; 829 } 830 return false; 831 } 832 833 static const uint32_t default_primarydac_adj[CHIP_LAST] = { 834 0x00000808, /* r100 */ 835 0x00000808, /* rv100 */ 836 0x00000808, /* rs100 */ 837 0x00000808, /* rv200 */ 838 0x00000808, /* rs200 */ 839 0x00000808, /* r200 */ 840 0x00000808, /* rv250 */ 841 0x00000000, /* rs300 */ 842 0x00000808, /* rv280 */ 843 0x00000808, /* r300 */ 844 0x00000808, /* r350 */ 845 0x00000808, /* rv350 */ 846 0x00000808, /* rv380 */ 847 0x00000808, /* r420 */ 848 0x00000808, /* r423 */ 849 0x00000808, /* rv410 */ 850 0x00000000, /* rs400 */ 851 0x00000000, /* rs480 */ 852 }; 853 854 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev, 855 struct radeon_encoder_primary_dac *p_dac) 856 { 857 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family]; 858 return; 859 } 860 861 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct 862 radeon_encoder 863 *encoder) 864 { 865 struct drm_device *dev = encoder->base.dev; 866 struct radeon_device *rdev = dev->dev_private; 867 uint16_t dac_info; 868 uint8_t rev, bg, dac; 869 struct radeon_encoder_primary_dac *p_dac = NULL; 870 int found = 0; 871 872 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), 873 GFP_KERNEL); 874 875 if (!p_dac) 876 return NULL; 877 878 /* check CRT table */ 879 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 880 if (dac_info) { 881 rev = RBIOS8(dac_info) & 0x3; 882 if (rev < 2) { 883 bg = RBIOS8(dac_info + 0x2) & 0xf; 884 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf; 885 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 886 } else { 887 bg = RBIOS8(dac_info + 0x2) & 0xf; 888 dac = RBIOS8(dac_info + 0x3) & 0xf; 889 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 890 } 891 /* if the values are zeros, use the table */ 892 if ((dac == 0) || (bg == 0)) 893 found = 0; 894 else 895 found = 1; 896 } 897 898 /* quirks */ 899 /* Radeon 7000 (RV100) */ 900 if (((dev->pdev->device == 0x5159) && 901 (dev->pdev->subsystem_vendor == 0x174B) && 902 (dev->pdev->subsystem_device == 0x7c28)) || 903 /* Radeon 9100 (R200) */ 904 ((dev->pdev->device == 0x514D) && 905 (dev->pdev->subsystem_vendor == 0x174B) && 906 (dev->pdev->subsystem_device == 0x7149))) { 907 /* vbios value is bad, use the default */ 908 found = 0; 909 } 910 911 if (!found) /* fallback to defaults */ 912 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac); 913 914 return p_dac; 915 } 916 917 enum radeon_tv_std 918 radeon_combios_get_tv_info(struct radeon_device *rdev) 919 { 920 struct drm_device *dev = rdev->ddev; 921 uint16_t tv_info; 922 enum radeon_tv_std tv_std = TV_STD_NTSC; 923 924 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 925 if (tv_info) { 926 if (RBIOS8(tv_info + 6) == 'T') { 927 switch (RBIOS8(tv_info + 7) & 0xf) { 928 case 1: 929 tv_std = TV_STD_NTSC; 930 DRM_DEBUG_KMS("Default TV standard: NTSC\n"); 931 break; 932 case 2: 933 tv_std = TV_STD_PAL; 934 DRM_DEBUG_KMS("Default TV standard: PAL\n"); 935 break; 936 case 3: 937 tv_std = TV_STD_PAL_M; 938 DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); 939 break; 940 case 4: 941 tv_std = TV_STD_PAL_60; 942 DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); 943 break; 944 case 5: 945 tv_std = TV_STD_NTSC_J; 946 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); 947 break; 948 case 6: 949 tv_std = TV_STD_SCART_PAL; 950 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n"); 951 break; 952 default: 953 tv_std = TV_STD_NTSC; 954 DRM_DEBUG_KMS 955 ("Unknown TV standard; defaulting to NTSC\n"); 956 break; 957 } 958 959 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { 960 case 0: 961 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n"); 962 break; 963 case 1: 964 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n"); 965 break; 966 case 2: 967 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n"); 968 break; 969 case 3: 970 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n"); 971 break; 972 default: 973 break; 974 } 975 } 976 } 977 return tv_std; 978 } 979 980 static const uint32_t default_tvdac_adj[CHIP_LAST] = { 981 0x00000000, /* r100 */ 982 0x00280000, /* rv100 */ 983 0x00000000, /* rs100 */ 984 0x00880000, /* rv200 */ 985 0x00000000, /* rs200 */ 986 0x00000000, /* r200 */ 987 0x00770000, /* rv250 */ 988 0x00290000, /* rs300 */ 989 0x00560000, /* rv280 */ 990 0x00780000, /* r300 */ 991 0x00770000, /* r350 */ 992 0x00780000, /* rv350 */ 993 0x00780000, /* rv380 */ 994 0x01080000, /* r420 */ 995 0x01080000, /* r423 */ 996 0x01080000, /* rv410 */ 997 0x00780000, /* rs400 */ 998 0x00780000, /* rs480 */ 999 }; 1000 1001 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev, 1002 struct radeon_encoder_tv_dac *tv_dac) 1003 { 1004 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family]; 1005 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250)) 1006 tv_dac->ps2_tvdac_adj = 0x00880000; 1007 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1008 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1009 return; 1010 } 1011 1012 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct 1013 radeon_encoder 1014 *encoder) 1015 { 1016 struct drm_device *dev = encoder->base.dev; 1017 struct radeon_device *rdev = dev->dev_private; 1018 uint16_t dac_info; 1019 uint8_t rev, bg, dac; 1020 struct radeon_encoder_tv_dac *tv_dac = NULL; 1021 int found = 0; 1022 1023 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 1024 if (!tv_dac) 1025 return NULL; 1026 1027 /* first check TV table */ 1028 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 1029 if (dac_info) { 1030 rev = RBIOS8(dac_info + 0x3); 1031 if (rev > 4) { 1032 bg = RBIOS8(dac_info + 0xc) & 0xf; 1033 dac = RBIOS8(dac_info + 0xd) & 0xf; 1034 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1035 1036 bg = RBIOS8(dac_info + 0xe) & 0xf; 1037 dac = RBIOS8(dac_info + 0xf) & 0xf; 1038 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1039 1040 bg = RBIOS8(dac_info + 0x10) & 0xf; 1041 dac = RBIOS8(dac_info + 0x11) & 0xf; 1042 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1043 /* if the values are all zeros, use the table */ 1044 if (tv_dac->ps2_tvdac_adj) 1045 found = 1; 1046 } else if (rev > 1) { 1047 bg = RBIOS8(dac_info + 0xc) & 0xf; 1048 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf; 1049 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1050 1051 bg = RBIOS8(dac_info + 0xd) & 0xf; 1052 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf; 1053 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1054 1055 bg = RBIOS8(dac_info + 0xe) & 0xf; 1056 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf; 1057 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1058 /* if the values are all zeros, use the table */ 1059 if (tv_dac->ps2_tvdac_adj) 1060 found = 1; 1061 } 1062 tv_dac->tv_std = radeon_combios_get_tv_info(rdev); 1063 } 1064 if (!found) { 1065 /* then check CRT table */ 1066 dac_info = 1067 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 1068 if (dac_info) { 1069 rev = RBIOS8(dac_info) & 0x3; 1070 if (rev < 2) { 1071 bg = RBIOS8(dac_info + 0x3) & 0xf; 1072 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf; 1073 tv_dac->ps2_tvdac_adj = 1074 (bg << 16) | (dac << 20); 1075 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1076 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1077 /* if the values are all zeros, use the table */ 1078 if (tv_dac->ps2_tvdac_adj) 1079 found = 1; 1080 } else { 1081 bg = RBIOS8(dac_info + 0x4) & 0xf; 1082 dac = RBIOS8(dac_info + 0x5) & 0xf; 1083 tv_dac->ps2_tvdac_adj = 1084 (bg << 16) | (dac << 20); 1085 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1086 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1087 /* if the values are all zeros, use the table */ 1088 if (tv_dac->ps2_tvdac_adj) 1089 found = 1; 1090 } 1091 } else { 1092 DRM_INFO("No TV DAC info found in BIOS\n"); 1093 } 1094 } 1095 1096 if (!found) /* fallback to defaults */ 1097 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac); 1098 1099 return tv_dac; 1100 } 1101 1102 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct 1103 radeon_device 1104 *rdev) 1105 { 1106 struct radeon_encoder_lvds *lvds = NULL; 1107 uint32_t fp_vert_stretch, fp_horz_stretch; 1108 uint32_t ppll_div_sel, ppll_val; 1109 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); 1110 1111 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 1112 1113 if (!lvds) 1114 return NULL; 1115 1116 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH); 1117 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH); 1118 1119 /* These should be fail-safe defaults, fingers crossed */ 1120 lvds->panel_pwr_delay = 200; 1121 lvds->panel_vcc_delay = 2000; 1122 1123 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 1124 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; 1125 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; 1126 1127 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) 1128 lvds->native_mode.vdisplay = 1129 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >> 1130 RADEON_VERT_PANEL_SHIFT) + 1; 1131 else 1132 lvds->native_mode.vdisplay = 1133 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1; 1134 1135 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) 1136 lvds->native_mode.hdisplay = 1137 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >> 1138 RADEON_HORZ_PANEL_SHIFT) + 1) * 8; 1139 else 1140 lvds->native_mode.hdisplay = 1141 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8; 1142 1143 if ((lvds->native_mode.hdisplay < 640) || 1144 (lvds->native_mode.vdisplay < 480)) { 1145 lvds->native_mode.hdisplay = 640; 1146 lvds->native_mode.vdisplay = 480; 1147 } 1148 1149 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; 1150 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel); 1151 if ((ppll_val & 0x000707ff) == 0x1bb) 1152 lvds->use_bios_dividers = false; 1153 else { 1154 lvds->panel_ref_divider = 1155 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; 1156 lvds->panel_post_divider = (ppll_val >> 16) & 0x7; 1157 lvds->panel_fb_divider = ppll_val & 0x7ff; 1158 1159 if ((lvds->panel_ref_divider != 0) && 1160 (lvds->panel_fb_divider > 3)) 1161 lvds->use_bios_dividers = true; 1162 } 1163 lvds->panel_vcc_delay = 200; 1164 1165 DRM_INFO("Panel info derived from registers\n"); 1166 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 1167 lvds->native_mode.vdisplay); 1168 1169 return lvds; 1170 } 1171 1172 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder 1173 *encoder) 1174 { 1175 struct drm_device *dev = encoder->base.dev; 1176 struct radeon_device *rdev = dev->dev_private; 1177 uint16_t lcd_info; 1178 uint32_t panel_setup; 1179 char stmp[30]; 1180 int tmp, i; 1181 struct radeon_encoder_lvds *lvds = NULL; 1182 1183 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 1184 1185 if (lcd_info) { 1186 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 1187 1188 if (!lvds) 1189 return NULL; 1190 1191 for (i = 0; i < 24; i++) 1192 stmp[i] = RBIOS8(lcd_info + i + 1); 1193 stmp[24] = 0; 1194 1195 DRM_INFO("Panel ID String: %s\n", stmp); 1196 1197 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19); 1198 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b); 1199 1200 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 1201 lvds->native_mode.vdisplay); 1202 1203 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); 1204 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000); 1205 1206 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24); 1207 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf; 1208 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf; 1209 1210 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e); 1211 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30); 1212 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31); 1213 if ((lvds->panel_ref_divider != 0) && 1214 (lvds->panel_fb_divider > 3)) 1215 lvds->use_bios_dividers = true; 1216 1217 panel_setup = RBIOS32(lcd_info + 0x39); 1218 lvds->lvds_gen_cntl = 0xff00; 1219 if (panel_setup & 0x1) 1220 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT; 1221 1222 if ((panel_setup >> 4) & 0x1) 1223 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE; 1224 1225 switch ((panel_setup >> 8) & 0x7) { 1226 case 0: 1227 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM; 1228 break; 1229 case 1: 1230 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY; 1231 break; 1232 case 2: 1233 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY; 1234 break; 1235 default: 1236 break; 1237 } 1238 1239 if ((panel_setup >> 16) & 0x1) 1240 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW; 1241 1242 if ((panel_setup >> 17) & 0x1) 1243 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW; 1244 1245 if ((panel_setup >> 18) & 0x1) 1246 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW; 1247 1248 if ((panel_setup >> 23) & 0x1) 1249 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL; 1250 1251 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000); 1252 1253 for (i = 0; i < 32; i++) { 1254 tmp = RBIOS16(lcd_info + 64 + i * 2); 1255 if (tmp == 0) 1256 break; 1257 1258 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) && 1259 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) { 1260 u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8; 1261 1262 if (hss > lvds->native_mode.hdisplay) 1263 hss = (10 - 1) * 8; 1264 1265 lvds->native_mode.htotal = lvds->native_mode.hdisplay + 1266 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8; 1267 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + 1268 hss; 1269 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + 1270 (RBIOS8(tmp + 23) * 8); 1271 1272 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + 1273 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26)); 1274 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + 1275 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26)); 1276 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + 1277 ((RBIOS16(tmp + 28) & 0xf800) >> 11); 1278 1279 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10; 1280 lvds->native_mode.flags = 0; 1281 /* set crtc values */ 1282 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1283 1284 } 1285 } 1286 } else { 1287 DRM_INFO("No panel info found in BIOS\n"); 1288 lvds = radeon_legacy_get_lvds_info_from_regs(rdev); 1289 } 1290 1291 if (lvds) 1292 encoder->native_mode = lvds->native_mode; 1293 return lvds; 1294 } 1295 1296 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = { 1297 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */ 1298 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */ 1299 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */ 1300 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */ 1301 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */ 1302 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */ 1303 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */ 1304 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */ 1305 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */ 1306 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */ 1307 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */ 1308 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */ 1309 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */ 1310 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */ 1311 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */ 1312 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */ 1313 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */ 1314 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */ 1315 }; 1316 1317 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 1318 struct radeon_encoder_int_tmds *tmds) 1319 { 1320 struct drm_device *dev = encoder->base.dev; 1321 struct radeon_device *rdev = dev->dev_private; 1322 int i; 1323 1324 for (i = 0; i < 4; i++) { 1325 tmds->tmds_pll[i].value = 1326 default_tmds_pll[rdev->family][i].value; 1327 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; 1328 } 1329 1330 return true; 1331 } 1332 1333 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 1334 struct radeon_encoder_int_tmds *tmds) 1335 { 1336 struct drm_device *dev = encoder->base.dev; 1337 struct radeon_device *rdev = dev->dev_private; 1338 uint16_t tmds_info; 1339 int i, n; 1340 uint8_t ver; 1341 1342 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 1343 1344 if (tmds_info) { 1345 ver = RBIOS8(tmds_info); 1346 DRM_DEBUG_KMS("DFP table revision: %d\n", ver); 1347 if (ver == 3) { 1348 n = RBIOS8(tmds_info + 5) + 1; 1349 if (n > 4) 1350 n = 4; 1351 for (i = 0; i < n; i++) { 1352 tmds->tmds_pll[i].value = 1353 RBIOS32(tmds_info + i * 10 + 0x08); 1354 tmds->tmds_pll[i].freq = 1355 RBIOS16(tmds_info + i * 10 + 0x10); 1356 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", 1357 tmds->tmds_pll[i].freq, 1358 tmds->tmds_pll[i].value); 1359 } 1360 } else if (ver == 4) { 1361 int stride = 0; 1362 n = RBIOS8(tmds_info + 5) + 1; 1363 if (n > 4) 1364 n = 4; 1365 for (i = 0; i < n; i++) { 1366 tmds->tmds_pll[i].value = 1367 RBIOS32(tmds_info + stride + 0x08); 1368 tmds->tmds_pll[i].freq = 1369 RBIOS16(tmds_info + stride + 0x10); 1370 if (i == 0) 1371 stride += 10; 1372 else 1373 stride += 6; 1374 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", 1375 tmds->tmds_pll[i].freq, 1376 tmds->tmds_pll[i].value); 1377 } 1378 } 1379 } else { 1380 DRM_INFO("No TMDS info found in BIOS\n"); 1381 return false; 1382 } 1383 return true; 1384 } 1385 1386 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 1387 struct radeon_encoder_ext_tmds *tmds) 1388 { 1389 struct drm_device *dev = encoder->base.dev; 1390 struct radeon_device *rdev = dev->dev_private; 1391 struct radeon_i2c_bus_rec i2c_bus; 1392 1393 /* default for macs */ 1394 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1395 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1396 1397 /* XXX some macs have duallink chips */ 1398 switch (rdev->mode_info.connector_table) { 1399 case CT_POWERBOOK_EXTERNAL: 1400 case CT_MINI_EXTERNAL: 1401 default: 1402 tmds->dvo_chip = DVO_SIL164; 1403 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1404 break; 1405 } 1406 1407 return true; 1408 } 1409 1410 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 1411 struct radeon_encoder_ext_tmds *tmds) 1412 { 1413 struct drm_device *dev = encoder->base.dev; 1414 struct radeon_device *rdev = dev->dev_private; 1415 uint16_t offset; 1416 uint8_t ver; 1417 enum radeon_combios_ddc gpio; 1418 struct radeon_i2c_bus_rec i2c_bus; 1419 1420 tmds->i2c_bus = NULL; 1421 if (rdev->flags & RADEON_IS_IGP) { 1422 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1423 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1424 tmds->dvo_chip = DVO_SIL164; 1425 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1426 } else { 1427 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1428 if (offset) { 1429 ver = RBIOS8(offset); 1430 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver); 1431 tmds->slave_addr = RBIOS8(offset + 4 + 2); 1432 tmds->slave_addr >>= 1; /* 7 bit addressing */ 1433 gpio = RBIOS8(offset + 4 + 3); 1434 if (gpio == DDC_LCD) { 1435 /* MM i2c */ 1436 i2c_bus.valid = true; 1437 i2c_bus.hw_capable = true; 1438 i2c_bus.mm_i2c = true; 1439 i2c_bus.i2c_id = 0xa0; 1440 } else 1441 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); 1442 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1443 } 1444 } 1445 1446 if (!tmds->i2c_bus) { 1447 DRM_INFO("No valid Ext TMDS info found in BIOS\n"); 1448 return false; 1449 } 1450 1451 return true; 1452 } 1453 1454 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) 1455 { 1456 struct radeon_device *rdev = dev->dev_private; 1457 struct radeon_i2c_bus_rec ddc_i2c; 1458 struct radeon_hpd hpd; 1459 1460 rdev->mode_info.connector_table = radeon_connector_table; 1461 if (rdev->mode_info.connector_table == CT_NONE) { 1462 #ifdef CONFIG_PPC_PMAC 1463 if (of_machine_is_compatible("PowerBook3,3")) { 1464 /* powerbook with VGA */ 1465 rdev->mode_info.connector_table = CT_POWERBOOK_VGA; 1466 } else if (of_machine_is_compatible("PowerBook3,4") || 1467 of_machine_is_compatible("PowerBook3,5")) { 1468 /* powerbook with internal tmds */ 1469 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL; 1470 } else if (of_machine_is_compatible("PowerBook5,1") || 1471 of_machine_is_compatible("PowerBook5,2") || 1472 of_machine_is_compatible("PowerBook5,3") || 1473 of_machine_is_compatible("PowerBook5,4") || 1474 of_machine_is_compatible("PowerBook5,5")) { 1475 /* powerbook with external single link tmds (sil164) */ 1476 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1477 } else if (of_machine_is_compatible("PowerBook5,6")) { 1478 /* powerbook with external dual or single link tmds */ 1479 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1480 } else if (of_machine_is_compatible("PowerBook5,7") || 1481 of_machine_is_compatible("PowerBook5,8") || 1482 of_machine_is_compatible("PowerBook5,9")) { 1483 /* PowerBook6,2 ? */ 1484 /* powerbook with external dual link tmds (sil1178?) */ 1485 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1486 } else if (of_machine_is_compatible("PowerBook4,1") || 1487 of_machine_is_compatible("PowerBook4,2") || 1488 of_machine_is_compatible("PowerBook4,3") || 1489 of_machine_is_compatible("PowerBook6,3") || 1490 of_machine_is_compatible("PowerBook6,5") || 1491 of_machine_is_compatible("PowerBook6,7")) { 1492 /* ibook */ 1493 rdev->mode_info.connector_table = CT_IBOOK; 1494 } else if (of_machine_is_compatible("PowerMac3,5")) { 1495 /* PowerMac G4 Silver radeon 7500 */ 1496 rdev->mode_info.connector_table = CT_MAC_G4_SILVER; 1497 } else if (of_machine_is_compatible("PowerMac4,4")) { 1498 /* emac */ 1499 rdev->mode_info.connector_table = CT_EMAC; 1500 } else if (of_machine_is_compatible("PowerMac10,1")) { 1501 /* mini with internal tmds */ 1502 rdev->mode_info.connector_table = CT_MINI_INTERNAL; 1503 } else if (of_machine_is_compatible("PowerMac10,2")) { 1504 /* mini with external tmds */ 1505 rdev->mode_info.connector_table = CT_MINI_EXTERNAL; 1506 } else if (of_machine_is_compatible("PowerMac12,1")) { 1507 /* PowerMac8,1 ? */ 1508 /* imac g5 isight */ 1509 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; 1510 } else if ((rdev->pdev->device == 0x4a48) && 1511 (rdev->pdev->subsystem_vendor == 0x1002) && 1512 (rdev->pdev->subsystem_device == 0x4a48)) { 1513 /* Mac X800 */ 1514 rdev->mode_info.connector_table = CT_MAC_X800; 1515 } else if ((of_machine_is_compatible("PowerMac7,2") || 1516 of_machine_is_compatible("PowerMac7,3")) && 1517 (rdev->pdev->device == 0x4150) && 1518 (rdev->pdev->subsystem_vendor == 0x1002) && 1519 (rdev->pdev->subsystem_device == 0x4150)) { 1520 /* Mac G5 tower 9600 */ 1521 rdev->mode_info.connector_table = CT_MAC_G5_9600; 1522 } else if ((rdev->pdev->device == 0x4c66) && 1523 (rdev->pdev->subsystem_vendor == 0x1002) && 1524 (rdev->pdev->subsystem_device == 0x4c66)) { 1525 /* SAM440ep RV250 embedded board */ 1526 rdev->mode_info.connector_table = CT_SAM440EP; 1527 } else 1528 #endif /* CONFIG_PPC_PMAC */ 1529 #ifdef CONFIG_PPC64 1530 if (ASIC_IS_RN50(rdev)) 1531 rdev->mode_info.connector_table = CT_RN50_POWER; 1532 else 1533 #endif 1534 rdev->mode_info.connector_table = CT_GENERIC; 1535 } 1536 1537 switch (rdev->mode_info.connector_table) { 1538 case CT_GENERIC: 1539 DRM_INFO("Connector Table: %d (generic)\n", 1540 rdev->mode_info.connector_table); 1541 /* these are the most common settings */ 1542 if (rdev->flags & RADEON_SINGLE_CRTC) { 1543 /* VGA - primary dac */ 1544 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1545 hpd.hpd = RADEON_HPD_NONE; 1546 radeon_add_legacy_encoder(dev, 1547 radeon_get_encoder_enum(dev, 1548 ATOM_DEVICE_CRT1_SUPPORT, 1549 1), 1550 ATOM_DEVICE_CRT1_SUPPORT); 1551 radeon_add_legacy_connector(dev, 0, 1552 ATOM_DEVICE_CRT1_SUPPORT, 1553 DRM_MODE_CONNECTOR_VGA, 1554 &ddc_i2c, 1555 CONNECTOR_OBJECT_ID_VGA, 1556 &hpd); 1557 } else if (rdev->flags & RADEON_IS_MOBILITY) { 1558 /* LVDS */ 1559 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); 1560 hpd.hpd = RADEON_HPD_NONE; 1561 radeon_add_legacy_encoder(dev, 1562 radeon_get_encoder_enum(dev, 1563 ATOM_DEVICE_LCD1_SUPPORT, 1564 0), 1565 ATOM_DEVICE_LCD1_SUPPORT); 1566 radeon_add_legacy_connector(dev, 0, 1567 ATOM_DEVICE_LCD1_SUPPORT, 1568 DRM_MODE_CONNECTOR_LVDS, 1569 &ddc_i2c, 1570 CONNECTOR_OBJECT_ID_LVDS, 1571 &hpd); 1572 1573 /* VGA - primary dac */ 1574 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1575 hpd.hpd = RADEON_HPD_NONE; 1576 radeon_add_legacy_encoder(dev, 1577 radeon_get_encoder_enum(dev, 1578 ATOM_DEVICE_CRT1_SUPPORT, 1579 1), 1580 ATOM_DEVICE_CRT1_SUPPORT); 1581 radeon_add_legacy_connector(dev, 1, 1582 ATOM_DEVICE_CRT1_SUPPORT, 1583 DRM_MODE_CONNECTOR_VGA, 1584 &ddc_i2c, 1585 CONNECTOR_OBJECT_ID_VGA, 1586 &hpd); 1587 } else { 1588 /* DVI-I - tv dac, int tmds */ 1589 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1590 hpd.hpd = RADEON_HPD_1; 1591 radeon_add_legacy_encoder(dev, 1592 radeon_get_encoder_enum(dev, 1593 ATOM_DEVICE_DFP1_SUPPORT, 1594 0), 1595 ATOM_DEVICE_DFP1_SUPPORT); 1596 radeon_add_legacy_encoder(dev, 1597 radeon_get_encoder_enum(dev, 1598 ATOM_DEVICE_CRT2_SUPPORT, 1599 2), 1600 ATOM_DEVICE_CRT2_SUPPORT); 1601 radeon_add_legacy_connector(dev, 0, 1602 ATOM_DEVICE_DFP1_SUPPORT | 1603 ATOM_DEVICE_CRT2_SUPPORT, 1604 DRM_MODE_CONNECTOR_DVII, 1605 &ddc_i2c, 1606 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1607 &hpd); 1608 1609 /* VGA - primary dac */ 1610 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1611 hpd.hpd = RADEON_HPD_NONE; 1612 radeon_add_legacy_encoder(dev, 1613 radeon_get_encoder_enum(dev, 1614 ATOM_DEVICE_CRT1_SUPPORT, 1615 1), 1616 ATOM_DEVICE_CRT1_SUPPORT); 1617 radeon_add_legacy_connector(dev, 1, 1618 ATOM_DEVICE_CRT1_SUPPORT, 1619 DRM_MODE_CONNECTOR_VGA, 1620 &ddc_i2c, 1621 CONNECTOR_OBJECT_ID_VGA, 1622 &hpd); 1623 } 1624 1625 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 1626 /* TV - tv dac */ 1627 ddc_i2c.valid = false; 1628 hpd.hpd = RADEON_HPD_NONE; 1629 radeon_add_legacy_encoder(dev, 1630 radeon_get_encoder_enum(dev, 1631 ATOM_DEVICE_TV1_SUPPORT, 1632 2), 1633 ATOM_DEVICE_TV1_SUPPORT); 1634 radeon_add_legacy_connector(dev, 2, 1635 ATOM_DEVICE_TV1_SUPPORT, 1636 DRM_MODE_CONNECTOR_SVIDEO, 1637 &ddc_i2c, 1638 CONNECTOR_OBJECT_ID_SVIDEO, 1639 &hpd); 1640 } 1641 break; 1642 case CT_IBOOK: 1643 DRM_INFO("Connector Table: %d (ibook)\n", 1644 rdev->mode_info.connector_table); 1645 /* LVDS */ 1646 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1647 hpd.hpd = RADEON_HPD_NONE; 1648 radeon_add_legacy_encoder(dev, 1649 radeon_get_encoder_enum(dev, 1650 ATOM_DEVICE_LCD1_SUPPORT, 1651 0), 1652 ATOM_DEVICE_LCD1_SUPPORT); 1653 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1654 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1655 CONNECTOR_OBJECT_ID_LVDS, 1656 &hpd); 1657 /* VGA - TV DAC */ 1658 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1659 hpd.hpd = RADEON_HPD_NONE; 1660 radeon_add_legacy_encoder(dev, 1661 radeon_get_encoder_enum(dev, 1662 ATOM_DEVICE_CRT2_SUPPORT, 1663 2), 1664 ATOM_DEVICE_CRT2_SUPPORT); 1665 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1666 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1667 CONNECTOR_OBJECT_ID_VGA, 1668 &hpd); 1669 /* TV - TV DAC */ 1670 ddc_i2c.valid = false; 1671 hpd.hpd = RADEON_HPD_NONE; 1672 radeon_add_legacy_encoder(dev, 1673 radeon_get_encoder_enum(dev, 1674 ATOM_DEVICE_TV1_SUPPORT, 1675 2), 1676 ATOM_DEVICE_TV1_SUPPORT); 1677 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1678 DRM_MODE_CONNECTOR_SVIDEO, 1679 &ddc_i2c, 1680 CONNECTOR_OBJECT_ID_SVIDEO, 1681 &hpd); 1682 break; 1683 case CT_POWERBOOK_EXTERNAL: 1684 DRM_INFO("Connector Table: %d (powerbook external tmds)\n", 1685 rdev->mode_info.connector_table); 1686 /* LVDS */ 1687 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1688 hpd.hpd = RADEON_HPD_NONE; 1689 radeon_add_legacy_encoder(dev, 1690 radeon_get_encoder_enum(dev, 1691 ATOM_DEVICE_LCD1_SUPPORT, 1692 0), 1693 ATOM_DEVICE_LCD1_SUPPORT); 1694 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1695 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1696 CONNECTOR_OBJECT_ID_LVDS, 1697 &hpd); 1698 /* DVI-I - primary dac, ext tmds */ 1699 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1700 hpd.hpd = RADEON_HPD_2; /* ??? */ 1701 radeon_add_legacy_encoder(dev, 1702 radeon_get_encoder_enum(dev, 1703 ATOM_DEVICE_DFP2_SUPPORT, 1704 0), 1705 ATOM_DEVICE_DFP2_SUPPORT); 1706 radeon_add_legacy_encoder(dev, 1707 radeon_get_encoder_enum(dev, 1708 ATOM_DEVICE_CRT1_SUPPORT, 1709 1), 1710 ATOM_DEVICE_CRT1_SUPPORT); 1711 /* XXX some are SL */ 1712 radeon_add_legacy_connector(dev, 1, 1713 ATOM_DEVICE_DFP2_SUPPORT | 1714 ATOM_DEVICE_CRT1_SUPPORT, 1715 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1716 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 1717 &hpd); 1718 /* TV - TV DAC */ 1719 ddc_i2c.valid = false; 1720 hpd.hpd = RADEON_HPD_NONE; 1721 radeon_add_legacy_encoder(dev, 1722 radeon_get_encoder_enum(dev, 1723 ATOM_DEVICE_TV1_SUPPORT, 1724 2), 1725 ATOM_DEVICE_TV1_SUPPORT); 1726 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1727 DRM_MODE_CONNECTOR_SVIDEO, 1728 &ddc_i2c, 1729 CONNECTOR_OBJECT_ID_SVIDEO, 1730 &hpd); 1731 break; 1732 case CT_POWERBOOK_INTERNAL: 1733 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", 1734 rdev->mode_info.connector_table); 1735 /* LVDS */ 1736 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1737 hpd.hpd = RADEON_HPD_NONE; 1738 radeon_add_legacy_encoder(dev, 1739 radeon_get_encoder_enum(dev, 1740 ATOM_DEVICE_LCD1_SUPPORT, 1741 0), 1742 ATOM_DEVICE_LCD1_SUPPORT); 1743 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1744 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1745 CONNECTOR_OBJECT_ID_LVDS, 1746 &hpd); 1747 /* DVI-I - primary dac, int tmds */ 1748 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1749 hpd.hpd = RADEON_HPD_1; /* ??? */ 1750 radeon_add_legacy_encoder(dev, 1751 radeon_get_encoder_enum(dev, 1752 ATOM_DEVICE_DFP1_SUPPORT, 1753 0), 1754 ATOM_DEVICE_DFP1_SUPPORT); 1755 radeon_add_legacy_encoder(dev, 1756 radeon_get_encoder_enum(dev, 1757 ATOM_DEVICE_CRT1_SUPPORT, 1758 1), 1759 ATOM_DEVICE_CRT1_SUPPORT); 1760 radeon_add_legacy_connector(dev, 1, 1761 ATOM_DEVICE_DFP1_SUPPORT | 1762 ATOM_DEVICE_CRT1_SUPPORT, 1763 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1764 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1765 &hpd); 1766 /* TV - TV DAC */ 1767 ddc_i2c.valid = false; 1768 hpd.hpd = RADEON_HPD_NONE; 1769 radeon_add_legacy_encoder(dev, 1770 radeon_get_encoder_enum(dev, 1771 ATOM_DEVICE_TV1_SUPPORT, 1772 2), 1773 ATOM_DEVICE_TV1_SUPPORT); 1774 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1775 DRM_MODE_CONNECTOR_SVIDEO, 1776 &ddc_i2c, 1777 CONNECTOR_OBJECT_ID_SVIDEO, 1778 &hpd); 1779 break; 1780 case CT_POWERBOOK_VGA: 1781 DRM_INFO("Connector Table: %d (powerbook vga)\n", 1782 rdev->mode_info.connector_table); 1783 /* LVDS */ 1784 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1785 hpd.hpd = RADEON_HPD_NONE; 1786 radeon_add_legacy_encoder(dev, 1787 radeon_get_encoder_enum(dev, 1788 ATOM_DEVICE_LCD1_SUPPORT, 1789 0), 1790 ATOM_DEVICE_LCD1_SUPPORT); 1791 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1792 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1793 CONNECTOR_OBJECT_ID_LVDS, 1794 &hpd); 1795 /* VGA - primary dac */ 1796 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1797 hpd.hpd = RADEON_HPD_NONE; 1798 radeon_add_legacy_encoder(dev, 1799 radeon_get_encoder_enum(dev, 1800 ATOM_DEVICE_CRT1_SUPPORT, 1801 1), 1802 ATOM_DEVICE_CRT1_SUPPORT); 1803 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 1804 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1805 CONNECTOR_OBJECT_ID_VGA, 1806 &hpd); 1807 /* TV - TV DAC */ 1808 ddc_i2c.valid = false; 1809 hpd.hpd = RADEON_HPD_NONE; 1810 radeon_add_legacy_encoder(dev, 1811 radeon_get_encoder_enum(dev, 1812 ATOM_DEVICE_TV1_SUPPORT, 1813 2), 1814 ATOM_DEVICE_TV1_SUPPORT); 1815 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1816 DRM_MODE_CONNECTOR_SVIDEO, 1817 &ddc_i2c, 1818 CONNECTOR_OBJECT_ID_SVIDEO, 1819 &hpd); 1820 break; 1821 case CT_MINI_EXTERNAL: 1822 DRM_INFO("Connector Table: %d (mini external tmds)\n", 1823 rdev->mode_info.connector_table); 1824 /* DVI-I - tv dac, ext tmds */ 1825 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1826 hpd.hpd = RADEON_HPD_2; /* ??? */ 1827 radeon_add_legacy_encoder(dev, 1828 radeon_get_encoder_enum(dev, 1829 ATOM_DEVICE_DFP2_SUPPORT, 1830 0), 1831 ATOM_DEVICE_DFP2_SUPPORT); 1832 radeon_add_legacy_encoder(dev, 1833 radeon_get_encoder_enum(dev, 1834 ATOM_DEVICE_CRT2_SUPPORT, 1835 2), 1836 ATOM_DEVICE_CRT2_SUPPORT); 1837 /* XXX are any DL? */ 1838 radeon_add_legacy_connector(dev, 0, 1839 ATOM_DEVICE_DFP2_SUPPORT | 1840 ATOM_DEVICE_CRT2_SUPPORT, 1841 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1842 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1843 &hpd); 1844 /* TV - TV DAC */ 1845 ddc_i2c.valid = false; 1846 hpd.hpd = RADEON_HPD_NONE; 1847 radeon_add_legacy_encoder(dev, 1848 radeon_get_encoder_enum(dev, 1849 ATOM_DEVICE_TV1_SUPPORT, 1850 2), 1851 ATOM_DEVICE_TV1_SUPPORT); 1852 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1853 DRM_MODE_CONNECTOR_SVIDEO, 1854 &ddc_i2c, 1855 CONNECTOR_OBJECT_ID_SVIDEO, 1856 &hpd); 1857 break; 1858 case CT_MINI_INTERNAL: 1859 DRM_INFO("Connector Table: %d (mini internal tmds)\n", 1860 rdev->mode_info.connector_table); 1861 /* DVI-I - tv dac, int tmds */ 1862 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1863 hpd.hpd = RADEON_HPD_1; /* ??? */ 1864 radeon_add_legacy_encoder(dev, 1865 radeon_get_encoder_enum(dev, 1866 ATOM_DEVICE_DFP1_SUPPORT, 1867 0), 1868 ATOM_DEVICE_DFP1_SUPPORT); 1869 radeon_add_legacy_encoder(dev, 1870 radeon_get_encoder_enum(dev, 1871 ATOM_DEVICE_CRT2_SUPPORT, 1872 2), 1873 ATOM_DEVICE_CRT2_SUPPORT); 1874 radeon_add_legacy_connector(dev, 0, 1875 ATOM_DEVICE_DFP1_SUPPORT | 1876 ATOM_DEVICE_CRT2_SUPPORT, 1877 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1878 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1879 &hpd); 1880 /* TV - TV DAC */ 1881 ddc_i2c.valid = false; 1882 hpd.hpd = RADEON_HPD_NONE; 1883 radeon_add_legacy_encoder(dev, 1884 radeon_get_encoder_enum(dev, 1885 ATOM_DEVICE_TV1_SUPPORT, 1886 2), 1887 ATOM_DEVICE_TV1_SUPPORT); 1888 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1889 DRM_MODE_CONNECTOR_SVIDEO, 1890 &ddc_i2c, 1891 CONNECTOR_OBJECT_ID_SVIDEO, 1892 &hpd); 1893 break; 1894 case CT_IMAC_G5_ISIGHT: 1895 DRM_INFO("Connector Table: %d (imac g5 isight)\n", 1896 rdev->mode_info.connector_table); 1897 /* DVI-D - int tmds */ 1898 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1899 hpd.hpd = RADEON_HPD_1; /* ??? */ 1900 radeon_add_legacy_encoder(dev, 1901 radeon_get_encoder_enum(dev, 1902 ATOM_DEVICE_DFP1_SUPPORT, 1903 0), 1904 ATOM_DEVICE_DFP1_SUPPORT); 1905 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT, 1906 DRM_MODE_CONNECTOR_DVID, &ddc_i2c, 1907 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 1908 &hpd); 1909 /* VGA - tv dac */ 1910 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1911 hpd.hpd = RADEON_HPD_NONE; 1912 radeon_add_legacy_encoder(dev, 1913 radeon_get_encoder_enum(dev, 1914 ATOM_DEVICE_CRT2_SUPPORT, 1915 2), 1916 ATOM_DEVICE_CRT2_SUPPORT); 1917 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1918 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1919 CONNECTOR_OBJECT_ID_VGA, 1920 &hpd); 1921 /* TV - TV DAC */ 1922 ddc_i2c.valid = false; 1923 hpd.hpd = RADEON_HPD_NONE; 1924 radeon_add_legacy_encoder(dev, 1925 radeon_get_encoder_enum(dev, 1926 ATOM_DEVICE_TV1_SUPPORT, 1927 2), 1928 ATOM_DEVICE_TV1_SUPPORT); 1929 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1930 DRM_MODE_CONNECTOR_SVIDEO, 1931 &ddc_i2c, 1932 CONNECTOR_OBJECT_ID_SVIDEO, 1933 &hpd); 1934 break; 1935 case CT_EMAC: 1936 DRM_INFO("Connector Table: %d (emac)\n", 1937 rdev->mode_info.connector_table); 1938 /* VGA - primary dac */ 1939 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1940 hpd.hpd = RADEON_HPD_NONE; 1941 radeon_add_legacy_encoder(dev, 1942 radeon_get_encoder_enum(dev, 1943 ATOM_DEVICE_CRT1_SUPPORT, 1944 1), 1945 ATOM_DEVICE_CRT1_SUPPORT); 1946 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1947 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1948 CONNECTOR_OBJECT_ID_VGA, 1949 &hpd); 1950 /* VGA - tv dac */ 1951 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1952 hpd.hpd = RADEON_HPD_NONE; 1953 radeon_add_legacy_encoder(dev, 1954 radeon_get_encoder_enum(dev, 1955 ATOM_DEVICE_CRT2_SUPPORT, 1956 2), 1957 ATOM_DEVICE_CRT2_SUPPORT); 1958 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1959 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1960 CONNECTOR_OBJECT_ID_VGA, 1961 &hpd); 1962 /* TV - TV DAC */ 1963 ddc_i2c.valid = false; 1964 hpd.hpd = RADEON_HPD_NONE; 1965 radeon_add_legacy_encoder(dev, 1966 radeon_get_encoder_enum(dev, 1967 ATOM_DEVICE_TV1_SUPPORT, 1968 2), 1969 ATOM_DEVICE_TV1_SUPPORT); 1970 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1971 DRM_MODE_CONNECTOR_SVIDEO, 1972 &ddc_i2c, 1973 CONNECTOR_OBJECT_ID_SVIDEO, 1974 &hpd); 1975 break; 1976 case CT_RN50_POWER: 1977 DRM_INFO("Connector Table: %d (rn50-power)\n", 1978 rdev->mode_info.connector_table); 1979 /* VGA - primary dac */ 1980 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1981 hpd.hpd = RADEON_HPD_NONE; 1982 radeon_add_legacy_encoder(dev, 1983 radeon_get_encoder_enum(dev, 1984 ATOM_DEVICE_CRT1_SUPPORT, 1985 1), 1986 ATOM_DEVICE_CRT1_SUPPORT); 1987 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1988 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1989 CONNECTOR_OBJECT_ID_VGA, 1990 &hpd); 1991 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1992 hpd.hpd = RADEON_HPD_NONE; 1993 radeon_add_legacy_encoder(dev, 1994 radeon_get_encoder_enum(dev, 1995 ATOM_DEVICE_CRT2_SUPPORT, 1996 2), 1997 ATOM_DEVICE_CRT2_SUPPORT); 1998 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1999 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2000 CONNECTOR_OBJECT_ID_VGA, 2001 &hpd); 2002 break; 2003 case CT_MAC_X800: 2004 DRM_INFO("Connector Table: %d (mac x800)\n", 2005 rdev->mode_info.connector_table); 2006 /* DVI - primary dac, internal tmds */ 2007 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2008 hpd.hpd = RADEON_HPD_1; /* ??? */ 2009 radeon_add_legacy_encoder(dev, 2010 radeon_get_encoder_enum(dev, 2011 ATOM_DEVICE_DFP1_SUPPORT, 2012 0), 2013 ATOM_DEVICE_DFP1_SUPPORT); 2014 radeon_add_legacy_encoder(dev, 2015 radeon_get_encoder_enum(dev, 2016 ATOM_DEVICE_CRT1_SUPPORT, 2017 1), 2018 ATOM_DEVICE_CRT1_SUPPORT); 2019 radeon_add_legacy_connector(dev, 0, 2020 ATOM_DEVICE_DFP1_SUPPORT | 2021 ATOM_DEVICE_CRT1_SUPPORT, 2022 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2023 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2024 &hpd); 2025 /* DVI - tv dac, dvo */ 2026 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 2027 hpd.hpd = RADEON_HPD_2; /* ??? */ 2028 radeon_add_legacy_encoder(dev, 2029 radeon_get_encoder_enum(dev, 2030 ATOM_DEVICE_DFP2_SUPPORT, 2031 0), 2032 ATOM_DEVICE_DFP2_SUPPORT); 2033 radeon_add_legacy_encoder(dev, 2034 radeon_get_encoder_enum(dev, 2035 ATOM_DEVICE_CRT2_SUPPORT, 2036 2), 2037 ATOM_DEVICE_CRT2_SUPPORT); 2038 radeon_add_legacy_connector(dev, 1, 2039 ATOM_DEVICE_DFP2_SUPPORT | 2040 ATOM_DEVICE_CRT2_SUPPORT, 2041 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2042 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 2043 &hpd); 2044 break; 2045 case CT_MAC_G5_9600: 2046 DRM_INFO("Connector Table: %d (mac g5 9600)\n", 2047 rdev->mode_info.connector_table); 2048 /* DVI - tv dac, dvo */ 2049 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2050 hpd.hpd = RADEON_HPD_1; /* ??? */ 2051 radeon_add_legacy_encoder(dev, 2052 radeon_get_encoder_enum(dev, 2053 ATOM_DEVICE_DFP2_SUPPORT, 2054 0), 2055 ATOM_DEVICE_DFP2_SUPPORT); 2056 radeon_add_legacy_encoder(dev, 2057 radeon_get_encoder_enum(dev, 2058 ATOM_DEVICE_CRT2_SUPPORT, 2059 2), 2060 ATOM_DEVICE_CRT2_SUPPORT); 2061 radeon_add_legacy_connector(dev, 0, 2062 ATOM_DEVICE_DFP2_SUPPORT | 2063 ATOM_DEVICE_CRT2_SUPPORT, 2064 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2065 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2066 &hpd); 2067 /* ADC - primary dac, internal tmds */ 2068 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2069 hpd.hpd = RADEON_HPD_2; /* ??? */ 2070 radeon_add_legacy_encoder(dev, 2071 radeon_get_encoder_enum(dev, 2072 ATOM_DEVICE_DFP1_SUPPORT, 2073 0), 2074 ATOM_DEVICE_DFP1_SUPPORT); 2075 radeon_add_legacy_encoder(dev, 2076 radeon_get_encoder_enum(dev, 2077 ATOM_DEVICE_CRT1_SUPPORT, 2078 1), 2079 ATOM_DEVICE_CRT1_SUPPORT); 2080 radeon_add_legacy_connector(dev, 1, 2081 ATOM_DEVICE_DFP1_SUPPORT | 2082 ATOM_DEVICE_CRT1_SUPPORT, 2083 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2084 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2085 &hpd); 2086 /* TV - TV DAC */ 2087 ddc_i2c.valid = false; 2088 hpd.hpd = RADEON_HPD_NONE; 2089 radeon_add_legacy_encoder(dev, 2090 radeon_get_encoder_enum(dev, 2091 ATOM_DEVICE_TV1_SUPPORT, 2092 2), 2093 ATOM_DEVICE_TV1_SUPPORT); 2094 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 2095 DRM_MODE_CONNECTOR_SVIDEO, 2096 &ddc_i2c, 2097 CONNECTOR_OBJECT_ID_SVIDEO, 2098 &hpd); 2099 break; 2100 case CT_SAM440EP: 2101 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n", 2102 rdev->mode_info.connector_table); 2103 /* LVDS */ 2104 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); 2105 hpd.hpd = RADEON_HPD_NONE; 2106 radeon_add_legacy_encoder(dev, 2107 radeon_get_encoder_enum(dev, 2108 ATOM_DEVICE_LCD1_SUPPORT, 2109 0), 2110 ATOM_DEVICE_LCD1_SUPPORT); 2111 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 2112 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 2113 CONNECTOR_OBJECT_ID_LVDS, 2114 &hpd); 2115 /* DVI-I - secondary dac, int tmds */ 2116 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2117 hpd.hpd = RADEON_HPD_1; /* ??? */ 2118 radeon_add_legacy_encoder(dev, 2119 radeon_get_encoder_enum(dev, 2120 ATOM_DEVICE_DFP1_SUPPORT, 2121 0), 2122 ATOM_DEVICE_DFP1_SUPPORT); 2123 radeon_add_legacy_encoder(dev, 2124 radeon_get_encoder_enum(dev, 2125 ATOM_DEVICE_CRT2_SUPPORT, 2126 2), 2127 ATOM_DEVICE_CRT2_SUPPORT); 2128 radeon_add_legacy_connector(dev, 1, 2129 ATOM_DEVICE_DFP1_SUPPORT | 2130 ATOM_DEVICE_CRT2_SUPPORT, 2131 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2132 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2133 &hpd); 2134 /* VGA - primary dac */ 2135 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2136 hpd.hpd = RADEON_HPD_NONE; 2137 radeon_add_legacy_encoder(dev, 2138 radeon_get_encoder_enum(dev, 2139 ATOM_DEVICE_CRT1_SUPPORT, 2140 1), 2141 ATOM_DEVICE_CRT1_SUPPORT); 2142 radeon_add_legacy_connector(dev, 2, 2143 ATOM_DEVICE_CRT1_SUPPORT, 2144 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2145 CONNECTOR_OBJECT_ID_VGA, 2146 &hpd); 2147 /* TV - TV DAC */ 2148 ddc_i2c.valid = false; 2149 hpd.hpd = RADEON_HPD_NONE; 2150 radeon_add_legacy_encoder(dev, 2151 radeon_get_encoder_enum(dev, 2152 ATOM_DEVICE_TV1_SUPPORT, 2153 2), 2154 ATOM_DEVICE_TV1_SUPPORT); 2155 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT, 2156 DRM_MODE_CONNECTOR_SVIDEO, 2157 &ddc_i2c, 2158 CONNECTOR_OBJECT_ID_SVIDEO, 2159 &hpd); 2160 break; 2161 case CT_MAC_G4_SILVER: 2162 DRM_INFO("Connector Table: %d (mac g4 silver)\n", 2163 rdev->mode_info.connector_table); 2164 /* DVI-I - tv dac, int tmds */ 2165 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2166 hpd.hpd = RADEON_HPD_1; /* ??? */ 2167 radeon_add_legacy_encoder(dev, 2168 radeon_get_encoder_enum(dev, 2169 ATOM_DEVICE_DFP1_SUPPORT, 2170 0), 2171 ATOM_DEVICE_DFP1_SUPPORT); 2172 radeon_add_legacy_encoder(dev, 2173 radeon_get_encoder_enum(dev, 2174 ATOM_DEVICE_CRT2_SUPPORT, 2175 2), 2176 ATOM_DEVICE_CRT2_SUPPORT); 2177 radeon_add_legacy_connector(dev, 0, 2178 ATOM_DEVICE_DFP1_SUPPORT | 2179 ATOM_DEVICE_CRT2_SUPPORT, 2180 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2181 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2182 &hpd); 2183 /* VGA - primary dac */ 2184 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2185 hpd.hpd = RADEON_HPD_NONE; 2186 radeon_add_legacy_encoder(dev, 2187 radeon_get_encoder_enum(dev, 2188 ATOM_DEVICE_CRT1_SUPPORT, 2189 1), 2190 ATOM_DEVICE_CRT1_SUPPORT); 2191 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 2192 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2193 CONNECTOR_OBJECT_ID_VGA, 2194 &hpd); 2195 /* TV - TV DAC */ 2196 ddc_i2c.valid = false; 2197 hpd.hpd = RADEON_HPD_NONE; 2198 radeon_add_legacy_encoder(dev, 2199 radeon_get_encoder_enum(dev, 2200 ATOM_DEVICE_TV1_SUPPORT, 2201 2), 2202 ATOM_DEVICE_TV1_SUPPORT); 2203 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 2204 DRM_MODE_CONNECTOR_SVIDEO, 2205 &ddc_i2c, 2206 CONNECTOR_OBJECT_ID_SVIDEO, 2207 &hpd); 2208 break; 2209 default: 2210 DRM_INFO("Connector table: %d (invalid)\n", 2211 rdev->mode_info.connector_table); 2212 return false; 2213 } 2214 2215 radeon_link_encoder_connector(dev); 2216 2217 return true; 2218 } 2219 2220 static bool radeon_apply_legacy_quirks(struct drm_device *dev, 2221 int bios_index, 2222 enum radeon_combios_connector 2223 *legacy_connector, 2224 struct radeon_i2c_bus_rec *ddc_i2c, 2225 struct radeon_hpd *hpd) 2226 { 2227 2228 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, 2229 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ 2230 if (dev->pdev->device == 0x515e && 2231 dev->pdev->subsystem_vendor == 0x1014) { 2232 if (*legacy_connector == CONNECTOR_CRT_LEGACY && 2233 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 2234 return false; 2235 } 2236 2237 /* X300 card with extra non-existent DVI port */ 2238 if (dev->pdev->device == 0x5B60 && 2239 dev->pdev->subsystem_vendor == 0x17af && 2240 dev->pdev->subsystem_device == 0x201e && bios_index == 2) { 2241 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) 2242 return false; 2243 } 2244 2245 return true; 2246 } 2247 2248 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev) 2249 { 2250 /* Acer 5102 has non-existent TV port */ 2251 if (dev->pdev->device == 0x5975 && 2252 dev->pdev->subsystem_vendor == 0x1025 && 2253 dev->pdev->subsystem_device == 0x009f) 2254 return false; 2255 2256 /* HP dc5750 has non-existent TV port */ 2257 if (dev->pdev->device == 0x5974 && 2258 dev->pdev->subsystem_vendor == 0x103c && 2259 dev->pdev->subsystem_device == 0x280a) 2260 return false; 2261 2262 /* MSI S270 has non-existent TV port */ 2263 if (dev->pdev->device == 0x5955 && 2264 dev->pdev->subsystem_vendor == 0x1462 && 2265 dev->pdev->subsystem_device == 0x0131) 2266 return false; 2267 2268 return true; 2269 } 2270 2271 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d) 2272 { 2273 struct radeon_device *rdev = dev->dev_private; 2274 uint32_t ext_tmds_info; 2275 2276 if (rdev->flags & RADEON_IS_IGP) { 2277 if (is_dvi_d) 2278 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 2279 else 2280 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2281 } 2282 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 2283 if (ext_tmds_info) { 2284 uint8_t rev = RBIOS8(ext_tmds_info); 2285 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5); 2286 if (rev >= 3) { 2287 if (is_dvi_d) 2288 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 2289 else 2290 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 2291 } else { 2292 if (flags & 1) { 2293 if (is_dvi_d) 2294 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 2295 else 2296 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 2297 } 2298 } 2299 } 2300 if (is_dvi_d) 2301 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 2302 else 2303 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2304 } 2305 2306 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) 2307 { 2308 struct radeon_device *rdev = dev->dev_private; 2309 uint32_t conn_info, entry, devices; 2310 uint16_t tmp, connector_object_id; 2311 enum radeon_combios_ddc ddc_type; 2312 enum radeon_combios_connector connector; 2313 int i = 0; 2314 struct radeon_i2c_bus_rec ddc_i2c; 2315 struct radeon_hpd hpd; 2316 2317 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE); 2318 if (conn_info) { 2319 for (i = 0; i < 4; i++) { 2320 entry = conn_info + 2 + i * 2; 2321 2322 if (!RBIOS16(entry)) 2323 break; 2324 2325 tmp = RBIOS16(entry); 2326 2327 connector = (tmp >> 12) & 0xf; 2328 2329 ddc_type = (tmp >> 8) & 0xf; 2330 if (ddc_type == 5) 2331 ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev); 2332 else 2333 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0); 2334 2335 switch (connector) { 2336 case CONNECTOR_PROPRIETARY_LEGACY: 2337 case CONNECTOR_DVI_I_LEGACY: 2338 case CONNECTOR_DVI_D_LEGACY: 2339 if ((tmp >> 4) & 0x1) 2340 hpd.hpd = RADEON_HPD_2; 2341 else 2342 hpd.hpd = RADEON_HPD_1; 2343 break; 2344 default: 2345 hpd.hpd = RADEON_HPD_NONE; 2346 break; 2347 } 2348 2349 if (!radeon_apply_legacy_quirks(dev, i, &connector, 2350 &ddc_i2c, &hpd)) 2351 continue; 2352 2353 switch (connector) { 2354 case CONNECTOR_PROPRIETARY_LEGACY: 2355 if ((tmp >> 4) & 0x1) 2356 devices = ATOM_DEVICE_DFP2_SUPPORT; 2357 else 2358 devices = ATOM_DEVICE_DFP1_SUPPORT; 2359 radeon_add_legacy_encoder(dev, 2360 radeon_get_encoder_enum 2361 (dev, devices, 0), 2362 devices); 2363 radeon_add_legacy_connector(dev, i, devices, 2364 legacy_connector_convert 2365 [connector], 2366 &ddc_i2c, 2367 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 2368 &hpd); 2369 break; 2370 case CONNECTOR_CRT_LEGACY: 2371 if (tmp & 0x1) { 2372 devices = ATOM_DEVICE_CRT2_SUPPORT; 2373 radeon_add_legacy_encoder(dev, 2374 radeon_get_encoder_enum 2375 (dev, 2376 ATOM_DEVICE_CRT2_SUPPORT, 2377 2), 2378 ATOM_DEVICE_CRT2_SUPPORT); 2379 } else { 2380 devices = ATOM_DEVICE_CRT1_SUPPORT; 2381 radeon_add_legacy_encoder(dev, 2382 radeon_get_encoder_enum 2383 (dev, 2384 ATOM_DEVICE_CRT1_SUPPORT, 2385 1), 2386 ATOM_DEVICE_CRT1_SUPPORT); 2387 } 2388 radeon_add_legacy_connector(dev, 2389 i, 2390 devices, 2391 legacy_connector_convert 2392 [connector], 2393 &ddc_i2c, 2394 CONNECTOR_OBJECT_ID_VGA, 2395 &hpd); 2396 break; 2397 case CONNECTOR_DVI_I_LEGACY: 2398 devices = 0; 2399 if (tmp & 0x1) { 2400 devices |= ATOM_DEVICE_CRT2_SUPPORT; 2401 radeon_add_legacy_encoder(dev, 2402 radeon_get_encoder_enum 2403 (dev, 2404 ATOM_DEVICE_CRT2_SUPPORT, 2405 2), 2406 ATOM_DEVICE_CRT2_SUPPORT); 2407 } else { 2408 devices |= ATOM_DEVICE_CRT1_SUPPORT; 2409 radeon_add_legacy_encoder(dev, 2410 radeon_get_encoder_enum 2411 (dev, 2412 ATOM_DEVICE_CRT1_SUPPORT, 2413 1), 2414 ATOM_DEVICE_CRT1_SUPPORT); 2415 } 2416 /* RV100 board with external TDMS bit mis-set. 2417 * Actually uses internal TMDS, clear the bit. 2418 */ 2419 if (dev->pdev->device == 0x5159 && 2420 dev->pdev->subsystem_vendor == 0x1014 && 2421 dev->pdev->subsystem_device == 0x029A) { 2422 tmp &= ~(1 << 4); 2423 } 2424 if ((tmp >> 4) & 0x1) { 2425 devices |= ATOM_DEVICE_DFP2_SUPPORT; 2426 radeon_add_legacy_encoder(dev, 2427 radeon_get_encoder_enum 2428 (dev, 2429 ATOM_DEVICE_DFP2_SUPPORT, 2430 0), 2431 ATOM_DEVICE_DFP2_SUPPORT); 2432 connector_object_id = combios_check_dl_dvi(dev, 0); 2433 } else { 2434 devices |= ATOM_DEVICE_DFP1_SUPPORT; 2435 radeon_add_legacy_encoder(dev, 2436 radeon_get_encoder_enum 2437 (dev, 2438 ATOM_DEVICE_DFP1_SUPPORT, 2439 0), 2440 ATOM_DEVICE_DFP1_SUPPORT); 2441 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2442 } 2443 radeon_add_legacy_connector(dev, 2444 i, 2445 devices, 2446 legacy_connector_convert 2447 [connector], 2448 &ddc_i2c, 2449 connector_object_id, 2450 &hpd); 2451 break; 2452 case CONNECTOR_DVI_D_LEGACY: 2453 if ((tmp >> 4) & 0x1) { 2454 devices = ATOM_DEVICE_DFP2_SUPPORT; 2455 connector_object_id = combios_check_dl_dvi(dev, 1); 2456 } else { 2457 devices = ATOM_DEVICE_DFP1_SUPPORT; 2458 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2459 } 2460 radeon_add_legacy_encoder(dev, 2461 radeon_get_encoder_enum 2462 (dev, devices, 0), 2463 devices); 2464 radeon_add_legacy_connector(dev, i, devices, 2465 legacy_connector_convert 2466 [connector], 2467 &ddc_i2c, 2468 connector_object_id, 2469 &hpd); 2470 break; 2471 case CONNECTOR_CTV_LEGACY: 2472 case CONNECTOR_STV_LEGACY: 2473 radeon_add_legacy_encoder(dev, 2474 radeon_get_encoder_enum 2475 (dev, 2476 ATOM_DEVICE_TV1_SUPPORT, 2477 2), 2478 ATOM_DEVICE_TV1_SUPPORT); 2479 radeon_add_legacy_connector(dev, i, 2480 ATOM_DEVICE_TV1_SUPPORT, 2481 legacy_connector_convert 2482 [connector], 2483 &ddc_i2c, 2484 CONNECTOR_OBJECT_ID_SVIDEO, 2485 &hpd); 2486 break; 2487 default: 2488 DRM_ERROR("Unknown connector type: %d\n", 2489 connector); 2490 continue; 2491 } 2492 2493 } 2494 } else { 2495 uint16_t tmds_info = 2496 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 2497 if (tmds_info) { 2498 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n"); 2499 2500 radeon_add_legacy_encoder(dev, 2501 radeon_get_encoder_enum(dev, 2502 ATOM_DEVICE_CRT1_SUPPORT, 2503 1), 2504 ATOM_DEVICE_CRT1_SUPPORT); 2505 radeon_add_legacy_encoder(dev, 2506 radeon_get_encoder_enum(dev, 2507 ATOM_DEVICE_DFP1_SUPPORT, 2508 0), 2509 ATOM_DEVICE_DFP1_SUPPORT); 2510 2511 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2512 hpd.hpd = RADEON_HPD_1; 2513 radeon_add_legacy_connector(dev, 2514 0, 2515 ATOM_DEVICE_CRT1_SUPPORT | 2516 ATOM_DEVICE_DFP1_SUPPORT, 2517 DRM_MODE_CONNECTOR_DVII, 2518 &ddc_i2c, 2519 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2520 &hpd); 2521 } else { 2522 uint16_t crt_info = 2523 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 2524 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n"); 2525 if (crt_info) { 2526 radeon_add_legacy_encoder(dev, 2527 radeon_get_encoder_enum(dev, 2528 ATOM_DEVICE_CRT1_SUPPORT, 2529 1), 2530 ATOM_DEVICE_CRT1_SUPPORT); 2531 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2532 hpd.hpd = RADEON_HPD_NONE; 2533 radeon_add_legacy_connector(dev, 2534 0, 2535 ATOM_DEVICE_CRT1_SUPPORT, 2536 DRM_MODE_CONNECTOR_VGA, 2537 &ddc_i2c, 2538 CONNECTOR_OBJECT_ID_VGA, 2539 &hpd); 2540 } else { 2541 DRM_DEBUG_KMS("No connector info found\n"); 2542 return false; 2543 } 2544 } 2545 } 2546 2547 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) { 2548 uint16_t lcd_info = 2549 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 2550 if (lcd_info) { 2551 uint16_t lcd_ddc_info = 2552 combios_get_table_offset(dev, 2553 COMBIOS_LCD_DDC_INFO_TABLE); 2554 2555 radeon_add_legacy_encoder(dev, 2556 radeon_get_encoder_enum(dev, 2557 ATOM_DEVICE_LCD1_SUPPORT, 2558 0), 2559 ATOM_DEVICE_LCD1_SUPPORT); 2560 2561 if (lcd_ddc_info) { 2562 ddc_type = RBIOS8(lcd_ddc_info + 2); 2563 switch (ddc_type) { 2564 case DDC_LCD: 2565 ddc_i2c = 2566 combios_setup_i2c_bus(rdev, 2567 DDC_LCD, 2568 RBIOS32(lcd_ddc_info + 3), 2569 RBIOS32(lcd_ddc_info + 7)); 2570 radeon_i2c_add(rdev, &ddc_i2c, "LCD"); 2571 break; 2572 case DDC_GPIO: 2573 ddc_i2c = 2574 combios_setup_i2c_bus(rdev, 2575 DDC_GPIO, 2576 RBIOS32(lcd_ddc_info + 3), 2577 RBIOS32(lcd_ddc_info + 7)); 2578 radeon_i2c_add(rdev, &ddc_i2c, "LCD"); 2579 break; 2580 default: 2581 ddc_i2c = 2582 combios_setup_i2c_bus(rdev, ddc_type, 0, 0); 2583 break; 2584 } 2585 DRM_DEBUG_KMS("LCD DDC Info Table found!\n"); 2586 } else 2587 ddc_i2c.valid = false; 2588 2589 hpd.hpd = RADEON_HPD_NONE; 2590 radeon_add_legacy_connector(dev, 2591 5, 2592 ATOM_DEVICE_LCD1_SUPPORT, 2593 DRM_MODE_CONNECTOR_LVDS, 2594 &ddc_i2c, 2595 CONNECTOR_OBJECT_ID_LVDS, 2596 &hpd); 2597 } 2598 } 2599 2600 /* check TV table */ 2601 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 2602 uint32_t tv_info = 2603 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 2604 if (tv_info) { 2605 if (RBIOS8(tv_info + 6) == 'T') { 2606 if (radeon_apply_legacy_tv_quirks(dev)) { 2607 hpd.hpd = RADEON_HPD_NONE; 2608 ddc_i2c.valid = false; 2609 radeon_add_legacy_encoder(dev, 2610 radeon_get_encoder_enum 2611 (dev, 2612 ATOM_DEVICE_TV1_SUPPORT, 2613 2), 2614 ATOM_DEVICE_TV1_SUPPORT); 2615 radeon_add_legacy_connector(dev, 6, 2616 ATOM_DEVICE_TV1_SUPPORT, 2617 DRM_MODE_CONNECTOR_SVIDEO, 2618 &ddc_i2c, 2619 CONNECTOR_OBJECT_ID_SVIDEO, 2620 &hpd); 2621 } 2622 } 2623 } 2624 } 2625 2626 radeon_link_encoder_connector(dev); 2627 2628 return true; 2629 } 2630 2631 static const char *thermal_controller_names[] = { 2632 "NONE", 2633 "lm63", 2634 "adm1032", 2635 }; 2636 2637 void radeon_combios_get_power_modes(struct radeon_device *rdev) 2638 { 2639 struct drm_device *dev = rdev->ddev; 2640 u16 offset, misc, misc2 = 0; 2641 u8 rev, blocks, tmp; 2642 int state_index = 0; 2643 struct radeon_i2c_bus_rec i2c_bus; 2644 2645 rdev->pm.default_power_state_index = -1; 2646 2647 /* allocate 2 power states */ 2648 rdev->pm.power_state = kcalloc(2, sizeof(struct radeon_power_state), 2649 GFP_KERNEL); 2650 if (rdev->pm.power_state) { 2651 /* allocate 1 clock mode per state */ 2652 rdev->pm.power_state[0].clock_info = 2653 kcalloc(1, sizeof(struct radeon_pm_clock_info), 2654 GFP_KERNEL); 2655 rdev->pm.power_state[1].clock_info = 2656 kcalloc(1, sizeof(struct radeon_pm_clock_info), 2657 GFP_KERNEL); 2658 if (!rdev->pm.power_state[0].clock_info || 2659 !rdev->pm.power_state[1].clock_info) 2660 goto pm_failed; 2661 } else 2662 goto pm_failed; 2663 2664 /* check for a thermal chip */ 2665 offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE); 2666 if (offset) { 2667 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0; 2668 2669 rev = RBIOS8(offset); 2670 2671 if (rev == 0) { 2672 thermal_controller = RBIOS8(offset + 3); 2673 gpio = RBIOS8(offset + 4) & 0x3f; 2674 i2c_addr = RBIOS8(offset + 5); 2675 } else if (rev == 1) { 2676 thermal_controller = RBIOS8(offset + 4); 2677 gpio = RBIOS8(offset + 5) & 0x3f; 2678 i2c_addr = RBIOS8(offset + 6); 2679 } else if (rev == 2) { 2680 thermal_controller = RBIOS8(offset + 4); 2681 gpio = RBIOS8(offset + 5) & 0x3f; 2682 i2c_addr = RBIOS8(offset + 6); 2683 clk_bit = RBIOS8(offset + 0xa); 2684 data_bit = RBIOS8(offset + 0xb); 2685 } 2686 if ((thermal_controller > 0) && (thermal_controller < 3)) { 2687 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2688 thermal_controller_names[thermal_controller], 2689 i2c_addr >> 1); 2690 if (gpio == DDC_LCD) { 2691 /* MM i2c */ 2692 i2c_bus.valid = true; 2693 i2c_bus.hw_capable = true; 2694 i2c_bus.mm_i2c = true; 2695 i2c_bus.i2c_id = 0xa0; 2696 } else if (gpio == DDC_GPIO) 2697 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit); 2698 else 2699 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); 2700 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2701 if (rdev->pm.i2c_bus) { 2702 struct i2c_board_info info = { }; 2703 const char *name = thermal_controller_names[thermal_controller]; 2704 info.addr = i2c_addr >> 1; 2705 strlcpy(info.type, name, sizeof(info.type)); 2706 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2707 } 2708 } 2709 } else { 2710 /* boards with a thermal chip, but no overdrive table */ 2711 2712 /* Asus 9600xt has an f75375 on the monid bus */ 2713 if ((dev->pdev->device == 0x4152) && 2714 (dev->pdev->subsystem_vendor == 0x1043) && 2715 (dev->pdev->subsystem_device == 0xc002)) { 2716 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 2717 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2718 if (rdev->pm.i2c_bus) { 2719 struct i2c_board_info info = { }; 2720 const char *name = "f75375"; 2721 info.addr = 0x28; 2722 strlcpy(info.type, name, sizeof(info.type)); 2723 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2724 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2725 name, info.addr); 2726 } 2727 } 2728 } 2729 2730 if (rdev->flags & RADEON_IS_MOBILITY) { 2731 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE); 2732 if (offset) { 2733 rev = RBIOS8(offset); 2734 blocks = RBIOS8(offset + 0x2); 2735 /* power mode 0 tends to be the only valid one */ 2736 rdev->pm.power_state[state_index].num_clock_modes = 1; 2737 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2); 2738 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6); 2739 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2740 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2741 goto default_mode; 2742 rdev->pm.power_state[state_index].type = 2743 POWER_STATE_TYPE_BATTERY; 2744 misc = RBIOS16(offset + 0x5 + 0x0); 2745 if (rev > 4) 2746 misc2 = RBIOS16(offset + 0x5 + 0xe); 2747 rdev->pm.power_state[state_index].misc = misc; 2748 rdev->pm.power_state[state_index].misc2 = misc2; 2749 if (misc & 0x4) { 2750 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO; 2751 if (misc & 0x8) 2752 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2753 true; 2754 else 2755 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2756 false; 2757 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true; 2758 if (rev < 6) { 2759 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = 2760 RBIOS16(offset + 0x5 + 0xb) * 4; 2761 tmp = RBIOS8(offset + 0x5 + 0xd); 2762 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); 2763 } else { 2764 u8 entries = RBIOS8(offset + 0x5 + 0xb); 2765 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc); 2766 if (entries && voltage_table_offset) { 2767 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = 2768 RBIOS16(voltage_table_offset) * 4; 2769 tmp = RBIOS8(voltage_table_offset + 0x2); 2770 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); 2771 } else 2772 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false; 2773 } 2774 switch ((misc2 & 0x700) >> 8) { 2775 case 0: 2776 default: 2777 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0; 2778 break; 2779 case 1: 2780 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33; 2781 break; 2782 case 2: 2783 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66; 2784 break; 2785 case 3: 2786 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99; 2787 break; 2788 case 4: 2789 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132; 2790 break; 2791 } 2792 } else 2793 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2794 if (rev > 6) 2795 rdev->pm.power_state[state_index].pcie_lanes = 2796 RBIOS8(offset + 0x5 + 0x10); 2797 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2798 state_index++; 2799 } else { 2800 /* XXX figure out some good default low power mode for mobility cards w/out power tables */ 2801 } 2802 } else { 2803 /* XXX figure out some good default low power mode for desktop cards */ 2804 } 2805 2806 default_mode: 2807 /* add the default mode */ 2808 rdev->pm.power_state[state_index].type = 2809 POWER_STATE_TYPE_DEFAULT; 2810 rdev->pm.power_state[state_index].num_clock_modes = 1; 2811 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 2812 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2813 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; 2814 if ((state_index > 0) && 2815 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO)) 2816 rdev->pm.power_state[state_index].clock_info[0].voltage = 2817 rdev->pm.power_state[0].clock_info[0].voltage; 2818 else 2819 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2820 rdev->pm.power_state[state_index].pcie_lanes = 16; 2821 rdev->pm.power_state[state_index].flags = 0; 2822 rdev->pm.default_power_state_index = state_index; 2823 rdev->pm.num_power_states = state_index + 1; 2824 2825 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2826 rdev->pm.current_clock_mode_index = 0; 2827 return; 2828 2829 pm_failed: 2830 rdev->pm.default_power_state_index = state_index; 2831 rdev->pm.num_power_states = 0; 2832 2833 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2834 rdev->pm.current_clock_mode_index = 0; 2835 } 2836 2837 void radeon_external_tmds_setup(struct drm_encoder *encoder) 2838 { 2839 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2840 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2841 2842 if (!tmds) 2843 return; 2844 2845 switch (tmds->dvo_chip) { 2846 case DVO_SIL164: 2847 /* sil 164 */ 2848 radeon_i2c_put_byte(tmds->i2c_bus, 2849 tmds->slave_addr, 2850 0x08, 0x30); 2851 radeon_i2c_put_byte(tmds->i2c_bus, 2852 tmds->slave_addr, 2853 0x09, 0x00); 2854 radeon_i2c_put_byte(tmds->i2c_bus, 2855 tmds->slave_addr, 2856 0x0a, 0x90); 2857 radeon_i2c_put_byte(tmds->i2c_bus, 2858 tmds->slave_addr, 2859 0x0c, 0x89); 2860 radeon_i2c_put_byte(tmds->i2c_bus, 2861 tmds->slave_addr, 2862 0x08, 0x3b); 2863 break; 2864 case DVO_SIL1178: 2865 /* sil 1178 - untested */ 2866 /* 2867 * 0x0f, 0x44 2868 * 0x0f, 0x4c 2869 * 0x0e, 0x01 2870 * 0x0a, 0x80 2871 * 0x09, 0x30 2872 * 0x0c, 0xc9 2873 * 0x0d, 0x70 2874 * 0x08, 0x32 2875 * 0x08, 0x33 2876 */ 2877 break; 2878 default: 2879 break; 2880 } 2881 2882 } 2883 2884 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) 2885 { 2886 struct drm_device *dev = encoder->dev; 2887 struct radeon_device *rdev = dev->dev_private; 2888 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2889 uint16_t offset; 2890 uint8_t blocks, slave_addr, rev; 2891 uint32_t index, id; 2892 uint32_t reg, val, and_mask, or_mask; 2893 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2894 2895 if (!tmds) 2896 return false; 2897 2898 if (rdev->flags & RADEON_IS_IGP) { 2899 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE); 2900 rev = RBIOS8(offset); 2901 if (offset) { 2902 rev = RBIOS8(offset); 2903 if (rev > 1) { 2904 blocks = RBIOS8(offset + 3); 2905 index = offset + 4; 2906 while (blocks > 0) { 2907 id = RBIOS16(index); 2908 index += 2; 2909 switch (id >> 13) { 2910 case 0: 2911 reg = (id & 0x1fff) * 4; 2912 val = RBIOS32(index); 2913 index += 4; 2914 WREG32(reg, val); 2915 break; 2916 case 2: 2917 reg = (id & 0x1fff) * 4; 2918 and_mask = RBIOS32(index); 2919 index += 4; 2920 or_mask = RBIOS32(index); 2921 index += 4; 2922 val = RREG32(reg); 2923 val = (val & and_mask) | or_mask; 2924 WREG32(reg, val); 2925 break; 2926 case 3: 2927 val = RBIOS16(index); 2928 index += 2; 2929 udelay(val); 2930 break; 2931 case 4: 2932 val = RBIOS16(index); 2933 index += 2; 2934 mdelay(val); 2935 break; 2936 case 6: 2937 slave_addr = id & 0xff; 2938 slave_addr >>= 1; /* 7 bit addressing */ 2939 index++; 2940 reg = RBIOS8(index); 2941 index++; 2942 val = RBIOS8(index); 2943 index++; 2944 radeon_i2c_put_byte(tmds->i2c_bus, 2945 slave_addr, 2946 reg, val); 2947 break; 2948 default: 2949 DRM_ERROR("Unknown id %d\n", id >> 13); 2950 break; 2951 } 2952 blocks--; 2953 } 2954 return true; 2955 } 2956 } 2957 } else { 2958 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 2959 if (offset) { 2960 index = offset + 10; 2961 id = RBIOS16(index); 2962 while (id != 0xffff) { 2963 index += 2; 2964 switch (id >> 13) { 2965 case 0: 2966 reg = (id & 0x1fff) * 4; 2967 val = RBIOS32(index); 2968 WREG32(reg, val); 2969 break; 2970 case 2: 2971 reg = (id & 0x1fff) * 4; 2972 and_mask = RBIOS32(index); 2973 index += 4; 2974 or_mask = RBIOS32(index); 2975 index += 4; 2976 val = RREG32(reg); 2977 val = (val & and_mask) | or_mask; 2978 WREG32(reg, val); 2979 break; 2980 case 4: 2981 val = RBIOS16(index); 2982 index += 2; 2983 udelay(val); 2984 break; 2985 case 5: 2986 reg = id & 0x1fff; 2987 and_mask = RBIOS32(index); 2988 index += 4; 2989 or_mask = RBIOS32(index); 2990 index += 4; 2991 val = RREG32_PLL(reg); 2992 val = (val & and_mask) | or_mask; 2993 WREG32_PLL(reg, val); 2994 break; 2995 case 6: 2996 reg = id & 0x1fff; 2997 val = RBIOS8(index); 2998 index += 1; 2999 radeon_i2c_put_byte(tmds->i2c_bus, 3000 tmds->slave_addr, 3001 reg, val); 3002 break; 3003 default: 3004 DRM_ERROR("Unknown id %d\n", id >> 13); 3005 break; 3006 } 3007 id = RBIOS16(index); 3008 } 3009 return true; 3010 } 3011 } 3012 return false; 3013 } 3014 3015 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset) 3016 { 3017 struct radeon_device *rdev = dev->dev_private; 3018 3019 if (offset) { 3020 while (RBIOS16(offset)) { 3021 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13); 3022 uint32_t addr = (RBIOS16(offset) & 0x1fff); 3023 uint32_t val, and_mask, or_mask; 3024 uint32_t tmp; 3025 3026 offset += 2; 3027 switch (cmd) { 3028 case 0: 3029 val = RBIOS32(offset); 3030 offset += 4; 3031 WREG32(addr, val); 3032 break; 3033 case 1: 3034 val = RBIOS32(offset); 3035 offset += 4; 3036 WREG32(addr, val); 3037 break; 3038 case 2: 3039 and_mask = RBIOS32(offset); 3040 offset += 4; 3041 or_mask = RBIOS32(offset); 3042 offset += 4; 3043 tmp = RREG32(addr); 3044 tmp &= and_mask; 3045 tmp |= or_mask; 3046 WREG32(addr, tmp); 3047 break; 3048 case 3: 3049 and_mask = RBIOS32(offset); 3050 offset += 4; 3051 or_mask = RBIOS32(offset); 3052 offset += 4; 3053 tmp = RREG32(addr); 3054 tmp &= and_mask; 3055 tmp |= or_mask; 3056 WREG32(addr, tmp); 3057 break; 3058 case 4: 3059 val = RBIOS16(offset); 3060 offset += 2; 3061 udelay(val); 3062 break; 3063 case 5: 3064 val = RBIOS16(offset); 3065 offset += 2; 3066 switch (addr) { 3067 case 8: 3068 while (val--) { 3069 if (! 3070 (RREG32_PLL 3071 (RADEON_CLK_PWRMGT_CNTL) & 3072 RADEON_MC_BUSY)) 3073 break; 3074 } 3075 break; 3076 case 9: 3077 while (val--) { 3078 if ((RREG32(RADEON_MC_STATUS) & 3079 RADEON_MC_IDLE)) 3080 break; 3081 } 3082 break; 3083 default: 3084 break; 3085 } 3086 break; 3087 default: 3088 break; 3089 } 3090 } 3091 } 3092 } 3093 3094 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset) 3095 { 3096 struct radeon_device *rdev = dev->dev_private; 3097 3098 if (offset) { 3099 while (RBIOS8(offset)) { 3100 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6); 3101 uint8_t addr = (RBIOS8(offset) & 0x3f); 3102 uint32_t val, shift, tmp; 3103 uint32_t and_mask, or_mask; 3104 3105 offset++; 3106 switch (cmd) { 3107 case 0: 3108 val = RBIOS32(offset); 3109 offset += 4; 3110 WREG32_PLL(addr, val); 3111 break; 3112 case 1: 3113 shift = RBIOS8(offset) * 8; 3114 offset++; 3115 and_mask = RBIOS8(offset) << shift; 3116 and_mask |= ~(0xff << shift); 3117 offset++; 3118 or_mask = RBIOS8(offset) << shift; 3119 offset++; 3120 tmp = RREG32_PLL(addr); 3121 tmp &= and_mask; 3122 tmp |= or_mask; 3123 WREG32_PLL(addr, tmp); 3124 break; 3125 case 2: 3126 case 3: 3127 tmp = 1000; 3128 switch (addr) { 3129 case 1: 3130 udelay(150); 3131 break; 3132 case 2: 3133 mdelay(1); 3134 break; 3135 case 3: 3136 while (tmp--) { 3137 if (! 3138 (RREG32_PLL 3139 (RADEON_CLK_PWRMGT_CNTL) & 3140 RADEON_MC_BUSY)) 3141 break; 3142 } 3143 break; 3144 case 4: 3145 while (tmp--) { 3146 if (RREG32_PLL 3147 (RADEON_CLK_PWRMGT_CNTL) & 3148 RADEON_DLL_READY) 3149 break; 3150 } 3151 break; 3152 case 5: 3153 tmp = 3154 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); 3155 if (tmp & RADEON_CG_NO1_DEBUG_0) { 3156 #if 0 3157 uint32_t mclk_cntl = 3158 RREG32_PLL 3159 (RADEON_MCLK_CNTL); 3160 mclk_cntl &= 0xffff0000; 3161 /*mclk_cntl |= 0x00001111;*//* ??? */ 3162 WREG32_PLL(RADEON_MCLK_CNTL, 3163 mclk_cntl); 3164 mdelay(10); 3165 #endif 3166 WREG32_PLL 3167 (RADEON_CLK_PWRMGT_CNTL, 3168 tmp & 3169 ~RADEON_CG_NO1_DEBUG_0); 3170 mdelay(10); 3171 } 3172 break; 3173 default: 3174 break; 3175 } 3176 break; 3177 default: 3178 break; 3179 } 3180 } 3181 } 3182 } 3183 3184 static void combios_parse_ram_reset_table(struct drm_device *dev, 3185 uint16_t offset) 3186 { 3187 struct radeon_device *rdev = dev->dev_private; 3188 uint32_t tmp; 3189 3190 if (offset) { 3191 uint8_t val = RBIOS8(offset); 3192 while (val != 0xff) { 3193 offset++; 3194 3195 if (val == 0x0f) { 3196 uint32_t channel_complete_mask; 3197 3198 if (ASIC_IS_R300(rdev)) 3199 channel_complete_mask = 3200 R300_MEM_PWRUP_COMPLETE; 3201 else 3202 channel_complete_mask = 3203 RADEON_MEM_PWRUP_COMPLETE; 3204 tmp = 20000; 3205 while (tmp--) { 3206 if ((RREG32(RADEON_MEM_STR_CNTL) & 3207 channel_complete_mask) == 3208 channel_complete_mask) 3209 break; 3210 } 3211 } else { 3212 uint32_t or_mask = RBIOS16(offset); 3213 offset += 2; 3214 3215 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3216 tmp &= RADEON_SDRAM_MODE_MASK; 3217 tmp |= or_mask; 3218 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 3219 3220 or_mask = val << 24; 3221 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3222 tmp &= RADEON_B3MEM_RESET_MASK; 3223 tmp |= or_mask; 3224 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 3225 } 3226 val = RBIOS8(offset); 3227 } 3228 } 3229 } 3230 3231 static uint32_t combios_detect_ram(struct drm_device *dev, int ram, 3232 int mem_addr_mapping) 3233 { 3234 struct radeon_device *rdev = dev->dev_private; 3235 uint32_t mem_cntl; 3236 uint32_t mem_size; 3237 uint32_t addr = 0; 3238 3239 mem_cntl = RREG32(RADEON_MEM_CNTL); 3240 if (mem_cntl & RV100_HALF_MODE) 3241 ram /= 2; 3242 mem_size = ram; 3243 mem_cntl &= ~(0xff << 8); 3244 mem_cntl |= (mem_addr_mapping & 0xff) << 8; 3245 WREG32(RADEON_MEM_CNTL, mem_cntl); 3246 RREG32(RADEON_MEM_CNTL); 3247 3248 /* sdram reset ? */ 3249 3250 /* something like this???? */ 3251 while (ram--) { 3252 addr = ram * 1024 * 1024; 3253 /* write to each page */ 3254 WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef); 3255 /* read back and verify */ 3256 if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef) 3257 return 0; 3258 } 3259 3260 return mem_size; 3261 } 3262 3263 static void combios_write_ram_size(struct drm_device *dev) 3264 { 3265 struct radeon_device *rdev = dev->dev_private; 3266 uint8_t rev; 3267 uint16_t offset; 3268 uint32_t mem_size = 0; 3269 uint32_t mem_cntl = 0; 3270 3271 /* should do something smarter here I guess... */ 3272 if (rdev->flags & RADEON_IS_IGP) 3273 return; 3274 3275 /* first check detected mem table */ 3276 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE); 3277 if (offset) { 3278 rev = RBIOS8(offset); 3279 if (rev < 3) { 3280 mem_cntl = RBIOS32(offset + 1); 3281 mem_size = RBIOS16(offset + 5); 3282 if ((rdev->family < CHIP_R200) && 3283 !ASIC_IS_RN50(rdev)) 3284 WREG32(RADEON_MEM_CNTL, mem_cntl); 3285 } 3286 } 3287 3288 if (!mem_size) { 3289 offset = 3290 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 3291 if (offset) { 3292 rev = RBIOS8(offset - 1); 3293 if (rev < 1) { 3294 if ((rdev->family < CHIP_R200) 3295 && !ASIC_IS_RN50(rdev)) { 3296 int ram = 0; 3297 int mem_addr_mapping = 0; 3298 3299 while (RBIOS8(offset)) { 3300 ram = RBIOS8(offset); 3301 mem_addr_mapping = 3302 RBIOS8(offset + 1); 3303 if (mem_addr_mapping != 0x25) 3304 ram *= 2; 3305 mem_size = 3306 combios_detect_ram(dev, ram, 3307 mem_addr_mapping); 3308 if (mem_size) 3309 break; 3310 offset += 2; 3311 } 3312 } else 3313 mem_size = RBIOS8(offset); 3314 } else { 3315 mem_size = RBIOS8(offset); 3316 mem_size *= 2; /* convert to MB */ 3317 } 3318 } 3319 } 3320 3321 mem_size *= (1024 * 1024); /* convert to bytes */ 3322 WREG32(RADEON_CONFIG_MEMSIZE, mem_size); 3323 } 3324 3325 void radeon_combios_asic_init(struct drm_device *dev) 3326 { 3327 struct radeon_device *rdev = dev->dev_private; 3328 uint16_t table; 3329 3330 /* port hardcoded mac stuff from radeonfb */ 3331 if (rdev->bios == NULL) 3332 return; 3333 3334 /* ASIC INIT 1 */ 3335 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE); 3336 if (table) 3337 combios_parse_mmio_table(dev, table); 3338 3339 /* PLL INIT */ 3340 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE); 3341 if (table) 3342 combios_parse_pll_table(dev, table); 3343 3344 /* ASIC INIT 2 */ 3345 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE); 3346 if (table) 3347 combios_parse_mmio_table(dev, table); 3348 3349 if (!(rdev->flags & RADEON_IS_IGP)) { 3350 /* ASIC INIT 4 */ 3351 table = 3352 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE); 3353 if (table) 3354 combios_parse_mmio_table(dev, table); 3355 3356 /* RAM RESET */ 3357 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE); 3358 if (table) 3359 combios_parse_ram_reset_table(dev, table); 3360 3361 /* ASIC INIT 3 */ 3362 table = 3363 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE); 3364 if (table) 3365 combios_parse_mmio_table(dev, table); 3366 3367 /* write CONFIG_MEMSIZE */ 3368 combios_write_ram_size(dev); 3369 } 3370 3371 /* quirk for rs4xx HP nx6125 laptop to make it resume 3372 * - it hangs on resume inside the dynclk 1 table. 3373 */ 3374 if (rdev->family == CHIP_RS480 && 3375 rdev->pdev->subsystem_vendor == 0x103c && 3376 rdev->pdev->subsystem_device == 0x308b) 3377 return; 3378 3379 /* quirk for rs4xx HP dv5000 laptop to make it resume 3380 * - it hangs on resume inside the dynclk 1 table. 3381 */ 3382 if (rdev->family == CHIP_RS480 && 3383 rdev->pdev->subsystem_vendor == 0x103c && 3384 rdev->pdev->subsystem_device == 0x30a4) 3385 return; 3386 3387 /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume 3388 * - it hangs on resume inside the dynclk 1 table. 3389 */ 3390 if (rdev->family == CHIP_RS480 && 3391 rdev->pdev->subsystem_vendor == 0x103c && 3392 rdev->pdev->subsystem_device == 0x30ae) 3393 return; 3394 3395 /* quirk for rs4xx HP Compaq dc5750 Small Form Factor to make it resume 3396 * - it hangs on resume inside the dynclk 1 table. 3397 */ 3398 if (rdev->family == CHIP_RS480 && 3399 rdev->pdev->subsystem_vendor == 0x103c && 3400 rdev->pdev->subsystem_device == 0x280a) 3401 return; 3402 /* quirk for rs4xx Toshiba Sattellite L20-183 latop to make it resume 3403 * - it hangs on resume inside the dynclk 1 table. 3404 */ 3405 if (rdev->family == CHIP_RS400 && 3406 rdev->pdev->subsystem_vendor == 0x1179 && 3407 rdev->pdev->subsystem_device == 0xff31) 3408 return; 3409 3410 /* DYN CLK 1 */ 3411 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); 3412 if (table) 3413 combios_parse_pll_table(dev, table); 3414 3415 } 3416 3417 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev) 3418 { 3419 struct radeon_device *rdev = dev->dev_private; 3420 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch; 3421 3422 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 3423 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3424 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH); 3425 3426 /* let the bios control the backlight */ 3427 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; 3428 3429 /* tell the bios not to handle mode switching */ 3430 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | 3431 RADEON_ACC_MODE_CHANGE); 3432 3433 /* tell the bios a driver is loaded */ 3434 bios_7_scratch |= RADEON_DRV_LOADED; 3435 3436 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 3437 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3438 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch); 3439 } 3440 3441 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock) 3442 { 3443 struct drm_device *dev = encoder->dev; 3444 struct radeon_device *rdev = dev->dev_private; 3445 uint32_t bios_6_scratch; 3446 3447 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3448 3449 if (lock) 3450 bios_6_scratch |= RADEON_DRIVER_CRITICAL; 3451 else 3452 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL; 3453 3454 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3455 } 3456 3457 void 3458 radeon_combios_connected_scratch_regs(struct drm_connector *connector, 3459 struct drm_encoder *encoder, 3460 bool connected) 3461 { 3462 struct drm_device *dev = connector->dev; 3463 struct radeon_device *rdev = dev->dev_private; 3464 struct radeon_connector *radeon_connector = 3465 to_radeon_connector(connector); 3466 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3467 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH); 3468 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 3469 3470 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 3471 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 3472 if (connected) { 3473 DRM_DEBUG_KMS("TV1 connected\n"); 3474 /* fix me */ 3475 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; 3476 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ 3477 bios_5_scratch |= RADEON_TV1_ON; 3478 bios_5_scratch |= RADEON_ACC_REQ_TV1; 3479 } else { 3480 DRM_DEBUG_KMS("TV1 disconnected\n"); 3481 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; 3482 bios_5_scratch &= ~RADEON_TV1_ON; 3483 bios_5_scratch &= ~RADEON_ACC_REQ_TV1; 3484 } 3485 } 3486 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 3487 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 3488 if (connected) { 3489 DRM_DEBUG_KMS("LCD1 connected\n"); 3490 bios_4_scratch |= RADEON_LCD1_ATTACHED; 3491 bios_5_scratch |= RADEON_LCD1_ON; 3492 bios_5_scratch |= RADEON_ACC_REQ_LCD1; 3493 } else { 3494 DRM_DEBUG_KMS("LCD1 disconnected\n"); 3495 bios_4_scratch &= ~RADEON_LCD1_ATTACHED; 3496 bios_5_scratch &= ~RADEON_LCD1_ON; 3497 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; 3498 } 3499 } 3500 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 3501 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 3502 if (connected) { 3503 DRM_DEBUG_KMS("CRT1 connected\n"); 3504 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; 3505 bios_5_scratch |= RADEON_CRT1_ON; 3506 bios_5_scratch |= RADEON_ACC_REQ_CRT1; 3507 } else { 3508 DRM_DEBUG_KMS("CRT1 disconnected\n"); 3509 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; 3510 bios_5_scratch &= ~RADEON_CRT1_ON; 3511 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; 3512 } 3513 } 3514 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 3515 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 3516 if (connected) { 3517 DRM_DEBUG_KMS("CRT2 connected\n"); 3518 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; 3519 bios_5_scratch |= RADEON_CRT2_ON; 3520 bios_5_scratch |= RADEON_ACC_REQ_CRT2; 3521 } else { 3522 DRM_DEBUG_KMS("CRT2 disconnected\n"); 3523 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; 3524 bios_5_scratch &= ~RADEON_CRT2_ON; 3525 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; 3526 } 3527 } 3528 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 3529 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 3530 if (connected) { 3531 DRM_DEBUG_KMS("DFP1 connected\n"); 3532 bios_4_scratch |= RADEON_DFP1_ATTACHED; 3533 bios_5_scratch |= RADEON_DFP1_ON; 3534 bios_5_scratch |= RADEON_ACC_REQ_DFP1; 3535 } else { 3536 DRM_DEBUG_KMS("DFP1 disconnected\n"); 3537 bios_4_scratch &= ~RADEON_DFP1_ATTACHED; 3538 bios_5_scratch &= ~RADEON_DFP1_ON; 3539 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; 3540 } 3541 } 3542 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 3543 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 3544 if (connected) { 3545 DRM_DEBUG_KMS("DFP2 connected\n"); 3546 bios_4_scratch |= RADEON_DFP2_ATTACHED; 3547 bios_5_scratch |= RADEON_DFP2_ON; 3548 bios_5_scratch |= RADEON_ACC_REQ_DFP2; 3549 } else { 3550 DRM_DEBUG_KMS("DFP2 disconnected\n"); 3551 bios_4_scratch &= ~RADEON_DFP2_ATTACHED; 3552 bios_5_scratch &= ~RADEON_DFP2_ON; 3553 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; 3554 } 3555 } 3556 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch); 3557 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3558 } 3559 3560 void 3561 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 3562 { 3563 struct drm_device *dev = encoder->dev; 3564 struct radeon_device *rdev = dev->dev_private; 3565 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3566 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 3567 3568 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 3569 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK; 3570 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT); 3571 } 3572 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 3573 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK; 3574 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT); 3575 } 3576 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 3577 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK; 3578 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT); 3579 } 3580 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 3581 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK; 3582 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT); 3583 } 3584 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 3585 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK; 3586 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT); 3587 } 3588 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 3589 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK; 3590 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT); 3591 } 3592 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3593 } 3594 3595 void 3596 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 3597 { 3598 struct drm_device *dev = encoder->dev; 3599 struct radeon_device *rdev = dev->dev_private; 3600 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3601 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3602 3603 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 3604 if (on) 3605 bios_6_scratch |= RADEON_TV_DPMS_ON; 3606 else 3607 bios_6_scratch &= ~RADEON_TV_DPMS_ON; 3608 } 3609 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3610 if (on) 3611 bios_6_scratch |= RADEON_CRT_DPMS_ON; 3612 else 3613 bios_6_scratch &= ~RADEON_CRT_DPMS_ON; 3614 } 3615 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3616 if (on) 3617 bios_6_scratch |= RADEON_LCD_DPMS_ON; 3618 else 3619 bios_6_scratch &= ~RADEON_LCD_DPMS_ON; 3620 } 3621 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 3622 if (on) 3623 bios_6_scratch |= RADEON_DFP_DPMS_ON; 3624 else 3625 bios_6_scratch &= ~RADEON_DFP_DPMS_ON; 3626 } 3627 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3628 } 3629