1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "radeon_reg.h" 30 #include "radeon.h" 31 #include "atom.h" 32 33 #include <linux/vga_switcheroo.h> 34 #include <linux/slab.h> 35 #include <linux/acpi.h> 36 /* 37 * BIOS. 38 */ 39 40 /* If you boot an IGP board with a discrete card as the primary, 41 * the IGP rom is not accessible via the rom bar as the IGP rom is 42 * part of the system bios. On boot, the system bios puts a 43 * copy of the igp rom at the start of vram if a discrete card is 44 * present. 45 */ 46 static bool igp_read_bios_from_vram(struct radeon_device *rdev) 47 { 48 uint8_t __iomem *bios; 49 resource_size_t vram_base; 50 resource_size_t size = 256 * 1024; /* ??? */ 51 52 if (!(rdev->flags & RADEON_IS_IGP)) 53 if (!radeon_card_posted(rdev)) 54 return false; 55 56 rdev->bios = NULL; 57 vram_base = pci_resource_start(rdev->pdev, 0); 58 bios = ioremap(vram_base, size); 59 if (!bios) { 60 return false; 61 } 62 63 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 64 iounmap(bios); 65 return false; 66 } 67 rdev->bios = kmalloc(size, GFP_KERNEL); 68 if (rdev->bios == NULL) { 69 iounmap(bios); 70 return false; 71 } 72 memcpy_fromio(rdev->bios, bios, size); 73 iounmap(bios); 74 return true; 75 } 76 77 static bool radeon_read_bios(struct radeon_device *rdev) 78 { 79 uint8_t __iomem *bios; 80 size_t size; 81 82 rdev->bios = NULL; 83 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 84 bios = pci_map_rom(rdev->pdev, &size); 85 if (!bios) { 86 return false; 87 } 88 89 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 90 pci_unmap_rom(rdev->pdev, bios); 91 return false; 92 } 93 rdev->bios = kmemdup(bios, size, GFP_KERNEL); 94 if (rdev->bios == NULL) { 95 pci_unmap_rom(rdev->pdev, bios); 96 return false; 97 } 98 pci_unmap_rom(rdev->pdev, bios); 99 return true; 100 } 101 102 static bool radeon_read_platform_bios(struct radeon_device *rdev) 103 { 104 uint8_t __iomem *bios; 105 size_t size; 106 107 rdev->bios = NULL; 108 109 bios = pci_platform_rom(rdev->pdev, &size); 110 if (!bios) { 111 return false; 112 } 113 114 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 115 return false; 116 } 117 rdev->bios = kmemdup(bios, size, GFP_KERNEL); 118 if (rdev->bios == NULL) { 119 return false; 120 } 121 122 return true; 123 } 124 125 #ifdef CONFIG_ACPI 126 /* ATRM is used to get the BIOS on the discrete cards in 127 * dual-gpu systems. 128 */ 129 /* retrieve the ROM in 4k blocks */ 130 #define ATRM_BIOS_PAGE 4096 131 /** 132 * radeon_atrm_call - fetch a chunk of the vbios 133 * 134 * @atrm_handle: acpi ATRM handle 135 * @bios: vbios image pointer 136 * @offset: offset of vbios image data to fetch 137 * @len: length of vbios image data to fetch 138 * 139 * Executes ATRM to fetch a chunk of the discrete 140 * vbios image on PX systems (all asics). 141 * Returns the length of the buffer fetched. 142 */ 143 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios, 144 int offset, int len) 145 { 146 acpi_status status; 147 union acpi_object atrm_arg_elements[2], *obj; 148 struct acpi_object_list atrm_arg; 149 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; 150 151 atrm_arg.count = 2; 152 atrm_arg.pointer = &atrm_arg_elements[0]; 153 154 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER; 155 atrm_arg_elements[0].integer.value = offset; 156 157 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER; 158 atrm_arg_elements[1].integer.value = len; 159 160 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer); 161 if (ACPI_FAILURE(status)) { 162 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status)); 163 return -ENODEV; 164 } 165 166 obj = (union acpi_object *)buffer.pointer; 167 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length); 168 len = obj->buffer.length; 169 kfree(buffer.pointer); 170 return len; 171 } 172 173 static bool radeon_atrm_get_bios(struct radeon_device *rdev) 174 { 175 int ret; 176 int size = 256 * 1024; 177 int i; 178 struct pci_dev *pdev = NULL; 179 acpi_handle dhandle, atrm_handle; 180 acpi_status status; 181 bool found = false; 182 183 /* ATRM is for the discrete card only */ 184 if (rdev->flags & RADEON_IS_IGP) 185 return false; 186 187 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 188 dhandle = ACPI_HANDLE(&pdev->dev); 189 if (!dhandle) 190 continue; 191 192 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 193 if (!ACPI_FAILURE(status)) { 194 found = true; 195 break; 196 } 197 } 198 199 if (!found) { 200 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 201 dhandle = ACPI_HANDLE(&pdev->dev); 202 if (!dhandle) 203 continue; 204 205 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 206 if (!ACPI_FAILURE(status)) { 207 found = true; 208 break; 209 } 210 } 211 } 212 213 if (!found) 214 return false; 215 216 rdev->bios = kmalloc(size, GFP_KERNEL); 217 if (!rdev->bios) { 218 DRM_ERROR("Unable to allocate bios\n"); 219 return false; 220 } 221 222 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 223 ret = radeon_atrm_call(atrm_handle, 224 rdev->bios, 225 (i * ATRM_BIOS_PAGE), 226 ATRM_BIOS_PAGE); 227 if (ret < ATRM_BIOS_PAGE) 228 break; 229 } 230 231 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 232 kfree(rdev->bios); 233 return false; 234 } 235 return true; 236 } 237 #else 238 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev) 239 { 240 return false; 241 } 242 #endif 243 244 static bool ni_read_disabled_bios(struct radeon_device *rdev) 245 { 246 u32 bus_cntl; 247 u32 d1vga_control; 248 u32 d2vga_control; 249 u32 vga_render_control; 250 u32 rom_cntl; 251 bool r; 252 253 bus_cntl = RREG32(R600_BUS_CNTL); 254 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 255 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 256 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 257 rom_cntl = RREG32(R600_ROM_CNTL); 258 259 /* enable the rom */ 260 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 261 if (!ASIC_IS_NODCE(rdev)) { 262 /* Disable VGA mode */ 263 WREG32(AVIVO_D1VGA_CONTROL, 264 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 265 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 266 WREG32(AVIVO_D2VGA_CONTROL, 267 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 268 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 269 WREG32(AVIVO_VGA_RENDER_CONTROL, 270 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 271 } 272 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 273 274 r = radeon_read_bios(rdev); 275 276 /* restore regs */ 277 WREG32(R600_BUS_CNTL, bus_cntl); 278 if (!ASIC_IS_NODCE(rdev)) { 279 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 280 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 281 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 282 } 283 WREG32(R600_ROM_CNTL, rom_cntl); 284 return r; 285 } 286 287 static bool r700_read_disabled_bios(struct radeon_device *rdev) 288 { 289 uint32_t viph_control; 290 uint32_t bus_cntl; 291 uint32_t d1vga_control; 292 uint32_t d2vga_control; 293 uint32_t vga_render_control; 294 uint32_t rom_cntl; 295 uint32_t cg_spll_func_cntl = 0; 296 uint32_t cg_spll_status; 297 bool r; 298 299 viph_control = RREG32(RADEON_VIPH_CONTROL); 300 bus_cntl = RREG32(R600_BUS_CNTL); 301 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 302 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 303 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 304 rom_cntl = RREG32(R600_ROM_CNTL); 305 306 /* disable VIP */ 307 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 308 /* enable the rom */ 309 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 310 /* Disable VGA mode */ 311 WREG32(AVIVO_D1VGA_CONTROL, 312 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 313 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 314 WREG32(AVIVO_D2VGA_CONTROL, 315 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 316 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 317 WREG32(AVIVO_VGA_RENDER_CONTROL, 318 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 319 320 if (rdev->family == CHIP_RV730) { 321 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 322 323 /* enable bypass mode */ 324 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 325 R600_SPLL_BYPASS_EN)); 326 327 /* wait for SPLL_CHG_STATUS to change to 1 */ 328 cg_spll_status = 0; 329 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 330 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 331 332 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 333 } else 334 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 335 336 r = radeon_read_bios(rdev); 337 338 /* restore regs */ 339 if (rdev->family == CHIP_RV730) { 340 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 341 342 /* wait for SPLL_CHG_STATUS to change to 1 */ 343 cg_spll_status = 0; 344 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 345 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 346 } 347 WREG32(RADEON_VIPH_CONTROL, viph_control); 348 WREG32(R600_BUS_CNTL, bus_cntl); 349 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 350 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 351 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 352 WREG32(R600_ROM_CNTL, rom_cntl); 353 return r; 354 } 355 356 static bool r600_read_disabled_bios(struct radeon_device *rdev) 357 { 358 uint32_t viph_control; 359 uint32_t bus_cntl; 360 uint32_t d1vga_control; 361 uint32_t d2vga_control; 362 uint32_t vga_render_control; 363 uint32_t rom_cntl; 364 uint32_t general_pwrmgt; 365 uint32_t low_vid_lower_gpio_cntl; 366 uint32_t medium_vid_lower_gpio_cntl; 367 uint32_t high_vid_lower_gpio_cntl; 368 uint32_t ctxsw_vid_lower_gpio_cntl; 369 uint32_t lower_gpio_enable; 370 bool r; 371 372 viph_control = RREG32(RADEON_VIPH_CONTROL); 373 bus_cntl = RREG32(R600_BUS_CNTL); 374 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 375 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 376 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 377 rom_cntl = RREG32(R600_ROM_CNTL); 378 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 379 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 380 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 381 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 382 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 383 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 384 385 /* disable VIP */ 386 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 387 /* enable the rom */ 388 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 389 /* Disable VGA mode */ 390 WREG32(AVIVO_D1VGA_CONTROL, 391 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 392 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 393 WREG32(AVIVO_D2VGA_CONTROL, 394 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 395 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 396 WREG32(AVIVO_VGA_RENDER_CONTROL, 397 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 398 399 WREG32(R600_ROM_CNTL, 400 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 401 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 402 R600_SCK_OVERWRITE)); 403 404 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 405 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 406 (low_vid_lower_gpio_cntl & ~0x400)); 407 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 408 (medium_vid_lower_gpio_cntl & ~0x400)); 409 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 410 (high_vid_lower_gpio_cntl & ~0x400)); 411 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 412 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 413 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 414 415 r = radeon_read_bios(rdev); 416 417 /* restore regs */ 418 WREG32(RADEON_VIPH_CONTROL, viph_control); 419 WREG32(R600_BUS_CNTL, bus_cntl); 420 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 421 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 422 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 423 WREG32(R600_ROM_CNTL, rom_cntl); 424 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 425 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 426 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 427 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 428 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 429 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 430 return r; 431 } 432 433 static bool avivo_read_disabled_bios(struct radeon_device *rdev) 434 { 435 uint32_t seprom_cntl1; 436 uint32_t viph_control; 437 uint32_t bus_cntl; 438 uint32_t d1vga_control; 439 uint32_t d2vga_control; 440 uint32_t vga_render_control; 441 uint32_t gpiopad_a; 442 uint32_t gpiopad_en; 443 uint32_t gpiopad_mask; 444 bool r; 445 446 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 447 viph_control = RREG32(RADEON_VIPH_CONTROL); 448 bus_cntl = RREG32(RV370_BUS_CNTL); 449 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 450 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 451 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 452 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 453 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 454 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 455 456 WREG32(RADEON_SEPROM_CNTL1, 457 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 458 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 459 WREG32(RADEON_GPIOPAD_A, 0); 460 WREG32(RADEON_GPIOPAD_EN, 0); 461 WREG32(RADEON_GPIOPAD_MASK, 0); 462 463 /* disable VIP */ 464 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 465 466 /* enable the rom */ 467 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 468 469 /* Disable VGA mode */ 470 WREG32(AVIVO_D1VGA_CONTROL, 471 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 472 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 473 WREG32(AVIVO_D2VGA_CONTROL, 474 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 475 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 476 WREG32(AVIVO_VGA_RENDER_CONTROL, 477 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 478 479 r = radeon_read_bios(rdev); 480 481 /* restore regs */ 482 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 483 WREG32(RADEON_VIPH_CONTROL, viph_control); 484 WREG32(RV370_BUS_CNTL, bus_cntl); 485 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 486 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 487 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 488 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 489 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 490 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 491 return r; 492 } 493 494 static bool legacy_read_disabled_bios(struct radeon_device *rdev) 495 { 496 uint32_t seprom_cntl1; 497 uint32_t viph_control; 498 uint32_t bus_cntl; 499 uint32_t crtc_gen_cntl; 500 uint32_t crtc2_gen_cntl; 501 uint32_t crtc_ext_cntl; 502 uint32_t fp2_gen_cntl; 503 bool r; 504 505 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 506 viph_control = RREG32(RADEON_VIPH_CONTROL); 507 if (rdev->flags & RADEON_IS_PCIE) 508 bus_cntl = RREG32(RV370_BUS_CNTL); 509 else 510 bus_cntl = RREG32(RADEON_BUS_CNTL); 511 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 512 crtc2_gen_cntl = 0; 513 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 514 fp2_gen_cntl = 0; 515 516 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 517 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 518 } 519 520 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 521 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 522 } 523 524 WREG32(RADEON_SEPROM_CNTL1, 525 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 526 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 527 528 /* disable VIP */ 529 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 530 531 /* enable the rom */ 532 if (rdev->flags & RADEON_IS_PCIE) 533 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 534 else 535 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 536 537 /* Turn off mem requests and CRTC for both controllers */ 538 WREG32(RADEON_CRTC_GEN_CNTL, 539 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 540 (RADEON_CRTC_DISP_REQ_EN_B | 541 RADEON_CRTC_EXT_DISP_EN))); 542 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 543 WREG32(RADEON_CRTC2_GEN_CNTL, 544 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 545 RADEON_CRTC2_DISP_REQ_EN_B)); 546 } 547 /* Turn off CRTC */ 548 WREG32(RADEON_CRTC_EXT_CNTL, 549 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 550 (RADEON_CRTC_SYNC_TRISTAT | 551 RADEON_CRTC_DISPLAY_DIS))); 552 553 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 554 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 555 } 556 557 r = radeon_read_bios(rdev); 558 559 /* restore regs */ 560 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 561 WREG32(RADEON_VIPH_CONTROL, viph_control); 562 if (rdev->flags & RADEON_IS_PCIE) 563 WREG32(RV370_BUS_CNTL, bus_cntl); 564 else 565 WREG32(RADEON_BUS_CNTL, bus_cntl); 566 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 567 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 568 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 569 } 570 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 571 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 572 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 573 } 574 return r; 575 } 576 577 static bool radeon_read_disabled_bios(struct radeon_device *rdev) 578 { 579 if (rdev->flags & RADEON_IS_IGP) 580 return igp_read_bios_from_vram(rdev); 581 else if (rdev->family >= CHIP_BARTS) 582 return ni_read_disabled_bios(rdev); 583 else if (rdev->family >= CHIP_RV770) 584 return r700_read_disabled_bios(rdev); 585 else if (rdev->family >= CHIP_R600) 586 return r600_read_disabled_bios(rdev); 587 else if (rdev->family >= CHIP_RS600) 588 return avivo_read_disabled_bios(rdev); 589 else 590 return legacy_read_disabled_bios(rdev); 591 } 592 593 #ifdef CONFIG_ACPI 594 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 595 { 596 bool ret = false; 597 struct acpi_table_header *hdr; 598 acpi_size tbl_size; 599 UEFI_ACPI_VFCT *vfct; 600 GOP_VBIOS_CONTENT *vbios; 601 VFCT_IMAGE_HEADER *vhdr; 602 603 if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size))) 604 return false; 605 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { 606 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); 607 goto out_unmap; 608 } 609 610 vfct = (UEFI_ACPI_VFCT *)hdr; 611 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) { 612 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); 613 goto out_unmap; 614 } 615 616 vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset); 617 vhdr = &vbios->VbiosHeader; 618 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n", 619 vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction, 620 vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength); 621 622 if (vhdr->PCIBus != rdev->pdev->bus->number || 623 vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) || 624 vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) || 625 vhdr->VendorID != rdev->pdev->vendor || 626 vhdr->DeviceID != rdev->pdev->device) { 627 DRM_INFO("ACPI VFCT table is not for this card\n"); 628 goto out_unmap; 629 } 630 631 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) { 632 DRM_ERROR("ACPI VFCT image truncated\n"); 633 goto out_unmap; 634 } 635 636 rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL); 637 ret = !!rdev->bios; 638 639 out_unmap: 640 return ret; 641 } 642 #else 643 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 644 { 645 return false; 646 } 647 #endif 648 649 bool radeon_get_bios(struct radeon_device *rdev) 650 { 651 bool r; 652 uint16_t tmp; 653 654 r = radeon_atrm_get_bios(rdev); 655 if (r == false) 656 r = radeon_acpi_vfct_bios(rdev); 657 if (r == false) 658 r = igp_read_bios_from_vram(rdev); 659 if (r == false) 660 r = radeon_read_bios(rdev); 661 if (r == false) { 662 r = radeon_read_disabled_bios(rdev); 663 } 664 if (r == false) { 665 r = radeon_read_platform_bios(rdev); 666 } 667 if (r == false || rdev->bios == NULL) { 668 DRM_ERROR("Unable to locate a BIOS ROM\n"); 669 rdev->bios = NULL; 670 return false; 671 } 672 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 673 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 674 goto free_bios; 675 } 676 677 tmp = RBIOS16(0x18); 678 if (RBIOS8(tmp + 0x14) != 0x0) { 679 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 680 goto free_bios; 681 } 682 683 rdev->bios_header_start = RBIOS16(0x48); 684 if (!rdev->bios_header_start) { 685 goto free_bios; 686 } 687 tmp = rdev->bios_header_start + 4; 688 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 689 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 690 rdev->is_atom_bios = true; 691 } else { 692 rdev->is_atom_bios = false; 693 } 694 695 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 696 return true; 697 free_bios: 698 kfree(rdev->bios); 699 rdev->bios = NULL; 700 return false; 701 } 702