1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include "drmP.h" 27 #include "radeon_drm.h" 28 #include "radeon.h" 29 30 #include "atom.h" 31 #include "atom-bits.h" 32 33 /* from radeon_encoder.c */ 34 extern uint32_t 35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, 36 uint8_t dac); 37 extern void radeon_link_encoder_connector(struct drm_device *dev); 38 extern void 39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, 40 uint32_t supported_device); 41 42 /* from radeon_connector.c */ 43 extern void 44 radeon_add_atom_connector(struct drm_device *dev, 45 uint32_t connector_id, 46 uint32_t supported_device, 47 int connector_type, 48 struct radeon_i2c_bus_rec *i2c_bus, 49 bool linkb, uint32_t igp_lane_info); 50 51 /* from radeon_legacy_encoder.c */ 52 extern void 53 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, 54 uint32_t supported_device); 55 56 union atom_supported_devices { 57 struct _ATOM_SUPPORTED_DEVICES_INFO info; 58 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2; 59 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1; 60 }; 61 62 static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device 63 *dev, uint8_t id) 64 { 65 struct radeon_device *rdev = dev->dev_private; 66 struct atom_context *ctx = rdev->mode_info.atom_context; 67 ATOM_GPIO_I2C_ASSIGMENT gpio; 68 struct radeon_i2c_bus_rec i2c; 69 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 70 struct _ATOM_GPIO_I2C_INFO *i2c_info; 71 uint16_t data_offset; 72 73 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 74 i2c.valid = false; 75 76 atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset); 77 78 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 79 80 gpio = i2c_info->asGPIO_Info[id]; 81 82 i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4; 83 i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4; 84 i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4; 85 i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4; 86 i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4; 87 i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4; 88 i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4; 89 i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4; 90 i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift); 91 i2c.mask_data_mask = (1 << gpio.ucDataMaskShift); 92 i2c.put_clk_mask = (1 << gpio.ucClkEnShift); 93 i2c.put_data_mask = (1 << gpio.ucDataEnShift); 94 i2c.get_clk_mask = (1 << gpio.ucClkY_Shift); 95 i2c.get_data_mask = (1 << gpio.ucDataY_Shift); 96 i2c.a_clk_mask = (1 << gpio.ucClkA_Shift); 97 i2c.a_data_mask = (1 << gpio.ucDataA_Shift); 98 i2c.valid = true; 99 100 return i2c; 101 } 102 103 static bool radeon_atom_apply_quirks(struct drm_device *dev, 104 uint32_t supported_device, 105 int *connector_type, 106 struct radeon_i2c_bus_rec *i2c_bus, 107 uint8_t *line_mux) 108 { 109 110 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ 111 if ((dev->pdev->device == 0x791e) && 112 (dev->pdev->subsystem_vendor == 0x1043) && 113 (dev->pdev->subsystem_device == 0x826d)) { 114 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && 115 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 116 *connector_type = DRM_MODE_CONNECTOR_DVID; 117 } 118 119 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */ 120 if ((dev->pdev->device == 0x7941) && 121 (dev->pdev->subsystem_vendor == 0x147b) && 122 (dev->pdev->subsystem_device == 0x2412)) { 123 if (*connector_type == DRM_MODE_CONNECTOR_DVII) 124 return false; 125 } 126 127 /* Falcon NW laptop lists vga ddc line for LVDS */ 128 if ((dev->pdev->device == 0x5653) && 129 (dev->pdev->subsystem_vendor == 0x1462) && 130 (dev->pdev->subsystem_device == 0x0291)) { 131 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) { 132 i2c_bus->valid = false; 133 *line_mux = 53; 134 } 135 } 136 137 /* Funky macbooks */ 138 if ((dev->pdev->device == 0x71C5) && 139 (dev->pdev->subsystem_vendor == 0x106b) && 140 (dev->pdev->subsystem_device == 0x0080)) { 141 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) || 142 (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) 143 return false; 144 } 145 146 /* some BIOSes seem to report DAC on HDMI - they hurt me with their lies */ 147 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) || 148 (*connector_type == DRM_MODE_CONNECTOR_HDMIB)) { 149 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { 150 return false; 151 } 152 } 153 154 /* ASUS HD 3600 XT board lists the DVI port as HDMI */ 155 if ((dev->pdev->device == 0x9598) && 156 (dev->pdev->subsystem_vendor == 0x1043) && 157 (dev->pdev->subsystem_device == 0x01da)) { 158 if (*connector_type == DRM_MODE_CONNECTOR_HDMIB) { 159 *connector_type = DRM_MODE_CONNECTOR_DVID; 160 } 161 } 162 163 return true; 164 } 165 166 const int supported_devices_connector_convert[] = { 167 DRM_MODE_CONNECTOR_Unknown, 168 DRM_MODE_CONNECTOR_VGA, 169 DRM_MODE_CONNECTOR_DVII, 170 DRM_MODE_CONNECTOR_DVID, 171 DRM_MODE_CONNECTOR_DVIA, 172 DRM_MODE_CONNECTOR_SVIDEO, 173 DRM_MODE_CONNECTOR_Composite, 174 DRM_MODE_CONNECTOR_LVDS, 175 DRM_MODE_CONNECTOR_Unknown, 176 DRM_MODE_CONNECTOR_Unknown, 177 DRM_MODE_CONNECTOR_HDMIA, 178 DRM_MODE_CONNECTOR_HDMIB, 179 DRM_MODE_CONNECTOR_Unknown, 180 DRM_MODE_CONNECTOR_Unknown, 181 DRM_MODE_CONNECTOR_9PinDIN, 182 DRM_MODE_CONNECTOR_DisplayPort 183 }; 184 185 const int object_connector_convert[] = { 186 DRM_MODE_CONNECTOR_Unknown, 187 DRM_MODE_CONNECTOR_DVII, 188 DRM_MODE_CONNECTOR_DVII, 189 DRM_MODE_CONNECTOR_DVID, 190 DRM_MODE_CONNECTOR_DVID, 191 DRM_MODE_CONNECTOR_VGA, 192 DRM_MODE_CONNECTOR_Composite, 193 DRM_MODE_CONNECTOR_SVIDEO, 194 DRM_MODE_CONNECTOR_Unknown, 195 DRM_MODE_CONNECTOR_9PinDIN, 196 DRM_MODE_CONNECTOR_Unknown, 197 DRM_MODE_CONNECTOR_HDMIA, 198 DRM_MODE_CONNECTOR_HDMIB, 199 DRM_MODE_CONNECTOR_HDMIB, 200 DRM_MODE_CONNECTOR_LVDS, 201 DRM_MODE_CONNECTOR_9PinDIN, 202 DRM_MODE_CONNECTOR_Unknown, 203 DRM_MODE_CONNECTOR_Unknown, 204 DRM_MODE_CONNECTOR_Unknown, 205 DRM_MODE_CONNECTOR_DisplayPort 206 }; 207 208 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) 209 { 210 struct radeon_device *rdev = dev->dev_private; 211 struct radeon_mode_info *mode_info = &rdev->mode_info; 212 struct atom_context *ctx = mode_info->atom_context; 213 int index = GetIndexIntoMasterTable(DATA, Object_Header); 214 uint16_t size, data_offset; 215 uint8_t frev, crev, line_mux = 0; 216 ATOM_CONNECTOR_OBJECT_TABLE *con_obj; 217 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; 218 ATOM_OBJECT_HEADER *obj_header; 219 int i, j, path_size, device_support; 220 int connector_type; 221 uint16_t igp_lane_info; 222 bool linkb; 223 struct radeon_i2c_bus_rec ddc_bus; 224 225 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset); 226 227 if (data_offset == 0) 228 return false; 229 230 if (crev < 2) 231 return false; 232 233 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); 234 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) 235 (ctx->bios + data_offset + 236 le16_to_cpu(obj_header->usDisplayPathTableOffset)); 237 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) 238 (ctx->bios + data_offset + 239 le16_to_cpu(obj_header->usConnectorObjectTableOffset)); 240 device_support = le16_to_cpu(obj_header->usDeviceSupport); 241 242 path_size = 0; 243 for (i = 0; i < path_obj->ucNumOfDispPath; i++) { 244 uint8_t *addr = (uint8_t *) path_obj->asDispPath; 245 ATOM_DISPLAY_OBJECT_PATH *path; 246 addr += path_size; 247 path = (ATOM_DISPLAY_OBJECT_PATH *) addr; 248 path_size += le16_to_cpu(path->usSize); 249 linkb = false; 250 251 if (device_support & le16_to_cpu(path->usDeviceTag)) { 252 uint8_t con_obj_id, con_obj_num, con_obj_type; 253 254 con_obj_id = 255 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) 256 >> OBJECT_ID_SHIFT; 257 con_obj_num = 258 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) 259 >> ENUM_ID_SHIFT; 260 con_obj_type = 261 (le16_to_cpu(path->usConnObjectId) & 262 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 263 264 if ((le16_to_cpu(path->usDeviceTag) == 265 ATOM_DEVICE_TV1_SUPPORT) 266 || (le16_to_cpu(path->usDeviceTag) == 267 ATOM_DEVICE_TV2_SUPPORT) 268 || (le16_to_cpu(path->usDeviceTag) == 269 ATOM_DEVICE_CV_SUPPORT)) 270 continue; 271 272 if ((rdev->family == CHIP_RS780) && 273 (con_obj_id == 274 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { 275 uint16_t igp_offset = 0; 276 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj; 277 278 index = 279 GetIndexIntoMasterTable(DATA, 280 IntegratedSystemInfo); 281 282 atom_parse_data_header(ctx, index, &size, &frev, 283 &crev, &igp_offset); 284 285 if (crev >= 2) { 286 igp_obj = 287 (ATOM_INTEGRATED_SYSTEM_INFO_V2 288 *) (ctx->bios + igp_offset); 289 290 if (igp_obj) { 291 uint32_t slot_config, ct; 292 293 if (con_obj_num == 1) 294 slot_config = 295 igp_obj-> 296 ulDDISlot1Config; 297 else 298 slot_config = 299 igp_obj-> 300 ulDDISlot2Config; 301 302 ct = (slot_config >> 16) & 0xff; 303 connector_type = 304 object_connector_convert 305 [ct]; 306 igp_lane_info = 307 slot_config & 0xffff; 308 } else 309 continue; 310 } else 311 continue; 312 } else { 313 igp_lane_info = 0; 314 connector_type = 315 object_connector_convert[con_obj_id]; 316 } 317 318 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 319 continue; 320 321 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); 322 j++) { 323 uint8_t enc_obj_id, enc_obj_num, enc_obj_type; 324 325 enc_obj_id = 326 (le16_to_cpu(path->usGraphicObjIds[j]) & 327 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 328 enc_obj_num = 329 (le16_to_cpu(path->usGraphicObjIds[j]) & 330 ENUM_ID_MASK) >> ENUM_ID_SHIFT; 331 enc_obj_type = 332 (le16_to_cpu(path->usGraphicObjIds[j]) & 333 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 334 335 /* FIXME: add support for router objects */ 336 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { 337 if (enc_obj_num == 2) 338 linkb = true; 339 else 340 linkb = false; 341 342 radeon_add_atom_encoder(dev, 343 enc_obj_id, 344 le16_to_cpu 345 (path-> 346 usDeviceTag)); 347 348 } 349 } 350 351 /* look up gpio for ddc */ 352 if ((le16_to_cpu(path->usDeviceTag) & 353 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 354 == 0) { 355 for (j = 0; j < con_obj->ucNumberOfObjects; j++) { 356 if (le16_to_cpu(path->usConnObjectId) == 357 le16_to_cpu(con_obj->asObjects[j]. 358 usObjectID)) { 359 ATOM_COMMON_RECORD_HEADER 360 *record = 361 (ATOM_COMMON_RECORD_HEADER 362 *) 363 (ctx->bios + data_offset + 364 le16_to_cpu(con_obj-> 365 asObjects[j]. 366 usRecordOffset)); 367 ATOM_I2C_RECORD *i2c_record; 368 369 while (record->ucRecordType > 0 370 && record-> 371 ucRecordType <= 372 ATOM_MAX_OBJECT_RECORD_NUMBER) { 373 DRM_ERROR 374 ("record type %d\n", 375 record-> 376 ucRecordType); 377 switch (record-> 378 ucRecordType) { 379 case ATOM_I2C_RECORD_TYPE: 380 i2c_record = 381 (ATOM_I2C_RECORD 382 *) record; 383 line_mux = 384 i2c_record-> 385 sucI2cId. 386 bfI2C_LineMux; 387 break; 388 } 389 record = 390 (ATOM_COMMON_RECORD_HEADER 391 *) ((char *)record 392 + 393 record-> 394 ucRecordSize); 395 } 396 break; 397 } 398 } 399 } else 400 line_mux = 0; 401 402 if ((le16_to_cpu(path->usDeviceTag) == 403 ATOM_DEVICE_TV1_SUPPORT) 404 || (le16_to_cpu(path->usDeviceTag) == 405 ATOM_DEVICE_TV2_SUPPORT) 406 || (le16_to_cpu(path->usDeviceTag) == 407 ATOM_DEVICE_CV_SUPPORT)) 408 ddc_bus.valid = false; 409 else 410 ddc_bus = radeon_lookup_gpio(dev, line_mux); 411 412 radeon_add_atom_connector(dev, 413 le16_to_cpu(path-> 414 usConnObjectId), 415 le16_to_cpu(path-> 416 usDeviceTag), 417 connector_type, &ddc_bus, 418 linkb, igp_lane_info); 419 420 } 421 } 422 423 radeon_link_encoder_connector(dev); 424 425 return true; 426 } 427 428 struct bios_connector { 429 bool valid; 430 uint8_t line_mux; 431 uint16_t devices; 432 int connector_type; 433 struct radeon_i2c_bus_rec ddc_bus; 434 }; 435 436 bool radeon_get_atom_connector_info_from_supported_devices_table(struct 437 drm_device 438 *dev) 439 { 440 struct radeon_device *rdev = dev->dev_private; 441 struct radeon_mode_info *mode_info = &rdev->mode_info; 442 struct atom_context *ctx = mode_info->atom_context; 443 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo); 444 uint16_t size, data_offset; 445 uint8_t frev, crev; 446 uint16_t device_support; 447 uint8_t dac; 448 union atom_supported_devices *supported_devices; 449 int i, j; 450 struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE]; 451 452 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset); 453 454 supported_devices = 455 (union atom_supported_devices *)(ctx->bios + data_offset); 456 457 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport); 458 459 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { 460 ATOM_CONNECTOR_INFO_I2C ci = 461 supported_devices->info.asConnInfo[i]; 462 463 bios_connectors[i].valid = false; 464 465 if (!(device_support & (1 << i))) { 466 continue; 467 } 468 469 if (i == ATOM_DEVICE_CV_INDEX) { 470 DRM_DEBUG("Skipping Component Video\n"); 471 continue; 472 } 473 474 if (i == ATOM_DEVICE_TV1_INDEX) { 475 DRM_DEBUG("Skipping TV Out\n"); 476 continue; 477 } 478 479 bios_connectors[i].connector_type = 480 supported_devices_connector_convert[ci.sucConnectorInfo. 481 sbfAccess. 482 bfConnectorType]; 483 484 if (bios_connectors[i].connector_type == 485 DRM_MODE_CONNECTOR_Unknown) 486 continue; 487 488 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; 489 490 if ((rdev->family == CHIP_RS690) || 491 (rdev->family == CHIP_RS740)) { 492 if ((i == ATOM_DEVICE_DFP2_INDEX) 493 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2)) 494 bios_connectors[i].line_mux = 495 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1; 496 else if ((i == ATOM_DEVICE_DFP3_INDEX) 497 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1)) 498 bios_connectors[i].line_mux = 499 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1; 500 else 501 bios_connectors[i].line_mux = 502 ci.sucI2cId.sbfAccess.bfI2C_LineMux; 503 } else 504 bios_connectors[i].line_mux = 505 ci.sucI2cId.sbfAccess.bfI2C_LineMux; 506 507 /* give tv unique connector ids */ 508 if (i == ATOM_DEVICE_TV1_INDEX) { 509 bios_connectors[i].ddc_bus.valid = false; 510 bios_connectors[i].line_mux = 50; 511 } else if (i == ATOM_DEVICE_TV2_INDEX) { 512 bios_connectors[i].ddc_bus.valid = false; 513 bios_connectors[i].line_mux = 51; 514 } else if (i == ATOM_DEVICE_CV_INDEX) { 515 bios_connectors[i].ddc_bus.valid = false; 516 bios_connectors[i].line_mux = 52; 517 } else 518 bios_connectors[i].ddc_bus = 519 radeon_lookup_gpio(dev, 520 bios_connectors[i].line_mux); 521 522 /* Always set the connector type to VGA for CRT1/CRT2. if they are 523 * shared with a DVI port, we'll pick up the DVI connector when we 524 * merge the outputs. Some bioses incorrectly list VGA ports as DVI. 525 */ 526 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) 527 bios_connectors[i].connector_type = 528 DRM_MODE_CONNECTOR_VGA; 529 530 if (!radeon_atom_apply_quirks 531 (dev, (1 << i), &bios_connectors[i].connector_type, 532 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux)) 533 continue; 534 535 bios_connectors[i].valid = true; 536 bios_connectors[i].devices = (1 << i); 537 538 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) 539 radeon_add_atom_encoder(dev, 540 radeon_get_encoder_id(dev, 541 (1 << i), 542 dac), 543 (1 << i)); 544 else 545 radeon_add_legacy_encoder(dev, 546 radeon_get_encoder_id(dev, 547 (1 << 548 i), 549 dac), 550 (1 << i)); 551 } 552 553 /* combine shared connectors */ 554 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { 555 if (bios_connectors[i].valid) { 556 for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) { 557 if (bios_connectors[j].valid && (i != j)) { 558 if (bios_connectors[i].line_mux == 559 bios_connectors[j].line_mux) { 560 if (((bios_connectors[i]. 561 devices & 562 (ATOM_DEVICE_DFP_SUPPORT)) 563 && (bios_connectors[j]. 564 devices & 565 (ATOM_DEVICE_CRT_SUPPORT))) 566 || 567 ((bios_connectors[j]. 568 devices & 569 (ATOM_DEVICE_DFP_SUPPORT)) 570 && (bios_connectors[i]. 571 devices & 572 (ATOM_DEVICE_CRT_SUPPORT)))) { 573 bios_connectors[i]. 574 devices |= 575 bios_connectors[j]. 576 devices; 577 bios_connectors[i]. 578 connector_type = 579 DRM_MODE_CONNECTOR_DVII; 580 bios_connectors[j]. 581 valid = false; 582 } 583 } 584 } 585 } 586 } 587 } 588 589 /* add the connectors */ 590 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { 591 if (bios_connectors[i].valid) 592 radeon_add_atom_connector(dev, 593 bios_connectors[i].line_mux, 594 bios_connectors[i].devices, 595 bios_connectors[i]. 596 connector_type, 597 &bios_connectors[i].ddc_bus, 598 false, 0); 599 } 600 601 radeon_link_encoder_connector(dev); 602 603 return true; 604 } 605 606 union firmware_info { 607 ATOM_FIRMWARE_INFO info; 608 ATOM_FIRMWARE_INFO_V1_2 info_12; 609 ATOM_FIRMWARE_INFO_V1_3 info_13; 610 ATOM_FIRMWARE_INFO_V1_4 info_14; 611 }; 612 613 bool radeon_atom_get_clock_info(struct drm_device *dev) 614 { 615 struct radeon_device *rdev = dev->dev_private; 616 struct radeon_mode_info *mode_info = &rdev->mode_info; 617 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 618 union firmware_info *firmware_info; 619 uint8_t frev, crev; 620 struct radeon_pll *p1pll = &rdev->clock.p1pll; 621 struct radeon_pll *p2pll = &rdev->clock.p2pll; 622 struct radeon_pll *spll = &rdev->clock.spll; 623 struct radeon_pll *mpll = &rdev->clock.mpll; 624 uint16_t data_offset; 625 626 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, 627 &crev, &data_offset); 628 629 firmware_info = 630 (union firmware_info *)(mode_info->atom_context->bios + 631 data_offset); 632 633 if (firmware_info) { 634 /* pixel clocks */ 635 p1pll->reference_freq = 636 le16_to_cpu(firmware_info->info.usReferenceClock); 637 p1pll->reference_div = 0; 638 639 p1pll->pll_out_min = 640 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); 641 p1pll->pll_out_max = 642 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); 643 644 if (p1pll->pll_out_min == 0) { 645 if (ASIC_IS_AVIVO(rdev)) 646 p1pll->pll_out_min = 64800; 647 else 648 p1pll->pll_out_min = 20000; 649 } 650 651 p1pll->pll_in_min = 652 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); 653 p1pll->pll_in_max = 654 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); 655 656 *p2pll = *p1pll; 657 658 /* system clock */ 659 spll->reference_freq = 660 le16_to_cpu(firmware_info->info.usReferenceClock); 661 spll->reference_div = 0; 662 663 spll->pll_out_min = 664 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); 665 spll->pll_out_max = 666 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); 667 668 /* ??? */ 669 if (spll->pll_out_min == 0) { 670 if (ASIC_IS_AVIVO(rdev)) 671 spll->pll_out_min = 64800; 672 else 673 spll->pll_out_min = 20000; 674 } 675 676 spll->pll_in_min = 677 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); 678 spll->pll_in_max = 679 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); 680 681 /* memory clock */ 682 mpll->reference_freq = 683 le16_to_cpu(firmware_info->info.usReferenceClock); 684 mpll->reference_div = 0; 685 686 mpll->pll_out_min = 687 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); 688 mpll->pll_out_max = 689 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); 690 691 /* ??? */ 692 if (mpll->pll_out_min == 0) { 693 if (ASIC_IS_AVIVO(rdev)) 694 mpll->pll_out_min = 64800; 695 else 696 mpll->pll_out_min = 20000; 697 } 698 699 mpll->pll_in_min = 700 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); 701 mpll->pll_in_max = 702 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); 703 704 rdev->clock.default_sclk = 705 le32_to_cpu(firmware_info->info.ulDefaultEngineClock); 706 rdev->clock.default_mclk = 707 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); 708 709 return true; 710 } 711 return false; 712 } 713 714 struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct 715 radeon_encoder 716 *encoder) 717 { 718 struct drm_device *dev = encoder->base.dev; 719 struct radeon_device *rdev = dev->dev_private; 720 struct radeon_mode_info *mode_info = &rdev->mode_info; 721 int index = GetIndexIntoMasterTable(DATA, TMDS_Info); 722 uint16_t data_offset; 723 struct _ATOM_TMDS_INFO *tmds_info; 724 uint8_t frev, crev; 725 uint16_t maxfreq; 726 int i; 727 struct radeon_encoder_int_tmds *tmds = NULL; 728 729 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, 730 &crev, &data_offset); 731 732 tmds_info = 733 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios + 734 data_offset); 735 736 if (tmds_info) { 737 tmds = 738 kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL); 739 740 if (!tmds) 741 return NULL; 742 743 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); 744 for (i = 0; i < 4; i++) { 745 tmds->tmds_pll[i].freq = 746 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency); 747 tmds->tmds_pll[i].value = 748 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f; 749 tmds->tmds_pll[i].value |= 750 (tmds_info->asMiscInfo[i]. 751 ucPLL_VCO_Gain & 0x3f) << 6; 752 tmds->tmds_pll[i].value |= 753 (tmds_info->asMiscInfo[i]. 754 ucPLL_DutyCycle & 0xf) << 12; 755 tmds->tmds_pll[i].value |= 756 (tmds_info->asMiscInfo[i]. 757 ucPLL_VoltageSwing & 0xf) << 16; 758 759 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n", 760 tmds->tmds_pll[i].freq, 761 tmds->tmds_pll[i].value); 762 763 if (maxfreq == tmds->tmds_pll[i].freq) { 764 tmds->tmds_pll[i].freq = 0xffffffff; 765 break; 766 } 767 } 768 } 769 return tmds; 770 } 771 772 union lvds_info { 773 struct _ATOM_LVDS_INFO info; 774 struct _ATOM_LVDS_INFO_V12 info_12; 775 }; 776 777 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct 778 radeon_encoder 779 *encoder) 780 { 781 struct drm_device *dev = encoder->base.dev; 782 struct radeon_device *rdev = dev->dev_private; 783 struct radeon_mode_info *mode_info = &rdev->mode_info; 784 int index = GetIndexIntoMasterTable(DATA, LVDS_Info); 785 uint16_t data_offset; 786 union lvds_info *lvds_info; 787 uint8_t frev, crev; 788 struct radeon_encoder_atom_dig *lvds = NULL; 789 790 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, 791 &crev, &data_offset); 792 793 lvds_info = 794 (union lvds_info *)(mode_info->atom_context->bios + data_offset); 795 796 if (lvds_info) { 797 lvds = 798 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 799 800 if (!lvds) 801 return NULL; 802 803 lvds->native_mode.dotclock = 804 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; 805 lvds->native_mode.panel_xres = 806 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); 807 lvds->native_mode.panel_yres = 808 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); 809 lvds->native_mode.hblank = 810 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); 811 lvds->native_mode.hoverplus = 812 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); 813 lvds->native_mode.hsync_width = 814 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); 815 lvds->native_mode.vblank = 816 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); 817 lvds->native_mode.voverplus = 818 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset); 819 lvds->native_mode.vsync_width = 820 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); 821 lvds->panel_pwr_delay = 822 le16_to_cpu(lvds_info->info.usOffDelayInMs); 823 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc; 824 825 encoder->native_mode = lvds->native_mode; 826 } 827 return lvds; 828 } 829 830 struct radeon_encoder_primary_dac * 831 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) 832 { 833 struct drm_device *dev = encoder->base.dev; 834 struct radeon_device *rdev = dev->dev_private; 835 struct radeon_mode_info *mode_info = &rdev->mode_info; 836 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 837 uint16_t data_offset; 838 struct _COMPASSIONATE_DATA *dac_info; 839 uint8_t frev, crev; 840 uint8_t bg, dac; 841 struct radeon_encoder_primary_dac *p_dac = NULL; 842 843 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset); 844 845 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset); 846 847 if (dac_info) { 848 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL); 849 850 if (!p_dac) 851 return NULL; 852 853 bg = dac_info->ucDAC1_BG_Adjustment; 854 dac = dac_info->ucDAC1_DAC_Adjustment; 855 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 856 857 } 858 return p_dac; 859 } 860 861 struct radeon_encoder_tv_dac * 862 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) 863 { 864 struct drm_device *dev = encoder->base.dev; 865 struct radeon_device *rdev = dev->dev_private; 866 struct radeon_mode_info *mode_info = &rdev->mode_info; 867 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 868 uint16_t data_offset; 869 struct _COMPASSIONATE_DATA *dac_info; 870 uint8_t frev, crev; 871 uint8_t bg, dac; 872 struct radeon_encoder_tv_dac *tv_dac = NULL; 873 874 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset); 875 876 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset); 877 878 if (dac_info) { 879 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 880 881 if (!tv_dac) 882 return NULL; 883 884 bg = dac_info->ucDAC2_CRT2_BG_Adjustment; 885 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment; 886 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 887 888 bg = dac_info->ucDAC2_PAL_BG_Adjustment; 889 dac = dac_info->ucDAC2_PAL_DAC_Adjustment; 890 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 891 892 bg = dac_info->ucDAC2_NTSC_BG_Adjustment; 893 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment; 894 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 895 896 } 897 return tv_dac; 898 } 899 900 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) 901 { 902 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args; 903 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating); 904 905 args.ucEnable = enable; 906 907 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 908 } 909 910 void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable) 911 { 912 ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args; 913 int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt); 914 915 args.ucEnable = enable; 916 917 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 918 } 919 920 void radeon_atom_set_engine_clock(struct radeon_device *rdev, 921 uint32_t eng_clock) 922 { 923 SET_ENGINE_CLOCK_PS_ALLOCATION args; 924 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); 925 926 args.ulTargetEngineClock = eng_clock; /* 10 khz */ 927 928 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 929 } 930 931 void radeon_atom_set_memory_clock(struct radeon_device *rdev, 932 uint32_t mem_clock) 933 { 934 SET_MEMORY_CLOCK_PS_ALLOCATION args; 935 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); 936 937 if (rdev->flags & RADEON_IS_IGP) 938 return; 939 940 args.ulTargetMemoryClock = mem_clock; /* 10 khz */ 941 942 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 943 } 944 945 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) 946 { 947 struct radeon_device *rdev = dev->dev_private; 948 uint32_t bios_2_scratch, bios_6_scratch; 949 950 if (rdev->family >= CHIP_R600) { 951 bios_2_scratch = RREG32(R600_BIOS_0_SCRATCH); 952 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 953 } else { 954 bios_2_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 955 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 956 } 957 958 /* let the bios control the backlight */ 959 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; 960 961 /* tell the bios not to handle mode switching */ 962 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE); 963 964 if (rdev->family >= CHIP_R600) { 965 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 966 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 967 } else { 968 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 969 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 970 } 971 972 } 973 974 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) 975 { 976 struct drm_device *dev = encoder->dev; 977 struct radeon_device *rdev = dev->dev_private; 978 uint32_t bios_6_scratch; 979 980 if (rdev->family >= CHIP_R600) 981 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 982 else 983 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 984 985 if (lock) 986 bios_6_scratch |= ATOM_S6_CRITICAL_STATE; 987 else 988 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; 989 990 if (rdev->family >= CHIP_R600) 991 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 992 else 993 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 994 } 995 996 /* at some point we may want to break this out into individual functions */ 997 void 998 radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 999 struct drm_encoder *encoder, 1000 bool connected) 1001 { 1002 struct drm_device *dev = connector->dev; 1003 struct radeon_device *rdev = dev->dev_private; 1004 struct radeon_connector *radeon_connector = 1005 to_radeon_connector(connector); 1006 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1007 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch; 1008 1009 if (rdev->family >= CHIP_R600) { 1010 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 1011 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 1012 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 1013 } else { 1014 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 1015 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 1016 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 1017 } 1018 1019 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 1020 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 1021 if (connected) { 1022 DRM_DEBUG("TV1 connected\n"); 1023 bios_3_scratch |= ATOM_S3_TV1_ACTIVE; 1024 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1; 1025 } else { 1026 DRM_DEBUG("TV1 disconnected\n"); 1027 bios_0_scratch &= ~ATOM_S0_TV1_MASK; 1028 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; 1029 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1; 1030 } 1031 } 1032 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) && 1033 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) { 1034 if (connected) { 1035 DRM_DEBUG("CV connected\n"); 1036 bios_3_scratch |= ATOM_S3_CV_ACTIVE; 1037 bios_6_scratch |= ATOM_S6_ACC_REQ_CV; 1038 } else { 1039 DRM_DEBUG("CV disconnected\n"); 1040 bios_0_scratch &= ~ATOM_S0_CV_MASK; 1041 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; 1042 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV; 1043 } 1044 } 1045 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 1046 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 1047 if (connected) { 1048 DRM_DEBUG("LCD1 connected\n"); 1049 bios_0_scratch |= ATOM_S0_LCD1; 1050 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; 1051 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; 1052 } else { 1053 DRM_DEBUG("LCD1 disconnected\n"); 1054 bios_0_scratch &= ~ATOM_S0_LCD1; 1055 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; 1056 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; 1057 } 1058 } 1059 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 1060 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 1061 if (connected) { 1062 DRM_DEBUG("CRT1 connected\n"); 1063 bios_0_scratch |= ATOM_S0_CRT1_COLOR; 1064 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; 1065 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; 1066 } else { 1067 DRM_DEBUG("CRT1 disconnected\n"); 1068 bios_0_scratch &= ~ATOM_S0_CRT1_MASK; 1069 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; 1070 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; 1071 } 1072 } 1073 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 1074 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 1075 if (connected) { 1076 DRM_DEBUG("CRT2 connected\n"); 1077 bios_0_scratch |= ATOM_S0_CRT2_COLOR; 1078 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; 1079 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; 1080 } else { 1081 DRM_DEBUG("CRT2 disconnected\n"); 1082 bios_0_scratch &= ~ATOM_S0_CRT2_MASK; 1083 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; 1084 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; 1085 } 1086 } 1087 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 1088 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 1089 if (connected) { 1090 DRM_DEBUG("DFP1 connected\n"); 1091 bios_0_scratch |= ATOM_S0_DFP1; 1092 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; 1093 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; 1094 } else { 1095 DRM_DEBUG("DFP1 disconnected\n"); 1096 bios_0_scratch &= ~ATOM_S0_DFP1; 1097 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; 1098 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; 1099 } 1100 } 1101 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 1102 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 1103 if (connected) { 1104 DRM_DEBUG("DFP2 connected\n"); 1105 bios_0_scratch |= ATOM_S0_DFP2; 1106 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; 1107 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; 1108 } else { 1109 DRM_DEBUG("DFP2 disconnected\n"); 1110 bios_0_scratch &= ~ATOM_S0_DFP2; 1111 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; 1112 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; 1113 } 1114 } 1115 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && 1116 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { 1117 if (connected) { 1118 DRM_DEBUG("DFP3 connected\n"); 1119 bios_0_scratch |= ATOM_S0_DFP3; 1120 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; 1121 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; 1122 } else { 1123 DRM_DEBUG("DFP3 disconnected\n"); 1124 bios_0_scratch &= ~ATOM_S0_DFP3; 1125 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; 1126 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; 1127 } 1128 } 1129 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && 1130 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { 1131 if (connected) { 1132 DRM_DEBUG("DFP4 connected\n"); 1133 bios_0_scratch |= ATOM_S0_DFP4; 1134 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; 1135 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; 1136 } else { 1137 DRM_DEBUG("DFP4 disconnected\n"); 1138 bios_0_scratch &= ~ATOM_S0_DFP4; 1139 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; 1140 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; 1141 } 1142 } 1143 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && 1144 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { 1145 if (connected) { 1146 DRM_DEBUG("DFP5 connected\n"); 1147 bios_0_scratch |= ATOM_S0_DFP5; 1148 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; 1149 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; 1150 } else { 1151 DRM_DEBUG("DFP5 disconnected\n"); 1152 bios_0_scratch &= ~ATOM_S0_DFP5; 1153 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; 1154 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; 1155 } 1156 } 1157 1158 if (rdev->family >= CHIP_R600) { 1159 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); 1160 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 1161 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 1162 } else { 1163 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 1164 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 1165 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 1166 } 1167 } 1168 1169 void 1170 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 1171 { 1172 struct drm_device *dev = encoder->dev; 1173 struct radeon_device *rdev = dev->dev_private; 1174 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1175 uint32_t bios_3_scratch; 1176 1177 if (rdev->family >= CHIP_R600) 1178 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 1179 else 1180 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 1181 1182 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 1183 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE; 1184 bios_3_scratch |= (crtc << 18); 1185 } 1186 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 1187 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE; 1188 bios_3_scratch |= (crtc << 24); 1189 } 1190 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 1191 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE; 1192 bios_3_scratch |= (crtc << 16); 1193 } 1194 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 1195 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE; 1196 bios_3_scratch |= (crtc << 20); 1197 } 1198 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 1199 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE; 1200 bios_3_scratch |= (crtc << 17); 1201 } 1202 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 1203 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE; 1204 bios_3_scratch |= (crtc << 19); 1205 } 1206 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 1207 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE; 1208 bios_3_scratch |= (crtc << 23); 1209 } 1210 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 1211 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE; 1212 bios_3_scratch |= (crtc << 25); 1213 } 1214 1215 if (rdev->family >= CHIP_R600) 1216 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 1217 else 1218 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 1219 } 1220 1221 void 1222 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 1223 { 1224 struct drm_device *dev = encoder->dev; 1225 struct radeon_device *rdev = dev->dev_private; 1226 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1227 uint32_t bios_2_scratch; 1228 1229 if (rdev->family >= CHIP_R600) 1230 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 1231 else 1232 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 1233 1234 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 1235 if (on) 1236 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE; 1237 else 1238 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE; 1239 } 1240 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 1241 if (on) 1242 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE; 1243 else 1244 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE; 1245 } 1246 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 1247 if (on) 1248 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE; 1249 else 1250 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE; 1251 } 1252 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 1253 if (on) 1254 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE; 1255 else 1256 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE; 1257 } 1258 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 1259 if (on) 1260 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE; 1261 else 1262 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE; 1263 } 1264 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 1265 if (on) 1266 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE; 1267 else 1268 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE; 1269 } 1270 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 1271 if (on) 1272 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE; 1273 else 1274 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE; 1275 } 1276 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 1277 if (on) 1278 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE; 1279 else 1280 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE; 1281 } 1282 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) { 1283 if (on) 1284 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE; 1285 else 1286 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE; 1287 } 1288 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) { 1289 if (on) 1290 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE; 1291 else 1292 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE; 1293 } 1294 1295 if (rdev->family >= CHIP_R600) 1296 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 1297 else 1298 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 1299 } 1300