1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/radeon_drm.h> 28 #include "radeon.h" 29 30 #include "atom.h" 31 #include "atom-bits.h" 32 33 extern void 34 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, 35 uint32_t supported_device, u16 caps); 36 37 /* from radeon_legacy_encoder.c */ 38 extern void 39 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, 40 uint32_t supported_device); 41 42 union atom_supported_devices { 43 struct _ATOM_SUPPORTED_DEVICES_INFO info; 44 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2; 45 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1; 46 }; 47 48 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev, 49 ATOM_GPIO_I2C_ASSIGMENT *gpio, 50 u8 index) 51 { 52 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */ 53 if ((rdev->family == CHIP_R420) || 54 (rdev->family == CHIP_R423) || 55 (rdev->family == CHIP_RV410)) { 56 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) || 57 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) || 58 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) { 59 gpio->ucClkMaskShift = 0x19; 60 gpio->ucDataMaskShift = 0x18; 61 } 62 } 63 64 /* some evergreen boards have bad data for this entry */ 65 if (ASIC_IS_DCE4(rdev)) { 66 if ((index == 7) && 67 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) && 68 (gpio->sucI2cId.ucAccess == 0)) { 69 gpio->sucI2cId.ucAccess = 0x97; 70 gpio->ucDataMaskShift = 8; 71 gpio->ucDataEnShift = 8; 72 gpio->ucDataY_Shift = 8; 73 gpio->ucDataA_Shift = 8; 74 } 75 } 76 77 /* some DCE3 boards have bad data for this entry */ 78 if (ASIC_IS_DCE3(rdev)) { 79 if ((index == 4) && 80 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) && 81 (gpio->sucI2cId.ucAccess == 0x94)) 82 gpio->sucI2cId.ucAccess = 0x14; 83 } 84 } 85 86 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio) 87 { 88 struct radeon_i2c_bus_rec i2c; 89 90 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 91 92 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; 93 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; 94 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4; 95 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4; 96 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4; 97 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4; 98 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4; 99 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4; 100 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); 101 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); 102 i2c.en_clk_mask = (1 << gpio->ucClkEnShift); 103 i2c.en_data_mask = (1 << gpio->ucDataEnShift); 104 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); 105 i2c.y_data_mask = (1 << gpio->ucDataY_Shift); 106 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); 107 i2c.a_data_mask = (1 << gpio->ucDataA_Shift); 108 109 if (gpio->sucI2cId.sbfAccess.bfHW_Capable) 110 i2c.hw_capable = true; 111 else 112 i2c.hw_capable = false; 113 114 if (gpio->sucI2cId.ucAccess == 0xa0) 115 i2c.mm_i2c = true; 116 else 117 i2c.mm_i2c = false; 118 119 i2c.i2c_id = gpio->sucI2cId.ucAccess; 120 121 if (i2c.mask_clk_reg) 122 i2c.valid = true; 123 else 124 i2c.valid = false; 125 126 return i2c; 127 } 128 129 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev, 130 uint8_t id) 131 { 132 struct atom_context *ctx = rdev->mode_info.atom_context; 133 ATOM_GPIO_I2C_ASSIGMENT *gpio; 134 struct radeon_i2c_bus_rec i2c; 135 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 136 struct _ATOM_GPIO_I2C_INFO *i2c_info; 137 uint16_t data_offset, size; 138 int i, num_indices; 139 140 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 141 i2c.valid = false; 142 143 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 144 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 145 146 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 147 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 148 149 gpio = &i2c_info->asGPIO_Info[0]; 150 for (i = 0; i < num_indices; i++) { 151 152 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); 153 154 if (gpio->sucI2cId.ucAccess == id) { 155 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); 156 break; 157 } 158 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 159 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 160 } 161 } 162 163 return i2c; 164 } 165 166 void radeon_atombios_i2c_init(struct radeon_device *rdev) 167 { 168 struct atom_context *ctx = rdev->mode_info.atom_context; 169 ATOM_GPIO_I2C_ASSIGMENT *gpio; 170 struct radeon_i2c_bus_rec i2c; 171 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 172 struct _ATOM_GPIO_I2C_INFO *i2c_info; 173 uint16_t data_offset, size; 174 int i, num_indices; 175 char stmp[32]; 176 177 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 178 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 179 180 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 181 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 182 183 gpio = &i2c_info->asGPIO_Info[0]; 184 for (i = 0; i < num_indices; i++) { 185 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); 186 187 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); 188 189 if (i2c.valid) { 190 sprintf(stmp, "0x%x", i2c.i2c_id); 191 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp); 192 } 193 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 194 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 195 } 196 } 197 } 198 199 struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev, 200 u8 id) 201 { 202 struct atom_context *ctx = rdev->mode_info.atom_context; 203 struct radeon_gpio_rec gpio; 204 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); 205 struct _ATOM_GPIO_PIN_LUT *gpio_info; 206 ATOM_GPIO_PIN_ASSIGNMENT *pin; 207 u16 data_offset, size; 208 int i, num_indices; 209 210 memset(&gpio, 0, sizeof(struct radeon_gpio_rec)); 211 gpio.valid = false; 212 213 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 214 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset); 215 216 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 217 sizeof(ATOM_GPIO_PIN_ASSIGNMENT); 218 219 pin = gpio_info->asGPIO_Pin; 220 for (i = 0; i < num_indices; i++) { 221 if (id == pin->ucGPIO_ID) { 222 gpio.id = pin->ucGPIO_ID; 223 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4; 224 gpio.shift = pin->ucGpioPinBitShift; 225 gpio.mask = (1 << pin->ucGpioPinBitShift); 226 gpio.valid = true; 227 break; 228 } 229 pin = (ATOM_GPIO_PIN_ASSIGNMENT *) 230 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT)); 231 } 232 } 233 234 return gpio; 235 } 236 237 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev, 238 struct radeon_gpio_rec *gpio) 239 { 240 struct radeon_hpd hpd; 241 u32 reg; 242 243 memset(&hpd, 0, sizeof(struct radeon_hpd)); 244 245 if (ASIC_IS_DCE6(rdev)) 246 reg = SI_DC_GPIO_HPD_A; 247 else if (ASIC_IS_DCE4(rdev)) 248 reg = EVERGREEN_DC_GPIO_HPD_A; 249 else 250 reg = AVIVO_DC_GPIO_HPD_A; 251 252 hpd.gpio = *gpio; 253 if (gpio->reg == reg) { 254 switch(gpio->mask) { 255 case (1 << 0): 256 hpd.hpd = RADEON_HPD_1; 257 break; 258 case (1 << 8): 259 hpd.hpd = RADEON_HPD_2; 260 break; 261 case (1 << 16): 262 hpd.hpd = RADEON_HPD_3; 263 break; 264 case (1 << 24): 265 hpd.hpd = RADEON_HPD_4; 266 break; 267 case (1 << 26): 268 hpd.hpd = RADEON_HPD_5; 269 break; 270 case (1 << 28): 271 hpd.hpd = RADEON_HPD_6; 272 break; 273 default: 274 hpd.hpd = RADEON_HPD_NONE; 275 break; 276 } 277 } else 278 hpd.hpd = RADEON_HPD_NONE; 279 return hpd; 280 } 281 282 static bool radeon_atom_apply_quirks(struct drm_device *dev, 283 uint32_t supported_device, 284 int *connector_type, 285 struct radeon_i2c_bus_rec *i2c_bus, 286 uint16_t *line_mux, 287 struct radeon_hpd *hpd) 288 { 289 290 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ 291 if ((dev->pdev->device == 0x791e) && 292 (dev->pdev->subsystem_vendor == 0x1043) && 293 (dev->pdev->subsystem_device == 0x826d)) { 294 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && 295 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 296 *connector_type = DRM_MODE_CONNECTOR_DVID; 297 } 298 299 /* Asrock RS600 board lists the DVI port as HDMI */ 300 if ((dev->pdev->device == 0x7941) && 301 (dev->pdev->subsystem_vendor == 0x1849) && 302 (dev->pdev->subsystem_device == 0x7941)) { 303 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && 304 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 305 *connector_type = DRM_MODE_CONNECTOR_DVID; 306 } 307 308 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */ 309 if ((dev->pdev->device == 0x796e) && 310 (dev->pdev->subsystem_vendor == 0x1462) && 311 (dev->pdev->subsystem_device == 0x7302)) { 312 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) || 313 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 314 return false; 315 } 316 317 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */ 318 if ((dev->pdev->device == 0x7941) && 319 (dev->pdev->subsystem_vendor == 0x147b) && 320 (dev->pdev->subsystem_device == 0x2412)) { 321 if (*connector_type == DRM_MODE_CONNECTOR_DVII) 322 return false; 323 } 324 325 /* Falcon NW laptop lists vga ddc line for LVDS */ 326 if ((dev->pdev->device == 0x5653) && 327 (dev->pdev->subsystem_vendor == 0x1462) && 328 (dev->pdev->subsystem_device == 0x0291)) { 329 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) { 330 i2c_bus->valid = false; 331 *line_mux = 53; 332 } 333 } 334 335 /* HIS X1300 is DVI+VGA, not DVI+DVI */ 336 if ((dev->pdev->device == 0x7146) && 337 (dev->pdev->subsystem_vendor == 0x17af) && 338 (dev->pdev->subsystem_device == 0x2058)) { 339 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) 340 return false; 341 } 342 343 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */ 344 if ((dev->pdev->device == 0x7142) && 345 (dev->pdev->subsystem_vendor == 0x1458) && 346 (dev->pdev->subsystem_device == 0x2134)) { 347 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) 348 return false; 349 } 350 351 352 /* Funky macbooks */ 353 if ((dev->pdev->device == 0x71C5) && 354 (dev->pdev->subsystem_vendor == 0x106b) && 355 (dev->pdev->subsystem_device == 0x0080)) { 356 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) || 357 (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) 358 return false; 359 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT) 360 *line_mux = 0x90; 361 } 362 363 /* mac rv630, rv730, others */ 364 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) && 365 (*connector_type == DRM_MODE_CONNECTOR_DVII)) { 366 *connector_type = DRM_MODE_CONNECTOR_9PinDIN; 367 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1; 368 } 369 370 /* ASUS HD 3600 XT board lists the DVI port as HDMI */ 371 if ((dev->pdev->device == 0x9598) && 372 (dev->pdev->subsystem_vendor == 0x1043) && 373 (dev->pdev->subsystem_device == 0x01da)) { 374 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 375 *connector_type = DRM_MODE_CONNECTOR_DVII; 376 } 377 } 378 379 /* ASUS HD 3600 board lists the DVI port as HDMI */ 380 if ((dev->pdev->device == 0x9598) && 381 (dev->pdev->subsystem_vendor == 0x1043) && 382 (dev->pdev->subsystem_device == 0x01e4)) { 383 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 384 *connector_type = DRM_MODE_CONNECTOR_DVII; 385 } 386 } 387 388 /* ASUS HD 3450 board lists the DVI port as HDMI */ 389 if ((dev->pdev->device == 0x95C5) && 390 (dev->pdev->subsystem_vendor == 0x1043) && 391 (dev->pdev->subsystem_device == 0x01e2)) { 392 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 393 *connector_type = DRM_MODE_CONNECTOR_DVII; 394 } 395 } 396 397 /* some BIOSes seem to report DAC on HDMI - usually this is a board with 398 * HDMI + VGA reporting as HDMI 399 */ 400 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 401 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { 402 *connector_type = DRM_MODE_CONNECTOR_VGA; 403 *line_mux = 0; 404 } 405 } 406 407 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port 408 * on the laptop and a DVI port on the docking station and 409 * both share the same encoder, hpd pin, and ddc line. 410 * So while the bios table is technically correct, 411 * we drop the DVI port here since xrandr has no concept of 412 * encoders and will try and drive both connectors 413 * with different crtcs which isn't possible on the hardware 414 * side and leaves no crtcs for LVDS or VGA. 415 */ 416 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) && 417 (dev->pdev->subsystem_vendor == 0x1025) && 418 (dev->pdev->subsystem_device == 0x013c)) { 419 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) && 420 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) { 421 /* actually it's a DVI-D port not DVI-I */ 422 *connector_type = DRM_MODE_CONNECTOR_DVID; 423 return false; 424 } 425 } 426 427 /* XFX Pine Group device rv730 reports no VGA DDC lines 428 * even though they are wired up to record 0x93 429 */ 430 if ((dev->pdev->device == 0x9498) && 431 (dev->pdev->subsystem_vendor == 0x1682) && 432 (dev->pdev->subsystem_device == 0x2452) && 433 (i2c_bus->valid == false) && 434 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) { 435 struct radeon_device *rdev = dev->dev_private; 436 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93); 437 } 438 439 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */ 440 if (((dev->pdev->device == 0x9802) || (dev->pdev->device == 0x9806)) && 441 (dev->pdev->subsystem_vendor == 0x1734) && 442 (dev->pdev->subsystem_device == 0x11bd)) { 443 if (*connector_type == DRM_MODE_CONNECTOR_VGA) { 444 *connector_type = DRM_MODE_CONNECTOR_DVII; 445 *line_mux = 0x3103; 446 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) { 447 *connector_type = DRM_MODE_CONNECTOR_DVII; 448 } 449 } 450 451 /* Fujitsu D3003-S2 board lists DVI-I as DVI-I and VGA */ 452 if ((dev->pdev->device == 0x9805) && 453 (dev->pdev->subsystem_vendor == 0x1734) && 454 (dev->pdev->subsystem_device == 0x11bd)) { 455 if (*connector_type == DRM_MODE_CONNECTOR_VGA) 456 return false; 457 } 458 459 return true; 460 } 461 462 static const int supported_devices_connector_convert[] = { 463 DRM_MODE_CONNECTOR_Unknown, 464 DRM_MODE_CONNECTOR_VGA, 465 DRM_MODE_CONNECTOR_DVII, 466 DRM_MODE_CONNECTOR_DVID, 467 DRM_MODE_CONNECTOR_DVIA, 468 DRM_MODE_CONNECTOR_SVIDEO, 469 DRM_MODE_CONNECTOR_Composite, 470 DRM_MODE_CONNECTOR_LVDS, 471 DRM_MODE_CONNECTOR_Unknown, 472 DRM_MODE_CONNECTOR_Unknown, 473 DRM_MODE_CONNECTOR_HDMIA, 474 DRM_MODE_CONNECTOR_HDMIB, 475 DRM_MODE_CONNECTOR_Unknown, 476 DRM_MODE_CONNECTOR_Unknown, 477 DRM_MODE_CONNECTOR_9PinDIN, 478 DRM_MODE_CONNECTOR_DisplayPort 479 }; 480 481 static const uint16_t supported_devices_connector_object_id_convert[] = { 482 CONNECTOR_OBJECT_ID_NONE, 483 CONNECTOR_OBJECT_ID_VGA, 484 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */ 485 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */ 486 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */ 487 CONNECTOR_OBJECT_ID_COMPOSITE, 488 CONNECTOR_OBJECT_ID_SVIDEO, 489 CONNECTOR_OBJECT_ID_LVDS, 490 CONNECTOR_OBJECT_ID_9PIN_DIN, 491 CONNECTOR_OBJECT_ID_9PIN_DIN, 492 CONNECTOR_OBJECT_ID_DISPLAYPORT, 493 CONNECTOR_OBJECT_ID_HDMI_TYPE_A, 494 CONNECTOR_OBJECT_ID_HDMI_TYPE_B, 495 CONNECTOR_OBJECT_ID_SVIDEO 496 }; 497 498 static const int object_connector_convert[] = { 499 DRM_MODE_CONNECTOR_Unknown, 500 DRM_MODE_CONNECTOR_DVII, 501 DRM_MODE_CONNECTOR_DVII, 502 DRM_MODE_CONNECTOR_DVID, 503 DRM_MODE_CONNECTOR_DVID, 504 DRM_MODE_CONNECTOR_VGA, 505 DRM_MODE_CONNECTOR_Composite, 506 DRM_MODE_CONNECTOR_SVIDEO, 507 DRM_MODE_CONNECTOR_Unknown, 508 DRM_MODE_CONNECTOR_Unknown, 509 DRM_MODE_CONNECTOR_9PinDIN, 510 DRM_MODE_CONNECTOR_Unknown, 511 DRM_MODE_CONNECTOR_HDMIA, 512 DRM_MODE_CONNECTOR_HDMIB, 513 DRM_MODE_CONNECTOR_LVDS, 514 DRM_MODE_CONNECTOR_9PinDIN, 515 DRM_MODE_CONNECTOR_Unknown, 516 DRM_MODE_CONNECTOR_Unknown, 517 DRM_MODE_CONNECTOR_Unknown, 518 DRM_MODE_CONNECTOR_DisplayPort, 519 DRM_MODE_CONNECTOR_eDP, 520 DRM_MODE_CONNECTOR_Unknown 521 }; 522 523 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) 524 { 525 struct radeon_device *rdev = dev->dev_private; 526 struct radeon_mode_info *mode_info = &rdev->mode_info; 527 struct atom_context *ctx = mode_info->atom_context; 528 int index = GetIndexIntoMasterTable(DATA, Object_Header); 529 u16 size, data_offset; 530 u8 frev, crev; 531 ATOM_CONNECTOR_OBJECT_TABLE *con_obj; 532 ATOM_ENCODER_OBJECT_TABLE *enc_obj; 533 ATOM_OBJECT_TABLE *router_obj; 534 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; 535 ATOM_OBJECT_HEADER *obj_header; 536 int i, j, k, path_size, device_support; 537 int connector_type; 538 u16 igp_lane_info, conn_id, connector_object_id; 539 struct radeon_i2c_bus_rec ddc_bus; 540 struct radeon_router router; 541 struct radeon_gpio_rec gpio; 542 struct radeon_hpd hpd; 543 544 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) 545 return false; 546 547 if (crev < 2) 548 return false; 549 550 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); 551 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) 552 (ctx->bios + data_offset + 553 le16_to_cpu(obj_header->usDisplayPathTableOffset)); 554 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) 555 (ctx->bios + data_offset + 556 le16_to_cpu(obj_header->usConnectorObjectTableOffset)); 557 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *) 558 (ctx->bios + data_offset + 559 le16_to_cpu(obj_header->usEncoderObjectTableOffset)); 560 router_obj = (ATOM_OBJECT_TABLE *) 561 (ctx->bios + data_offset + 562 le16_to_cpu(obj_header->usRouterObjectTableOffset)); 563 device_support = le16_to_cpu(obj_header->usDeviceSupport); 564 565 path_size = 0; 566 for (i = 0; i < path_obj->ucNumOfDispPath; i++) { 567 uint8_t *addr = (uint8_t *) path_obj->asDispPath; 568 ATOM_DISPLAY_OBJECT_PATH *path; 569 addr += path_size; 570 path = (ATOM_DISPLAY_OBJECT_PATH *) addr; 571 path_size += le16_to_cpu(path->usSize); 572 573 if (device_support & le16_to_cpu(path->usDeviceTag)) { 574 uint8_t con_obj_id, con_obj_num, con_obj_type; 575 576 con_obj_id = 577 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) 578 >> OBJECT_ID_SHIFT; 579 con_obj_num = 580 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) 581 >> ENUM_ID_SHIFT; 582 con_obj_type = 583 (le16_to_cpu(path->usConnObjectId) & 584 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 585 586 /* TODO CV support */ 587 if (le16_to_cpu(path->usDeviceTag) == 588 ATOM_DEVICE_CV_SUPPORT) 589 continue; 590 591 /* IGP chips */ 592 if ((rdev->flags & RADEON_IS_IGP) && 593 (con_obj_id == 594 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { 595 uint16_t igp_offset = 0; 596 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj; 597 598 index = 599 GetIndexIntoMasterTable(DATA, 600 IntegratedSystemInfo); 601 602 if (atom_parse_data_header(ctx, index, &size, &frev, 603 &crev, &igp_offset)) { 604 605 if (crev >= 2) { 606 igp_obj = 607 (ATOM_INTEGRATED_SYSTEM_INFO_V2 608 *) (ctx->bios + igp_offset); 609 610 if (igp_obj) { 611 uint32_t slot_config, ct; 612 613 if (con_obj_num == 1) 614 slot_config = 615 igp_obj-> 616 ulDDISlot1Config; 617 else 618 slot_config = 619 igp_obj-> 620 ulDDISlot2Config; 621 622 ct = (slot_config >> 16) & 0xff; 623 connector_type = 624 object_connector_convert 625 [ct]; 626 connector_object_id = ct; 627 igp_lane_info = 628 slot_config & 0xffff; 629 } else 630 continue; 631 } else 632 continue; 633 } else { 634 igp_lane_info = 0; 635 connector_type = 636 object_connector_convert[con_obj_id]; 637 connector_object_id = con_obj_id; 638 } 639 } else { 640 igp_lane_info = 0; 641 connector_type = 642 object_connector_convert[con_obj_id]; 643 connector_object_id = con_obj_id; 644 } 645 646 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 647 continue; 648 649 router.ddc_valid = false; 650 router.cd_valid = false; 651 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) { 652 uint8_t grph_obj_id, grph_obj_num, grph_obj_type; 653 654 grph_obj_id = 655 (le16_to_cpu(path->usGraphicObjIds[j]) & 656 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 657 grph_obj_num = 658 (le16_to_cpu(path->usGraphicObjIds[j]) & 659 ENUM_ID_MASK) >> ENUM_ID_SHIFT; 660 grph_obj_type = 661 (le16_to_cpu(path->usGraphicObjIds[j]) & 662 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 663 664 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { 665 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) { 666 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID); 667 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) { 668 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 669 (ctx->bios + data_offset + 670 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); 671 ATOM_ENCODER_CAP_RECORD *cap_record; 672 u16 caps = 0; 673 674 while (record->ucRecordSize > 0 && 675 record->ucRecordType > 0 && 676 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 677 switch (record->ucRecordType) { 678 case ATOM_ENCODER_CAP_RECORD_TYPE: 679 cap_record =(ATOM_ENCODER_CAP_RECORD *) 680 record; 681 caps = le16_to_cpu(cap_record->usEncoderCap); 682 break; 683 } 684 record = (ATOM_COMMON_RECORD_HEADER *) 685 ((char *)record + record->ucRecordSize); 686 } 687 radeon_add_atom_encoder(dev, 688 encoder_obj, 689 le16_to_cpu 690 (path-> 691 usDeviceTag), 692 caps); 693 } 694 } 695 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) { 696 for (k = 0; k < router_obj->ucNumberOfObjects; k++) { 697 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); 698 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) { 699 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 700 (ctx->bios + data_offset + 701 le16_to_cpu(router_obj->asObjects[k].usRecordOffset)); 702 ATOM_I2C_RECORD *i2c_record; 703 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 704 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path; 705 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path; 706 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table = 707 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) 708 (ctx->bios + data_offset + 709 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); 710 u8 *num_dst_objs = (u8 *) 711 ((u8 *)router_src_dst_table + 1 + 712 (router_src_dst_table->ucNumberOfSrc * 2)); 713 u16 *dst_objs = (u16 *)(num_dst_objs + 1); 714 int enum_id; 715 716 router.router_id = router_obj_id; 717 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) { 718 if (le16_to_cpu(path->usConnObjectId) == 719 le16_to_cpu(dst_objs[enum_id])) 720 break; 721 } 722 723 while (record->ucRecordSize > 0 && 724 record->ucRecordType > 0 && 725 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 726 switch (record->ucRecordType) { 727 case ATOM_I2C_RECORD_TYPE: 728 i2c_record = 729 (ATOM_I2C_RECORD *) 730 record; 731 i2c_config = 732 (ATOM_I2C_ID_CONFIG_ACCESS *) 733 &i2c_record->sucI2cId; 734 router.i2c_info = 735 radeon_lookup_i2c_gpio(rdev, 736 i2c_config-> 737 ucAccess); 738 router.i2c_addr = i2c_record->ucI2CAddr >> 1; 739 break; 740 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE: 741 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *) 742 record; 743 router.ddc_valid = true; 744 router.ddc_mux_type = ddc_path->ucMuxType; 745 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin; 746 router.ddc_mux_state = ddc_path->ucMuxState[enum_id]; 747 break; 748 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE: 749 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *) 750 record; 751 router.cd_valid = true; 752 router.cd_mux_type = cd_path->ucMuxType; 753 router.cd_mux_control_pin = cd_path->ucMuxControlPin; 754 router.cd_mux_state = cd_path->ucMuxState[enum_id]; 755 break; 756 } 757 record = (ATOM_COMMON_RECORD_HEADER *) 758 ((char *)record + record->ucRecordSize); 759 } 760 } 761 } 762 } 763 } 764 765 /* look up gpio for ddc, hpd */ 766 ddc_bus.valid = false; 767 hpd.hpd = RADEON_HPD_NONE; 768 if ((le16_to_cpu(path->usDeviceTag) & 769 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { 770 for (j = 0; j < con_obj->ucNumberOfObjects; j++) { 771 if (le16_to_cpu(path->usConnObjectId) == 772 le16_to_cpu(con_obj->asObjects[j]. 773 usObjectID)) { 774 ATOM_COMMON_RECORD_HEADER 775 *record = 776 (ATOM_COMMON_RECORD_HEADER 777 *) 778 (ctx->bios + data_offset + 779 le16_to_cpu(con_obj-> 780 asObjects[j]. 781 usRecordOffset)); 782 ATOM_I2C_RECORD *i2c_record; 783 ATOM_HPD_INT_RECORD *hpd_record; 784 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 785 786 while (record->ucRecordSize > 0 && 787 record->ucRecordType > 0 && 788 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 789 switch (record->ucRecordType) { 790 case ATOM_I2C_RECORD_TYPE: 791 i2c_record = 792 (ATOM_I2C_RECORD *) 793 record; 794 i2c_config = 795 (ATOM_I2C_ID_CONFIG_ACCESS *) 796 &i2c_record->sucI2cId; 797 ddc_bus = radeon_lookup_i2c_gpio(rdev, 798 i2c_config-> 799 ucAccess); 800 break; 801 case ATOM_HPD_INT_RECORD_TYPE: 802 hpd_record = 803 (ATOM_HPD_INT_RECORD *) 804 record; 805 gpio = radeon_atombios_lookup_gpio(rdev, 806 hpd_record->ucHPDIntGPIOID); 807 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio); 808 hpd.plugged_state = hpd_record->ucPlugged_PinState; 809 break; 810 } 811 record = 812 (ATOM_COMMON_RECORD_HEADER 813 *) ((char *)record 814 + 815 record-> 816 ucRecordSize); 817 } 818 break; 819 } 820 } 821 } 822 823 /* needed for aux chan transactions */ 824 ddc_bus.hpd = hpd.hpd; 825 826 conn_id = le16_to_cpu(path->usConnObjectId); 827 828 if (!radeon_atom_apply_quirks 829 (dev, le16_to_cpu(path->usDeviceTag), &connector_type, 830 &ddc_bus, &conn_id, &hpd)) 831 continue; 832 833 radeon_add_atom_connector(dev, 834 conn_id, 835 le16_to_cpu(path-> 836 usDeviceTag), 837 connector_type, &ddc_bus, 838 igp_lane_info, 839 connector_object_id, 840 &hpd, 841 &router); 842 843 } 844 } 845 846 radeon_link_encoder_connector(dev); 847 848 return true; 849 } 850 851 static uint16_t atombios_get_connector_object_id(struct drm_device *dev, 852 int connector_type, 853 uint16_t devices) 854 { 855 struct radeon_device *rdev = dev->dev_private; 856 857 if (rdev->flags & RADEON_IS_IGP) { 858 return supported_devices_connector_object_id_convert 859 [connector_type]; 860 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) || 861 (connector_type == DRM_MODE_CONNECTOR_DVID)) && 862 (devices & ATOM_DEVICE_DFP2_SUPPORT)) { 863 struct radeon_mode_info *mode_info = &rdev->mode_info; 864 struct atom_context *ctx = mode_info->atom_context; 865 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info); 866 uint16_t size, data_offset; 867 uint8_t frev, crev; 868 ATOM_XTMDS_INFO *xtmds; 869 870 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) { 871 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset); 872 873 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) { 874 if (connector_type == DRM_MODE_CONNECTOR_DVII) 875 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 876 else 877 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 878 } else { 879 if (connector_type == DRM_MODE_CONNECTOR_DVII) 880 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 881 else 882 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 883 } 884 } else 885 return supported_devices_connector_object_id_convert 886 [connector_type]; 887 } else { 888 return supported_devices_connector_object_id_convert 889 [connector_type]; 890 } 891 } 892 893 struct bios_connector { 894 bool valid; 895 uint16_t line_mux; 896 uint16_t devices; 897 int connector_type; 898 struct radeon_i2c_bus_rec ddc_bus; 899 struct radeon_hpd hpd; 900 }; 901 902 bool radeon_get_atom_connector_info_from_supported_devices_table(struct 903 drm_device 904 *dev) 905 { 906 struct radeon_device *rdev = dev->dev_private; 907 struct radeon_mode_info *mode_info = &rdev->mode_info; 908 struct atom_context *ctx = mode_info->atom_context; 909 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo); 910 uint16_t size, data_offset; 911 uint8_t frev, crev; 912 uint16_t device_support; 913 uint8_t dac; 914 union atom_supported_devices *supported_devices; 915 int i, j, max_device; 916 struct bios_connector *bios_connectors; 917 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE; 918 struct radeon_router router; 919 920 router.ddc_valid = false; 921 router.cd_valid = false; 922 923 bios_connectors = kzalloc(bc_size, GFP_KERNEL); 924 if (!bios_connectors) 925 return false; 926 927 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, 928 &data_offset)) { 929 kfree(bios_connectors); 930 return false; 931 } 932 933 supported_devices = 934 (union atom_supported_devices *)(ctx->bios + data_offset); 935 936 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport); 937 938 if (frev > 1) 939 max_device = ATOM_MAX_SUPPORTED_DEVICE; 940 else 941 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO; 942 943 for (i = 0; i < max_device; i++) { 944 ATOM_CONNECTOR_INFO_I2C ci = 945 supported_devices->info.asConnInfo[i]; 946 947 bios_connectors[i].valid = false; 948 949 if (!(device_support & (1 << i))) { 950 continue; 951 } 952 953 if (i == ATOM_DEVICE_CV_INDEX) { 954 DRM_DEBUG_KMS("Skipping Component Video\n"); 955 continue; 956 } 957 958 bios_connectors[i].connector_type = 959 supported_devices_connector_convert[ci.sucConnectorInfo. 960 sbfAccess. 961 bfConnectorType]; 962 963 if (bios_connectors[i].connector_type == 964 DRM_MODE_CONNECTOR_Unknown) 965 continue; 966 967 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; 968 969 bios_connectors[i].line_mux = 970 ci.sucI2cId.ucAccess; 971 972 /* give tv unique connector ids */ 973 if (i == ATOM_DEVICE_TV1_INDEX) { 974 bios_connectors[i].ddc_bus.valid = false; 975 bios_connectors[i].line_mux = 50; 976 } else if (i == ATOM_DEVICE_TV2_INDEX) { 977 bios_connectors[i].ddc_bus.valid = false; 978 bios_connectors[i].line_mux = 51; 979 } else if (i == ATOM_DEVICE_CV_INDEX) { 980 bios_connectors[i].ddc_bus.valid = false; 981 bios_connectors[i].line_mux = 52; 982 } else 983 bios_connectors[i].ddc_bus = 984 radeon_lookup_i2c_gpio(rdev, 985 bios_connectors[i].line_mux); 986 987 if ((crev > 1) && (frev > 1)) { 988 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap; 989 switch (isb) { 990 case 0x4: 991 bios_connectors[i].hpd.hpd = RADEON_HPD_1; 992 break; 993 case 0xa: 994 bios_connectors[i].hpd.hpd = RADEON_HPD_2; 995 break; 996 default: 997 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; 998 break; 999 } 1000 } else { 1001 if (i == ATOM_DEVICE_DFP1_INDEX) 1002 bios_connectors[i].hpd.hpd = RADEON_HPD_1; 1003 else if (i == ATOM_DEVICE_DFP2_INDEX) 1004 bios_connectors[i].hpd.hpd = RADEON_HPD_2; 1005 else 1006 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; 1007 } 1008 1009 /* Always set the connector type to VGA for CRT1/CRT2. if they are 1010 * shared with a DVI port, we'll pick up the DVI connector when we 1011 * merge the outputs. Some bioses incorrectly list VGA ports as DVI. 1012 */ 1013 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) 1014 bios_connectors[i].connector_type = 1015 DRM_MODE_CONNECTOR_VGA; 1016 1017 if (!radeon_atom_apply_quirks 1018 (dev, (1 << i), &bios_connectors[i].connector_type, 1019 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux, 1020 &bios_connectors[i].hpd)) 1021 continue; 1022 1023 bios_connectors[i].valid = true; 1024 bios_connectors[i].devices = (1 << i); 1025 1026 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) 1027 radeon_add_atom_encoder(dev, 1028 radeon_get_encoder_enum(dev, 1029 (1 << i), 1030 dac), 1031 (1 << i), 1032 0); 1033 else 1034 radeon_add_legacy_encoder(dev, 1035 radeon_get_encoder_enum(dev, 1036 (1 << i), 1037 dac), 1038 (1 << i)); 1039 } 1040 1041 /* combine shared connectors */ 1042 for (i = 0; i < max_device; i++) { 1043 if (bios_connectors[i].valid) { 1044 for (j = 0; j < max_device; j++) { 1045 if (bios_connectors[j].valid && (i != j)) { 1046 if (bios_connectors[i].line_mux == 1047 bios_connectors[j].line_mux) { 1048 /* make sure not to combine LVDS */ 1049 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1050 bios_connectors[i].line_mux = 53; 1051 bios_connectors[i].ddc_bus.valid = false; 1052 continue; 1053 } 1054 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1055 bios_connectors[j].line_mux = 53; 1056 bios_connectors[j].ddc_bus.valid = false; 1057 continue; 1058 } 1059 /* combine analog and digital for DVI-I */ 1060 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 1061 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) || 1062 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 1063 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) { 1064 bios_connectors[i].devices |= 1065 bios_connectors[j].devices; 1066 bios_connectors[i].connector_type = 1067 DRM_MODE_CONNECTOR_DVII; 1068 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) 1069 bios_connectors[i].hpd = 1070 bios_connectors[j].hpd; 1071 bios_connectors[j].valid = false; 1072 } 1073 } 1074 } 1075 } 1076 } 1077 } 1078 1079 /* add the connectors */ 1080 for (i = 0; i < max_device; i++) { 1081 if (bios_connectors[i].valid) { 1082 uint16_t connector_object_id = 1083 atombios_get_connector_object_id(dev, 1084 bios_connectors[i].connector_type, 1085 bios_connectors[i].devices); 1086 radeon_add_atom_connector(dev, 1087 bios_connectors[i].line_mux, 1088 bios_connectors[i].devices, 1089 bios_connectors[i]. 1090 connector_type, 1091 &bios_connectors[i].ddc_bus, 1092 0, 1093 connector_object_id, 1094 &bios_connectors[i].hpd, 1095 &router); 1096 } 1097 } 1098 1099 radeon_link_encoder_connector(dev); 1100 1101 kfree(bios_connectors); 1102 return true; 1103 } 1104 1105 union firmware_info { 1106 ATOM_FIRMWARE_INFO info; 1107 ATOM_FIRMWARE_INFO_V1_2 info_12; 1108 ATOM_FIRMWARE_INFO_V1_3 info_13; 1109 ATOM_FIRMWARE_INFO_V1_4 info_14; 1110 ATOM_FIRMWARE_INFO_V2_1 info_21; 1111 ATOM_FIRMWARE_INFO_V2_2 info_22; 1112 }; 1113 1114 bool radeon_atom_get_clock_info(struct drm_device *dev) 1115 { 1116 struct radeon_device *rdev = dev->dev_private; 1117 struct radeon_mode_info *mode_info = &rdev->mode_info; 1118 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 1119 union firmware_info *firmware_info; 1120 uint8_t frev, crev; 1121 struct radeon_pll *p1pll = &rdev->clock.p1pll; 1122 struct radeon_pll *p2pll = &rdev->clock.p2pll; 1123 struct radeon_pll *dcpll = &rdev->clock.dcpll; 1124 struct radeon_pll *spll = &rdev->clock.spll; 1125 struct radeon_pll *mpll = &rdev->clock.mpll; 1126 uint16_t data_offset; 1127 1128 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1129 &frev, &crev, &data_offset)) { 1130 firmware_info = 1131 (union firmware_info *)(mode_info->atom_context->bios + 1132 data_offset); 1133 /* pixel clocks */ 1134 p1pll->reference_freq = 1135 le16_to_cpu(firmware_info->info.usReferenceClock); 1136 p1pll->reference_div = 0; 1137 1138 if (crev < 2) 1139 p1pll->pll_out_min = 1140 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); 1141 else 1142 p1pll->pll_out_min = 1143 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); 1144 p1pll->pll_out_max = 1145 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); 1146 1147 if (crev >= 4) { 1148 p1pll->lcd_pll_out_min = 1149 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100; 1150 if (p1pll->lcd_pll_out_min == 0) 1151 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 1152 p1pll->lcd_pll_out_max = 1153 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100; 1154 if (p1pll->lcd_pll_out_max == 0) 1155 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 1156 } else { 1157 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 1158 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 1159 } 1160 1161 if (p1pll->pll_out_min == 0) { 1162 if (ASIC_IS_AVIVO(rdev)) 1163 p1pll->pll_out_min = 64800; 1164 else 1165 p1pll->pll_out_min = 20000; 1166 } 1167 1168 p1pll->pll_in_min = 1169 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); 1170 p1pll->pll_in_max = 1171 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); 1172 1173 *p2pll = *p1pll; 1174 1175 /* system clock */ 1176 if (ASIC_IS_DCE4(rdev)) 1177 spll->reference_freq = 1178 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock); 1179 else 1180 spll->reference_freq = 1181 le16_to_cpu(firmware_info->info.usReferenceClock); 1182 spll->reference_div = 0; 1183 1184 spll->pll_out_min = 1185 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); 1186 spll->pll_out_max = 1187 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); 1188 1189 /* ??? */ 1190 if (spll->pll_out_min == 0) { 1191 if (ASIC_IS_AVIVO(rdev)) 1192 spll->pll_out_min = 64800; 1193 else 1194 spll->pll_out_min = 20000; 1195 } 1196 1197 spll->pll_in_min = 1198 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); 1199 spll->pll_in_max = 1200 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); 1201 1202 /* memory clock */ 1203 if (ASIC_IS_DCE4(rdev)) 1204 mpll->reference_freq = 1205 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock); 1206 else 1207 mpll->reference_freq = 1208 le16_to_cpu(firmware_info->info.usReferenceClock); 1209 mpll->reference_div = 0; 1210 1211 mpll->pll_out_min = 1212 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); 1213 mpll->pll_out_max = 1214 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); 1215 1216 /* ??? */ 1217 if (mpll->pll_out_min == 0) { 1218 if (ASIC_IS_AVIVO(rdev)) 1219 mpll->pll_out_min = 64800; 1220 else 1221 mpll->pll_out_min = 20000; 1222 } 1223 1224 mpll->pll_in_min = 1225 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); 1226 mpll->pll_in_max = 1227 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); 1228 1229 rdev->clock.default_sclk = 1230 le32_to_cpu(firmware_info->info.ulDefaultEngineClock); 1231 rdev->clock.default_mclk = 1232 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); 1233 1234 if (ASIC_IS_DCE4(rdev)) { 1235 rdev->clock.default_dispclk = 1236 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); 1237 if (rdev->clock.default_dispclk == 0) { 1238 if (ASIC_IS_DCE6(rdev)) 1239 rdev->clock.default_dispclk = 60000; /* 600 Mhz */ 1240 else if (ASIC_IS_DCE5(rdev)) 1241 rdev->clock.default_dispclk = 54000; /* 540 Mhz */ 1242 else 1243 rdev->clock.default_dispclk = 60000; /* 600 Mhz */ 1244 } 1245 /* set a reasonable default for DP */ 1246 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) { 1247 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n", 1248 rdev->clock.default_dispclk / 100); 1249 rdev->clock.default_dispclk = 60000; 1250 } 1251 rdev->clock.dp_extclk = 1252 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); 1253 rdev->clock.current_dispclk = rdev->clock.default_dispclk; 1254 } 1255 *dcpll = *p1pll; 1256 1257 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock); 1258 if (rdev->clock.max_pixel_clock == 0) 1259 rdev->clock.max_pixel_clock = 40000; 1260 1261 /* not technically a clock, but... */ 1262 rdev->mode_info.firmware_flags = 1263 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess); 1264 1265 return true; 1266 } 1267 1268 return false; 1269 } 1270 1271 union igp_info { 1272 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 1273 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 1274 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; 1275 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; 1276 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; 1277 }; 1278 1279 bool radeon_atombios_sideport_present(struct radeon_device *rdev) 1280 { 1281 struct radeon_mode_info *mode_info = &rdev->mode_info; 1282 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1283 union igp_info *igp_info; 1284 u8 frev, crev; 1285 u16 data_offset; 1286 1287 /* sideport is AMD only */ 1288 if (rdev->family == CHIP_RS600) 1289 return false; 1290 1291 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1292 &frev, &crev, &data_offset)) { 1293 igp_info = (union igp_info *)(mode_info->atom_context->bios + 1294 data_offset); 1295 switch (crev) { 1296 case 1: 1297 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock)) 1298 return true; 1299 break; 1300 case 2: 1301 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock)) 1302 return true; 1303 break; 1304 default: 1305 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 1306 break; 1307 } 1308 } 1309 return false; 1310 } 1311 1312 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 1313 struct radeon_encoder_int_tmds *tmds) 1314 { 1315 struct drm_device *dev = encoder->base.dev; 1316 struct radeon_device *rdev = dev->dev_private; 1317 struct radeon_mode_info *mode_info = &rdev->mode_info; 1318 int index = GetIndexIntoMasterTable(DATA, TMDS_Info); 1319 uint16_t data_offset; 1320 struct _ATOM_TMDS_INFO *tmds_info; 1321 uint8_t frev, crev; 1322 uint16_t maxfreq; 1323 int i; 1324 1325 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1326 &frev, &crev, &data_offset)) { 1327 tmds_info = 1328 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios + 1329 data_offset); 1330 1331 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); 1332 for (i = 0; i < 4; i++) { 1333 tmds->tmds_pll[i].freq = 1334 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency); 1335 tmds->tmds_pll[i].value = 1336 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f; 1337 tmds->tmds_pll[i].value |= 1338 (tmds_info->asMiscInfo[i]. 1339 ucPLL_VCO_Gain & 0x3f) << 6; 1340 tmds->tmds_pll[i].value |= 1341 (tmds_info->asMiscInfo[i]. 1342 ucPLL_DutyCycle & 0xf) << 12; 1343 tmds->tmds_pll[i].value |= 1344 (tmds_info->asMiscInfo[i]. 1345 ucPLL_VoltageSwing & 0xf) << 16; 1346 1347 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n", 1348 tmds->tmds_pll[i].freq, 1349 tmds->tmds_pll[i].value); 1350 1351 if (maxfreq == tmds->tmds_pll[i].freq) { 1352 tmds->tmds_pll[i].freq = 0xffffffff; 1353 break; 1354 } 1355 } 1356 return true; 1357 } 1358 return false; 1359 } 1360 1361 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 1362 struct radeon_atom_ss *ss, 1363 int id) 1364 { 1365 struct radeon_mode_info *mode_info = &rdev->mode_info; 1366 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info); 1367 uint16_t data_offset, size; 1368 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info; 1369 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign; 1370 uint8_t frev, crev; 1371 int i, num_indices; 1372 1373 memset(ss, 0, sizeof(struct radeon_atom_ss)); 1374 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1375 &frev, &crev, &data_offset)) { 1376 ss_info = 1377 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset); 1378 1379 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1380 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT); 1381 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*) 1382 ((u8 *)&ss_info->asSS_Info[0]); 1383 for (i = 0; i < num_indices; i++) { 1384 if (ss_assign->ucSS_Id == id) { 1385 ss->percentage = 1386 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage); 1387 ss->type = ss_assign->ucSpreadSpectrumType; 1388 ss->step = ss_assign->ucSS_Step; 1389 ss->delay = ss_assign->ucSS_Delay; 1390 ss->range = ss_assign->ucSS_Range; 1391 ss->refdiv = ss_assign->ucRecommendedRef_Div; 1392 return true; 1393 } 1394 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*) 1395 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT)); 1396 } 1397 } 1398 return false; 1399 } 1400 1401 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev, 1402 struct radeon_atom_ss *ss, 1403 int id) 1404 { 1405 struct radeon_mode_info *mode_info = &rdev->mode_info; 1406 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1407 u16 data_offset, size; 1408 union igp_info *igp_info; 1409 u8 frev, crev; 1410 u16 percentage = 0, rate = 0; 1411 1412 /* get any igp specific overrides */ 1413 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1414 &frev, &crev, &data_offset)) { 1415 igp_info = (union igp_info *) 1416 (mode_info->atom_context->bios + data_offset); 1417 switch (crev) { 1418 case 6: 1419 switch (id) { 1420 case ASIC_INTERNAL_SS_ON_TMDS: 1421 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage); 1422 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz); 1423 break; 1424 case ASIC_INTERNAL_SS_ON_HDMI: 1425 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage); 1426 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz); 1427 break; 1428 case ASIC_INTERNAL_SS_ON_LVDS: 1429 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage); 1430 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz); 1431 break; 1432 } 1433 break; 1434 case 7: 1435 switch (id) { 1436 case ASIC_INTERNAL_SS_ON_TMDS: 1437 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage); 1438 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz); 1439 break; 1440 case ASIC_INTERNAL_SS_ON_HDMI: 1441 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage); 1442 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz); 1443 break; 1444 case ASIC_INTERNAL_SS_ON_LVDS: 1445 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage); 1446 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz); 1447 break; 1448 } 1449 break; 1450 case 8: 1451 switch (id) { 1452 case ASIC_INTERNAL_SS_ON_TMDS: 1453 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage); 1454 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz); 1455 break; 1456 case ASIC_INTERNAL_SS_ON_HDMI: 1457 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage); 1458 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz); 1459 break; 1460 case ASIC_INTERNAL_SS_ON_LVDS: 1461 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage); 1462 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz); 1463 break; 1464 } 1465 break; 1466 default: 1467 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 1468 break; 1469 } 1470 if (percentage) 1471 ss->percentage = percentage; 1472 if (rate) 1473 ss->rate = rate; 1474 } 1475 } 1476 1477 union asic_ss_info { 1478 struct _ATOM_ASIC_INTERNAL_SS_INFO info; 1479 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2; 1480 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3; 1481 }; 1482 1483 union asic_ss_assignment { 1484 struct _ATOM_ASIC_SS_ASSIGNMENT v1; 1485 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2; 1486 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3; 1487 }; 1488 1489 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 1490 struct radeon_atom_ss *ss, 1491 int id, u32 clock) 1492 { 1493 struct radeon_mode_info *mode_info = &rdev->mode_info; 1494 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 1495 uint16_t data_offset, size; 1496 union asic_ss_info *ss_info; 1497 union asic_ss_assignment *ss_assign; 1498 uint8_t frev, crev; 1499 int i, num_indices; 1500 1501 if (id == ASIC_INTERNAL_MEMORY_SS) { 1502 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT)) 1503 return false; 1504 } 1505 if (id == ASIC_INTERNAL_ENGINE_SS) { 1506 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT)) 1507 return false; 1508 } 1509 1510 memset(ss, 0, sizeof(struct radeon_atom_ss)); 1511 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1512 &frev, &crev, &data_offset)) { 1513 1514 ss_info = 1515 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset); 1516 1517 switch (frev) { 1518 case 1: 1519 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1520 sizeof(ATOM_ASIC_SS_ASSIGNMENT); 1521 1522 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]); 1523 for (i = 0; i < num_indices; i++) { 1524 if ((ss_assign->v1.ucClockIndication == id) && 1525 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) { 1526 ss->percentage = 1527 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage); 1528 ss->type = ss_assign->v1.ucSpreadSpectrumMode; 1529 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz); 1530 ss->percentage_divider = 100; 1531 return true; 1532 } 1533 ss_assign = (union asic_ss_assignment *) 1534 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT)); 1535 } 1536 break; 1537 case 2: 1538 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1539 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); 1540 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]); 1541 for (i = 0; i < num_indices; i++) { 1542 if ((ss_assign->v2.ucClockIndication == id) && 1543 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) { 1544 ss->percentage = 1545 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage); 1546 ss->type = ss_assign->v2.ucSpreadSpectrumMode; 1547 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz); 1548 ss->percentage_divider = 100; 1549 if ((crev == 2) && 1550 ((id == ASIC_INTERNAL_ENGINE_SS) || 1551 (id == ASIC_INTERNAL_MEMORY_SS))) 1552 ss->rate /= 100; 1553 return true; 1554 } 1555 ss_assign = (union asic_ss_assignment *) 1556 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2)); 1557 } 1558 break; 1559 case 3: 1560 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1561 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); 1562 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]); 1563 for (i = 0; i < num_indices; i++) { 1564 if ((ss_assign->v3.ucClockIndication == id) && 1565 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) { 1566 ss->percentage = 1567 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage); 1568 ss->type = ss_assign->v3.ucSpreadSpectrumMode; 1569 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz); 1570 if (ss_assign->v3.ucSpreadSpectrumMode & 1571 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK) 1572 ss->percentage_divider = 1000; 1573 else 1574 ss->percentage_divider = 100; 1575 if ((id == ASIC_INTERNAL_ENGINE_SS) || 1576 (id == ASIC_INTERNAL_MEMORY_SS)) 1577 ss->rate /= 100; 1578 if (rdev->flags & RADEON_IS_IGP) 1579 radeon_atombios_get_igp_ss_overrides(rdev, ss, id); 1580 return true; 1581 } 1582 ss_assign = (union asic_ss_assignment *) 1583 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3)); 1584 } 1585 break; 1586 default: 1587 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev); 1588 break; 1589 } 1590 1591 } 1592 return false; 1593 } 1594 1595 union lvds_info { 1596 struct _ATOM_LVDS_INFO info; 1597 struct _ATOM_LVDS_INFO_V12 info_12; 1598 }; 1599 1600 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct 1601 radeon_encoder 1602 *encoder) 1603 { 1604 struct drm_device *dev = encoder->base.dev; 1605 struct radeon_device *rdev = dev->dev_private; 1606 struct radeon_mode_info *mode_info = &rdev->mode_info; 1607 int index = GetIndexIntoMasterTable(DATA, LVDS_Info); 1608 uint16_t data_offset, misc; 1609 union lvds_info *lvds_info; 1610 uint8_t frev, crev; 1611 struct radeon_encoder_atom_dig *lvds = NULL; 1612 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1613 1614 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1615 &frev, &crev, &data_offset)) { 1616 lvds_info = 1617 (union lvds_info *)(mode_info->atom_context->bios + data_offset); 1618 lvds = 1619 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 1620 1621 if (!lvds) 1622 return NULL; 1623 1624 lvds->native_mode.clock = 1625 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; 1626 lvds->native_mode.hdisplay = 1627 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); 1628 lvds->native_mode.vdisplay = 1629 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); 1630 lvds->native_mode.htotal = lvds->native_mode.hdisplay + 1631 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); 1632 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + 1633 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); 1634 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + 1635 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); 1636 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + 1637 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); 1638 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + 1639 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset); 1640 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + 1641 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); 1642 lvds->panel_pwr_delay = 1643 le16_to_cpu(lvds_info->info.usOffDelayInMs); 1644 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc; 1645 1646 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess); 1647 if (misc & ATOM_VSYNC_POLARITY) 1648 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC; 1649 if (misc & ATOM_HSYNC_POLARITY) 1650 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC; 1651 if (misc & ATOM_COMPOSITESYNC) 1652 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC; 1653 if (misc & ATOM_INTERLACE) 1654 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE; 1655 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1656 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; 1657 1658 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize); 1659 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize); 1660 1661 /* set crtc values */ 1662 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1663 1664 lvds->lcd_ss_id = lvds_info->info.ucSS_Id; 1665 1666 encoder->native_mode = lvds->native_mode; 1667 1668 if (encoder_enum == 2) 1669 lvds->linkb = true; 1670 else 1671 lvds->linkb = false; 1672 1673 /* parse the lcd record table */ 1674 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) { 1675 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record; 1676 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record; 1677 bool bad_record = false; 1678 u8 *record; 1679 1680 if ((frev == 1) && (crev < 2)) 1681 /* absolute */ 1682 record = (u8 *)(mode_info->atom_context->bios + 1683 le16_to_cpu(lvds_info->info.usModePatchTableOffset)); 1684 else 1685 /* relative */ 1686 record = (u8 *)(mode_info->atom_context->bios + 1687 data_offset + 1688 le16_to_cpu(lvds_info->info.usModePatchTableOffset)); 1689 while (*record != ATOM_RECORD_END_TYPE) { 1690 switch (*record) { 1691 case LCD_MODE_PATCH_RECORD_MODE_TYPE: 1692 record += sizeof(ATOM_PATCH_RECORD_MODE); 1693 break; 1694 case LCD_RTS_RECORD_TYPE: 1695 record += sizeof(ATOM_LCD_RTS_RECORD); 1696 break; 1697 case LCD_CAP_RECORD_TYPE: 1698 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP); 1699 break; 1700 case LCD_FAKE_EDID_PATCH_RECORD_TYPE: 1701 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record; 1702 if (fake_edid_record->ucFakeEDIDLength) { 1703 struct edid *edid; 1704 int edid_size = 1705 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength); 1706 edid = kmalloc(edid_size, GFP_KERNEL); 1707 if (edid) { 1708 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0], 1709 fake_edid_record->ucFakeEDIDLength); 1710 1711 if (drm_edid_is_valid(edid)) { 1712 rdev->mode_info.bios_hardcoded_edid = edid; 1713 rdev->mode_info.bios_hardcoded_edid_size = edid_size; 1714 } else 1715 kfree(edid); 1716 } 1717 } 1718 record += fake_edid_record->ucFakeEDIDLength ? 1719 fake_edid_record->ucFakeEDIDLength + 2 : 1720 sizeof(ATOM_FAKE_EDID_PATCH_RECORD); 1721 break; 1722 case LCD_PANEL_RESOLUTION_RECORD_TYPE: 1723 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record; 1724 lvds->native_mode.width_mm = panel_res_record->usHSize; 1725 lvds->native_mode.height_mm = panel_res_record->usVSize; 1726 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD); 1727 break; 1728 default: 1729 DRM_ERROR("Bad LCD record %d\n", *record); 1730 bad_record = true; 1731 break; 1732 } 1733 if (bad_record) 1734 break; 1735 } 1736 } 1737 } 1738 return lvds; 1739 } 1740 1741 struct radeon_encoder_primary_dac * 1742 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) 1743 { 1744 struct drm_device *dev = encoder->base.dev; 1745 struct radeon_device *rdev = dev->dev_private; 1746 struct radeon_mode_info *mode_info = &rdev->mode_info; 1747 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 1748 uint16_t data_offset; 1749 struct _COMPASSIONATE_DATA *dac_info; 1750 uint8_t frev, crev; 1751 uint8_t bg, dac; 1752 struct radeon_encoder_primary_dac *p_dac = NULL; 1753 1754 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1755 &frev, &crev, &data_offset)) { 1756 dac_info = (struct _COMPASSIONATE_DATA *) 1757 (mode_info->atom_context->bios + data_offset); 1758 1759 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL); 1760 1761 if (!p_dac) 1762 return NULL; 1763 1764 bg = dac_info->ucDAC1_BG_Adjustment; 1765 dac = dac_info->ucDAC1_DAC_Adjustment; 1766 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 1767 1768 } 1769 return p_dac; 1770 } 1771 1772 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 1773 struct drm_display_mode *mode) 1774 { 1775 struct radeon_mode_info *mode_info = &rdev->mode_info; 1776 ATOM_ANALOG_TV_INFO *tv_info; 1777 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; 1778 ATOM_DTD_FORMAT *dtd_timings; 1779 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1780 u8 frev, crev; 1781 u16 data_offset, misc; 1782 1783 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL, 1784 &frev, &crev, &data_offset)) 1785 return false; 1786 1787 switch (crev) { 1788 case 1: 1789 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); 1790 if (index >= MAX_SUPPORTED_TV_TIMING) 1791 return false; 1792 1793 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); 1794 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); 1795 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); 1796 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) + 1797 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); 1798 1799 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); 1800 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); 1801 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); 1802 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) + 1803 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); 1804 1805 mode->flags = 0; 1806 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess); 1807 if (misc & ATOM_VSYNC_POLARITY) 1808 mode->flags |= DRM_MODE_FLAG_NVSYNC; 1809 if (misc & ATOM_HSYNC_POLARITY) 1810 mode->flags |= DRM_MODE_FLAG_NHSYNC; 1811 if (misc & ATOM_COMPOSITESYNC) 1812 mode->flags |= DRM_MODE_FLAG_CSYNC; 1813 if (misc & ATOM_INTERLACE) 1814 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1815 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1816 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1817 1818 mode->crtc_clock = mode->clock = 1819 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; 1820 1821 if (index == 1) { 1822 /* PAL timings appear to have wrong values for totals */ 1823 mode->crtc_htotal -= 1; 1824 mode->crtc_vtotal -= 1; 1825 } 1826 break; 1827 case 2: 1828 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset); 1829 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2) 1830 return false; 1831 1832 dtd_timings = &tv_info_v1_2->aModeTimings[index]; 1833 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) + 1834 le16_to_cpu(dtd_timings->usHBlanking_Time); 1835 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive); 1836 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) + 1837 le16_to_cpu(dtd_timings->usHSyncOffset); 1838 mode->crtc_hsync_end = mode->crtc_hsync_start + 1839 le16_to_cpu(dtd_timings->usHSyncWidth); 1840 1841 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) + 1842 le16_to_cpu(dtd_timings->usVBlanking_Time); 1843 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive); 1844 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) + 1845 le16_to_cpu(dtd_timings->usVSyncOffset); 1846 mode->crtc_vsync_end = mode->crtc_vsync_start + 1847 le16_to_cpu(dtd_timings->usVSyncWidth); 1848 1849 mode->flags = 0; 1850 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); 1851 if (misc & ATOM_VSYNC_POLARITY) 1852 mode->flags |= DRM_MODE_FLAG_NVSYNC; 1853 if (misc & ATOM_HSYNC_POLARITY) 1854 mode->flags |= DRM_MODE_FLAG_NHSYNC; 1855 if (misc & ATOM_COMPOSITESYNC) 1856 mode->flags |= DRM_MODE_FLAG_CSYNC; 1857 if (misc & ATOM_INTERLACE) 1858 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1859 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1860 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1861 1862 mode->crtc_clock = mode->clock = 1863 le16_to_cpu(dtd_timings->usPixClk) * 10; 1864 break; 1865 } 1866 return true; 1867 } 1868 1869 enum radeon_tv_std 1870 radeon_atombios_get_tv_info(struct radeon_device *rdev) 1871 { 1872 struct radeon_mode_info *mode_info = &rdev->mode_info; 1873 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1874 uint16_t data_offset; 1875 uint8_t frev, crev; 1876 struct _ATOM_ANALOG_TV_INFO *tv_info; 1877 enum radeon_tv_std tv_std = TV_STD_NTSC; 1878 1879 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1880 &frev, &crev, &data_offset)) { 1881 1882 tv_info = (struct _ATOM_ANALOG_TV_INFO *) 1883 (mode_info->atom_context->bios + data_offset); 1884 1885 switch (tv_info->ucTV_BootUpDefaultStandard) { 1886 case ATOM_TV_NTSC: 1887 tv_std = TV_STD_NTSC; 1888 DRM_DEBUG_KMS("Default TV standard: NTSC\n"); 1889 break; 1890 case ATOM_TV_NTSCJ: 1891 tv_std = TV_STD_NTSC_J; 1892 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); 1893 break; 1894 case ATOM_TV_PAL: 1895 tv_std = TV_STD_PAL; 1896 DRM_DEBUG_KMS("Default TV standard: PAL\n"); 1897 break; 1898 case ATOM_TV_PALM: 1899 tv_std = TV_STD_PAL_M; 1900 DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); 1901 break; 1902 case ATOM_TV_PALN: 1903 tv_std = TV_STD_PAL_N; 1904 DRM_DEBUG_KMS("Default TV standard: PAL-N\n"); 1905 break; 1906 case ATOM_TV_PALCN: 1907 tv_std = TV_STD_PAL_CN; 1908 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n"); 1909 break; 1910 case ATOM_TV_PAL60: 1911 tv_std = TV_STD_PAL_60; 1912 DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); 1913 break; 1914 case ATOM_TV_SECAM: 1915 tv_std = TV_STD_SECAM; 1916 DRM_DEBUG_KMS("Default TV standard: SECAM\n"); 1917 break; 1918 default: 1919 tv_std = TV_STD_NTSC; 1920 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n"); 1921 break; 1922 } 1923 } 1924 return tv_std; 1925 } 1926 1927 struct radeon_encoder_tv_dac * 1928 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) 1929 { 1930 struct drm_device *dev = encoder->base.dev; 1931 struct radeon_device *rdev = dev->dev_private; 1932 struct radeon_mode_info *mode_info = &rdev->mode_info; 1933 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 1934 uint16_t data_offset; 1935 struct _COMPASSIONATE_DATA *dac_info; 1936 uint8_t frev, crev; 1937 uint8_t bg, dac; 1938 struct radeon_encoder_tv_dac *tv_dac = NULL; 1939 1940 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1941 &frev, &crev, &data_offset)) { 1942 1943 dac_info = (struct _COMPASSIONATE_DATA *) 1944 (mode_info->atom_context->bios + data_offset); 1945 1946 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 1947 1948 if (!tv_dac) 1949 return NULL; 1950 1951 bg = dac_info->ucDAC2_CRT2_BG_Adjustment; 1952 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment; 1953 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1954 1955 bg = dac_info->ucDAC2_PAL_BG_Adjustment; 1956 dac = dac_info->ucDAC2_PAL_DAC_Adjustment; 1957 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1958 1959 bg = dac_info->ucDAC2_NTSC_BG_Adjustment; 1960 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment; 1961 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1962 1963 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev); 1964 } 1965 return tv_dac; 1966 } 1967 1968 static const char *thermal_controller_names[] = { 1969 "NONE", 1970 "lm63", 1971 "adm1032", 1972 "adm1030", 1973 "max6649", 1974 "lm63", /* lm64 */ 1975 "f75375", 1976 "asc7xxx", 1977 }; 1978 1979 static const char *pp_lib_thermal_controller_names[] = { 1980 "NONE", 1981 "lm63", 1982 "adm1032", 1983 "adm1030", 1984 "max6649", 1985 "lm63", /* lm64 */ 1986 "f75375", 1987 "RV6xx", 1988 "RV770", 1989 "adt7473", 1990 "NONE", 1991 "External GPIO", 1992 "Evergreen", 1993 "emc2103", 1994 "Sumo", 1995 "Northern Islands", 1996 "Southern Islands", 1997 "lm96163", 1998 "Sea Islands", 1999 }; 2000 2001 union power_info { 2002 struct _ATOM_POWERPLAY_INFO info; 2003 struct _ATOM_POWERPLAY_INFO_V2 info_2; 2004 struct _ATOM_POWERPLAY_INFO_V3 info_3; 2005 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 2006 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 2007 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 2008 }; 2009 2010 union pplib_clock_info { 2011 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 2012 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 2013 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 2014 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 2015 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 2016 struct _ATOM_PPLIB_CI_CLOCK_INFO ci; 2017 }; 2018 2019 union pplib_power_state { 2020 struct _ATOM_PPLIB_STATE v1; 2021 struct _ATOM_PPLIB_STATE_V2 v2; 2022 }; 2023 2024 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev, 2025 int state_index, 2026 u32 misc, u32 misc2) 2027 { 2028 rdev->pm.power_state[state_index].misc = misc; 2029 rdev->pm.power_state[state_index].misc2 = misc2; 2030 /* order matters! */ 2031 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) 2032 rdev->pm.power_state[state_index].type = 2033 POWER_STATE_TYPE_POWERSAVE; 2034 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE) 2035 rdev->pm.power_state[state_index].type = 2036 POWER_STATE_TYPE_BATTERY; 2037 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE) 2038 rdev->pm.power_state[state_index].type = 2039 POWER_STATE_TYPE_BATTERY; 2040 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) 2041 rdev->pm.power_state[state_index].type = 2042 POWER_STATE_TYPE_BALANCED; 2043 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) { 2044 rdev->pm.power_state[state_index].type = 2045 POWER_STATE_TYPE_PERFORMANCE; 2046 rdev->pm.power_state[state_index].flags &= 2047 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2048 } 2049 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE) 2050 rdev->pm.power_state[state_index].type = 2051 POWER_STATE_TYPE_BALANCED; 2052 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { 2053 rdev->pm.power_state[state_index].type = 2054 POWER_STATE_TYPE_DEFAULT; 2055 rdev->pm.default_power_state_index = state_index; 2056 rdev->pm.power_state[state_index].default_clock_mode = 2057 &rdev->pm.power_state[state_index].clock_info[0]; 2058 } else if (state_index == 0) { 2059 rdev->pm.power_state[state_index].clock_info[0].flags |= 2060 RADEON_PM_MODE_NO_DISPLAY; 2061 } 2062 } 2063 2064 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev) 2065 { 2066 struct radeon_mode_info *mode_info = &rdev->mode_info; 2067 u32 misc, misc2 = 0; 2068 int num_modes = 0, i; 2069 int state_index = 0; 2070 struct radeon_i2c_bus_rec i2c_bus; 2071 union power_info *power_info; 2072 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2073 u16 data_offset; 2074 u8 frev, crev; 2075 2076 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2077 &frev, &crev, &data_offset)) 2078 return state_index; 2079 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2080 2081 /* add the i2c bus for thermal/fan chip */ 2082 if ((power_info->info.ucOverdriveThermalController > 0) && 2083 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) { 2084 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2085 thermal_controller_names[power_info->info.ucOverdriveThermalController], 2086 power_info->info.ucOverdriveControllerAddress >> 1); 2087 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine); 2088 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2089 if (rdev->pm.i2c_bus) { 2090 struct i2c_board_info info = { }; 2091 const char *name = thermal_controller_names[power_info->info. 2092 ucOverdriveThermalController]; 2093 info.addr = power_info->info.ucOverdriveControllerAddress >> 1; 2094 strlcpy(info.type, name, sizeof(info.type)); 2095 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2096 } 2097 } 2098 num_modes = power_info->info.ucNumOfPowerModeEntries; 2099 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK) 2100 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK; 2101 if (num_modes == 0) 2102 return state_index; 2103 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL); 2104 if (!rdev->pm.power_state) 2105 return state_index; 2106 /* last mode is usually default, array is low to high */ 2107 for (i = 0; i < num_modes; i++) { 2108 rdev->pm.power_state[state_index].clock_info = 2109 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); 2110 if (!rdev->pm.power_state[state_index].clock_info) 2111 return state_index; 2112 rdev->pm.power_state[state_index].num_clock_modes = 1; 2113 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2114 switch (frev) { 2115 case 1: 2116 rdev->pm.power_state[state_index].clock_info[0].mclk = 2117 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock); 2118 rdev->pm.power_state[state_index].clock_info[0].sclk = 2119 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock); 2120 /* skip invalid modes */ 2121 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2122 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2123 continue; 2124 rdev->pm.power_state[state_index].pcie_lanes = 2125 power_info->info.asPowerPlayInfo[i].ucNumPciELanes; 2126 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo); 2127 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2128 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2129 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2130 VOLTAGE_GPIO; 2131 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2132 radeon_atombios_lookup_gpio(rdev, 2133 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex); 2134 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2135 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2136 true; 2137 else 2138 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2139 false; 2140 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2141 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2142 VOLTAGE_VDDC; 2143 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2144 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex; 2145 } 2146 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2147 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0); 2148 state_index++; 2149 break; 2150 case 2: 2151 rdev->pm.power_state[state_index].clock_info[0].mclk = 2152 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock); 2153 rdev->pm.power_state[state_index].clock_info[0].sclk = 2154 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock); 2155 /* skip invalid modes */ 2156 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2157 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2158 continue; 2159 rdev->pm.power_state[state_index].pcie_lanes = 2160 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes; 2161 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo); 2162 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2); 2163 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2164 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2165 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2166 VOLTAGE_GPIO; 2167 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2168 radeon_atombios_lookup_gpio(rdev, 2169 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex); 2170 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2171 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2172 true; 2173 else 2174 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2175 false; 2176 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2177 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2178 VOLTAGE_VDDC; 2179 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2180 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex; 2181 } 2182 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2183 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); 2184 state_index++; 2185 break; 2186 case 3: 2187 rdev->pm.power_state[state_index].clock_info[0].mclk = 2188 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock); 2189 rdev->pm.power_state[state_index].clock_info[0].sclk = 2190 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock); 2191 /* skip invalid modes */ 2192 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2193 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2194 continue; 2195 rdev->pm.power_state[state_index].pcie_lanes = 2196 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes; 2197 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo); 2198 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2); 2199 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2200 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2201 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2202 VOLTAGE_GPIO; 2203 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2204 radeon_atombios_lookup_gpio(rdev, 2205 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex); 2206 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2207 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2208 true; 2209 else 2210 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2211 false; 2212 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2213 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2214 VOLTAGE_VDDC; 2215 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2216 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex; 2217 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) { 2218 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled = 2219 true; 2220 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id = 2221 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex; 2222 } 2223 } 2224 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2225 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); 2226 state_index++; 2227 break; 2228 } 2229 } 2230 /* last mode is usually default */ 2231 if (rdev->pm.default_power_state_index == -1) { 2232 rdev->pm.power_state[state_index - 1].type = 2233 POWER_STATE_TYPE_DEFAULT; 2234 rdev->pm.default_power_state_index = state_index - 1; 2235 rdev->pm.power_state[state_index - 1].default_clock_mode = 2236 &rdev->pm.power_state[state_index - 1].clock_info[0]; 2237 rdev->pm.power_state[state_index].flags &= 2238 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2239 rdev->pm.power_state[state_index].misc = 0; 2240 rdev->pm.power_state[state_index].misc2 = 0; 2241 } 2242 return state_index; 2243 } 2244 2245 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev, 2246 ATOM_PPLIB_THERMALCONTROLLER *controller) 2247 { 2248 struct radeon_i2c_bus_rec i2c_bus; 2249 2250 /* add the i2c bus for thermal/fan chip */ 2251 if (controller->ucType > 0) { 2252 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN) 2253 rdev->pm.no_fan = true; 2254 rdev->pm.fan_pulses_per_revolution = 2255 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK; 2256 if (rdev->pm.fan_pulses_per_revolution) { 2257 rdev->pm.fan_min_rpm = controller->ucFanMinRPM; 2258 rdev->pm.fan_max_rpm = controller->ucFanMaxRPM; 2259 } 2260 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) { 2261 DRM_INFO("Internal thermal controller %s fan control\n", 2262 (controller->ucFanParameters & 2263 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2264 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX; 2265 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) { 2266 DRM_INFO("Internal thermal controller %s fan control\n", 2267 (controller->ucFanParameters & 2268 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2269 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770; 2270 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) { 2271 DRM_INFO("Internal thermal controller %s fan control\n", 2272 (controller->ucFanParameters & 2273 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2274 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN; 2275 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) { 2276 DRM_INFO("Internal thermal controller %s fan control\n", 2277 (controller->ucFanParameters & 2278 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2279 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO; 2280 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) { 2281 DRM_INFO("Internal thermal controller %s fan control\n", 2282 (controller->ucFanParameters & 2283 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2284 rdev->pm.int_thermal_type = THERMAL_TYPE_NI; 2285 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) { 2286 DRM_INFO("Internal thermal controller %s fan control\n", 2287 (controller->ucFanParameters & 2288 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2289 rdev->pm.int_thermal_type = THERMAL_TYPE_SI; 2290 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) { 2291 DRM_INFO("Internal thermal controller %s fan control\n", 2292 (controller->ucFanParameters & 2293 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2294 rdev->pm.int_thermal_type = THERMAL_TYPE_CI; 2295 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) { 2296 DRM_INFO("Internal thermal controller %s fan control\n", 2297 (controller->ucFanParameters & 2298 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2299 rdev->pm.int_thermal_type = THERMAL_TYPE_KV; 2300 } else if (controller->ucType == 2301 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) { 2302 DRM_INFO("External GPIO thermal controller %s fan control\n", 2303 (controller->ucFanParameters & 2304 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2305 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO; 2306 } else if (controller->ucType == 2307 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) { 2308 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n", 2309 (controller->ucFanParameters & 2310 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2311 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL; 2312 } else if (controller->ucType == 2313 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) { 2314 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n", 2315 (controller->ucFanParameters & 2316 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2317 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL; 2318 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) { 2319 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n", 2320 pp_lib_thermal_controller_names[controller->ucType], 2321 controller->ucI2cAddress >> 1, 2322 (controller->ucFanParameters & 2323 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2324 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL; 2325 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine); 2326 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2327 if (rdev->pm.i2c_bus) { 2328 struct i2c_board_info info = { }; 2329 const char *name = pp_lib_thermal_controller_names[controller->ucType]; 2330 info.addr = controller->ucI2cAddress >> 1; 2331 strlcpy(info.type, name, sizeof(info.type)); 2332 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2333 } 2334 } else { 2335 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n", 2336 controller->ucType, 2337 controller->ucI2cAddress >> 1, 2338 (controller->ucFanParameters & 2339 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2340 } 2341 } 2342 } 2343 2344 void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 2345 u16 *vddc, u16 *vddci, u16 *mvdd) 2346 { 2347 struct radeon_mode_info *mode_info = &rdev->mode_info; 2348 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 2349 u8 frev, crev; 2350 u16 data_offset; 2351 union firmware_info *firmware_info; 2352 2353 *vddc = 0; 2354 *vddci = 0; 2355 *mvdd = 0; 2356 2357 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2358 &frev, &crev, &data_offset)) { 2359 firmware_info = 2360 (union firmware_info *)(mode_info->atom_context->bios + 2361 data_offset); 2362 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage); 2363 if ((frev == 2) && (crev >= 2)) { 2364 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage); 2365 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage); 2366 } 2367 } 2368 } 2369 2370 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev, 2371 int state_index, int mode_index, 2372 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info) 2373 { 2374 int j; 2375 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings); 2376 u32 misc2 = le16_to_cpu(non_clock_info->usClassification); 2377 u16 vddc, vddci, mvdd; 2378 2379 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 2380 2381 rdev->pm.power_state[state_index].misc = misc; 2382 rdev->pm.power_state[state_index].misc2 = misc2; 2383 rdev->pm.power_state[state_index].pcie_lanes = 2384 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> 2385 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 2386 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { 2387 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: 2388 rdev->pm.power_state[state_index].type = 2389 POWER_STATE_TYPE_BATTERY; 2390 break; 2391 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED: 2392 rdev->pm.power_state[state_index].type = 2393 POWER_STATE_TYPE_BALANCED; 2394 break; 2395 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: 2396 rdev->pm.power_state[state_index].type = 2397 POWER_STATE_TYPE_PERFORMANCE; 2398 break; 2399 case ATOM_PPLIB_CLASSIFICATION_UI_NONE: 2400 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) 2401 rdev->pm.power_state[state_index].type = 2402 POWER_STATE_TYPE_PERFORMANCE; 2403 break; 2404 } 2405 rdev->pm.power_state[state_index].flags = 0; 2406 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) 2407 rdev->pm.power_state[state_index].flags |= 2408 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2409 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) { 2410 rdev->pm.power_state[state_index].type = 2411 POWER_STATE_TYPE_DEFAULT; 2412 rdev->pm.default_power_state_index = state_index; 2413 rdev->pm.power_state[state_index].default_clock_mode = 2414 &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; 2415 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) { 2416 /* NI chips post without MC ucode, so default clocks are strobe mode only */ 2417 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk; 2418 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk; 2419 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage; 2420 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci; 2421 } else { 2422 u16 max_vddci = 0; 2423 2424 if (ASIC_IS_DCE4(rdev)) 2425 radeon_atom_get_max_voltage(rdev, 2426 SET_VOLTAGE_TYPE_ASIC_VDDCI, 2427 &max_vddci); 2428 /* patch the table values with the default sclk/mclk from firmware info */ 2429 for (j = 0; j < mode_index; j++) { 2430 rdev->pm.power_state[state_index].clock_info[j].mclk = 2431 rdev->clock.default_mclk; 2432 rdev->pm.power_state[state_index].clock_info[j].sclk = 2433 rdev->clock.default_sclk; 2434 if (vddc) 2435 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage = 2436 vddc; 2437 if (max_vddci) 2438 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci = 2439 max_vddci; 2440 } 2441 } 2442 } 2443 } 2444 2445 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev, 2446 int state_index, int mode_index, 2447 union pplib_clock_info *clock_info) 2448 { 2449 u32 sclk, mclk; 2450 u16 vddc; 2451 2452 if (rdev->flags & RADEON_IS_IGP) { 2453 if (rdev->family >= CHIP_PALM) { 2454 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); 2455 sclk |= clock_info->sumo.ucEngineClockHigh << 16; 2456 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2457 } else { 2458 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow); 2459 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; 2460 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2461 } 2462 } else if (rdev->family >= CHIP_BONAIRE) { 2463 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); 2464 sclk |= clock_info->ci.ucEngineClockHigh << 16; 2465 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); 2466 mclk |= clock_info->ci.ucMemoryClockHigh << 16; 2467 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2468 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2469 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2470 VOLTAGE_NONE; 2471 } else if (rdev->family >= CHIP_TAHITI) { 2472 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 2473 sclk |= clock_info->si.ucEngineClockHigh << 16; 2474 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 2475 mclk |= clock_info->si.ucMemoryClockHigh << 16; 2476 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2477 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2478 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2479 VOLTAGE_SW; 2480 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2481 le16_to_cpu(clock_info->si.usVDDC); 2482 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = 2483 le16_to_cpu(clock_info->si.usVDDCI); 2484 } else if (rdev->family >= CHIP_CEDAR) { 2485 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); 2486 sclk |= clock_info->evergreen.ucEngineClockHigh << 16; 2487 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow); 2488 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16; 2489 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2490 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2491 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2492 VOLTAGE_SW; 2493 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2494 le16_to_cpu(clock_info->evergreen.usVDDC); 2495 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = 2496 le16_to_cpu(clock_info->evergreen.usVDDCI); 2497 } else { 2498 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow); 2499 sclk |= clock_info->r600.ucEngineClockHigh << 16; 2500 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow); 2501 mclk |= clock_info->r600.ucMemoryClockHigh << 16; 2502 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2503 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2504 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2505 VOLTAGE_SW; 2506 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2507 le16_to_cpu(clock_info->r600.usVDDC); 2508 } 2509 2510 /* patch up vddc if necessary */ 2511 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) { 2512 case ATOM_VIRTUAL_VOLTAGE_ID0: 2513 case ATOM_VIRTUAL_VOLTAGE_ID1: 2514 case ATOM_VIRTUAL_VOLTAGE_ID2: 2515 case ATOM_VIRTUAL_VOLTAGE_ID3: 2516 case ATOM_VIRTUAL_VOLTAGE_ID4: 2517 case ATOM_VIRTUAL_VOLTAGE_ID5: 2518 case ATOM_VIRTUAL_VOLTAGE_ID6: 2519 case ATOM_VIRTUAL_VOLTAGE_ID7: 2520 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, 2521 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage, 2522 &vddc) == 0) 2523 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc; 2524 break; 2525 default: 2526 break; 2527 } 2528 2529 if (rdev->flags & RADEON_IS_IGP) { 2530 /* skip invalid modes */ 2531 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) 2532 return false; 2533 } else { 2534 /* skip invalid modes */ 2535 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || 2536 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) 2537 return false; 2538 } 2539 return true; 2540 } 2541 2542 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev) 2543 { 2544 struct radeon_mode_info *mode_info = &rdev->mode_info; 2545 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2546 union pplib_power_state *power_state; 2547 int i, j; 2548 int state_index = 0, mode_index = 0; 2549 union pplib_clock_info *clock_info; 2550 bool valid; 2551 union power_info *power_info; 2552 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2553 u16 data_offset; 2554 u8 frev, crev; 2555 2556 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2557 &frev, &crev, &data_offset)) 2558 return state_index; 2559 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2560 2561 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2562 if (power_info->pplib.ucNumStates == 0) 2563 return state_index; 2564 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2565 power_info->pplib.ucNumStates, GFP_KERNEL); 2566 if (!rdev->pm.power_state) 2567 return state_index; 2568 /* first mode is usually default, followed by low to high */ 2569 for (i = 0; i < power_info->pplib.ucNumStates; i++) { 2570 mode_index = 0; 2571 power_state = (union pplib_power_state *) 2572 (mode_info->atom_context->bios + data_offset + 2573 le16_to_cpu(power_info->pplib.usStateArrayOffset) + 2574 i * power_info->pplib.ucStateEntrySize); 2575 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2576 (mode_info->atom_context->bios + data_offset + 2577 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) + 2578 (power_state->v1.ucNonClockStateIndex * 2579 power_info->pplib.ucNonClockSize)); 2580 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) * 2581 ((power_info->pplib.ucStateEntrySize - 1) ? 2582 (power_info->pplib.ucStateEntrySize - 1) : 1), 2583 GFP_KERNEL); 2584 if (!rdev->pm.power_state[i].clock_info) 2585 return state_index; 2586 if (power_info->pplib.ucStateEntrySize - 1) { 2587 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) { 2588 clock_info = (union pplib_clock_info *) 2589 (mode_info->atom_context->bios + data_offset + 2590 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) + 2591 (power_state->v1.ucClockStateIndices[j] * 2592 power_info->pplib.ucClockInfoSize)); 2593 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2594 state_index, mode_index, 2595 clock_info); 2596 if (valid) 2597 mode_index++; 2598 } 2599 } else { 2600 rdev->pm.power_state[state_index].clock_info[0].mclk = 2601 rdev->clock.default_mclk; 2602 rdev->pm.power_state[state_index].clock_info[0].sclk = 2603 rdev->clock.default_sclk; 2604 mode_index++; 2605 } 2606 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2607 if (mode_index) { 2608 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, 2609 non_clock_info); 2610 state_index++; 2611 } 2612 } 2613 /* if multiple clock modes, mark the lowest as no display */ 2614 for (i = 0; i < state_index; i++) { 2615 if (rdev->pm.power_state[i].num_clock_modes > 1) 2616 rdev->pm.power_state[i].clock_info[0].flags |= 2617 RADEON_PM_MODE_NO_DISPLAY; 2618 } 2619 /* first mode is usually default */ 2620 if (rdev->pm.default_power_state_index == -1) { 2621 rdev->pm.power_state[0].type = 2622 POWER_STATE_TYPE_DEFAULT; 2623 rdev->pm.default_power_state_index = 0; 2624 rdev->pm.power_state[0].default_clock_mode = 2625 &rdev->pm.power_state[0].clock_info[0]; 2626 } 2627 return state_index; 2628 } 2629 2630 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev) 2631 { 2632 struct radeon_mode_info *mode_info = &rdev->mode_info; 2633 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2634 union pplib_power_state *power_state; 2635 int i, j, non_clock_array_index, clock_array_index; 2636 int state_index = 0, mode_index = 0; 2637 union pplib_clock_info *clock_info; 2638 struct _StateArray *state_array; 2639 struct _ClockInfoArray *clock_info_array; 2640 struct _NonClockInfoArray *non_clock_info_array; 2641 bool valid; 2642 union power_info *power_info; 2643 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2644 u16 data_offset; 2645 u8 frev, crev; 2646 u8 *power_state_offset; 2647 2648 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2649 &frev, &crev, &data_offset)) 2650 return state_index; 2651 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2652 2653 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2654 state_array = (struct _StateArray *) 2655 (mode_info->atom_context->bios + data_offset + 2656 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 2657 clock_info_array = (struct _ClockInfoArray *) 2658 (mode_info->atom_context->bios + data_offset + 2659 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 2660 non_clock_info_array = (struct _NonClockInfoArray *) 2661 (mode_info->atom_context->bios + data_offset + 2662 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 2663 if (state_array->ucNumEntries == 0) 2664 return state_index; 2665 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2666 state_array->ucNumEntries, GFP_KERNEL); 2667 if (!rdev->pm.power_state) 2668 return state_index; 2669 power_state_offset = (u8 *)state_array->states; 2670 for (i = 0; i < state_array->ucNumEntries; i++) { 2671 mode_index = 0; 2672 power_state = (union pplib_power_state *)power_state_offset; 2673 non_clock_array_index = power_state->v2.nonClockInfoIndex; 2674 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2675 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 2676 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) * 2677 (power_state->v2.ucNumDPMLevels ? 2678 power_state->v2.ucNumDPMLevels : 1), 2679 GFP_KERNEL); 2680 if (!rdev->pm.power_state[i].clock_info) 2681 return state_index; 2682 if (power_state->v2.ucNumDPMLevels) { 2683 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 2684 clock_array_index = power_state->v2.clockInfoIndex[j]; 2685 clock_info = (union pplib_clock_info *) 2686 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 2687 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2688 state_index, mode_index, 2689 clock_info); 2690 if (valid) 2691 mode_index++; 2692 } 2693 } else { 2694 rdev->pm.power_state[state_index].clock_info[0].mclk = 2695 rdev->clock.default_mclk; 2696 rdev->pm.power_state[state_index].clock_info[0].sclk = 2697 rdev->clock.default_sclk; 2698 mode_index++; 2699 } 2700 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2701 if (mode_index) { 2702 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, 2703 non_clock_info); 2704 state_index++; 2705 } 2706 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 2707 } 2708 /* if multiple clock modes, mark the lowest as no display */ 2709 for (i = 0; i < state_index; i++) { 2710 if (rdev->pm.power_state[i].num_clock_modes > 1) 2711 rdev->pm.power_state[i].clock_info[0].flags |= 2712 RADEON_PM_MODE_NO_DISPLAY; 2713 } 2714 /* first mode is usually default */ 2715 if (rdev->pm.default_power_state_index == -1) { 2716 rdev->pm.power_state[0].type = 2717 POWER_STATE_TYPE_DEFAULT; 2718 rdev->pm.default_power_state_index = 0; 2719 rdev->pm.power_state[0].default_clock_mode = 2720 &rdev->pm.power_state[0].clock_info[0]; 2721 } 2722 return state_index; 2723 } 2724 2725 void radeon_atombios_get_power_modes(struct radeon_device *rdev) 2726 { 2727 struct radeon_mode_info *mode_info = &rdev->mode_info; 2728 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2729 u16 data_offset; 2730 u8 frev, crev; 2731 int state_index = 0; 2732 2733 rdev->pm.default_power_state_index = -1; 2734 2735 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2736 &frev, &crev, &data_offset)) { 2737 switch (frev) { 2738 case 1: 2739 case 2: 2740 case 3: 2741 state_index = radeon_atombios_parse_power_table_1_3(rdev); 2742 break; 2743 case 4: 2744 case 5: 2745 state_index = radeon_atombios_parse_power_table_4_5(rdev); 2746 break; 2747 case 6: 2748 state_index = radeon_atombios_parse_power_table_6(rdev); 2749 break; 2750 default: 2751 break; 2752 } 2753 } 2754 2755 if (state_index == 0) { 2756 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL); 2757 if (rdev->pm.power_state) { 2758 rdev->pm.power_state[0].clock_info = 2759 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); 2760 if (rdev->pm.power_state[0].clock_info) { 2761 /* add the default mode */ 2762 rdev->pm.power_state[state_index].type = 2763 POWER_STATE_TYPE_DEFAULT; 2764 rdev->pm.power_state[state_index].num_clock_modes = 1; 2765 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 2766 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2767 rdev->pm.power_state[state_index].default_clock_mode = 2768 &rdev->pm.power_state[state_index].clock_info[0]; 2769 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2770 rdev->pm.power_state[state_index].pcie_lanes = 16; 2771 rdev->pm.default_power_state_index = state_index; 2772 rdev->pm.power_state[state_index].flags = 0; 2773 state_index++; 2774 } 2775 } 2776 } 2777 2778 rdev->pm.num_power_states = state_index; 2779 2780 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2781 rdev->pm.current_clock_mode_index = 0; 2782 if (rdev->pm.default_power_state_index >= 0) 2783 rdev->pm.current_vddc = 2784 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 2785 else 2786 rdev->pm.current_vddc = 0; 2787 } 2788 2789 union get_clock_dividers { 2790 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1; 2791 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2; 2792 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; 2793 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4; 2794 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; 2795 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in; 2796 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out; 2797 }; 2798 2799 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 2800 u8 clock_type, 2801 u32 clock, 2802 bool strobe_mode, 2803 struct atom_clock_dividers *dividers) 2804 { 2805 union get_clock_dividers args; 2806 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL); 2807 u8 frev, crev; 2808 2809 memset(&args, 0, sizeof(args)); 2810 memset(dividers, 0, sizeof(struct atom_clock_dividers)); 2811 2812 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2813 return -EINVAL; 2814 2815 switch (crev) { 2816 case 1: 2817 /* r4xx, r5xx */ 2818 args.v1.ucAction = clock_type; 2819 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */ 2820 2821 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2822 2823 dividers->post_div = args.v1.ucPostDiv; 2824 dividers->fb_div = args.v1.ucFbDiv; 2825 dividers->enable_post_div = true; 2826 break; 2827 case 2: 2828 case 3: 2829 case 5: 2830 /* r6xx, r7xx, evergreen, ni, si */ 2831 if (rdev->family <= CHIP_RV770) { 2832 args.v2.ucAction = clock_type; 2833 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */ 2834 2835 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2836 2837 dividers->post_div = args.v2.ucPostDiv; 2838 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); 2839 dividers->ref_div = args.v2.ucAction; 2840 if (rdev->family == CHIP_RV770) { 2841 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ? 2842 true : false; 2843 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0; 2844 } else 2845 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false; 2846 } else { 2847 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { 2848 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); 2849 2850 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2851 2852 dividers->post_div = args.v3.ucPostDiv; 2853 dividers->enable_post_div = (args.v3.ucCntlFlag & 2854 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 2855 dividers->enable_dithen = (args.v3.ucCntlFlag & 2856 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 2857 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); 2858 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); 2859 dividers->ref_div = args.v3.ucRefDiv; 2860 dividers->vco_mode = (args.v3.ucCntlFlag & 2861 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 2862 } else { 2863 /* for SI we use ComputeMemoryClockParam for memory plls */ 2864 if (rdev->family >= CHIP_TAHITI) 2865 return -EINVAL; 2866 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); 2867 if (strobe_mode) 2868 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN; 2869 2870 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2871 2872 dividers->post_div = args.v5.ucPostDiv; 2873 dividers->enable_post_div = (args.v5.ucCntlFlag & 2874 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 2875 dividers->enable_dithen = (args.v5.ucCntlFlag & 2876 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 2877 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv); 2878 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac); 2879 dividers->ref_div = args.v5.ucRefDiv; 2880 dividers->vco_mode = (args.v5.ucCntlFlag & 2881 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 2882 } 2883 } 2884 break; 2885 case 4: 2886 /* fusion */ 2887 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */ 2888 2889 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2890 2891 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; 2892 dividers->real_clock = le32_to_cpu(args.v4.ulClock); 2893 break; 2894 case 6: 2895 /* CI */ 2896 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */ 2897 args.v6_in.ulClock.ulComputeClockFlag = clock_type; 2898 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ 2899 2900 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2901 2902 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv); 2903 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac); 2904 dividers->ref_div = args.v6_out.ucPllRefDiv; 2905 dividers->post_div = args.v6_out.ucPllPostDiv; 2906 dividers->flags = args.v6_out.ucPllCntlFlag; 2907 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock); 2908 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; 2909 break; 2910 default: 2911 return -EINVAL; 2912 } 2913 return 0; 2914 } 2915 2916 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 2917 u32 clock, 2918 bool strobe_mode, 2919 struct atom_mpll_param *mpll_param) 2920 { 2921 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args; 2922 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam); 2923 u8 frev, crev; 2924 2925 memset(&args, 0, sizeof(args)); 2926 memset(mpll_param, 0, sizeof(struct atom_mpll_param)); 2927 2928 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2929 return -EINVAL; 2930 2931 switch (frev) { 2932 case 2: 2933 switch (crev) { 2934 case 1: 2935 /* SI */ 2936 args.ulClock = cpu_to_le32(clock); /* 10 khz */ 2937 args.ucInputFlag = 0; 2938 if (strobe_mode) 2939 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN; 2940 2941 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2942 2943 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac); 2944 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv); 2945 mpll_param->post_div = args.ucPostDiv; 2946 mpll_param->dll_speed = args.ucDllSpeed; 2947 mpll_param->bwcntl = args.ucBWCntl; 2948 mpll_param->vco_mode = 2949 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK); 2950 mpll_param->yclk_sel = 2951 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0; 2952 mpll_param->qdr = 2953 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0; 2954 mpll_param->half_rate = 2955 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0; 2956 break; 2957 default: 2958 return -EINVAL; 2959 } 2960 break; 2961 default: 2962 return -EINVAL; 2963 } 2964 return 0; 2965 } 2966 2967 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) 2968 { 2969 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args; 2970 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating); 2971 2972 args.ucEnable = enable; 2973 2974 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2975 } 2976 2977 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev) 2978 { 2979 GET_ENGINE_CLOCK_PS_ALLOCATION args; 2980 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); 2981 2982 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2983 return le32_to_cpu(args.ulReturnEngineClock); 2984 } 2985 2986 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev) 2987 { 2988 GET_MEMORY_CLOCK_PS_ALLOCATION args; 2989 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); 2990 2991 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2992 return le32_to_cpu(args.ulReturnMemoryClock); 2993 } 2994 2995 void radeon_atom_set_engine_clock(struct radeon_device *rdev, 2996 uint32_t eng_clock) 2997 { 2998 SET_ENGINE_CLOCK_PS_ALLOCATION args; 2999 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); 3000 3001 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */ 3002 3003 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3004 } 3005 3006 void radeon_atom_set_memory_clock(struct radeon_device *rdev, 3007 uint32_t mem_clock) 3008 { 3009 SET_MEMORY_CLOCK_PS_ALLOCATION args; 3010 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); 3011 3012 if (rdev->flags & RADEON_IS_IGP) 3013 return; 3014 3015 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */ 3016 3017 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3018 } 3019 3020 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 3021 u32 eng_clock, u32 mem_clock) 3022 { 3023 SET_ENGINE_CLOCK_PS_ALLOCATION args; 3024 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 3025 u32 tmp; 3026 3027 memset(&args, 0, sizeof(args)); 3028 3029 tmp = eng_clock & SET_CLOCK_FREQ_MASK; 3030 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24); 3031 3032 args.ulTargetEngineClock = cpu_to_le32(tmp); 3033 if (mem_clock) 3034 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK); 3035 3036 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3037 } 3038 3039 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 3040 u32 mem_clock) 3041 { 3042 u32 args; 3043 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 3044 3045 args = cpu_to_le32(mem_clock); /* 10 khz */ 3046 3047 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3048 } 3049 3050 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 3051 u32 mem_clock) 3052 { 3053 SET_MEMORY_CLOCK_PS_ALLOCATION args; 3054 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 3055 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24); 3056 3057 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */ 3058 3059 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3060 } 3061 3062 union set_voltage { 3063 struct _SET_VOLTAGE_PS_ALLOCATION alloc; 3064 struct _SET_VOLTAGE_PARAMETERS v1; 3065 struct _SET_VOLTAGE_PARAMETERS_V2 v2; 3066 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; 3067 }; 3068 3069 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type) 3070 { 3071 union set_voltage args; 3072 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3073 u8 frev, crev, volt_index = voltage_level; 3074 3075 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3076 return; 3077 3078 /* 0xff01 is a flag rather then an actual voltage */ 3079 if (voltage_level == 0xff01) 3080 return; 3081 3082 switch (crev) { 3083 case 1: 3084 args.v1.ucVoltageType = voltage_type; 3085 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE; 3086 args.v1.ucVoltageIndex = volt_index; 3087 break; 3088 case 2: 3089 args.v2.ucVoltageType = voltage_type; 3090 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE; 3091 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3092 break; 3093 case 3: 3094 args.v3.ucVoltageType = voltage_type; 3095 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE; 3096 args.v3.usVoltageLevel = cpu_to_le16(voltage_level); 3097 break; 3098 default: 3099 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3100 return; 3101 } 3102 3103 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3104 } 3105 3106 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 3107 u16 voltage_id, u16 *voltage) 3108 { 3109 union set_voltage args; 3110 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3111 u8 frev, crev; 3112 3113 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3114 return -EINVAL; 3115 3116 switch (crev) { 3117 case 1: 3118 return -EINVAL; 3119 case 2: 3120 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE; 3121 args.v2.ucVoltageMode = 0; 3122 args.v2.usVoltageLevel = 0; 3123 3124 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3125 3126 *voltage = le16_to_cpu(args.v2.usVoltageLevel); 3127 break; 3128 case 3: 3129 args.v3.ucVoltageType = voltage_type; 3130 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL; 3131 args.v3.usVoltageLevel = cpu_to_le16(voltage_id); 3132 3133 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3134 3135 *voltage = le16_to_cpu(args.v3.usVoltageLevel); 3136 break; 3137 default: 3138 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3139 return -EINVAL; 3140 } 3141 3142 return 0; 3143 } 3144 3145 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 3146 u16 *voltage, 3147 u16 leakage_idx) 3148 { 3149 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage); 3150 } 3151 3152 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 3153 u16 *leakage_id) 3154 { 3155 union set_voltage args; 3156 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3157 u8 frev, crev; 3158 3159 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3160 return -EINVAL; 3161 3162 switch (crev) { 3163 case 3: 3164 case 4: 3165 args.v3.ucVoltageType = 0; 3166 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID; 3167 args.v3.usVoltageLevel = 0; 3168 3169 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3170 3171 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel); 3172 break; 3173 default: 3174 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3175 return -EINVAL; 3176 } 3177 3178 return 0; 3179 } 3180 3181 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 3182 u16 *vddc, u16 *vddci, 3183 u16 virtual_voltage_id, 3184 u16 vbios_voltage_id) 3185 { 3186 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo); 3187 u8 frev, crev; 3188 u16 data_offset, size; 3189 int i, j; 3190 ATOM_ASIC_PROFILING_INFO_V2_1 *profile; 3191 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf; 3192 3193 *vddc = 0; 3194 *vddci = 0; 3195 3196 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3197 &frev, &crev, &data_offset)) 3198 return -EINVAL; 3199 3200 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *) 3201 (rdev->mode_info.atom_context->bios + data_offset); 3202 3203 switch (frev) { 3204 case 1: 3205 return -EINVAL; 3206 case 2: 3207 switch (crev) { 3208 case 1: 3209 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1)) 3210 return -EINVAL; 3211 leakage_bin = (u16 *) 3212 (rdev->mode_info.atom_context->bios + data_offset + 3213 le16_to_cpu(profile->usLeakageBinArrayOffset)); 3214 vddc_id_buf = (u16 *) 3215 (rdev->mode_info.atom_context->bios + data_offset + 3216 le16_to_cpu(profile->usElbVDDC_IdArrayOffset)); 3217 vddc_buf = (u16 *) 3218 (rdev->mode_info.atom_context->bios + data_offset + 3219 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset)); 3220 vddci_id_buf = (u16 *) 3221 (rdev->mode_info.atom_context->bios + data_offset + 3222 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset)); 3223 vddci_buf = (u16 *) 3224 (rdev->mode_info.atom_context->bios + data_offset + 3225 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset)); 3226 3227 if (profile->ucElbVDDC_Num > 0) { 3228 for (i = 0; i < profile->ucElbVDDC_Num; i++) { 3229 if (vddc_id_buf[i] == virtual_voltage_id) { 3230 for (j = 0; j < profile->ucLeakageBinNum; j++) { 3231 if (vbios_voltage_id <= leakage_bin[j]) { 3232 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i]; 3233 break; 3234 } 3235 } 3236 break; 3237 } 3238 } 3239 } 3240 if (profile->ucElbVDDCI_Num > 0) { 3241 for (i = 0; i < profile->ucElbVDDCI_Num; i++) { 3242 if (vddci_id_buf[i] == virtual_voltage_id) { 3243 for (j = 0; j < profile->ucLeakageBinNum; j++) { 3244 if (vbios_voltage_id <= leakage_bin[j]) { 3245 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i]; 3246 break; 3247 } 3248 } 3249 break; 3250 } 3251 } 3252 } 3253 break; 3254 default: 3255 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3256 return -EINVAL; 3257 } 3258 break; 3259 default: 3260 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3261 return -EINVAL; 3262 } 3263 3264 return 0; 3265 } 3266 3267 union get_voltage_info { 3268 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in; 3269 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out; 3270 }; 3271 3272 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 3273 u16 virtual_voltage_id, 3274 u16 *voltage) 3275 { 3276 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo); 3277 u32 entry_id; 3278 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; 3279 union get_voltage_info args; 3280 3281 for (entry_id = 0; entry_id < count; entry_id++) { 3282 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == 3283 virtual_voltage_id) 3284 break; 3285 } 3286 3287 if (entry_id >= count) 3288 return -EINVAL; 3289 3290 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC; 3291 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE; 3292 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id); 3293 args.in.ulSCLKFreq = 3294 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); 3295 3296 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3297 3298 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel); 3299 3300 return 0; 3301 } 3302 3303 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 3304 u16 voltage_level, u8 voltage_type, 3305 u32 *gpio_value, u32 *gpio_mask) 3306 { 3307 union set_voltage args; 3308 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3309 u8 frev, crev; 3310 3311 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3312 return -EINVAL; 3313 3314 switch (crev) { 3315 case 1: 3316 return -EINVAL; 3317 case 2: 3318 args.v2.ucVoltageType = voltage_type; 3319 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK; 3320 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3321 3322 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3323 3324 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2); 3325 3326 args.v2.ucVoltageType = voltage_type; 3327 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL; 3328 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3329 3330 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3331 3332 *gpio_value = le32_to_cpu(*(u32 *)&args.v2); 3333 break; 3334 default: 3335 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3336 return -EINVAL; 3337 } 3338 3339 return 0; 3340 } 3341 3342 union voltage_object_info { 3343 struct _ATOM_VOLTAGE_OBJECT_INFO v1; 3344 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2; 3345 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; 3346 }; 3347 3348 union voltage_object { 3349 struct _ATOM_VOLTAGE_OBJECT v1; 3350 struct _ATOM_VOLTAGE_OBJECT_V2 v2; 3351 union _ATOM_VOLTAGE_OBJECT_V3 v3; 3352 }; 3353 3354 static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1, 3355 u8 voltage_type) 3356 { 3357 u32 size = le16_to_cpu(v1->sHeader.usStructureSize); 3358 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]); 3359 u8 *start = (u8 *)v1; 3360 3361 while (offset < size) { 3362 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset); 3363 if (vo->ucVoltageType == voltage_type) 3364 return vo; 3365 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) + 3366 vo->asFormula.ucNumOfVoltageEntries; 3367 } 3368 return NULL; 3369 } 3370 3371 static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2, 3372 u8 voltage_type) 3373 { 3374 u32 size = le16_to_cpu(v2->sHeader.usStructureSize); 3375 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]); 3376 u8 *start = (u8*)v2; 3377 3378 while (offset < size) { 3379 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset); 3380 if (vo->ucVoltageType == voltage_type) 3381 return vo; 3382 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) + 3383 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY)); 3384 } 3385 return NULL; 3386 } 3387 3388 static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3, 3389 u8 voltage_type, u8 voltage_mode) 3390 { 3391 u32 size = le16_to_cpu(v3->sHeader.usStructureSize); 3392 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]); 3393 u8 *start = (u8*)v3; 3394 3395 while (offset < size) { 3396 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset); 3397 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) && 3398 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode)) 3399 return vo; 3400 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize); 3401 } 3402 return NULL; 3403 } 3404 3405 bool 3406 radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 3407 u8 voltage_type, u8 voltage_mode) 3408 { 3409 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3410 u8 frev, crev; 3411 u16 data_offset, size; 3412 union voltage_object_info *voltage_info; 3413 union voltage_object *voltage_object = NULL; 3414 3415 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3416 &frev, &crev, &data_offset)) { 3417 voltage_info = (union voltage_object_info *) 3418 (rdev->mode_info.atom_context->bios + data_offset); 3419 3420 switch (frev) { 3421 case 1: 3422 case 2: 3423 switch (crev) { 3424 case 1: 3425 voltage_object = (union voltage_object *) 3426 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3427 if (voltage_object && 3428 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO)) 3429 return true; 3430 break; 3431 case 2: 3432 voltage_object = (union voltage_object *) 3433 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3434 if (voltage_object && 3435 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO)) 3436 return true; 3437 break; 3438 default: 3439 DRM_ERROR("unknown voltage object table\n"); 3440 return false; 3441 } 3442 break; 3443 case 3: 3444 switch (crev) { 3445 case 1: 3446 if (atom_lookup_voltage_object_v3(&voltage_info->v3, 3447 voltage_type, voltage_mode)) 3448 return true; 3449 break; 3450 default: 3451 DRM_ERROR("unknown voltage object table\n"); 3452 return false; 3453 } 3454 break; 3455 default: 3456 DRM_ERROR("unknown voltage object table\n"); 3457 return false; 3458 } 3459 3460 } 3461 return false; 3462 } 3463 3464 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 3465 u8 voltage_type, 3466 u8 *svd_gpio_id, u8 *svc_gpio_id) 3467 { 3468 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3469 u8 frev, crev; 3470 u16 data_offset, size; 3471 union voltage_object_info *voltage_info; 3472 union voltage_object *voltage_object = NULL; 3473 3474 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3475 &frev, &crev, &data_offset)) { 3476 voltage_info = (union voltage_object_info *) 3477 (rdev->mode_info.atom_context->bios + data_offset); 3478 3479 switch (frev) { 3480 case 3: 3481 switch (crev) { 3482 case 1: 3483 voltage_object = (union voltage_object *) 3484 atom_lookup_voltage_object_v3(&voltage_info->v3, 3485 voltage_type, 3486 VOLTAGE_OBJ_SVID2); 3487 if (voltage_object) { 3488 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId; 3489 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId; 3490 } else { 3491 return -EINVAL; 3492 } 3493 break; 3494 default: 3495 DRM_ERROR("unknown voltage object table\n"); 3496 return -EINVAL; 3497 } 3498 break; 3499 default: 3500 DRM_ERROR("unknown voltage object table\n"); 3501 return -EINVAL; 3502 } 3503 3504 } 3505 return 0; 3506 } 3507 3508 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 3509 u8 voltage_type, u16 *max_voltage) 3510 { 3511 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3512 u8 frev, crev; 3513 u16 data_offset, size; 3514 union voltage_object_info *voltage_info; 3515 union voltage_object *voltage_object = NULL; 3516 3517 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3518 &frev, &crev, &data_offset)) { 3519 voltage_info = (union voltage_object_info *) 3520 (rdev->mode_info.atom_context->bios + data_offset); 3521 3522 switch (crev) { 3523 case 1: 3524 voltage_object = (union voltage_object *) 3525 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3526 if (voltage_object) { 3527 ATOM_VOLTAGE_FORMULA *formula = 3528 &voltage_object->v1.asFormula; 3529 if (formula->ucFlag & 1) 3530 *max_voltage = 3531 le16_to_cpu(formula->usVoltageBaseLevel) + 3532 formula->ucNumOfVoltageEntries / 2 * 3533 le16_to_cpu(formula->usVoltageStep); 3534 else 3535 *max_voltage = 3536 le16_to_cpu(formula->usVoltageBaseLevel) + 3537 (formula->ucNumOfVoltageEntries - 1) * 3538 le16_to_cpu(formula->usVoltageStep); 3539 return 0; 3540 } 3541 break; 3542 case 2: 3543 voltage_object = (union voltage_object *) 3544 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3545 if (voltage_object) { 3546 ATOM_VOLTAGE_FORMULA_V2 *formula = 3547 &voltage_object->v2.asFormula; 3548 if (formula->ucNumOfVoltageEntries) { 3549 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *) 3550 ((u8 *)&formula->asVIDAdjustEntries[0] + 3551 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1))); 3552 *max_voltage = 3553 le16_to_cpu(lut->usVoltageValue); 3554 return 0; 3555 } 3556 } 3557 break; 3558 default: 3559 DRM_ERROR("unknown voltage object table\n"); 3560 return -EINVAL; 3561 } 3562 3563 } 3564 return -EINVAL; 3565 } 3566 3567 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 3568 u8 voltage_type, u16 *min_voltage) 3569 { 3570 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3571 u8 frev, crev; 3572 u16 data_offset, size; 3573 union voltage_object_info *voltage_info; 3574 union voltage_object *voltage_object = NULL; 3575 3576 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3577 &frev, &crev, &data_offset)) { 3578 voltage_info = (union voltage_object_info *) 3579 (rdev->mode_info.atom_context->bios + data_offset); 3580 3581 switch (crev) { 3582 case 1: 3583 voltage_object = (union voltage_object *) 3584 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3585 if (voltage_object) { 3586 ATOM_VOLTAGE_FORMULA *formula = 3587 &voltage_object->v1.asFormula; 3588 *min_voltage = 3589 le16_to_cpu(formula->usVoltageBaseLevel); 3590 return 0; 3591 } 3592 break; 3593 case 2: 3594 voltage_object = (union voltage_object *) 3595 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3596 if (voltage_object) { 3597 ATOM_VOLTAGE_FORMULA_V2 *formula = 3598 &voltage_object->v2.asFormula; 3599 if (formula->ucNumOfVoltageEntries) { 3600 *min_voltage = 3601 le16_to_cpu(formula->asVIDAdjustEntries[ 3602 0 3603 ].usVoltageValue); 3604 return 0; 3605 } 3606 } 3607 break; 3608 default: 3609 DRM_ERROR("unknown voltage object table\n"); 3610 return -EINVAL; 3611 } 3612 3613 } 3614 return -EINVAL; 3615 } 3616 3617 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 3618 u8 voltage_type, u16 *voltage_step) 3619 { 3620 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3621 u8 frev, crev; 3622 u16 data_offset, size; 3623 union voltage_object_info *voltage_info; 3624 union voltage_object *voltage_object = NULL; 3625 3626 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3627 &frev, &crev, &data_offset)) { 3628 voltage_info = (union voltage_object_info *) 3629 (rdev->mode_info.atom_context->bios + data_offset); 3630 3631 switch (crev) { 3632 case 1: 3633 voltage_object = (union voltage_object *) 3634 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3635 if (voltage_object) { 3636 ATOM_VOLTAGE_FORMULA *formula = 3637 &voltage_object->v1.asFormula; 3638 if (formula->ucFlag & 1) 3639 *voltage_step = 3640 (le16_to_cpu(formula->usVoltageStep) + 1) / 2; 3641 else 3642 *voltage_step = 3643 le16_to_cpu(formula->usVoltageStep); 3644 return 0; 3645 } 3646 break; 3647 case 2: 3648 return -EINVAL; 3649 default: 3650 DRM_ERROR("unknown voltage object table\n"); 3651 return -EINVAL; 3652 } 3653 3654 } 3655 return -EINVAL; 3656 } 3657 3658 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 3659 u8 voltage_type, 3660 u16 nominal_voltage, 3661 u16 *true_voltage) 3662 { 3663 u16 min_voltage, max_voltage, voltage_step; 3664 3665 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage)) 3666 return -EINVAL; 3667 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage)) 3668 return -EINVAL; 3669 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step)) 3670 return -EINVAL; 3671 3672 if (nominal_voltage <= min_voltage) 3673 *true_voltage = min_voltage; 3674 else if (nominal_voltage >= max_voltage) 3675 *true_voltage = max_voltage; 3676 else 3677 *true_voltage = min_voltage + 3678 ((nominal_voltage - min_voltage) / voltage_step) * 3679 voltage_step; 3680 3681 return 0; 3682 } 3683 3684 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 3685 u8 voltage_type, u8 voltage_mode, 3686 struct atom_voltage_table *voltage_table) 3687 { 3688 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3689 u8 frev, crev; 3690 u16 data_offset, size; 3691 int i, ret; 3692 union voltage_object_info *voltage_info; 3693 union voltage_object *voltage_object = NULL; 3694 3695 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3696 &frev, &crev, &data_offset)) { 3697 voltage_info = (union voltage_object_info *) 3698 (rdev->mode_info.atom_context->bios + data_offset); 3699 3700 switch (frev) { 3701 case 1: 3702 case 2: 3703 switch (crev) { 3704 case 1: 3705 DRM_ERROR("old table version %d, %d\n", frev, crev); 3706 return -EINVAL; 3707 case 2: 3708 voltage_object = (union voltage_object *) 3709 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3710 if (voltage_object) { 3711 ATOM_VOLTAGE_FORMULA_V2 *formula = 3712 &voltage_object->v2.asFormula; 3713 VOLTAGE_LUT_ENTRY *lut; 3714 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES) 3715 return -EINVAL; 3716 lut = &formula->asVIDAdjustEntries[0]; 3717 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) { 3718 voltage_table->entries[i].value = 3719 le16_to_cpu(lut->usVoltageValue); 3720 ret = radeon_atom_get_voltage_gpio_settings(rdev, 3721 voltage_table->entries[i].value, 3722 voltage_type, 3723 &voltage_table->entries[i].smio_low, 3724 &voltage_table->mask_low); 3725 if (ret) 3726 return ret; 3727 lut = (VOLTAGE_LUT_ENTRY *) 3728 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY)); 3729 } 3730 voltage_table->count = formula->ucNumOfVoltageEntries; 3731 return 0; 3732 } 3733 break; 3734 default: 3735 DRM_ERROR("unknown voltage object table\n"); 3736 return -EINVAL; 3737 } 3738 break; 3739 case 3: 3740 switch (crev) { 3741 case 1: 3742 voltage_object = (union voltage_object *) 3743 atom_lookup_voltage_object_v3(&voltage_info->v3, 3744 voltage_type, voltage_mode); 3745 if (voltage_object) { 3746 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio = 3747 &voltage_object->v3.asGpioVoltageObj; 3748 VOLTAGE_LUT_ENTRY_V2 *lut; 3749 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES) 3750 return -EINVAL; 3751 lut = &gpio->asVolGpioLut[0]; 3752 for (i = 0; i < gpio->ucGpioEntryNum; i++) { 3753 voltage_table->entries[i].value = 3754 le16_to_cpu(lut->usVoltageValue); 3755 voltage_table->entries[i].smio_low = 3756 le32_to_cpu(lut->ulVoltageId); 3757 lut = (VOLTAGE_LUT_ENTRY_V2 *) 3758 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2)); 3759 } 3760 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal); 3761 voltage_table->count = gpio->ucGpioEntryNum; 3762 voltage_table->phase_delay = gpio->ucPhaseDelay; 3763 return 0; 3764 } 3765 break; 3766 default: 3767 DRM_ERROR("unknown voltage object table\n"); 3768 return -EINVAL; 3769 } 3770 break; 3771 default: 3772 DRM_ERROR("unknown voltage object table\n"); 3773 return -EINVAL; 3774 } 3775 } 3776 return -EINVAL; 3777 } 3778 3779 union vram_info { 3780 struct _ATOM_VRAM_INFO_V3 v1_3; 3781 struct _ATOM_VRAM_INFO_V4 v1_4; 3782 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; 3783 }; 3784 3785 int radeon_atom_get_memory_info(struct radeon_device *rdev, 3786 u8 module_index, struct atom_memory_info *mem_info) 3787 { 3788 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3789 u8 frev, crev, i; 3790 u16 data_offset, size; 3791 union vram_info *vram_info; 3792 3793 memset(mem_info, 0, sizeof(struct atom_memory_info)); 3794 3795 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3796 &frev, &crev, &data_offset)) { 3797 vram_info = (union vram_info *) 3798 (rdev->mode_info.atom_context->bios + data_offset); 3799 switch (frev) { 3800 case 1: 3801 switch (crev) { 3802 case 3: 3803 /* r6xx */ 3804 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) { 3805 ATOM_VRAM_MODULE_V3 *vram_module = 3806 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo; 3807 3808 for (i = 0; i < module_index; i++) { 3809 if (le16_to_cpu(vram_module->usSize) == 0) 3810 return -EINVAL; 3811 vram_module = (ATOM_VRAM_MODULE_V3 *) 3812 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize)); 3813 } 3814 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf; 3815 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0; 3816 } else 3817 return -EINVAL; 3818 break; 3819 case 4: 3820 /* r7xx, evergreen */ 3821 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) { 3822 ATOM_VRAM_MODULE_V4 *vram_module = 3823 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo; 3824 3825 for (i = 0; i < module_index; i++) { 3826 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3827 return -EINVAL; 3828 vram_module = (ATOM_VRAM_MODULE_V4 *) 3829 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3830 } 3831 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf; 3832 mem_info->mem_type = vram_module->ucMemoryType & 0xf0; 3833 } else 3834 return -EINVAL; 3835 break; 3836 default: 3837 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3838 return -EINVAL; 3839 } 3840 break; 3841 case 2: 3842 switch (crev) { 3843 case 1: 3844 /* ni */ 3845 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { 3846 ATOM_VRAM_MODULE_V7 *vram_module = 3847 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo; 3848 3849 for (i = 0; i < module_index; i++) { 3850 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3851 return -EINVAL; 3852 vram_module = (ATOM_VRAM_MODULE_V7 *) 3853 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3854 } 3855 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf; 3856 mem_info->mem_type = vram_module->ucMemoryType & 0xf0; 3857 } else 3858 return -EINVAL; 3859 break; 3860 default: 3861 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3862 return -EINVAL; 3863 } 3864 break; 3865 default: 3866 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3867 return -EINVAL; 3868 } 3869 return 0; 3870 } 3871 return -EINVAL; 3872 } 3873 3874 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 3875 bool gddr5, u8 module_index, 3876 struct atom_memory_clock_range_table *mclk_range_table) 3877 { 3878 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3879 u8 frev, crev, i; 3880 u16 data_offset, size; 3881 union vram_info *vram_info; 3882 u32 mem_timing_size = gddr5 ? 3883 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT); 3884 3885 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table)); 3886 3887 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3888 &frev, &crev, &data_offset)) { 3889 vram_info = (union vram_info *) 3890 (rdev->mode_info.atom_context->bios + data_offset); 3891 switch (frev) { 3892 case 1: 3893 switch (crev) { 3894 case 3: 3895 DRM_ERROR("old table version %d, %d\n", frev, crev); 3896 return -EINVAL; 3897 case 4: 3898 /* r7xx, evergreen */ 3899 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) { 3900 ATOM_VRAM_MODULE_V4 *vram_module = 3901 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo; 3902 ATOM_MEMORY_TIMING_FORMAT *format; 3903 3904 for (i = 0; i < module_index; i++) { 3905 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3906 return -EINVAL; 3907 vram_module = (ATOM_VRAM_MODULE_V4 *) 3908 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3909 } 3910 mclk_range_table->num_entries = (u8) 3911 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) / 3912 mem_timing_size); 3913 format = &vram_module->asMemTiming[0]; 3914 for (i = 0; i < mclk_range_table->num_entries; i++) { 3915 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange); 3916 format = (ATOM_MEMORY_TIMING_FORMAT *) 3917 ((u8 *)format + mem_timing_size); 3918 } 3919 } else 3920 return -EINVAL; 3921 break; 3922 default: 3923 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3924 return -EINVAL; 3925 } 3926 break; 3927 case 2: 3928 DRM_ERROR("new table version %d, %d\n", frev, crev); 3929 return -EINVAL; 3930 default: 3931 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3932 return -EINVAL; 3933 } 3934 return 0; 3935 } 3936 return -EINVAL; 3937 } 3938 3939 #define MEM_ID_MASK 0xff000000 3940 #define MEM_ID_SHIFT 24 3941 #define CLOCK_RANGE_MASK 0x00ffffff 3942 #define CLOCK_RANGE_SHIFT 0 3943 #define LOW_NIBBLE_MASK 0xf 3944 #define DATA_EQU_PREV 0 3945 #define DATA_FROM_TABLE 4 3946 3947 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 3948 u8 module_index, 3949 struct atom_mc_reg_table *reg_table) 3950 { 3951 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3952 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0; 3953 u32 i = 0, j; 3954 u16 data_offset, size; 3955 union vram_info *vram_info; 3956 3957 memset(reg_table, 0, sizeof(struct atom_mc_reg_table)); 3958 3959 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3960 &frev, &crev, &data_offset)) { 3961 vram_info = (union vram_info *) 3962 (rdev->mode_info.atom_context->bios + data_offset); 3963 switch (frev) { 3964 case 1: 3965 DRM_ERROR("old table version %d, %d\n", frev, crev); 3966 return -EINVAL; 3967 case 2: 3968 switch (crev) { 3969 case 1: 3970 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { 3971 ATOM_INIT_REG_BLOCK *reg_block = 3972 (ATOM_INIT_REG_BLOCK *) 3973 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); 3974 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = 3975 (ATOM_MEMORY_SETTING_DATA_BLOCK *) 3976 ((u8 *)reg_block + (2 * sizeof(u16)) + 3977 le16_to_cpu(reg_block->usRegIndexTblSize)); 3978 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0]; 3979 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) / 3980 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1; 3981 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE) 3982 return -EINVAL; 3983 while (i < num_entries) { 3984 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER) 3985 break; 3986 reg_table->mc_reg_address[i].s1 = 3987 (u16)(le16_to_cpu(format->usRegIndex)); 3988 reg_table->mc_reg_address[i].pre_reg_data = 3989 (u8)(format->ucPreRegDataLength); 3990 i++; 3991 format = (ATOM_INIT_REG_INDEX_FORMAT *) 3992 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT)); 3993 } 3994 reg_table->last = i; 3995 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && 3996 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) { 3997 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) 3998 >> MEM_ID_SHIFT); 3999 if (module_index == t_mem_id) { 4000 reg_table->mc_reg_table_entry[num_ranges].mclk_max = 4001 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) 4002 >> CLOCK_RANGE_SHIFT); 4003 for (i = 0, j = 1; i < reg_table->last; i++) { 4004 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { 4005 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 4006 (u32)le32_to_cpu(*((u32 *)reg_data + j)); 4007 j++; 4008 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { 4009 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 4010 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1]; 4011 } 4012 } 4013 num_ranges++; 4014 } 4015 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) 4016 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); 4017 } 4018 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) 4019 return -EINVAL; 4020 reg_table->num_entries = num_ranges; 4021 } else 4022 return -EINVAL; 4023 break; 4024 default: 4025 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 4026 return -EINVAL; 4027 } 4028 break; 4029 default: 4030 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 4031 return -EINVAL; 4032 } 4033 return 0; 4034 } 4035 return -EINVAL; 4036 } 4037 4038 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) 4039 { 4040 struct radeon_device *rdev = dev->dev_private; 4041 uint32_t bios_2_scratch, bios_6_scratch; 4042 4043 if (rdev->family >= CHIP_R600) { 4044 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 4045 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 4046 } else { 4047 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 4048 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 4049 } 4050 4051 /* let the bios control the backlight */ 4052 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; 4053 4054 /* tell the bios not to handle mode switching */ 4055 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; 4056 4057 /* clear the vbios dpms state */ 4058 if (ASIC_IS_DCE4(rdev)) 4059 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE; 4060 4061 if (rdev->family >= CHIP_R600) { 4062 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 4063 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 4064 } else { 4065 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 4066 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 4067 } 4068 4069 } 4070 4071 void radeon_save_bios_scratch_regs(struct radeon_device *rdev) 4072 { 4073 uint32_t scratch_reg; 4074 int i; 4075 4076 if (rdev->family >= CHIP_R600) 4077 scratch_reg = R600_BIOS_0_SCRATCH; 4078 else 4079 scratch_reg = RADEON_BIOS_0_SCRATCH; 4080 4081 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) 4082 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4)); 4083 } 4084 4085 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev) 4086 { 4087 uint32_t scratch_reg; 4088 int i; 4089 4090 if (rdev->family >= CHIP_R600) 4091 scratch_reg = R600_BIOS_0_SCRATCH; 4092 else 4093 scratch_reg = RADEON_BIOS_0_SCRATCH; 4094 4095 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) 4096 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]); 4097 } 4098 4099 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) 4100 { 4101 struct drm_device *dev = encoder->dev; 4102 struct radeon_device *rdev = dev->dev_private; 4103 uint32_t bios_6_scratch; 4104 4105 if (rdev->family >= CHIP_R600) 4106 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 4107 else 4108 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 4109 4110 if (lock) { 4111 bios_6_scratch |= ATOM_S6_CRITICAL_STATE; 4112 bios_6_scratch &= ~ATOM_S6_ACC_MODE; 4113 } else { 4114 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; 4115 bios_6_scratch |= ATOM_S6_ACC_MODE; 4116 } 4117 4118 if (rdev->family >= CHIP_R600) 4119 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 4120 else 4121 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 4122 } 4123 4124 /* at some point we may want to break this out into individual functions */ 4125 void 4126 radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 4127 struct drm_encoder *encoder, 4128 bool connected) 4129 { 4130 struct drm_device *dev = connector->dev; 4131 struct radeon_device *rdev = dev->dev_private; 4132 struct radeon_connector *radeon_connector = 4133 to_radeon_connector(connector); 4134 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4135 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch; 4136 4137 if (rdev->family >= CHIP_R600) { 4138 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 4139 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 4140 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 4141 } else { 4142 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 4143 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 4144 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 4145 } 4146 4147 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 4148 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 4149 if (connected) { 4150 DRM_DEBUG_KMS("TV1 connected\n"); 4151 bios_3_scratch |= ATOM_S3_TV1_ACTIVE; 4152 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1; 4153 } else { 4154 DRM_DEBUG_KMS("TV1 disconnected\n"); 4155 bios_0_scratch &= ~ATOM_S0_TV1_MASK; 4156 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; 4157 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1; 4158 } 4159 } 4160 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) && 4161 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) { 4162 if (connected) { 4163 DRM_DEBUG_KMS("CV connected\n"); 4164 bios_3_scratch |= ATOM_S3_CV_ACTIVE; 4165 bios_6_scratch |= ATOM_S6_ACC_REQ_CV; 4166 } else { 4167 DRM_DEBUG_KMS("CV disconnected\n"); 4168 bios_0_scratch &= ~ATOM_S0_CV_MASK; 4169 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; 4170 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV; 4171 } 4172 } 4173 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 4174 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 4175 if (connected) { 4176 DRM_DEBUG_KMS("LCD1 connected\n"); 4177 bios_0_scratch |= ATOM_S0_LCD1; 4178 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; 4179 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; 4180 } else { 4181 DRM_DEBUG_KMS("LCD1 disconnected\n"); 4182 bios_0_scratch &= ~ATOM_S0_LCD1; 4183 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; 4184 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; 4185 } 4186 } 4187 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 4188 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 4189 if (connected) { 4190 DRM_DEBUG_KMS("CRT1 connected\n"); 4191 bios_0_scratch |= ATOM_S0_CRT1_COLOR; 4192 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; 4193 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; 4194 } else { 4195 DRM_DEBUG_KMS("CRT1 disconnected\n"); 4196 bios_0_scratch &= ~ATOM_S0_CRT1_MASK; 4197 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; 4198 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; 4199 } 4200 } 4201 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 4202 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 4203 if (connected) { 4204 DRM_DEBUG_KMS("CRT2 connected\n"); 4205 bios_0_scratch |= ATOM_S0_CRT2_COLOR; 4206 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; 4207 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; 4208 } else { 4209 DRM_DEBUG_KMS("CRT2 disconnected\n"); 4210 bios_0_scratch &= ~ATOM_S0_CRT2_MASK; 4211 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; 4212 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; 4213 } 4214 } 4215 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 4216 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 4217 if (connected) { 4218 DRM_DEBUG_KMS("DFP1 connected\n"); 4219 bios_0_scratch |= ATOM_S0_DFP1; 4220 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; 4221 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; 4222 } else { 4223 DRM_DEBUG_KMS("DFP1 disconnected\n"); 4224 bios_0_scratch &= ~ATOM_S0_DFP1; 4225 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; 4226 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; 4227 } 4228 } 4229 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 4230 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 4231 if (connected) { 4232 DRM_DEBUG_KMS("DFP2 connected\n"); 4233 bios_0_scratch |= ATOM_S0_DFP2; 4234 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; 4235 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; 4236 } else { 4237 DRM_DEBUG_KMS("DFP2 disconnected\n"); 4238 bios_0_scratch &= ~ATOM_S0_DFP2; 4239 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; 4240 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; 4241 } 4242 } 4243 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && 4244 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { 4245 if (connected) { 4246 DRM_DEBUG_KMS("DFP3 connected\n"); 4247 bios_0_scratch |= ATOM_S0_DFP3; 4248 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; 4249 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; 4250 } else { 4251 DRM_DEBUG_KMS("DFP3 disconnected\n"); 4252 bios_0_scratch &= ~ATOM_S0_DFP3; 4253 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; 4254 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; 4255 } 4256 } 4257 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && 4258 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { 4259 if (connected) { 4260 DRM_DEBUG_KMS("DFP4 connected\n"); 4261 bios_0_scratch |= ATOM_S0_DFP4; 4262 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; 4263 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; 4264 } else { 4265 DRM_DEBUG_KMS("DFP4 disconnected\n"); 4266 bios_0_scratch &= ~ATOM_S0_DFP4; 4267 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; 4268 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; 4269 } 4270 } 4271 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && 4272 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { 4273 if (connected) { 4274 DRM_DEBUG_KMS("DFP5 connected\n"); 4275 bios_0_scratch |= ATOM_S0_DFP5; 4276 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; 4277 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; 4278 } else { 4279 DRM_DEBUG_KMS("DFP5 disconnected\n"); 4280 bios_0_scratch &= ~ATOM_S0_DFP5; 4281 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; 4282 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; 4283 } 4284 } 4285 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) && 4286 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) { 4287 if (connected) { 4288 DRM_DEBUG_KMS("DFP6 connected\n"); 4289 bios_0_scratch |= ATOM_S0_DFP6; 4290 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE; 4291 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6; 4292 } else { 4293 DRM_DEBUG_KMS("DFP6 disconnected\n"); 4294 bios_0_scratch &= ~ATOM_S0_DFP6; 4295 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE; 4296 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6; 4297 } 4298 } 4299 4300 if (rdev->family >= CHIP_R600) { 4301 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); 4302 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 4303 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 4304 } else { 4305 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 4306 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 4307 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 4308 } 4309 } 4310 4311 void 4312 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 4313 { 4314 struct drm_device *dev = encoder->dev; 4315 struct radeon_device *rdev = dev->dev_private; 4316 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4317 uint32_t bios_3_scratch; 4318 4319 if (ASIC_IS_DCE4(rdev)) 4320 return; 4321 4322 if (rdev->family >= CHIP_R600) 4323 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 4324 else 4325 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 4326 4327 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 4328 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE; 4329 bios_3_scratch |= (crtc << 18); 4330 } 4331 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 4332 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE; 4333 bios_3_scratch |= (crtc << 24); 4334 } 4335 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 4336 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE; 4337 bios_3_scratch |= (crtc << 16); 4338 } 4339 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 4340 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE; 4341 bios_3_scratch |= (crtc << 20); 4342 } 4343 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 4344 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE; 4345 bios_3_scratch |= (crtc << 17); 4346 } 4347 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 4348 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE; 4349 bios_3_scratch |= (crtc << 19); 4350 } 4351 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 4352 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE; 4353 bios_3_scratch |= (crtc << 23); 4354 } 4355 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 4356 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE; 4357 bios_3_scratch |= (crtc << 25); 4358 } 4359 4360 if (rdev->family >= CHIP_R600) 4361 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 4362 else 4363 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 4364 } 4365 4366 void 4367 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 4368 { 4369 struct drm_device *dev = encoder->dev; 4370 struct radeon_device *rdev = dev->dev_private; 4371 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4372 uint32_t bios_2_scratch; 4373 4374 if (ASIC_IS_DCE4(rdev)) 4375 return; 4376 4377 if (rdev->family >= CHIP_R600) 4378 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 4379 else 4380 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 4381 4382 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 4383 if (on) 4384 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE; 4385 else 4386 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE; 4387 } 4388 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 4389 if (on) 4390 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE; 4391 else 4392 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE; 4393 } 4394 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 4395 if (on) 4396 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE; 4397 else 4398 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE; 4399 } 4400 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 4401 if (on) 4402 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE; 4403 else 4404 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE; 4405 } 4406 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 4407 if (on) 4408 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE; 4409 else 4410 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE; 4411 } 4412 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 4413 if (on) 4414 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE; 4415 else 4416 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE; 4417 } 4418 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 4419 if (on) 4420 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE; 4421 else 4422 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE; 4423 } 4424 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 4425 if (on) 4426 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE; 4427 else 4428 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE; 4429 } 4430 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) { 4431 if (on) 4432 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE; 4433 else 4434 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE; 4435 } 4436 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) { 4437 if (on) 4438 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE; 4439 else 4440 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE; 4441 } 4442 4443 if (rdev->family >= CHIP_R600) 4444 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 4445 else 4446 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 4447 } 4448