1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include "drmP.h" 27 #include "radeon_drm.h" 28 #include "radeon.h" 29 30 #include "atom.h" 31 #include "atom-bits.h" 32 33 /* from radeon_encoder.c */ 34 extern uint32_t 35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, 36 uint8_t dac); 37 extern void radeon_link_encoder_connector(struct drm_device *dev); 38 extern void 39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, 40 uint32_t supported_device); 41 42 /* from radeon_connector.c */ 43 extern void 44 radeon_add_atom_connector(struct drm_device *dev, 45 uint32_t connector_id, 46 uint32_t supported_device, 47 int connector_type, 48 struct radeon_i2c_bus_rec *i2c_bus, 49 bool linkb, uint32_t igp_lane_info, 50 uint16_t connector_object_id, 51 struct radeon_hpd *hpd); 52 53 /* from radeon_legacy_encoder.c */ 54 extern void 55 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, 56 uint32_t supported_device); 57 58 union atom_supported_devices { 59 struct _ATOM_SUPPORTED_DEVICES_INFO info; 60 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2; 61 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1; 62 }; 63 64 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev, 65 uint8_t id) 66 { 67 struct atom_context *ctx = rdev->mode_info.atom_context; 68 ATOM_GPIO_I2C_ASSIGMENT *gpio; 69 struct radeon_i2c_bus_rec i2c; 70 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 71 struct _ATOM_GPIO_I2C_INFO *i2c_info; 72 uint16_t data_offset; 73 int i; 74 75 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 76 i2c.valid = false; 77 78 atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset); 79 80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 81 82 83 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { 84 gpio = &i2c_info->asGPIO_Info[i]; 85 86 if (gpio->sucI2cId.ucAccess == id) { 87 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; 88 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; 89 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4; 90 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4; 91 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4; 92 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4; 93 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4; 94 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4; 95 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); 96 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); 97 i2c.en_clk_mask = (1 << gpio->ucClkEnShift); 98 i2c.en_data_mask = (1 << gpio->ucDataEnShift); 99 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); 100 i2c.y_data_mask = (1 << gpio->ucDataY_Shift); 101 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); 102 i2c.a_data_mask = (1 << gpio->ucDataA_Shift); 103 104 if (gpio->sucI2cId.sbfAccess.bfHW_Capable) 105 i2c.hw_capable = true; 106 else 107 i2c.hw_capable = false; 108 109 if (gpio->sucI2cId.ucAccess == 0xa0) 110 i2c.mm_i2c = true; 111 else 112 i2c.mm_i2c = false; 113 114 i2c.i2c_id = gpio->sucI2cId.ucAccess; 115 116 i2c.valid = true; 117 break; 118 } 119 } 120 121 return i2c; 122 } 123 124 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev, 125 u8 id) 126 { 127 struct atom_context *ctx = rdev->mode_info.atom_context; 128 struct radeon_gpio_rec gpio; 129 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); 130 struct _ATOM_GPIO_PIN_LUT *gpio_info; 131 ATOM_GPIO_PIN_ASSIGNMENT *pin; 132 u16 data_offset, size; 133 int i, num_indices; 134 135 memset(&gpio, 0, sizeof(struct radeon_gpio_rec)); 136 gpio.valid = false; 137 138 atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset); 139 140 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset); 141 142 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / sizeof(ATOM_GPIO_PIN_ASSIGNMENT); 143 144 for (i = 0; i < num_indices; i++) { 145 pin = &gpio_info->asGPIO_Pin[i]; 146 if (id == pin->ucGPIO_ID) { 147 gpio.id = pin->ucGPIO_ID; 148 gpio.reg = pin->usGpioPin_AIndex * 4; 149 gpio.mask = (1 << pin->ucGpioPinBitShift); 150 gpio.valid = true; 151 break; 152 } 153 } 154 155 return gpio; 156 } 157 158 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev, 159 struct radeon_gpio_rec *gpio) 160 { 161 struct radeon_hpd hpd; 162 hpd.gpio = *gpio; 163 if (gpio->reg == AVIVO_DC_GPIO_HPD_A) { 164 switch(gpio->mask) { 165 case (1 << 0): 166 hpd.hpd = RADEON_HPD_1; 167 break; 168 case (1 << 8): 169 hpd.hpd = RADEON_HPD_2; 170 break; 171 case (1 << 16): 172 hpd.hpd = RADEON_HPD_3; 173 break; 174 case (1 << 24): 175 hpd.hpd = RADEON_HPD_4; 176 break; 177 case (1 << 26): 178 hpd.hpd = RADEON_HPD_5; 179 break; 180 case (1 << 28): 181 hpd.hpd = RADEON_HPD_6; 182 break; 183 default: 184 hpd.hpd = RADEON_HPD_NONE; 185 break; 186 } 187 } else 188 hpd.hpd = RADEON_HPD_NONE; 189 return hpd; 190 } 191 192 static bool radeon_atom_apply_quirks(struct drm_device *dev, 193 uint32_t supported_device, 194 int *connector_type, 195 struct radeon_i2c_bus_rec *i2c_bus, 196 uint16_t *line_mux, 197 struct radeon_hpd *hpd) 198 { 199 200 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ 201 if ((dev->pdev->device == 0x791e) && 202 (dev->pdev->subsystem_vendor == 0x1043) && 203 (dev->pdev->subsystem_device == 0x826d)) { 204 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && 205 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 206 *connector_type = DRM_MODE_CONNECTOR_DVID; 207 } 208 209 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */ 210 if ((dev->pdev->device == 0x7941) && 211 (dev->pdev->subsystem_vendor == 0x147b) && 212 (dev->pdev->subsystem_device == 0x2412)) { 213 if (*connector_type == DRM_MODE_CONNECTOR_DVII) 214 return false; 215 } 216 217 /* Falcon NW laptop lists vga ddc line for LVDS */ 218 if ((dev->pdev->device == 0x5653) && 219 (dev->pdev->subsystem_vendor == 0x1462) && 220 (dev->pdev->subsystem_device == 0x0291)) { 221 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) { 222 i2c_bus->valid = false; 223 *line_mux = 53; 224 } 225 } 226 227 /* HIS X1300 is DVI+VGA, not DVI+DVI */ 228 if ((dev->pdev->device == 0x7146) && 229 (dev->pdev->subsystem_vendor == 0x17af) && 230 (dev->pdev->subsystem_device == 0x2058)) { 231 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) 232 return false; 233 } 234 235 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */ 236 if ((dev->pdev->device == 0x7142) && 237 (dev->pdev->subsystem_vendor == 0x1458) && 238 (dev->pdev->subsystem_device == 0x2134)) { 239 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) 240 return false; 241 } 242 243 244 /* Funky macbooks */ 245 if ((dev->pdev->device == 0x71C5) && 246 (dev->pdev->subsystem_vendor == 0x106b) && 247 (dev->pdev->subsystem_device == 0x0080)) { 248 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) || 249 (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) 250 return false; 251 } 252 253 /* ASUS HD 3600 XT board lists the DVI port as HDMI */ 254 if ((dev->pdev->device == 0x9598) && 255 (dev->pdev->subsystem_vendor == 0x1043) && 256 (dev->pdev->subsystem_device == 0x01da)) { 257 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 258 *connector_type = DRM_MODE_CONNECTOR_DVII; 259 } 260 } 261 262 /* ASUS HD 3450 board lists the DVI port as HDMI */ 263 if ((dev->pdev->device == 0x95C5) && 264 (dev->pdev->subsystem_vendor == 0x1043) && 265 (dev->pdev->subsystem_device == 0x01e2)) { 266 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 267 *connector_type = DRM_MODE_CONNECTOR_DVII; 268 } 269 } 270 271 /* some BIOSes seem to report DAC on HDMI - usually this is a board with 272 * HDMI + VGA reporting as HDMI 273 */ 274 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 275 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { 276 *connector_type = DRM_MODE_CONNECTOR_VGA; 277 *line_mux = 0; 278 } 279 } 280 281 /* Acer laptop reports DVI-D as DVI-I */ 282 if ((dev->pdev->device == 0x95c4) && 283 (dev->pdev->subsystem_vendor == 0x1025) && 284 (dev->pdev->subsystem_device == 0x013c)) { 285 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) && 286 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) 287 *connector_type = DRM_MODE_CONNECTOR_DVID; 288 } 289 290 return true; 291 } 292 293 const int supported_devices_connector_convert[] = { 294 DRM_MODE_CONNECTOR_Unknown, 295 DRM_MODE_CONNECTOR_VGA, 296 DRM_MODE_CONNECTOR_DVII, 297 DRM_MODE_CONNECTOR_DVID, 298 DRM_MODE_CONNECTOR_DVIA, 299 DRM_MODE_CONNECTOR_SVIDEO, 300 DRM_MODE_CONNECTOR_Composite, 301 DRM_MODE_CONNECTOR_LVDS, 302 DRM_MODE_CONNECTOR_Unknown, 303 DRM_MODE_CONNECTOR_Unknown, 304 DRM_MODE_CONNECTOR_HDMIA, 305 DRM_MODE_CONNECTOR_HDMIB, 306 DRM_MODE_CONNECTOR_Unknown, 307 DRM_MODE_CONNECTOR_Unknown, 308 DRM_MODE_CONNECTOR_9PinDIN, 309 DRM_MODE_CONNECTOR_DisplayPort 310 }; 311 312 const uint16_t supported_devices_connector_object_id_convert[] = { 313 CONNECTOR_OBJECT_ID_NONE, 314 CONNECTOR_OBJECT_ID_VGA, 315 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */ 316 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */ 317 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */ 318 CONNECTOR_OBJECT_ID_COMPOSITE, 319 CONNECTOR_OBJECT_ID_SVIDEO, 320 CONNECTOR_OBJECT_ID_LVDS, 321 CONNECTOR_OBJECT_ID_9PIN_DIN, 322 CONNECTOR_OBJECT_ID_9PIN_DIN, 323 CONNECTOR_OBJECT_ID_DISPLAYPORT, 324 CONNECTOR_OBJECT_ID_HDMI_TYPE_A, 325 CONNECTOR_OBJECT_ID_HDMI_TYPE_B, 326 CONNECTOR_OBJECT_ID_SVIDEO 327 }; 328 329 const int object_connector_convert[] = { 330 DRM_MODE_CONNECTOR_Unknown, 331 DRM_MODE_CONNECTOR_DVII, 332 DRM_MODE_CONNECTOR_DVII, 333 DRM_MODE_CONNECTOR_DVID, 334 DRM_MODE_CONNECTOR_DVID, 335 DRM_MODE_CONNECTOR_VGA, 336 DRM_MODE_CONNECTOR_Composite, 337 DRM_MODE_CONNECTOR_SVIDEO, 338 DRM_MODE_CONNECTOR_Unknown, 339 DRM_MODE_CONNECTOR_Unknown, 340 DRM_MODE_CONNECTOR_9PinDIN, 341 DRM_MODE_CONNECTOR_Unknown, 342 DRM_MODE_CONNECTOR_HDMIA, 343 DRM_MODE_CONNECTOR_HDMIB, 344 DRM_MODE_CONNECTOR_LVDS, 345 DRM_MODE_CONNECTOR_9PinDIN, 346 DRM_MODE_CONNECTOR_Unknown, 347 DRM_MODE_CONNECTOR_Unknown, 348 DRM_MODE_CONNECTOR_Unknown, 349 DRM_MODE_CONNECTOR_DisplayPort 350 }; 351 352 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) 353 { 354 struct radeon_device *rdev = dev->dev_private; 355 struct radeon_mode_info *mode_info = &rdev->mode_info; 356 struct atom_context *ctx = mode_info->atom_context; 357 int index = GetIndexIntoMasterTable(DATA, Object_Header); 358 u16 size, data_offset; 359 u8 frev, crev; 360 ATOM_CONNECTOR_OBJECT_TABLE *con_obj; 361 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; 362 ATOM_OBJECT_HEADER *obj_header; 363 int i, j, path_size, device_support; 364 int connector_type; 365 u16 igp_lane_info, conn_id, connector_object_id; 366 bool linkb; 367 struct radeon_i2c_bus_rec ddc_bus; 368 struct radeon_gpio_rec gpio; 369 struct radeon_hpd hpd; 370 371 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset); 372 373 if (data_offset == 0) 374 return false; 375 376 if (crev < 2) 377 return false; 378 379 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); 380 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) 381 (ctx->bios + data_offset + 382 le16_to_cpu(obj_header->usDisplayPathTableOffset)); 383 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) 384 (ctx->bios + data_offset + 385 le16_to_cpu(obj_header->usConnectorObjectTableOffset)); 386 device_support = le16_to_cpu(obj_header->usDeviceSupport); 387 388 path_size = 0; 389 for (i = 0; i < path_obj->ucNumOfDispPath; i++) { 390 uint8_t *addr = (uint8_t *) path_obj->asDispPath; 391 ATOM_DISPLAY_OBJECT_PATH *path; 392 addr += path_size; 393 path = (ATOM_DISPLAY_OBJECT_PATH *) addr; 394 path_size += le16_to_cpu(path->usSize); 395 linkb = false; 396 if (device_support & le16_to_cpu(path->usDeviceTag)) { 397 uint8_t con_obj_id, con_obj_num, con_obj_type; 398 399 con_obj_id = 400 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) 401 >> OBJECT_ID_SHIFT; 402 con_obj_num = 403 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) 404 >> ENUM_ID_SHIFT; 405 con_obj_type = 406 (le16_to_cpu(path->usConnObjectId) & 407 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 408 409 /* TODO CV support */ 410 if (le16_to_cpu(path->usDeviceTag) == 411 ATOM_DEVICE_CV_SUPPORT) 412 continue; 413 414 /* IGP chips */ 415 if ((rdev->flags & RADEON_IS_IGP) && 416 (con_obj_id == 417 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { 418 uint16_t igp_offset = 0; 419 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj; 420 421 index = 422 GetIndexIntoMasterTable(DATA, 423 IntegratedSystemInfo); 424 425 atom_parse_data_header(ctx, index, &size, &frev, 426 &crev, &igp_offset); 427 428 if (crev >= 2) { 429 igp_obj = 430 (ATOM_INTEGRATED_SYSTEM_INFO_V2 431 *) (ctx->bios + igp_offset); 432 433 if (igp_obj) { 434 uint32_t slot_config, ct; 435 436 if (con_obj_num == 1) 437 slot_config = 438 igp_obj-> 439 ulDDISlot1Config; 440 else 441 slot_config = 442 igp_obj-> 443 ulDDISlot2Config; 444 445 ct = (slot_config >> 16) & 0xff; 446 connector_type = 447 object_connector_convert 448 [ct]; 449 connector_object_id = ct; 450 igp_lane_info = 451 slot_config & 0xffff; 452 } else 453 continue; 454 } else 455 continue; 456 } else { 457 igp_lane_info = 0; 458 connector_type = 459 object_connector_convert[con_obj_id]; 460 connector_object_id = con_obj_id; 461 } 462 463 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 464 continue; 465 466 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); 467 j++) { 468 uint8_t enc_obj_id, enc_obj_num, enc_obj_type; 469 470 enc_obj_id = 471 (le16_to_cpu(path->usGraphicObjIds[j]) & 472 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 473 enc_obj_num = 474 (le16_to_cpu(path->usGraphicObjIds[j]) & 475 ENUM_ID_MASK) >> ENUM_ID_SHIFT; 476 enc_obj_type = 477 (le16_to_cpu(path->usGraphicObjIds[j]) & 478 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 479 480 /* FIXME: add support for router objects */ 481 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { 482 if (enc_obj_num == 2) 483 linkb = true; 484 else 485 linkb = false; 486 487 radeon_add_atom_encoder(dev, 488 enc_obj_id, 489 le16_to_cpu 490 (path-> 491 usDeviceTag)); 492 493 } 494 } 495 496 /* look up gpio for ddc, hpd */ 497 if ((le16_to_cpu(path->usDeviceTag) & 498 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { 499 for (j = 0; j < con_obj->ucNumberOfObjects; j++) { 500 if (le16_to_cpu(path->usConnObjectId) == 501 le16_to_cpu(con_obj->asObjects[j]. 502 usObjectID)) { 503 ATOM_COMMON_RECORD_HEADER 504 *record = 505 (ATOM_COMMON_RECORD_HEADER 506 *) 507 (ctx->bios + data_offset + 508 le16_to_cpu(con_obj-> 509 asObjects[j]. 510 usRecordOffset)); 511 ATOM_I2C_RECORD *i2c_record; 512 ATOM_HPD_INT_RECORD *hpd_record; 513 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 514 hpd.hpd = RADEON_HPD_NONE; 515 516 while (record->ucRecordType > 0 517 && record-> 518 ucRecordType <= 519 ATOM_MAX_OBJECT_RECORD_NUMBER) { 520 switch (record->ucRecordType) { 521 case ATOM_I2C_RECORD_TYPE: 522 i2c_record = 523 (ATOM_I2C_RECORD *) 524 record; 525 i2c_config = 526 (ATOM_I2C_ID_CONFIG_ACCESS *) 527 &i2c_record->sucI2cId; 528 ddc_bus = radeon_lookup_i2c_gpio(rdev, 529 i2c_config-> 530 ucAccess); 531 break; 532 case ATOM_HPD_INT_RECORD_TYPE: 533 hpd_record = 534 (ATOM_HPD_INT_RECORD *) 535 record; 536 gpio = radeon_lookup_gpio(rdev, 537 hpd_record->ucHPDIntGPIOID); 538 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio); 539 hpd.plugged_state = hpd_record->ucPlugged_PinState; 540 break; 541 } 542 record = 543 (ATOM_COMMON_RECORD_HEADER 544 *) ((char *)record 545 + 546 record-> 547 ucRecordSize); 548 } 549 break; 550 } 551 } 552 } else { 553 hpd.hpd = RADEON_HPD_NONE; 554 ddc_bus.valid = false; 555 } 556 557 conn_id = le16_to_cpu(path->usConnObjectId); 558 559 if (!radeon_atom_apply_quirks 560 (dev, le16_to_cpu(path->usDeviceTag), &connector_type, 561 &ddc_bus, &conn_id, &hpd)) 562 continue; 563 564 radeon_add_atom_connector(dev, 565 conn_id, 566 le16_to_cpu(path-> 567 usDeviceTag), 568 connector_type, &ddc_bus, 569 linkb, igp_lane_info, 570 connector_object_id, 571 &hpd); 572 573 } 574 } 575 576 radeon_link_encoder_connector(dev); 577 578 return true; 579 } 580 581 static uint16_t atombios_get_connector_object_id(struct drm_device *dev, 582 int connector_type, 583 uint16_t devices) 584 { 585 struct radeon_device *rdev = dev->dev_private; 586 587 if (rdev->flags & RADEON_IS_IGP) { 588 return supported_devices_connector_object_id_convert 589 [connector_type]; 590 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) || 591 (connector_type == DRM_MODE_CONNECTOR_DVID)) && 592 (devices & ATOM_DEVICE_DFP2_SUPPORT)) { 593 struct radeon_mode_info *mode_info = &rdev->mode_info; 594 struct atom_context *ctx = mode_info->atom_context; 595 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info); 596 uint16_t size, data_offset; 597 uint8_t frev, crev; 598 ATOM_XTMDS_INFO *xtmds; 599 600 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset); 601 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset); 602 603 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) { 604 if (connector_type == DRM_MODE_CONNECTOR_DVII) 605 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 606 else 607 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 608 } else { 609 if (connector_type == DRM_MODE_CONNECTOR_DVII) 610 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 611 else 612 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 613 } 614 } else { 615 return supported_devices_connector_object_id_convert 616 [connector_type]; 617 } 618 } 619 620 struct bios_connector { 621 bool valid; 622 uint16_t line_mux; 623 uint16_t devices; 624 int connector_type; 625 struct radeon_i2c_bus_rec ddc_bus; 626 struct radeon_hpd hpd; 627 }; 628 629 bool radeon_get_atom_connector_info_from_supported_devices_table(struct 630 drm_device 631 *dev) 632 { 633 struct radeon_device *rdev = dev->dev_private; 634 struct radeon_mode_info *mode_info = &rdev->mode_info; 635 struct atom_context *ctx = mode_info->atom_context; 636 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo); 637 uint16_t size, data_offset; 638 uint8_t frev, crev; 639 uint16_t device_support; 640 uint8_t dac; 641 union atom_supported_devices *supported_devices; 642 int i, j, max_device; 643 struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE]; 644 645 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset); 646 647 supported_devices = 648 (union atom_supported_devices *)(ctx->bios + data_offset); 649 650 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport); 651 652 if (frev > 1) 653 max_device = ATOM_MAX_SUPPORTED_DEVICE; 654 else 655 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO; 656 657 for (i = 0; i < max_device; i++) { 658 ATOM_CONNECTOR_INFO_I2C ci = 659 supported_devices->info.asConnInfo[i]; 660 661 bios_connectors[i].valid = false; 662 663 if (!(device_support & (1 << i))) { 664 continue; 665 } 666 667 if (i == ATOM_DEVICE_CV_INDEX) { 668 DRM_DEBUG("Skipping Component Video\n"); 669 continue; 670 } 671 672 bios_connectors[i].connector_type = 673 supported_devices_connector_convert[ci.sucConnectorInfo. 674 sbfAccess. 675 bfConnectorType]; 676 677 if (bios_connectors[i].connector_type == 678 DRM_MODE_CONNECTOR_Unknown) 679 continue; 680 681 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; 682 683 bios_connectors[i].line_mux = 684 ci.sucI2cId.ucAccess; 685 686 /* give tv unique connector ids */ 687 if (i == ATOM_DEVICE_TV1_INDEX) { 688 bios_connectors[i].ddc_bus.valid = false; 689 bios_connectors[i].line_mux = 50; 690 } else if (i == ATOM_DEVICE_TV2_INDEX) { 691 bios_connectors[i].ddc_bus.valid = false; 692 bios_connectors[i].line_mux = 51; 693 } else if (i == ATOM_DEVICE_CV_INDEX) { 694 bios_connectors[i].ddc_bus.valid = false; 695 bios_connectors[i].line_mux = 52; 696 } else 697 bios_connectors[i].ddc_bus = 698 radeon_lookup_i2c_gpio(rdev, 699 bios_connectors[i].line_mux); 700 701 if ((crev > 1) && (frev > 1)) { 702 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap; 703 switch (isb) { 704 case 0x4: 705 bios_connectors[i].hpd.hpd = RADEON_HPD_1; 706 break; 707 case 0xa: 708 bios_connectors[i].hpd.hpd = RADEON_HPD_2; 709 break; 710 default: 711 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; 712 break; 713 } 714 } else { 715 if (i == ATOM_DEVICE_DFP1_INDEX) 716 bios_connectors[i].hpd.hpd = RADEON_HPD_1; 717 else if (i == ATOM_DEVICE_DFP2_INDEX) 718 bios_connectors[i].hpd.hpd = RADEON_HPD_2; 719 else 720 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; 721 } 722 723 /* Always set the connector type to VGA for CRT1/CRT2. if they are 724 * shared with a DVI port, we'll pick up the DVI connector when we 725 * merge the outputs. Some bioses incorrectly list VGA ports as DVI. 726 */ 727 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) 728 bios_connectors[i].connector_type = 729 DRM_MODE_CONNECTOR_VGA; 730 731 if (!radeon_atom_apply_quirks 732 (dev, (1 << i), &bios_connectors[i].connector_type, 733 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux, 734 &bios_connectors[i].hpd)) 735 continue; 736 737 bios_connectors[i].valid = true; 738 bios_connectors[i].devices = (1 << i); 739 740 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) 741 radeon_add_atom_encoder(dev, 742 radeon_get_encoder_id(dev, 743 (1 << i), 744 dac), 745 (1 << i)); 746 else 747 radeon_add_legacy_encoder(dev, 748 radeon_get_encoder_id(dev, 749 (1 << i), 750 dac), 751 (1 << i)); 752 } 753 754 /* combine shared connectors */ 755 for (i = 0; i < max_device; i++) { 756 if (bios_connectors[i].valid) { 757 for (j = 0; j < max_device; j++) { 758 if (bios_connectors[j].valid && (i != j)) { 759 if (bios_connectors[i].line_mux == 760 bios_connectors[j].line_mux) { 761 /* make sure not to combine LVDS */ 762 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 763 bios_connectors[i].line_mux = 53; 764 bios_connectors[i].ddc_bus.valid = false; 765 continue; 766 } 767 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 768 bios_connectors[j].line_mux = 53; 769 bios_connectors[j].ddc_bus.valid = false; 770 continue; 771 } 772 /* combine analog and digital for DVI-I */ 773 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 774 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) || 775 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 776 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) { 777 bios_connectors[i].devices |= 778 bios_connectors[j].devices; 779 bios_connectors[i].connector_type = 780 DRM_MODE_CONNECTOR_DVII; 781 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) 782 bios_connectors[i].hpd = 783 bios_connectors[j].hpd; 784 bios_connectors[j].valid = false; 785 } 786 } 787 } 788 } 789 } 790 } 791 792 /* add the connectors */ 793 for (i = 0; i < max_device; i++) { 794 if (bios_connectors[i].valid) { 795 uint16_t connector_object_id = 796 atombios_get_connector_object_id(dev, 797 bios_connectors[i].connector_type, 798 bios_connectors[i].devices); 799 radeon_add_atom_connector(dev, 800 bios_connectors[i].line_mux, 801 bios_connectors[i].devices, 802 bios_connectors[i]. 803 connector_type, 804 &bios_connectors[i].ddc_bus, 805 false, 0, 806 connector_object_id, 807 &bios_connectors[i].hpd); 808 } 809 } 810 811 radeon_link_encoder_connector(dev); 812 813 return true; 814 } 815 816 union firmware_info { 817 ATOM_FIRMWARE_INFO info; 818 ATOM_FIRMWARE_INFO_V1_2 info_12; 819 ATOM_FIRMWARE_INFO_V1_3 info_13; 820 ATOM_FIRMWARE_INFO_V1_4 info_14; 821 }; 822 823 bool radeon_atom_get_clock_info(struct drm_device *dev) 824 { 825 struct radeon_device *rdev = dev->dev_private; 826 struct radeon_mode_info *mode_info = &rdev->mode_info; 827 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 828 union firmware_info *firmware_info; 829 uint8_t frev, crev; 830 struct radeon_pll *p1pll = &rdev->clock.p1pll; 831 struct radeon_pll *p2pll = &rdev->clock.p2pll; 832 struct radeon_pll *spll = &rdev->clock.spll; 833 struct radeon_pll *mpll = &rdev->clock.mpll; 834 uint16_t data_offset; 835 836 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, 837 &crev, &data_offset); 838 839 firmware_info = 840 (union firmware_info *)(mode_info->atom_context->bios + 841 data_offset); 842 843 if (firmware_info) { 844 /* pixel clocks */ 845 p1pll->reference_freq = 846 le16_to_cpu(firmware_info->info.usReferenceClock); 847 p1pll->reference_div = 0; 848 849 if (crev < 2) 850 p1pll->pll_out_min = 851 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); 852 else 853 p1pll->pll_out_min = 854 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); 855 p1pll->pll_out_max = 856 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); 857 858 if (p1pll->pll_out_min == 0) { 859 if (ASIC_IS_AVIVO(rdev)) 860 p1pll->pll_out_min = 64800; 861 else 862 p1pll->pll_out_min = 20000; 863 } else if (p1pll->pll_out_min > 64800) { 864 /* Limiting the pll output range is a good thing generally as 865 * it limits the number of possible pll combinations for a given 866 * frequency presumably to the ones that work best on each card. 867 * However, certain duallink DVI monitors seem to like 868 * pll combinations that would be limited by this at least on 869 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per 870 * family. 871 */ 872 if (!radeon_new_pll) 873 p1pll->pll_out_min = 64800; 874 } 875 876 p1pll->pll_in_min = 877 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); 878 p1pll->pll_in_max = 879 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); 880 881 *p2pll = *p1pll; 882 883 /* system clock */ 884 spll->reference_freq = 885 le16_to_cpu(firmware_info->info.usReferenceClock); 886 spll->reference_div = 0; 887 888 spll->pll_out_min = 889 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); 890 spll->pll_out_max = 891 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); 892 893 /* ??? */ 894 if (spll->pll_out_min == 0) { 895 if (ASIC_IS_AVIVO(rdev)) 896 spll->pll_out_min = 64800; 897 else 898 spll->pll_out_min = 20000; 899 } 900 901 spll->pll_in_min = 902 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); 903 spll->pll_in_max = 904 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); 905 906 /* memory clock */ 907 mpll->reference_freq = 908 le16_to_cpu(firmware_info->info.usReferenceClock); 909 mpll->reference_div = 0; 910 911 mpll->pll_out_min = 912 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); 913 mpll->pll_out_max = 914 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); 915 916 /* ??? */ 917 if (mpll->pll_out_min == 0) { 918 if (ASIC_IS_AVIVO(rdev)) 919 mpll->pll_out_min = 64800; 920 else 921 mpll->pll_out_min = 20000; 922 } 923 924 mpll->pll_in_min = 925 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); 926 mpll->pll_in_max = 927 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); 928 929 rdev->clock.default_sclk = 930 le32_to_cpu(firmware_info->info.ulDefaultEngineClock); 931 rdev->clock.default_mclk = 932 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); 933 934 return true; 935 } 936 return false; 937 } 938 939 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 940 struct radeon_encoder_int_tmds *tmds) 941 { 942 struct drm_device *dev = encoder->base.dev; 943 struct radeon_device *rdev = dev->dev_private; 944 struct radeon_mode_info *mode_info = &rdev->mode_info; 945 int index = GetIndexIntoMasterTable(DATA, TMDS_Info); 946 uint16_t data_offset; 947 struct _ATOM_TMDS_INFO *tmds_info; 948 uint8_t frev, crev; 949 uint16_t maxfreq; 950 int i; 951 952 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, 953 &crev, &data_offset); 954 955 tmds_info = 956 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios + 957 data_offset); 958 959 if (tmds_info) { 960 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); 961 for (i = 0; i < 4; i++) { 962 tmds->tmds_pll[i].freq = 963 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency); 964 tmds->tmds_pll[i].value = 965 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f; 966 tmds->tmds_pll[i].value |= 967 (tmds_info->asMiscInfo[i]. 968 ucPLL_VCO_Gain & 0x3f) << 6; 969 tmds->tmds_pll[i].value |= 970 (tmds_info->asMiscInfo[i]. 971 ucPLL_DutyCycle & 0xf) << 12; 972 tmds->tmds_pll[i].value |= 973 (tmds_info->asMiscInfo[i]. 974 ucPLL_VoltageSwing & 0xf) << 16; 975 976 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n", 977 tmds->tmds_pll[i].freq, 978 tmds->tmds_pll[i].value); 979 980 if (maxfreq == tmds->tmds_pll[i].freq) { 981 tmds->tmds_pll[i].freq = 0xffffffff; 982 break; 983 } 984 } 985 return true; 986 } 987 return false; 988 } 989 990 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct 991 radeon_encoder 992 *encoder, 993 int id) 994 { 995 struct drm_device *dev = encoder->base.dev; 996 struct radeon_device *rdev = dev->dev_private; 997 struct radeon_mode_info *mode_info = &rdev->mode_info; 998 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info); 999 uint16_t data_offset; 1000 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info; 1001 uint8_t frev, crev; 1002 struct radeon_atom_ss *ss = NULL; 1003 int i; 1004 1005 if (id > ATOM_MAX_SS_ENTRY) 1006 return NULL; 1007 1008 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, 1009 &crev, &data_offset); 1010 1011 ss_info = 1012 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset); 1013 1014 if (ss_info) { 1015 ss = 1016 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL); 1017 1018 if (!ss) 1019 return NULL; 1020 1021 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) { 1022 if (ss_info->asSS_Info[i].ucSS_Id == id) { 1023 ss->percentage = 1024 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage); 1025 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType; 1026 ss->step = ss_info->asSS_Info[i].ucSS_Step; 1027 ss->delay = ss_info->asSS_Info[i].ucSS_Delay; 1028 ss->range = ss_info->asSS_Info[i].ucSS_Range; 1029 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div; 1030 break; 1031 } 1032 } 1033 } 1034 return ss; 1035 } 1036 1037 union lvds_info { 1038 struct _ATOM_LVDS_INFO info; 1039 struct _ATOM_LVDS_INFO_V12 info_12; 1040 }; 1041 1042 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct 1043 radeon_encoder 1044 *encoder) 1045 { 1046 struct drm_device *dev = encoder->base.dev; 1047 struct radeon_device *rdev = dev->dev_private; 1048 struct radeon_mode_info *mode_info = &rdev->mode_info; 1049 int index = GetIndexIntoMasterTable(DATA, LVDS_Info); 1050 uint16_t data_offset, misc; 1051 union lvds_info *lvds_info; 1052 uint8_t frev, crev; 1053 struct radeon_encoder_atom_dig *lvds = NULL; 1054 1055 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, 1056 &crev, &data_offset); 1057 1058 lvds_info = 1059 (union lvds_info *)(mode_info->atom_context->bios + data_offset); 1060 1061 if (lvds_info) { 1062 lvds = 1063 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 1064 1065 if (!lvds) 1066 return NULL; 1067 1068 lvds->native_mode.clock = 1069 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; 1070 lvds->native_mode.hdisplay = 1071 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); 1072 lvds->native_mode.vdisplay = 1073 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); 1074 lvds->native_mode.htotal = lvds->native_mode.hdisplay + 1075 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); 1076 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + 1077 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); 1078 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + 1079 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); 1080 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + 1081 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); 1082 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + 1083 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); 1084 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + 1085 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); 1086 lvds->panel_pwr_delay = 1087 le16_to_cpu(lvds_info->info.usOffDelayInMs); 1088 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc; 1089 1090 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess); 1091 if (misc & ATOM_VSYNC_POLARITY) 1092 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC; 1093 if (misc & ATOM_HSYNC_POLARITY) 1094 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC; 1095 if (misc & ATOM_COMPOSITESYNC) 1096 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC; 1097 if (misc & ATOM_INTERLACE) 1098 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE; 1099 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1100 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; 1101 1102 /* set crtc values */ 1103 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1104 1105 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id); 1106 1107 encoder->native_mode = lvds->native_mode; 1108 } 1109 return lvds; 1110 } 1111 1112 struct radeon_encoder_primary_dac * 1113 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) 1114 { 1115 struct drm_device *dev = encoder->base.dev; 1116 struct radeon_device *rdev = dev->dev_private; 1117 struct radeon_mode_info *mode_info = &rdev->mode_info; 1118 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 1119 uint16_t data_offset; 1120 struct _COMPASSIONATE_DATA *dac_info; 1121 uint8_t frev, crev; 1122 uint8_t bg, dac; 1123 struct radeon_encoder_primary_dac *p_dac = NULL; 1124 1125 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset); 1126 1127 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset); 1128 1129 if (dac_info) { 1130 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL); 1131 1132 if (!p_dac) 1133 return NULL; 1134 1135 bg = dac_info->ucDAC1_BG_Adjustment; 1136 dac = dac_info->ucDAC1_DAC_Adjustment; 1137 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 1138 1139 } 1140 return p_dac; 1141 } 1142 1143 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 1144 struct drm_display_mode *mode) 1145 { 1146 struct radeon_mode_info *mode_info = &rdev->mode_info; 1147 ATOM_ANALOG_TV_INFO *tv_info; 1148 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; 1149 ATOM_DTD_FORMAT *dtd_timings; 1150 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1151 u8 frev, crev; 1152 u16 data_offset, misc; 1153 1154 atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset); 1155 1156 switch (crev) { 1157 case 1: 1158 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); 1159 if (index > MAX_SUPPORTED_TV_TIMING) 1160 return false; 1161 1162 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); 1163 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); 1164 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); 1165 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) + 1166 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); 1167 1168 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); 1169 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); 1170 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); 1171 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) + 1172 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); 1173 1174 mode->flags = 0; 1175 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess); 1176 if (misc & ATOM_VSYNC_POLARITY) 1177 mode->flags |= DRM_MODE_FLAG_NVSYNC; 1178 if (misc & ATOM_HSYNC_POLARITY) 1179 mode->flags |= DRM_MODE_FLAG_NHSYNC; 1180 if (misc & ATOM_COMPOSITESYNC) 1181 mode->flags |= DRM_MODE_FLAG_CSYNC; 1182 if (misc & ATOM_INTERLACE) 1183 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1184 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1185 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1186 1187 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; 1188 1189 if (index == 1) { 1190 /* PAL timings appear to have wrong values for totals */ 1191 mode->crtc_htotal -= 1; 1192 mode->crtc_vtotal -= 1; 1193 } 1194 break; 1195 case 2: 1196 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset); 1197 if (index > MAX_SUPPORTED_TV_TIMING_V1_2) 1198 return false; 1199 1200 dtd_timings = &tv_info_v1_2->aModeTimings[index]; 1201 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) + 1202 le16_to_cpu(dtd_timings->usHBlanking_Time); 1203 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive); 1204 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) + 1205 le16_to_cpu(dtd_timings->usHSyncOffset); 1206 mode->crtc_hsync_end = mode->crtc_hsync_start + 1207 le16_to_cpu(dtd_timings->usHSyncWidth); 1208 1209 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) + 1210 le16_to_cpu(dtd_timings->usVBlanking_Time); 1211 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive); 1212 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) + 1213 le16_to_cpu(dtd_timings->usVSyncOffset); 1214 mode->crtc_vsync_end = mode->crtc_vsync_start + 1215 le16_to_cpu(dtd_timings->usVSyncWidth); 1216 1217 mode->flags = 0; 1218 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); 1219 if (misc & ATOM_VSYNC_POLARITY) 1220 mode->flags |= DRM_MODE_FLAG_NVSYNC; 1221 if (misc & ATOM_HSYNC_POLARITY) 1222 mode->flags |= DRM_MODE_FLAG_NHSYNC; 1223 if (misc & ATOM_COMPOSITESYNC) 1224 mode->flags |= DRM_MODE_FLAG_CSYNC; 1225 if (misc & ATOM_INTERLACE) 1226 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1227 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1228 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1229 1230 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10; 1231 break; 1232 } 1233 return true; 1234 } 1235 1236 enum radeon_tv_std 1237 radeon_atombios_get_tv_info(struct radeon_device *rdev) 1238 { 1239 struct radeon_mode_info *mode_info = &rdev->mode_info; 1240 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1241 uint16_t data_offset; 1242 uint8_t frev, crev; 1243 struct _ATOM_ANALOG_TV_INFO *tv_info; 1244 enum radeon_tv_std tv_std = TV_STD_NTSC; 1245 1246 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset); 1247 1248 tv_info = (struct _ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); 1249 1250 switch (tv_info->ucTV_BootUpDefaultStandard) { 1251 case ATOM_TV_NTSC: 1252 tv_std = TV_STD_NTSC; 1253 DRM_INFO("Default TV standard: NTSC\n"); 1254 break; 1255 case ATOM_TV_NTSCJ: 1256 tv_std = TV_STD_NTSC_J; 1257 DRM_INFO("Default TV standard: NTSC-J\n"); 1258 break; 1259 case ATOM_TV_PAL: 1260 tv_std = TV_STD_PAL; 1261 DRM_INFO("Default TV standard: PAL\n"); 1262 break; 1263 case ATOM_TV_PALM: 1264 tv_std = TV_STD_PAL_M; 1265 DRM_INFO("Default TV standard: PAL-M\n"); 1266 break; 1267 case ATOM_TV_PALN: 1268 tv_std = TV_STD_PAL_N; 1269 DRM_INFO("Default TV standard: PAL-N\n"); 1270 break; 1271 case ATOM_TV_PALCN: 1272 tv_std = TV_STD_PAL_CN; 1273 DRM_INFO("Default TV standard: PAL-CN\n"); 1274 break; 1275 case ATOM_TV_PAL60: 1276 tv_std = TV_STD_PAL_60; 1277 DRM_INFO("Default TV standard: PAL-60\n"); 1278 break; 1279 case ATOM_TV_SECAM: 1280 tv_std = TV_STD_SECAM; 1281 DRM_INFO("Default TV standard: SECAM\n"); 1282 break; 1283 default: 1284 tv_std = TV_STD_NTSC; 1285 DRM_INFO("Unknown TV standard; defaulting to NTSC\n"); 1286 break; 1287 } 1288 return tv_std; 1289 } 1290 1291 struct radeon_encoder_tv_dac * 1292 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) 1293 { 1294 struct drm_device *dev = encoder->base.dev; 1295 struct radeon_device *rdev = dev->dev_private; 1296 struct radeon_mode_info *mode_info = &rdev->mode_info; 1297 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 1298 uint16_t data_offset; 1299 struct _COMPASSIONATE_DATA *dac_info; 1300 uint8_t frev, crev; 1301 uint8_t bg, dac; 1302 struct radeon_encoder_tv_dac *tv_dac = NULL; 1303 1304 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset); 1305 1306 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset); 1307 1308 if (dac_info) { 1309 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 1310 1311 if (!tv_dac) 1312 return NULL; 1313 1314 bg = dac_info->ucDAC2_CRT2_BG_Adjustment; 1315 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment; 1316 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1317 1318 bg = dac_info->ucDAC2_PAL_BG_Adjustment; 1319 dac = dac_info->ucDAC2_PAL_DAC_Adjustment; 1320 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1321 1322 bg = dac_info->ucDAC2_NTSC_BG_Adjustment; 1323 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment; 1324 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1325 1326 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev); 1327 } 1328 return tv_dac; 1329 } 1330 1331 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) 1332 { 1333 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args; 1334 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating); 1335 1336 args.ucEnable = enable; 1337 1338 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1339 } 1340 1341 void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable) 1342 { 1343 ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args; 1344 int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt); 1345 1346 args.ucEnable = enable; 1347 1348 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1349 } 1350 1351 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev) 1352 { 1353 GET_ENGINE_CLOCK_PS_ALLOCATION args; 1354 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); 1355 1356 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1357 return args.ulReturnEngineClock; 1358 } 1359 1360 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev) 1361 { 1362 GET_MEMORY_CLOCK_PS_ALLOCATION args; 1363 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); 1364 1365 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1366 return args.ulReturnMemoryClock; 1367 } 1368 1369 void radeon_atom_set_engine_clock(struct radeon_device *rdev, 1370 uint32_t eng_clock) 1371 { 1372 SET_ENGINE_CLOCK_PS_ALLOCATION args; 1373 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); 1374 1375 args.ulTargetEngineClock = eng_clock; /* 10 khz */ 1376 1377 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1378 } 1379 1380 void radeon_atom_set_memory_clock(struct radeon_device *rdev, 1381 uint32_t mem_clock) 1382 { 1383 SET_MEMORY_CLOCK_PS_ALLOCATION args; 1384 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); 1385 1386 if (rdev->flags & RADEON_IS_IGP) 1387 return; 1388 1389 args.ulTargetMemoryClock = mem_clock; /* 10 khz */ 1390 1391 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1392 } 1393 1394 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) 1395 { 1396 struct radeon_device *rdev = dev->dev_private; 1397 uint32_t bios_2_scratch, bios_6_scratch; 1398 1399 if (rdev->family >= CHIP_R600) { 1400 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 1401 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 1402 } else { 1403 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 1404 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 1405 } 1406 1407 /* let the bios control the backlight */ 1408 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; 1409 1410 /* tell the bios not to handle mode switching */ 1411 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE); 1412 1413 if (rdev->family >= CHIP_R600) { 1414 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 1415 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 1416 } else { 1417 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 1418 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 1419 } 1420 1421 } 1422 1423 void radeon_save_bios_scratch_regs(struct radeon_device *rdev) 1424 { 1425 uint32_t scratch_reg; 1426 int i; 1427 1428 if (rdev->family >= CHIP_R600) 1429 scratch_reg = R600_BIOS_0_SCRATCH; 1430 else 1431 scratch_reg = RADEON_BIOS_0_SCRATCH; 1432 1433 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) 1434 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4)); 1435 } 1436 1437 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev) 1438 { 1439 uint32_t scratch_reg; 1440 int i; 1441 1442 if (rdev->family >= CHIP_R600) 1443 scratch_reg = R600_BIOS_0_SCRATCH; 1444 else 1445 scratch_reg = RADEON_BIOS_0_SCRATCH; 1446 1447 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) 1448 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]); 1449 } 1450 1451 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) 1452 { 1453 struct drm_device *dev = encoder->dev; 1454 struct radeon_device *rdev = dev->dev_private; 1455 uint32_t bios_6_scratch; 1456 1457 if (rdev->family >= CHIP_R600) 1458 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 1459 else 1460 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 1461 1462 if (lock) 1463 bios_6_scratch |= ATOM_S6_CRITICAL_STATE; 1464 else 1465 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; 1466 1467 if (rdev->family >= CHIP_R600) 1468 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 1469 else 1470 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 1471 } 1472 1473 /* at some point we may want to break this out into individual functions */ 1474 void 1475 radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 1476 struct drm_encoder *encoder, 1477 bool connected) 1478 { 1479 struct drm_device *dev = connector->dev; 1480 struct radeon_device *rdev = dev->dev_private; 1481 struct radeon_connector *radeon_connector = 1482 to_radeon_connector(connector); 1483 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1484 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch; 1485 1486 if (rdev->family >= CHIP_R600) { 1487 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 1488 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 1489 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 1490 } else { 1491 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 1492 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 1493 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 1494 } 1495 1496 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 1497 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 1498 if (connected) { 1499 DRM_DEBUG("TV1 connected\n"); 1500 bios_3_scratch |= ATOM_S3_TV1_ACTIVE; 1501 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1; 1502 } else { 1503 DRM_DEBUG("TV1 disconnected\n"); 1504 bios_0_scratch &= ~ATOM_S0_TV1_MASK; 1505 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; 1506 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1; 1507 } 1508 } 1509 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) && 1510 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) { 1511 if (connected) { 1512 DRM_DEBUG("CV connected\n"); 1513 bios_3_scratch |= ATOM_S3_CV_ACTIVE; 1514 bios_6_scratch |= ATOM_S6_ACC_REQ_CV; 1515 } else { 1516 DRM_DEBUG("CV disconnected\n"); 1517 bios_0_scratch &= ~ATOM_S0_CV_MASK; 1518 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; 1519 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV; 1520 } 1521 } 1522 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 1523 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 1524 if (connected) { 1525 DRM_DEBUG("LCD1 connected\n"); 1526 bios_0_scratch |= ATOM_S0_LCD1; 1527 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; 1528 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; 1529 } else { 1530 DRM_DEBUG("LCD1 disconnected\n"); 1531 bios_0_scratch &= ~ATOM_S0_LCD1; 1532 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; 1533 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; 1534 } 1535 } 1536 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 1537 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 1538 if (connected) { 1539 DRM_DEBUG("CRT1 connected\n"); 1540 bios_0_scratch |= ATOM_S0_CRT1_COLOR; 1541 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; 1542 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; 1543 } else { 1544 DRM_DEBUG("CRT1 disconnected\n"); 1545 bios_0_scratch &= ~ATOM_S0_CRT1_MASK; 1546 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; 1547 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; 1548 } 1549 } 1550 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 1551 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 1552 if (connected) { 1553 DRM_DEBUG("CRT2 connected\n"); 1554 bios_0_scratch |= ATOM_S0_CRT2_COLOR; 1555 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; 1556 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; 1557 } else { 1558 DRM_DEBUG("CRT2 disconnected\n"); 1559 bios_0_scratch &= ~ATOM_S0_CRT2_MASK; 1560 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; 1561 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; 1562 } 1563 } 1564 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 1565 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 1566 if (connected) { 1567 DRM_DEBUG("DFP1 connected\n"); 1568 bios_0_scratch |= ATOM_S0_DFP1; 1569 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; 1570 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; 1571 } else { 1572 DRM_DEBUG("DFP1 disconnected\n"); 1573 bios_0_scratch &= ~ATOM_S0_DFP1; 1574 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; 1575 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; 1576 } 1577 } 1578 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 1579 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 1580 if (connected) { 1581 DRM_DEBUG("DFP2 connected\n"); 1582 bios_0_scratch |= ATOM_S0_DFP2; 1583 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; 1584 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; 1585 } else { 1586 DRM_DEBUG("DFP2 disconnected\n"); 1587 bios_0_scratch &= ~ATOM_S0_DFP2; 1588 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; 1589 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; 1590 } 1591 } 1592 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && 1593 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { 1594 if (connected) { 1595 DRM_DEBUG("DFP3 connected\n"); 1596 bios_0_scratch |= ATOM_S0_DFP3; 1597 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; 1598 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; 1599 } else { 1600 DRM_DEBUG("DFP3 disconnected\n"); 1601 bios_0_scratch &= ~ATOM_S0_DFP3; 1602 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; 1603 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; 1604 } 1605 } 1606 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && 1607 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { 1608 if (connected) { 1609 DRM_DEBUG("DFP4 connected\n"); 1610 bios_0_scratch |= ATOM_S0_DFP4; 1611 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; 1612 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; 1613 } else { 1614 DRM_DEBUG("DFP4 disconnected\n"); 1615 bios_0_scratch &= ~ATOM_S0_DFP4; 1616 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; 1617 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; 1618 } 1619 } 1620 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && 1621 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { 1622 if (connected) { 1623 DRM_DEBUG("DFP5 connected\n"); 1624 bios_0_scratch |= ATOM_S0_DFP5; 1625 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; 1626 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; 1627 } else { 1628 DRM_DEBUG("DFP5 disconnected\n"); 1629 bios_0_scratch &= ~ATOM_S0_DFP5; 1630 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; 1631 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; 1632 } 1633 } 1634 1635 if (rdev->family >= CHIP_R600) { 1636 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); 1637 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 1638 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 1639 } else { 1640 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 1641 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 1642 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 1643 } 1644 } 1645 1646 void 1647 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 1648 { 1649 struct drm_device *dev = encoder->dev; 1650 struct radeon_device *rdev = dev->dev_private; 1651 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1652 uint32_t bios_3_scratch; 1653 1654 if (rdev->family >= CHIP_R600) 1655 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 1656 else 1657 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 1658 1659 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 1660 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE; 1661 bios_3_scratch |= (crtc << 18); 1662 } 1663 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 1664 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE; 1665 bios_3_scratch |= (crtc << 24); 1666 } 1667 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 1668 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE; 1669 bios_3_scratch |= (crtc << 16); 1670 } 1671 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 1672 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE; 1673 bios_3_scratch |= (crtc << 20); 1674 } 1675 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 1676 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE; 1677 bios_3_scratch |= (crtc << 17); 1678 } 1679 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 1680 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE; 1681 bios_3_scratch |= (crtc << 19); 1682 } 1683 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 1684 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE; 1685 bios_3_scratch |= (crtc << 23); 1686 } 1687 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 1688 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE; 1689 bios_3_scratch |= (crtc << 25); 1690 } 1691 1692 if (rdev->family >= CHIP_R600) 1693 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 1694 else 1695 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 1696 } 1697 1698 void 1699 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 1700 { 1701 struct drm_device *dev = encoder->dev; 1702 struct radeon_device *rdev = dev->dev_private; 1703 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1704 uint32_t bios_2_scratch; 1705 1706 if (rdev->family >= CHIP_R600) 1707 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 1708 else 1709 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 1710 1711 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 1712 if (on) 1713 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE; 1714 else 1715 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE; 1716 } 1717 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 1718 if (on) 1719 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE; 1720 else 1721 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE; 1722 } 1723 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 1724 if (on) 1725 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE; 1726 else 1727 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE; 1728 } 1729 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 1730 if (on) 1731 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE; 1732 else 1733 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE; 1734 } 1735 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 1736 if (on) 1737 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE; 1738 else 1739 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE; 1740 } 1741 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 1742 if (on) 1743 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE; 1744 else 1745 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE; 1746 } 1747 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 1748 if (on) 1749 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE; 1750 else 1751 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE; 1752 } 1753 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 1754 if (on) 1755 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE; 1756 else 1757 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE; 1758 } 1759 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) { 1760 if (on) 1761 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE; 1762 else 1763 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE; 1764 } 1765 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) { 1766 if (on) 1767 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE; 1768 else 1769 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE; 1770 } 1771 1772 if (rdev->family >= CHIP_R600) 1773 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 1774 else 1775 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 1776 } 1777