1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/radeon_drm.h> 28 #include "radeon.h" 29 30 #include "atom.h" 31 #include "atom-bits.h" 32 33 extern void 34 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, 35 uint32_t supported_device, u16 caps); 36 37 /* from radeon_legacy_encoder.c */ 38 extern void 39 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, 40 uint32_t supported_device); 41 42 union atom_supported_devices { 43 struct _ATOM_SUPPORTED_DEVICES_INFO info; 44 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2; 45 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1; 46 }; 47 48 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev, 49 ATOM_GPIO_I2C_ASSIGMENT *gpio, 50 u8 index) 51 { 52 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */ 53 if ((rdev->family == CHIP_R420) || 54 (rdev->family == CHIP_R423) || 55 (rdev->family == CHIP_RV410)) { 56 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) || 57 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) || 58 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) { 59 gpio->ucClkMaskShift = 0x19; 60 gpio->ucDataMaskShift = 0x18; 61 } 62 } 63 64 /* some evergreen boards have bad data for this entry */ 65 if (ASIC_IS_DCE4(rdev)) { 66 if ((index == 7) && 67 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) && 68 (gpio->sucI2cId.ucAccess == 0)) { 69 gpio->sucI2cId.ucAccess = 0x97; 70 gpio->ucDataMaskShift = 8; 71 gpio->ucDataEnShift = 8; 72 gpio->ucDataY_Shift = 8; 73 gpio->ucDataA_Shift = 8; 74 } 75 } 76 77 /* some DCE3 boards have bad data for this entry */ 78 if (ASIC_IS_DCE3(rdev)) { 79 if ((index == 4) && 80 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) && 81 (gpio->sucI2cId.ucAccess == 0x94)) 82 gpio->sucI2cId.ucAccess = 0x14; 83 } 84 } 85 86 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio) 87 { 88 struct radeon_i2c_bus_rec i2c; 89 90 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 91 92 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; 93 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; 94 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4; 95 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4; 96 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4; 97 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4; 98 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4; 99 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4; 100 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); 101 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); 102 i2c.en_clk_mask = (1 << gpio->ucClkEnShift); 103 i2c.en_data_mask = (1 << gpio->ucDataEnShift); 104 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); 105 i2c.y_data_mask = (1 << gpio->ucDataY_Shift); 106 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); 107 i2c.a_data_mask = (1 << gpio->ucDataA_Shift); 108 109 if (gpio->sucI2cId.sbfAccess.bfHW_Capable) 110 i2c.hw_capable = true; 111 else 112 i2c.hw_capable = false; 113 114 if (gpio->sucI2cId.ucAccess == 0xa0) 115 i2c.mm_i2c = true; 116 else 117 i2c.mm_i2c = false; 118 119 i2c.i2c_id = gpio->sucI2cId.ucAccess; 120 121 if (i2c.mask_clk_reg) 122 i2c.valid = true; 123 else 124 i2c.valid = false; 125 126 return i2c; 127 } 128 129 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev, 130 uint8_t id) 131 { 132 struct atom_context *ctx = rdev->mode_info.atom_context; 133 ATOM_GPIO_I2C_ASSIGMENT *gpio; 134 struct radeon_i2c_bus_rec i2c; 135 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 136 struct _ATOM_GPIO_I2C_INFO *i2c_info; 137 uint16_t data_offset, size; 138 int i, num_indices; 139 140 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 141 i2c.valid = false; 142 143 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 144 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 145 146 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 147 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 148 149 gpio = &i2c_info->asGPIO_Info[0]; 150 for (i = 0; i < num_indices; i++) { 151 152 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); 153 154 if (gpio->sucI2cId.ucAccess == id) { 155 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); 156 break; 157 } 158 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 159 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 160 } 161 } 162 163 return i2c; 164 } 165 166 void radeon_atombios_i2c_init(struct radeon_device *rdev) 167 { 168 struct atom_context *ctx = rdev->mode_info.atom_context; 169 ATOM_GPIO_I2C_ASSIGMENT *gpio; 170 struct radeon_i2c_bus_rec i2c; 171 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 172 struct _ATOM_GPIO_I2C_INFO *i2c_info; 173 uint16_t data_offset, size; 174 int i, num_indices; 175 char stmp[32]; 176 177 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 178 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 179 180 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 181 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 182 183 gpio = &i2c_info->asGPIO_Info[0]; 184 for (i = 0; i < num_indices; i++) { 185 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); 186 187 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); 188 189 if (i2c.valid) { 190 sprintf(stmp, "0x%x", i2c.i2c_id); 191 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp); 192 } 193 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 194 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 195 } 196 } 197 } 198 199 static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev, 200 u8 id) 201 { 202 struct atom_context *ctx = rdev->mode_info.atom_context; 203 struct radeon_gpio_rec gpio; 204 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); 205 struct _ATOM_GPIO_PIN_LUT *gpio_info; 206 ATOM_GPIO_PIN_ASSIGNMENT *pin; 207 u16 data_offset, size; 208 int i, num_indices; 209 210 memset(&gpio, 0, sizeof(struct radeon_gpio_rec)); 211 gpio.valid = false; 212 213 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 214 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset); 215 216 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 217 sizeof(ATOM_GPIO_PIN_ASSIGNMENT); 218 219 pin = gpio_info->asGPIO_Pin; 220 for (i = 0; i < num_indices; i++) { 221 if (id == pin->ucGPIO_ID) { 222 gpio.id = pin->ucGPIO_ID; 223 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4; 224 gpio.mask = (1 << pin->ucGpioPinBitShift); 225 gpio.valid = true; 226 break; 227 } 228 pin = (ATOM_GPIO_PIN_ASSIGNMENT *) 229 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT)); 230 } 231 } 232 233 return gpio; 234 } 235 236 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev, 237 struct radeon_gpio_rec *gpio) 238 { 239 struct radeon_hpd hpd; 240 u32 reg; 241 242 memset(&hpd, 0, sizeof(struct radeon_hpd)); 243 244 if (ASIC_IS_DCE6(rdev)) 245 reg = SI_DC_GPIO_HPD_A; 246 else if (ASIC_IS_DCE4(rdev)) 247 reg = EVERGREEN_DC_GPIO_HPD_A; 248 else 249 reg = AVIVO_DC_GPIO_HPD_A; 250 251 hpd.gpio = *gpio; 252 if (gpio->reg == reg) { 253 switch(gpio->mask) { 254 case (1 << 0): 255 hpd.hpd = RADEON_HPD_1; 256 break; 257 case (1 << 8): 258 hpd.hpd = RADEON_HPD_2; 259 break; 260 case (1 << 16): 261 hpd.hpd = RADEON_HPD_3; 262 break; 263 case (1 << 24): 264 hpd.hpd = RADEON_HPD_4; 265 break; 266 case (1 << 26): 267 hpd.hpd = RADEON_HPD_5; 268 break; 269 case (1 << 28): 270 hpd.hpd = RADEON_HPD_6; 271 break; 272 default: 273 hpd.hpd = RADEON_HPD_NONE; 274 break; 275 } 276 } else 277 hpd.hpd = RADEON_HPD_NONE; 278 return hpd; 279 } 280 281 static bool radeon_atom_apply_quirks(struct drm_device *dev, 282 uint32_t supported_device, 283 int *connector_type, 284 struct radeon_i2c_bus_rec *i2c_bus, 285 uint16_t *line_mux, 286 struct radeon_hpd *hpd) 287 { 288 289 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ 290 if ((dev->pdev->device == 0x791e) && 291 (dev->pdev->subsystem_vendor == 0x1043) && 292 (dev->pdev->subsystem_device == 0x826d)) { 293 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && 294 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 295 *connector_type = DRM_MODE_CONNECTOR_DVID; 296 } 297 298 /* Asrock RS600 board lists the DVI port as HDMI */ 299 if ((dev->pdev->device == 0x7941) && 300 (dev->pdev->subsystem_vendor == 0x1849) && 301 (dev->pdev->subsystem_device == 0x7941)) { 302 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && 303 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 304 *connector_type = DRM_MODE_CONNECTOR_DVID; 305 } 306 307 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */ 308 if ((dev->pdev->device == 0x796e) && 309 (dev->pdev->subsystem_vendor == 0x1462) && 310 (dev->pdev->subsystem_device == 0x7302)) { 311 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) || 312 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 313 return false; 314 } 315 316 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */ 317 if ((dev->pdev->device == 0x7941) && 318 (dev->pdev->subsystem_vendor == 0x147b) && 319 (dev->pdev->subsystem_device == 0x2412)) { 320 if (*connector_type == DRM_MODE_CONNECTOR_DVII) 321 return false; 322 } 323 324 /* Falcon NW laptop lists vga ddc line for LVDS */ 325 if ((dev->pdev->device == 0x5653) && 326 (dev->pdev->subsystem_vendor == 0x1462) && 327 (dev->pdev->subsystem_device == 0x0291)) { 328 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) { 329 i2c_bus->valid = false; 330 *line_mux = 53; 331 } 332 } 333 334 /* HIS X1300 is DVI+VGA, not DVI+DVI */ 335 if ((dev->pdev->device == 0x7146) && 336 (dev->pdev->subsystem_vendor == 0x17af) && 337 (dev->pdev->subsystem_device == 0x2058)) { 338 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) 339 return false; 340 } 341 342 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */ 343 if ((dev->pdev->device == 0x7142) && 344 (dev->pdev->subsystem_vendor == 0x1458) && 345 (dev->pdev->subsystem_device == 0x2134)) { 346 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) 347 return false; 348 } 349 350 351 /* Funky macbooks */ 352 if ((dev->pdev->device == 0x71C5) && 353 (dev->pdev->subsystem_vendor == 0x106b) && 354 (dev->pdev->subsystem_device == 0x0080)) { 355 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) || 356 (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) 357 return false; 358 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT) 359 *line_mux = 0x90; 360 } 361 362 /* mac rv630, rv730, others */ 363 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) && 364 (*connector_type == DRM_MODE_CONNECTOR_DVII)) { 365 *connector_type = DRM_MODE_CONNECTOR_9PinDIN; 366 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1; 367 } 368 369 /* ASUS HD 3600 XT board lists the DVI port as HDMI */ 370 if ((dev->pdev->device == 0x9598) && 371 (dev->pdev->subsystem_vendor == 0x1043) && 372 (dev->pdev->subsystem_device == 0x01da)) { 373 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 374 *connector_type = DRM_MODE_CONNECTOR_DVII; 375 } 376 } 377 378 /* ASUS HD 3600 board lists the DVI port as HDMI */ 379 if ((dev->pdev->device == 0x9598) && 380 (dev->pdev->subsystem_vendor == 0x1043) && 381 (dev->pdev->subsystem_device == 0x01e4)) { 382 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 383 *connector_type = DRM_MODE_CONNECTOR_DVII; 384 } 385 } 386 387 /* ASUS HD 3450 board lists the DVI port as HDMI */ 388 if ((dev->pdev->device == 0x95C5) && 389 (dev->pdev->subsystem_vendor == 0x1043) && 390 (dev->pdev->subsystem_device == 0x01e2)) { 391 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 392 *connector_type = DRM_MODE_CONNECTOR_DVII; 393 } 394 } 395 396 /* some BIOSes seem to report DAC on HDMI - usually this is a board with 397 * HDMI + VGA reporting as HDMI 398 */ 399 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 400 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { 401 *connector_type = DRM_MODE_CONNECTOR_VGA; 402 *line_mux = 0; 403 } 404 } 405 406 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port 407 * on the laptop and a DVI port on the docking station and 408 * both share the same encoder, hpd pin, and ddc line. 409 * So while the bios table is technically correct, 410 * we drop the DVI port here since xrandr has no concept of 411 * encoders and will try and drive both connectors 412 * with different crtcs which isn't possible on the hardware 413 * side and leaves no crtcs for LVDS or VGA. 414 */ 415 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) && 416 (dev->pdev->subsystem_vendor == 0x1025) && 417 (dev->pdev->subsystem_device == 0x013c)) { 418 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) && 419 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) { 420 /* actually it's a DVI-D port not DVI-I */ 421 *connector_type = DRM_MODE_CONNECTOR_DVID; 422 return false; 423 } 424 } 425 426 /* XFX Pine Group device rv730 reports no VGA DDC lines 427 * even though they are wired up to record 0x93 428 */ 429 if ((dev->pdev->device == 0x9498) && 430 (dev->pdev->subsystem_vendor == 0x1682) && 431 (dev->pdev->subsystem_device == 0x2452) && 432 (i2c_bus->valid == false) && 433 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) { 434 struct radeon_device *rdev = dev->dev_private; 435 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93); 436 } 437 438 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */ 439 if (((dev->pdev->device == 0x9802) || (dev->pdev->device == 0x9806)) && 440 (dev->pdev->subsystem_vendor == 0x1734) && 441 (dev->pdev->subsystem_device == 0x11bd)) { 442 if (*connector_type == DRM_MODE_CONNECTOR_VGA) { 443 *connector_type = DRM_MODE_CONNECTOR_DVII; 444 *line_mux = 0x3103; 445 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) { 446 *connector_type = DRM_MODE_CONNECTOR_DVII; 447 } 448 } 449 450 451 return true; 452 } 453 454 const int supported_devices_connector_convert[] = { 455 DRM_MODE_CONNECTOR_Unknown, 456 DRM_MODE_CONNECTOR_VGA, 457 DRM_MODE_CONNECTOR_DVII, 458 DRM_MODE_CONNECTOR_DVID, 459 DRM_MODE_CONNECTOR_DVIA, 460 DRM_MODE_CONNECTOR_SVIDEO, 461 DRM_MODE_CONNECTOR_Composite, 462 DRM_MODE_CONNECTOR_LVDS, 463 DRM_MODE_CONNECTOR_Unknown, 464 DRM_MODE_CONNECTOR_Unknown, 465 DRM_MODE_CONNECTOR_HDMIA, 466 DRM_MODE_CONNECTOR_HDMIB, 467 DRM_MODE_CONNECTOR_Unknown, 468 DRM_MODE_CONNECTOR_Unknown, 469 DRM_MODE_CONNECTOR_9PinDIN, 470 DRM_MODE_CONNECTOR_DisplayPort 471 }; 472 473 const uint16_t supported_devices_connector_object_id_convert[] = { 474 CONNECTOR_OBJECT_ID_NONE, 475 CONNECTOR_OBJECT_ID_VGA, 476 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */ 477 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */ 478 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */ 479 CONNECTOR_OBJECT_ID_COMPOSITE, 480 CONNECTOR_OBJECT_ID_SVIDEO, 481 CONNECTOR_OBJECT_ID_LVDS, 482 CONNECTOR_OBJECT_ID_9PIN_DIN, 483 CONNECTOR_OBJECT_ID_9PIN_DIN, 484 CONNECTOR_OBJECT_ID_DISPLAYPORT, 485 CONNECTOR_OBJECT_ID_HDMI_TYPE_A, 486 CONNECTOR_OBJECT_ID_HDMI_TYPE_B, 487 CONNECTOR_OBJECT_ID_SVIDEO 488 }; 489 490 const int object_connector_convert[] = { 491 DRM_MODE_CONNECTOR_Unknown, 492 DRM_MODE_CONNECTOR_DVII, 493 DRM_MODE_CONNECTOR_DVII, 494 DRM_MODE_CONNECTOR_DVID, 495 DRM_MODE_CONNECTOR_DVID, 496 DRM_MODE_CONNECTOR_VGA, 497 DRM_MODE_CONNECTOR_Composite, 498 DRM_MODE_CONNECTOR_SVIDEO, 499 DRM_MODE_CONNECTOR_Unknown, 500 DRM_MODE_CONNECTOR_Unknown, 501 DRM_MODE_CONNECTOR_9PinDIN, 502 DRM_MODE_CONNECTOR_Unknown, 503 DRM_MODE_CONNECTOR_HDMIA, 504 DRM_MODE_CONNECTOR_HDMIB, 505 DRM_MODE_CONNECTOR_LVDS, 506 DRM_MODE_CONNECTOR_9PinDIN, 507 DRM_MODE_CONNECTOR_Unknown, 508 DRM_MODE_CONNECTOR_Unknown, 509 DRM_MODE_CONNECTOR_Unknown, 510 DRM_MODE_CONNECTOR_DisplayPort, 511 DRM_MODE_CONNECTOR_eDP, 512 DRM_MODE_CONNECTOR_Unknown 513 }; 514 515 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) 516 { 517 struct radeon_device *rdev = dev->dev_private; 518 struct radeon_mode_info *mode_info = &rdev->mode_info; 519 struct atom_context *ctx = mode_info->atom_context; 520 int index = GetIndexIntoMasterTable(DATA, Object_Header); 521 u16 size, data_offset; 522 u8 frev, crev; 523 ATOM_CONNECTOR_OBJECT_TABLE *con_obj; 524 ATOM_ENCODER_OBJECT_TABLE *enc_obj; 525 ATOM_OBJECT_TABLE *router_obj; 526 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; 527 ATOM_OBJECT_HEADER *obj_header; 528 int i, j, k, path_size, device_support; 529 int connector_type; 530 u16 igp_lane_info, conn_id, connector_object_id; 531 struct radeon_i2c_bus_rec ddc_bus; 532 struct radeon_router router; 533 struct radeon_gpio_rec gpio; 534 struct radeon_hpd hpd; 535 536 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) 537 return false; 538 539 if (crev < 2) 540 return false; 541 542 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); 543 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) 544 (ctx->bios + data_offset + 545 le16_to_cpu(obj_header->usDisplayPathTableOffset)); 546 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) 547 (ctx->bios + data_offset + 548 le16_to_cpu(obj_header->usConnectorObjectTableOffset)); 549 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *) 550 (ctx->bios + data_offset + 551 le16_to_cpu(obj_header->usEncoderObjectTableOffset)); 552 router_obj = (ATOM_OBJECT_TABLE *) 553 (ctx->bios + data_offset + 554 le16_to_cpu(obj_header->usRouterObjectTableOffset)); 555 device_support = le16_to_cpu(obj_header->usDeviceSupport); 556 557 path_size = 0; 558 for (i = 0; i < path_obj->ucNumOfDispPath; i++) { 559 uint8_t *addr = (uint8_t *) path_obj->asDispPath; 560 ATOM_DISPLAY_OBJECT_PATH *path; 561 addr += path_size; 562 path = (ATOM_DISPLAY_OBJECT_PATH *) addr; 563 path_size += le16_to_cpu(path->usSize); 564 565 if (device_support & le16_to_cpu(path->usDeviceTag)) { 566 uint8_t con_obj_id, con_obj_num, con_obj_type; 567 568 con_obj_id = 569 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) 570 >> OBJECT_ID_SHIFT; 571 con_obj_num = 572 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) 573 >> ENUM_ID_SHIFT; 574 con_obj_type = 575 (le16_to_cpu(path->usConnObjectId) & 576 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 577 578 /* TODO CV support */ 579 if (le16_to_cpu(path->usDeviceTag) == 580 ATOM_DEVICE_CV_SUPPORT) 581 continue; 582 583 /* IGP chips */ 584 if ((rdev->flags & RADEON_IS_IGP) && 585 (con_obj_id == 586 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { 587 uint16_t igp_offset = 0; 588 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj; 589 590 index = 591 GetIndexIntoMasterTable(DATA, 592 IntegratedSystemInfo); 593 594 if (atom_parse_data_header(ctx, index, &size, &frev, 595 &crev, &igp_offset)) { 596 597 if (crev >= 2) { 598 igp_obj = 599 (ATOM_INTEGRATED_SYSTEM_INFO_V2 600 *) (ctx->bios + igp_offset); 601 602 if (igp_obj) { 603 uint32_t slot_config, ct; 604 605 if (con_obj_num == 1) 606 slot_config = 607 igp_obj-> 608 ulDDISlot1Config; 609 else 610 slot_config = 611 igp_obj-> 612 ulDDISlot2Config; 613 614 ct = (slot_config >> 16) & 0xff; 615 connector_type = 616 object_connector_convert 617 [ct]; 618 connector_object_id = ct; 619 igp_lane_info = 620 slot_config & 0xffff; 621 } else 622 continue; 623 } else 624 continue; 625 } else { 626 igp_lane_info = 0; 627 connector_type = 628 object_connector_convert[con_obj_id]; 629 connector_object_id = con_obj_id; 630 } 631 } else { 632 igp_lane_info = 0; 633 connector_type = 634 object_connector_convert[con_obj_id]; 635 connector_object_id = con_obj_id; 636 } 637 638 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 639 continue; 640 641 router.ddc_valid = false; 642 router.cd_valid = false; 643 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) { 644 uint8_t grph_obj_id, grph_obj_num, grph_obj_type; 645 646 grph_obj_id = 647 (le16_to_cpu(path->usGraphicObjIds[j]) & 648 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 649 grph_obj_num = 650 (le16_to_cpu(path->usGraphicObjIds[j]) & 651 ENUM_ID_MASK) >> ENUM_ID_SHIFT; 652 grph_obj_type = 653 (le16_to_cpu(path->usGraphicObjIds[j]) & 654 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 655 656 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { 657 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) { 658 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID); 659 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) { 660 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 661 (ctx->bios + data_offset + 662 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); 663 ATOM_ENCODER_CAP_RECORD *cap_record; 664 u16 caps = 0; 665 666 while (record->ucRecordSize > 0 && 667 record->ucRecordType > 0 && 668 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 669 switch (record->ucRecordType) { 670 case ATOM_ENCODER_CAP_RECORD_TYPE: 671 cap_record =(ATOM_ENCODER_CAP_RECORD *) 672 record; 673 caps = le16_to_cpu(cap_record->usEncoderCap); 674 break; 675 } 676 record = (ATOM_COMMON_RECORD_HEADER *) 677 ((char *)record + record->ucRecordSize); 678 } 679 radeon_add_atom_encoder(dev, 680 encoder_obj, 681 le16_to_cpu 682 (path-> 683 usDeviceTag), 684 caps); 685 } 686 } 687 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) { 688 for (k = 0; k < router_obj->ucNumberOfObjects; k++) { 689 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); 690 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) { 691 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 692 (ctx->bios + data_offset + 693 le16_to_cpu(router_obj->asObjects[k].usRecordOffset)); 694 ATOM_I2C_RECORD *i2c_record; 695 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 696 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path; 697 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path; 698 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table = 699 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) 700 (ctx->bios + data_offset + 701 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); 702 u8 *num_dst_objs = (u8 *) 703 ((u8 *)router_src_dst_table + 1 + 704 (router_src_dst_table->ucNumberOfSrc * 2)); 705 u16 *dst_objs = (u16 *)(num_dst_objs + 1); 706 int enum_id; 707 708 router.router_id = router_obj_id; 709 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) { 710 if (le16_to_cpu(path->usConnObjectId) == 711 le16_to_cpu(dst_objs[enum_id])) 712 break; 713 } 714 715 while (record->ucRecordSize > 0 && 716 record->ucRecordType > 0 && 717 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 718 switch (record->ucRecordType) { 719 case ATOM_I2C_RECORD_TYPE: 720 i2c_record = 721 (ATOM_I2C_RECORD *) 722 record; 723 i2c_config = 724 (ATOM_I2C_ID_CONFIG_ACCESS *) 725 &i2c_record->sucI2cId; 726 router.i2c_info = 727 radeon_lookup_i2c_gpio(rdev, 728 i2c_config-> 729 ucAccess); 730 router.i2c_addr = i2c_record->ucI2CAddr >> 1; 731 break; 732 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE: 733 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *) 734 record; 735 router.ddc_valid = true; 736 router.ddc_mux_type = ddc_path->ucMuxType; 737 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin; 738 router.ddc_mux_state = ddc_path->ucMuxState[enum_id]; 739 break; 740 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE: 741 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *) 742 record; 743 router.cd_valid = true; 744 router.cd_mux_type = cd_path->ucMuxType; 745 router.cd_mux_control_pin = cd_path->ucMuxControlPin; 746 router.cd_mux_state = cd_path->ucMuxState[enum_id]; 747 break; 748 } 749 record = (ATOM_COMMON_RECORD_HEADER *) 750 ((char *)record + record->ucRecordSize); 751 } 752 } 753 } 754 } 755 } 756 757 /* look up gpio for ddc, hpd */ 758 ddc_bus.valid = false; 759 hpd.hpd = RADEON_HPD_NONE; 760 if ((le16_to_cpu(path->usDeviceTag) & 761 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { 762 for (j = 0; j < con_obj->ucNumberOfObjects; j++) { 763 if (le16_to_cpu(path->usConnObjectId) == 764 le16_to_cpu(con_obj->asObjects[j]. 765 usObjectID)) { 766 ATOM_COMMON_RECORD_HEADER 767 *record = 768 (ATOM_COMMON_RECORD_HEADER 769 *) 770 (ctx->bios + data_offset + 771 le16_to_cpu(con_obj-> 772 asObjects[j]. 773 usRecordOffset)); 774 ATOM_I2C_RECORD *i2c_record; 775 ATOM_HPD_INT_RECORD *hpd_record; 776 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 777 778 while (record->ucRecordSize > 0 && 779 record->ucRecordType > 0 && 780 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 781 switch (record->ucRecordType) { 782 case ATOM_I2C_RECORD_TYPE: 783 i2c_record = 784 (ATOM_I2C_RECORD *) 785 record; 786 i2c_config = 787 (ATOM_I2C_ID_CONFIG_ACCESS *) 788 &i2c_record->sucI2cId; 789 ddc_bus = radeon_lookup_i2c_gpio(rdev, 790 i2c_config-> 791 ucAccess); 792 break; 793 case ATOM_HPD_INT_RECORD_TYPE: 794 hpd_record = 795 (ATOM_HPD_INT_RECORD *) 796 record; 797 gpio = radeon_lookup_gpio(rdev, 798 hpd_record->ucHPDIntGPIOID); 799 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio); 800 hpd.plugged_state = hpd_record->ucPlugged_PinState; 801 break; 802 } 803 record = 804 (ATOM_COMMON_RECORD_HEADER 805 *) ((char *)record 806 + 807 record-> 808 ucRecordSize); 809 } 810 break; 811 } 812 } 813 } 814 815 /* needed for aux chan transactions */ 816 ddc_bus.hpd = hpd.hpd; 817 818 conn_id = le16_to_cpu(path->usConnObjectId); 819 820 if (!radeon_atom_apply_quirks 821 (dev, le16_to_cpu(path->usDeviceTag), &connector_type, 822 &ddc_bus, &conn_id, &hpd)) 823 continue; 824 825 radeon_add_atom_connector(dev, 826 conn_id, 827 le16_to_cpu(path-> 828 usDeviceTag), 829 connector_type, &ddc_bus, 830 igp_lane_info, 831 connector_object_id, 832 &hpd, 833 &router); 834 835 } 836 } 837 838 radeon_link_encoder_connector(dev); 839 840 return true; 841 } 842 843 static uint16_t atombios_get_connector_object_id(struct drm_device *dev, 844 int connector_type, 845 uint16_t devices) 846 { 847 struct radeon_device *rdev = dev->dev_private; 848 849 if (rdev->flags & RADEON_IS_IGP) { 850 return supported_devices_connector_object_id_convert 851 [connector_type]; 852 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) || 853 (connector_type == DRM_MODE_CONNECTOR_DVID)) && 854 (devices & ATOM_DEVICE_DFP2_SUPPORT)) { 855 struct radeon_mode_info *mode_info = &rdev->mode_info; 856 struct atom_context *ctx = mode_info->atom_context; 857 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info); 858 uint16_t size, data_offset; 859 uint8_t frev, crev; 860 ATOM_XTMDS_INFO *xtmds; 861 862 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) { 863 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset); 864 865 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) { 866 if (connector_type == DRM_MODE_CONNECTOR_DVII) 867 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 868 else 869 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 870 } else { 871 if (connector_type == DRM_MODE_CONNECTOR_DVII) 872 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 873 else 874 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 875 } 876 } else 877 return supported_devices_connector_object_id_convert 878 [connector_type]; 879 } else { 880 return supported_devices_connector_object_id_convert 881 [connector_type]; 882 } 883 } 884 885 struct bios_connector { 886 bool valid; 887 uint16_t line_mux; 888 uint16_t devices; 889 int connector_type; 890 struct radeon_i2c_bus_rec ddc_bus; 891 struct radeon_hpd hpd; 892 }; 893 894 bool radeon_get_atom_connector_info_from_supported_devices_table(struct 895 drm_device 896 *dev) 897 { 898 struct radeon_device *rdev = dev->dev_private; 899 struct radeon_mode_info *mode_info = &rdev->mode_info; 900 struct atom_context *ctx = mode_info->atom_context; 901 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo); 902 uint16_t size, data_offset; 903 uint8_t frev, crev; 904 uint16_t device_support; 905 uint8_t dac; 906 union atom_supported_devices *supported_devices; 907 int i, j, max_device; 908 struct bios_connector *bios_connectors; 909 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE; 910 struct radeon_router router; 911 912 router.ddc_valid = false; 913 router.cd_valid = false; 914 915 bios_connectors = kzalloc(bc_size, GFP_KERNEL); 916 if (!bios_connectors) 917 return false; 918 919 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, 920 &data_offset)) { 921 kfree(bios_connectors); 922 return false; 923 } 924 925 supported_devices = 926 (union atom_supported_devices *)(ctx->bios + data_offset); 927 928 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport); 929 930 if (frev > 1) 931 max_device = ATOM_MAX_SUPPORTED_DEVICE; 932 else 933 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO; 934 935 for (i = 0; i < max_device; i++) { 936 ATOM_CONNECTOR_INFO_I2C ci = 937 supported_devices->info.asConnInfo[i]; 938 939 bios_connectors[i].valid = false; 940 941 if (!(device_support & (1 << i))) { 942 continue; 943 } 944 945 if (i == ATOM_DEVICE_CV_INDEX) { 946 DRM_DEBUG_KMS("Skipping Component Video\n"); 947 continue; 948 } 949 950 bios_connectors[i].connector_type = 951 supported_devices_connector_convert[ci.sucConnectorInfo. 952 sbfAccess. 953 bfConnectorType]; 954 955 if (bios_connectors[i].connector_type == 956 DRM_MODE_CONNECTOR_Unknown) 957 continue; 958 959 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; 960 961 bios_connectors[i].line_mux = 962 ci.sucI2cId.ucAccess; 963 964 /* give tv unique connector ids */ 965 if (i == ATOM_DEVICE_TV1_INDEX) { 966 bios_connectors[i].ddc_bus.valid = false; 967 bios_connectors[i].line_mux = 50; 968 } else if (i == ATOM_DEVICE_TV2_INDEX) { 969 bios_connectors[i].ddc_bus.valid = false; 970 bios_connectors[i].line_mux = 51; 971 } else if (i == ATOM_DEVICE_CV_INDEX) { 972 bios_connectors[i].ddc_bus.valid = false; 973 bios_connectors[i].line_mux = 52; 974 } else 975 bios_connectors[i].ddc_bus = 976 radeon_lookup_i2c_gpio(rdev, 977 bios_connectors[i].line_mux); 978 979 if ((crev > 1) && (frev > 1)) { 980 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap; 981 switch (isb) { 982 case 0x4: 983 bios_connectors[i].hpd.hpd = RADEON_HPD_1; 984 break; 985 case 0xa: 986 bios_connectors[i].hpd.hpd = RADEON_HPD_2; 987 break; 988 default: 989 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; 990 break; 991 } 992 } else { 993 if (i == ATOM_DEVICE_DFP1_INDEX) 994 bios_connectors[i].hpd.hpd = RADEON_HPD_1; 995 else if (i == ATOM_DEVICE_DFP2_INDEX) 996 bios_connectors[i].hpd.hpd = RADEON_HPD_2; 997 else 998 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; 999 } 1000 1001 /* Always set the connector type to VGA for CRT1/CRT2. if they are 1002 * shared with a DVI port, we'll pick up the DVI connector when we 1003 * merge the outputs. Some bioses incorrectly list VGA ports as DVI. 1004 */ 1005 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) 1006 bios_connectors[i].connector_type = 1007 DRM_MODE_CONNECTOR_VGA; 1008 1009 if (!radeon_atom_apply_quirks 1010 (dev, (1 << i), &bios_connectors[i].connector_type, 1011 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux, 1012 &bios_connectors[i].hpd)) 1013 continue; 1014 1015 bios_connectors[i].valid = true; 1016 bios_connectors[i].devices = (1 << i); 1017 1018 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) 1019 radeon_add_atom_encoder(dev, 1020 radeon_get_encoder_enum(dev, 1021 (1 << i), 1022 dac), 1023 (1 << i), 1024 0); 1025 else 1026 radeon_add_legacy_encoder(dev, 1027 radeon_get_encoder_enum(dev, 1028 (1 << i), 1029 dac), 1030 (1 << i)); 1031 } 1032 1033 /* combine shared connectors */ 1034 for (i = 0; i < max_device; i++) { 1035 if (bios_connectors[i].valid) { 1036 for (j = 0; j < max_device; j++) { 1037 if (bios_connectors[j].valid && (i != j)) { 1038 if (bios_connectors[i].line_mux == 1039 bios_connectors[j].line_mux) { 1040 /* make sure not to combine LVDS */ 1041 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1042 bios_connectors[i].line_mux = 53; 1043 bios_connectors[i].ddc_bus.valid = false; 1044 continue; 1045 } 1046 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1047 bios_connectors[j].line_mux = 53; 1048 bios_connectors[j].ddc_bus.valid = false; 1049 continue; 1050 } 1051 /* combine analog and digital for DVI-I */ 1052 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 1053 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) || 1054 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 1055 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) { 1056 bios_connectors[i].devices |= 1057 bios_connectors[j].devices; 1058 bios_connectors[i].connector_type = 1059 DRM_MODE_CONNECTOR_DVII; 1060 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) 1061 bios_connectors[i].hpd = 1062 bios_connectors[j].hpd; 1063 bios_connectors[j].valid = false; 1064 } 1065 } 1066 } 1067 } 1068 } 1069 } 1070 1071 /* add the connectors */ 1072 for (i = 0; i < max_device; i++) { 1073 if (bios_connectors[i].valid) { 1074 uint16_t connector_object_id = 1075 atombios_get_connector_object_id(dev, 1076 bios_connectors[i].connector_type, 1077 bios_connectors[i].devices); 1078 radeon_add_atom_connector(dev, 1079 bios_connectors[i].line_mux, 1080 bios_connectors[i].devices, 1081 bios_connectors[i]. 1082 connector_type, 1083 &bios_connectors[i].ddc_bus, 1084 0, 1085 connector_object_id, 1086 &bios_connectors[i].hpd, 1087 &router); 1088 } 1089 } 1090 1091 radeon_link_encoder_connector(dev); 1092 1093 kfree(bios_connectors); 1094 return true; 1095 } 1096 1097 union firmware_info { 1098 ATOM_FIRMWARE_INFO info; 1099 ATOM_FIRMWARE_INFO_V1_2 info_12; 1100 ATOM_FIRMWARE_INFO_V1_3 info_13; 1101 ATOM_FIRMWARE_INFO_V1_4 info_14; 1102 ATOM_FIRMWARE_INFO_V2_1 info_21; 1103 ATOM_FIRMWARE_INFO_V2_2 info_22; 1104 }; 1105 1106 bool radeon_atom_get_clock_info(struct drm_device *dev) 1107 { 1108 struct radeon_device *rdev = dev->dev_private; 1109 struct radeon_mode_info *mode_info = &rdev->mode_info; 1110 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 1111 union firmware_info *firmware_info; 1112 uint8_t frev, crev; 1113 struct radeon_pll *p1pll = &rdev->clock.p1pll; 1114 struct radeon_pll *p2pll = &rdev->clock.p2pll; 1115 struct radeon_pll *dcpll = &rdev->clock.dcpll; 1116 struct radeon_pll *spll = &rdev->clock.spll; 1117 struct radeon_pll *mpll = &rdev->clock.mpll; 1118 uint16_t data_offset; 1119 1120 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1121 &frev, &crev, &data_offset)) { 1122 firmware_info = 1123 (union firmware_info *)(mode_info->atom_context->bios + 1124 data_offset); 1125 /* pixel clocks */ 1126 p1pll->reference_freq = 1127 le16_to_cpu(firmware_info->info.usReferenceClock); 1128 p1pll->reference_div = 0; 1129 1130 if (crev < 2) 1131 p1pll->pll_out_min = 1132 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); 1133 else 1134 p1pll->pll_out_min = 1135 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); 1136 p1pll->pll_out_max = 1137 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); 1138 1139 if (crev >= 4) { 1140 p1pll->lcd_pll_out_min = 1141 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100; 1142 if (p1pll->lcd_pll_out_min == 0) 1143 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 1144 p1pll->lcd_pll_out_max = 1145 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100; 1146 if (p1pll->lcd_pll_out_max == 0) 1147 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 1148 } else { 1149 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 1150 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 1151 } 1152 1153 if (p1pll->pll_out_min == 0) { 1154 if (ASIC_IS_AVIVO(rdev)) 1155 p1pll->pll_out_min = 64800; 1156 else 1157 p1pll->pll_out_min = 20000; 1158 } 1159 1160 p1pll->pll_in_min = 1161 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); 1162 p1pll->pll_in_max = 1163 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); 1164 1165 *p2pll = *p1pll; 1166 1167 /* system clock */ 1168 if (ASIC_IS_DCE4(rdev)) 1169 spll->reference_freq = 1170 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock); 1171 else 1172 spll->reference_freq = 1173 le16_to_cpu(firmware_info->info.usReferenceClock); 1174 spll->reference_div = 0; 1175 1176 spll->pll_out_min = 1177 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); 1178 spll->pll_out_max = 1179 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); 1180 1181 /* ??? */ 1182 if (spll->pll_out_min == 0) { 1183 if (ASIC_IS_AVIVO(rdev)) 1184 spll->pll_out_min = 64800; 1185 else 1186 spll->pll_out_min = 20000; 1187 } 1188 1189 spll->pll_in_min = 1190 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); 1191 spll->pll_in_max = 1192 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); 1193 1194 /* memory clock */ 1195 if (ASIC_IS_DCE4(rdev)) 1196 mpll->reference_freq = 1197 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock); 1198 else 1199 mpll->reference_freq = 1200 le16_to_cpu(firmware_info->info.usReferenceClock); 1201 mpll->reference_div = 0; 1202 1203 mpll->pll_out_min = 1204 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); 1205 mpll->pll_out_max = 1206 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); 1207 1208 /* ??? */ 1209 if (mpll->pll_out_min == 0) { 1210 if (ASIC_IS_AVIVO(rdev)) 1211 mpll->pll_out_min = 64800; 1212 else 1213 mpll->pll_out_min = 20000; 1214 } 1215 1216 mpll->pll_in_min = 1217 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); 1218 mpll->pll_in_max = 1219 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); 1220 1221 rdev->clock.default_sclk = 1222 le32_to_cpu(firmware_info->info.ulDefaultEngineClock); 1223 rdev->clock.default_mclk = 1224 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); 1225 1226 if (ASIC_IS_DCE4(rdev)) { 1227 rdev->clock.default_dispclk = 1228 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); 1229 if (rdev->clock.default_dispclk == 0) { 1230 if (ASIC_IS_DCE6(rdev)) 1231 rdev->clock.default_dispclk = 60000; /* 600 Mhz */ 1232 else if (ASIC_IS_DCE5(rdev)) 1233 rdev->clock.default_dispclk = 54000; /* 540 Mhz */ 1234 else 1235 rdev->clock.default_dispclk = 60000; /* 600 Mhz */ 1236 } 1237 /* set a reasonable default for DP */ 1238 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) { 1239 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n", 1240 rdev->clock.default_dispclk / 100); 1241 rdev->clock.default_dispclk = 60000; 1242 } 1243 rdev->clock.dp_extclk = 1244 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); 1245 rdev->clock.current_dispclk = rdev->clock.default_dispclk; 1246 } 1247 *dcpll = *p1pll; 1248 1249 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock); 1250 if (rdev->clock.max_pixel_clock == 0) 1251 rdev->clock.max_pixel_clock = 40000; 1252 1253 /* not technically a clock, but... */ 1254 rdev->mode_info.firmware_flags = 1255 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess); 1256 1257 return true; 1258 } 1259 1260 return false; 1261 } 1262 1263 union igp_info { 1264 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 1265 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 1266 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; 1267 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; 1268 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; 1269 }; 1270 1271 bool radeon_atombios_sideport_present(struct radeon_device *rdev) 1272 { 1273 struct radeon_mode_info *mode_info = &rdev->mode_info; 1274 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1275 union igp_info *igp_info; 1276 u8 frev, crev; 1277 u16 data_offset; 1278 1279 /* sideport is AMD only */ 1280 if (rdev->family == CHIP_RS600) 1281 return false; 1282 1283 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1284 &frev, &crev, &data_offset)) { 1285 igp_info = (union igp_info *)(mode_info->atom_context->bios + 1286 data_offset); 1287 switch (crev) { 1288 case 1: 1289 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock)) 1290 return true; 1291 break; 1292 case 2: 1293 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock)) 1294 return true; 1295 break; 1296 default: 1297 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 1298 break; 1299 } 1300 } 1301 return false; 1302 } 1303 1304 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 1305 struct radeon_encoder_int_tmds *tmds) 1306 { 1307 struct drm_device *dev = encoder->base.dev; 1308 struct radeon_device *rdev = dev->dev_private; 1309 struct radeon_mode_info *mode_info = &rdev->mode_info; 1310 int index = GetIndexIntoMasterTable(DATA, TMDS_Info); 1311 uint16_t data_offset; 1312 struct _ATOM_TMDS_INFO *tmds_info; 1313 uint8_t frev, crev; 1314 uint16_t maxfreq; 1315 int i; 1316 1317 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1318 &frev, &crev, &data_offset)) { 1319 tmds_info = 1320 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios + 1321 data_offset); 1322 1323 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); 1324 for (i = 0; i < 4; i++) { 1325 tmds->tmds_pll[i].freq = 1326 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency); 1327 tmds->tmds_pll[i].value = 1328 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f; 1329 tmds->tmds_pll[i].value |= 1330 (tmds_info->asMiscInfo[i]. 1331 ucPLL_VCO_Gain & 0x3f) << 6; 1332 tmds->tmds_pll[i].value |= 1333 (tmds_info->asMiscInfo[i]. 1334 ucPLL_DutyCycle & 0xf) << 12; 1335 tmds->tmds_pll[i].value |= 1336 (tmds_info->asMiscInfo[i]. 1337 ucPLL_VoltageSwing & 0xf) << 16; 1338 1339 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n", 1340 tmds->tmds_pll[i].freq, 1341 tmds->tmds_pll[i].value); 1342 1343 if (maxfreq == tmds->tmds_pll[i].freq) { 1344 tmds->tmds_pll[i].freq = 0xffffffff; 1345 break; 1346 } 1347 } 1348 return true; 1349 } 1350 return false; 1351 } 1352 1353 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 1354 struct radeon_atom_ss *ss, 1355 int id) 1356 { 1357 struct radeon_mode_info *mode_info = &rdev->mode_info; 1358 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info); 1359 uint16_t data_offset, size; 1360 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info; 1361 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign; 1362 uint8_t frev, crev; 1363 int i, num_indices; 1364 1365 memset(ss, 0, sizeof(struct radeon_atom_ss)); 1366 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1367 &frev, &crev, &data_offset)) { 1368 ss_info = 1369 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset); 1370 1371 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1372 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT); 1373 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*) 1374 ((u8 *)&ss_info->asSS_Info[0]); 1375 for (i = 0; i < num_indices; i++) { 1376 if (ss_assign->ucSS_Id == id) { 1377 ss->percentage = 1378 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage); 1379 ss->type = ss_assign->ucSpreadSpectrumType; 1380 ss->step = ss_assign->ucSS_Step; 1381 ss->delay = ss_assign->ucSS_Delay; 1382 ss->range = ss_assign->ucSS_Range; 1383 ss->refdiv = ss_assign->ucRecommendedRef_Div; 1384 return true; 1385 } 1386 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*) 1387 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT)); 1388 } 1389 } 1390 return false; 1391 } 1392 1393 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev, 1394 struct radeon_atom_ss *ss, 1395 int id) 1396 { 1397 struct radeon_mode_info *mode_info = &rdev->mode_info; 1398 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1399 u16 data_offset, size; 1400 union igp_info *igp_info; 1401 u8 frev, crev; 1402 u16 percentage = 0, rate = 0; 1403 1404 /* get any igp specific overrides */ 1405 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1406 &frev, &crev, &data_offset)) { 1407 igp_info = (union igp_info *) 1408 (mode_info->atom_context->bios + data_offset); 1409 switch (crev) { 1410 case 6: 1411 switch (id) { 1412 case ASIC_INTERNAL_SS_ON_TMDS: 1413 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage); 1414 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz); 1415 break; 1416 case ASIC_INTERNAL_SS_ON_HDMI: 1417 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage); 1418 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz); 1419 break; 1420 case ASIC_INTERNAL_SS_ON_LVDS: 1421 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage); 1422 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz); 1423 break; 1424 } 1425 break; 1426 case 7: 1427 switch (id) { 1428 case ASIC_INTERNAL_SS_ON_TMDS: 1429 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage); 1430 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz); 1431 break; 1432 case ASIC_INTERNAL_SS_ON_HDMI: 1433 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage); 1434 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz); 1435 break; 1436 case ASIC_INTERNAL_SS_ON_LVDS: 1437 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage); 1438 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz); 1439 break; 1440 } 1441 break; 1442 case 8: 1443 switch (id) { 1444 case ASIC_INTERNAL_SS_ON_TMDS: 1445 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage); 1446 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz); 1447 break; 1448 case ASIC_INTERNAL_SS_ON_HDMI: 1449 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage); 1450 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz); 1451 break; 1452 case ASIC_INTERNAL_SS_ON_LVDS: 1453 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage); 1454 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz); 1455 break; 1456 } 1457 break; 1458 default: 1459 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 1460 break; 1461 } 1462 if (percentage) 1463 ss->percentage = percentage; 1464 if (rate) 1465 ss->rate = rate; 1466 } 1467 } 1468 1469 union asic_ss_info { 1470 struct _ATOM_ASIC_INTERNAL_SS_INFO info; 1471 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2; 1472 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3; 1473 }; 1474 1475 union asic_ss_assignment { 1476 struct _ATOM_ASIC_SS_ASSIGNMENT v1; 1477 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2; 1478 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3; 1479 }; 1480 1481 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 1482 struct radeon_atom_ss *ss, 1483 int id, u32 clock) 1484 { 1485 struct radeon_mode_info *mode_info = &rdev->mode_info; 1486 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 1487 uint16_t data_offset, size; 1488 union asic_ss_info *ss_info; 1489 union asic_ss_assignment *ss_assign; 1490 uint8_t frev, crev; 1491 int i, num_indices; 1492 1493 if (id == ASIC_INTERNAL_MEMORY_SS) { 1494 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT)) 1495 return false; 1496 } 1497 if (id == ASIC_INTERNAL_ENGINE_SS) { 1498 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT)) 1499 return false; 1500 } 1501 1502 memset(ss, 0, sizeof(struct radeon_atom_ss)); 1503 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1504 &frev, &crev, &data_offset)) { 1505 1506 ss_info = 1507 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset); 1508 1509 switch (frev) { 1510 case 1: 1511 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1512 sizeof(ATOM_ASIC_SS_ASSIGNMENT); 1513 1514 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]); 1515 for (i = 0; i < num_indices; i++) { 1516 if ((ss_assign->v1.ucClockIndication == id) && 1517 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) { 1518 ss->percentage = 1519 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage); 1520 ss->type = ss_assign->v1.ucSpreadSpectrumMode; 1521 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz); 1522 ss->percentage_divider = 100; 1523 return true; 1524 } 1525 ss_assign = (union asic_ss_assignment *) 1526 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT)); 1527 } 1528 break; 1529 case 2: 1530 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1531 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); 1532 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]); 1533 for (i = 0; i < num_indices; i++) { 1534 if ((ss_assign->v2.ucClockIndication == id) && 1535 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) { 1536 ss->percentage = 1537 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage); 1538 ss->type = ss_assign->v2.ucSpreadSpectrumMode; 1539 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz); 1540 ss->percentage_divider = 100; 1541 if ((crev == 2) && 1542 ((id == ASIC_INTERNAL_ENGINE_SS) || 1543 (id == ASIC_INTERNAL_MEMORY_SS))) 1544 ss->rate /= 100; 1545 return true; 1546 } 1547 ss_assign = (union asic_ss_assignment *) 1548 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2)); 1549 } 1550 break; 1551 case 3: 1552 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1553 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); 1554 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]); 1555 for (i = 0; i < num_indices; i++) { 1556 if ((ss_assign->v3.ucClockIndication == id) && 1557 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) { 1558 ss->percentage = 1559 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage); 1560 ss->type = ss_assign->v3.ucSpreadSpectrumMode; 1561 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz); 1562 if (ss_assign->v3.ucSpreadSpectrumMode & 1563 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK) 1564 ss->percentage_divider = 1000; 1565 else 1566 ss->percentage_divider = 100; 1567 if ((id == ASIC_INTERNAL_ENGINE_SS) || 1568 (id == ASIC_INTERNAL_MEMORY_SS)) 1569 ss->rate /= 100; 1570 if (rdev->flags & RADEON_IS_IGP) 1571 radeon_atombios_get_igp_ss_overrides(rdev, ss, id); 1572 return true; 1573 } 1574 ss_assign = (union asic_ss_assignment *) 1575 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3)); 1576 } 1577 break; 1578 default: 1579 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev); 1580 break; 1581 } 1582 1583 } 1584 return false; 1585 } 1586 1587 union lvds_info { 1588 struct _ATOM_LVDS_INFO info; 1589 struct _ATOM_LVDS_INFO_V12 info_12; 1590 }; 1591 1592 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct 1593 radeon_encoder 1594 *encoder) 1595 { 1596 struct drm_device *dev = encoder->base.dev; 1597 struct radeon_device *rdev = dev->dev_private; 1598 struct radeon_mode_info *mode_info = &rdev->mode_info; 1599 int index = GetIndexIntoMasterTable(DATA, LVDS_Info); 1600 uint16_t data_offset, misc; 1601 union lvds_info *lvds_info; 1602 uint8_t frev, crev; 1603 struct radeon_encoder_atom_dig *lvds = NULL; 1604 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1605 1606 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1607 &frev, &crev, &data_offset)) { 1608 lvds_info = 1609 (union lvds_info *)(mode_info->atom_context->bios + data_offset); 1610 lvds = 1611 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 1612 1613 if (!lvds) 1614 return NULL; 1615 1616 lvds->native_mode.clock = 1617 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; 1618 lvds->native_mode.hdisplay = 1619 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); 1620 lvds->native_mode.vdisplay = 1621 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); 1622 lvds->native_mode.htotal = lvds->native_mode.hdisplay + 1623 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); 1624 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + 1625 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); 1626 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + 1627 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); 1628 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + 1629 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); 1630 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + 1631 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset); 1632 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + 1633 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); 1634 lvds->panel_pwr_delay = 1635 le16_to_cpu(lvds_info->info.usOffDelayInMs); 1636 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc; 1637 1638 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess); 1639 if (misc & ATOM_VSYNC_POLARITY) 1640 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC; 1641 if (misc & ATOM_HSYNC_POLARITY) 1642 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC; 1643 if (misc & ATOM_COMPOSITESYNC) 1644 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC; 1645 if (misc & ATOM_INTERLACE) 1646 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE; 1647 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1648 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; 1649 1650 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize); 1651 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize); 1652 1653 /* set crtc values */ 1654 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1655 1656 lvds->lcd_ss_id = lvds_info->info.ucSS_Id; 1657 1658 encoder->native_mode = lvds->native_mode; 1659 1660 if (encoder_enum == 2) 1661 lvds->linkb = true; 1662 else 1663 lvds->linkb = false; 1664 1665 /* parse the lcd record table */ 1666 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) { 1667 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record; 1668 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record; 1669 bool bad_record = false; 1670 u8 *record; 1671 1672 if ((frev == 1) && (crev < 2)) 1673 /* absolute */ 1674 record = (u8 *)(mode_info->atom_context->bios + 1675 le16_to_cpu(lvds_info->info.usModePatchTableOffset)); 1676 else 1677 /* relative */ 1678 record = (u8 *)(mode_info->atom_context->bios + 1679 data_offset + 1680 le16_to_cpu(lvds_info->info.usModePatchTableOffset)); 1681 while (*record != ATOM_RECORD_END_TYPE) { 1682 switch (*record) { 1683 case LCD_MODE_PATCH_RECORD_MODE_TYPE: 1684 record += sizeof(ATOM_PATCH_RECORD_MODE); 1685 break; 1686 case LCD_RTS_RECORD_TYPE: 1687 record += sizeof(ATOM_LCD_RTS_RECORD); 1688 break; 1689 case LCD_CAP_RECORD_TYPE: 1690 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP); 1691 break; 1692 case LCD_FAKE_EDID_PATCH_RECORD_TYPE: 1693 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record; 1694 if (fake_edid_record->ucFakeEDIDLength) { 1695 struct edid *edid; 1696 int edid_size = 1697 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength); 1698 edid = kmalloc(edid_size, GFP_KERNEL); 1699 if (edid) { 1700 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0], 1701 fake_edid_record->ucFakeEDIDLength); 1702 1703 if (drm_edid_is_valid(edid)) { 1704 rdev->mode_info.bios_hardcoded_edid = edid; 1705 rdev->mode_info.bios_hardcoded_edid_size = edid_size; 1706 } else 1707 kfree(edid); 1708 } 1709 } 1710 record += fake_edid_record->ucFakeEDIDLength ? 1711 fake_edid_record->ucFakeEDIDLength + 2 : 1712 sizeof(ATOM_FAKE_EDID_PATCH_RECORD); 1713 break; 1714 case LCD_PANEL_RESOLUTION_RECORD_TYPE: 1715 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record; 1716 lvds->native_mode.width_mm = panel_res_record->usHSize; 1717 lvds->native_mode.height_mm = panel_res_record->usVSize; 1718 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD); 1719 break; 1720 default: 1721 DRM_ERROR("Bad LCD record %d\n", *record); 1722 bad_record = true; 1723 break; 1724 } 1725 if (bad_record) 1726 break; 1727 } 1728 } 1729 } 1730 return lvds; 1731 } 1732 1733 struct radeon_encoder_primary_dac * 1734 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) 1735 { 1736 struct drm_device *dev = encoder->base.dev; 1737 struct radeon_device *rdev = dev->dev_private; 1738 struct radeon_mode_info *mode_info = &rdev->mode_info; 1739 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 1740 uint16_t data_offset; 1741 struct _COMPASSIONATE_DATA *dac_info; 1742 uint8_t frev, crev; 1743 uint8_t bg, dac; 1744 struct radeon_encoder_primary_dac *p_dac = NULL; 1745 1746 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1747 &frev, &crev, &data_offset)) { 1748 dac_info = (struct _COMPASSIONATE_DATA *) 1749 (mode_info->atom_context->bios + data_offset); 1750 1751 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL); 1752 1753 if (!p_dac) 1754 return NULL; 1755 1756 bg = dac_info->ucDAC1_BG_Adjustment; 1757 dac = dac_info->ucDAC1_DAC_Adjustment; 1758 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 1759 1760 } 1761 return p_dac; 1762 } 1763 1764 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 1765 struct drm_display_mode *mode) 1766 { 1767 struct radeon_mode_info *mode_info = &rdev->mode_info; 1768 ATOM_ANALOG_TV_INFO *tv_info; 1769 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; 1770 ATOM_DTD_FORMAT *dtd_timings; 1771 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1772 u8 frev, crev; 1773 u16 data_offset, misc; 1774 1775 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL, 1776 &frev, &crev, &data_offset)) 1777 return false; 1778 1779 switch (crev) { 1780 case 1: 1781 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); 1782 if (index >= MAX_SUPPORTED_TV_TIMING) 1783 return false; 1784 1785 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); 1786 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); 1787 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); 1788 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) + 1789 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); 1790 1791 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); 1792 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); 1793 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); 1794 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) + 1795 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); 1796 1797 mode->flags = 0; 1798 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess); 1799 if (misc & ATOM_VSYNC_POLARITY) 1800 mode->flags |= DRM_MODE_FLAG_NVSYNC; 1801 if (misc & ATOM_HSYNC_POLARITY) 1802 mode->flags |= DRM_MODE_FLAG_NHSYNC; 1803 if (misc & ATOM_COMPOSITESYNC) 1804 mode->flags |= DRM_MODE_FLAG_CSYNC; 1805 if (misc & ATOM_INTERLACE) 1806 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1807 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1808 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1809 1810 mode->crtc_clock = mode->clock = 1811 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; 1812 1813 if (index == 1) { 1814 /* PAL timings appear to have wrong values for totals */ 1815 mode->crtc_htotal -= 1; 1816 mode->crtc_vtotal -= 1; 1817 } 1818 break; 1819 case 2: 1820 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset); 1821 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2) 1822 return false; 1823 1824 dtd_timings = &tv_info_v1_2->aModeTimings[index]; 1825 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) + 1826 le16_to_cpu(dtd_timings->usHBlanking_Time); 1827 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive); 1828 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) + 1829 le16_to_cpu(dtd_timings->usHSyncOffset); 1830 mode->crtc_hsync_end = mode->crtc_hsync_start + 1831 le16_to_cpu(dtd_timings->usHSyncWidth); 1832 1833 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) + 1834 le16_to_cpu(dtd_timings->usVBlanking_Time); 1835 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive); 1836 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) + 1837 le16_to_cpu(dtd_timings->usVSyncOffset); 1838 mode->crtc_vsync_end = mode->crtc_vsync_start + 1839 le16_to_cpu(dtd_timings->usVSyncWidth); 1840 1841 mode->flags = 0; 1842 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); 1843 if (misc & ATOM_VSYNC_POLARITY) 1844 mode->flags |= DRM_MODE_FLAG_NVSYNC; 1845 if (misc & ATOM_HSYNC_POLARITY) 1846 mode->flags |= DRM_MODE_FLAG_NHSYNC; 1847 if (misc & ATOM_COMPOSITESYNC) 1848 mode->flags |= DRM_MODE_FLAG_CSYNC; 1849 if (misc & ATOM_INTERLACE) 1850 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1851 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1852 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1853 1854 mode->crtc_clock = mode->clock = 1855 le16_to_cpu(dtd_timings->usPixClk) * 10; 1856 break; 1857 } 1858 return true; 1859 } 1860 1861 enum radeon_tv_std 1862 radeon_atombios_get_tv_info(struct radeon_device *rdev) 1863 { 1864 struct radeon_mode_info *mode_info = &rdev->mode_info; 1865 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1866 uint16_t data_offset; 1867 uint8_t frev, crev; 1868 struct _ATOM_ANALOG_TV_INFO *tv_info; 1869 enum radeon_tv_std tv_std = TV_STD_NTSC; 1870 1871 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1872 &frev, &crev, &data_offset)) { 1873 1874 tv_info = (struct _ATOM_ANALOG_TV_INFO *) 1875 (mode_info->atom_context->bios + data_offset); 1876 1877 switch (tv_info->ucTV_BootUpDefaultStandard) { 1878 case ATOM_TV_NTSC: 1879 tv_std = TV_STD_NTSC; 1880 DRM_DEBUG_KMS("Default TV standard: NTSC\n"); 1881 break; 1882 case ATOM_TV_NTSCJ: 1883 tv_std = TV_STD_NTSC_J; 1884 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); 1885 break; 1886 case ATOM_TV_PAL: 1887 tv_std = TV_STD_PAL; 1888 DRM_DEBUG_KMS("Default TV standard: PAL\n"); 1889 break; 1890 case ATOM_TV_PALM: 1891 tv_std = TV_STD_PAL_M; 1892 DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); 1893 break; 1894 case ATOM_TV_PALN: 1895 tv_std = TV_STD_PAL_N; 1896 DRM_DEBUG_KMS("Default TV standard: PAL-N\n"); 1897 break; 1898 case ATOM_TV_PALCN: 1899 tv_std = TV_STD_PAL_CN; 1900 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n"); 1901 break; 1902 case ATOM_TV_PAL60: 1903 tv_std = TV_STD_PAL_60; 1904 DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); 1905 break; 1906 case ATOM_TV_SECAM: 1907 tv_std = TV_STD_SECAM; 1908 DRM_DEBUG_KMS("Default TV standard: SECAM\n"); 1909 break; 1910 default: 1911 tv_std = TV_STD_NTSC; 1912 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n"); 1913 break; 1914 } 1915 } 1916 return tv_std; 1917 } 1918 1919 struct radeon_encoder_tv_dac * 1920 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) 1921 { 1922 struct drm_device *dev = encoder->base.dev; 1923 struct radeon_device *rdev = dev->dev_private; 1924 struct radeon_mode_info *mode_info = &rdev->mode_info; 1925 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 1926 uint16_t data_offset; 1927 struct _COMPASSIONATE_DATA *dac_info; 1928 uint8_t frev, crev; 1929 uint8_t bg, dac; 1930 struct radeon_encoder_tv_dac *tv_dac = NULL; 1931 1932 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1933 &frev, &crev, &data_offset)) { 1934 1935 dac_info = (struct _COMPASSIONATE_DATA *) 1936 (mode_info->atom_context->bios + data_offset); 1937 1938 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 1939 1940 if (!tv_dac) 1941 return NULL; 1942 1943 bg = dac_info->ucDAC2_CRT2_BG_Adjustment; 1944 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment; 1945 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1946 1947 bg = dac_info->ucDAC2_PAL_BG_Adjustment; 1948 dac = dac_info->ucDAC2_PAL_DAC_Adjustment; 1949 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1950 1951 bg = dac_info->ucDAC2_NTSC_BG_Adjustment; 1952 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment; 1953 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1954 1955 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev); 1956 } 1957 return tv_dac; 1958 } 1959 1960 static const char *thermal_controller_names[] = { 1961 "NONE", 1962 "lm63", 1963 "adm1032", 1964 "adm1030", 1965 "max6649", 1966 "lm64", 1967 "f75375", 1968 "asc7xxx", 1969 }; 1970 1971 static const char *pp_lib_thermal_controller_names[] = { 1972 "NONE", 1973 "lm63", 1974 "adm1032", 1975 "adm1030", 1976 "max6649", 1977 "lm64", 1978 "f75375", 1979 "RV6xx", 1980 "RV770", 1981 "adt7473", 1982 "NONE", 1983 "External GPIO", 1984 "Evergreen", 1985 "emc2103", 1986 "Sumo", 1987 "Northern Islands", 1988 "Southern Islands", 1989 "lm96163", 1990 "Sea Islands", 1991 }; 1992 1993 union power_info { 1994 struct _ATOM_POWERPLAY_INFO info; 1995 struct _ATOM_POWERPLAY_INFO_V2 info_2; 1996 struct _ATOM_POWERPLAY_INFO_V3 info_3; 1997 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 1998 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 1999 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 2000 }; 2001 2002 union pplib_clock_info { 2003 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 2004 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 2005 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 2006 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 2007 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 2008 struct _ATOM_PPLIB_CI_CLOCK_INFO ci; 2009 }; 2010 2011 union pplib_power_state { 2012 struct _ATOM_PPLIB_STATE v1; 2013 struct _ATOM_PPLIB_STATE_V2 v2; 2014 }; 2015 2016 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev, 2017 int state_index, 2018 u32 misc, u32 misc2) 2019 { 2020 rdev->pm.power_state[state_index].misc = misc; 2021 rdev->pm.power_state[state_index].misc2 = misc2; 2022 /* order matters! */ 2023 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) 2024 rdev->pm.power_state[state_index].type = 2025 POWER_STATE_TYPE_POWERSAVE; 2026 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE) 2027 rdev->pm.power_state[state_index].type = 2028 POWER_STATE_TYPE_BATTERY; 2029 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE) 2030 rdev->pm.power_state[state_index].type = 2031 POWER_STATE_TYPE_BATTERY; 2032 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) 2033 rdev->pm.power_state[state_index].type = 2034 POWER_STATE_TYPE_BALANCED; 2035 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) { 2036 rdev->pm.power_state[state_index].type = 2037 POWER_STATE_TYPE_PERFORMANCE; 2038 rdev->pm.power_state[state_index].flags &= 2039 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2040 } 2041 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE) 2042 rdev->pm.power_state[state_index].type = 2043 POWER_STATE_TYPE_BALANCED; 2044 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { 2045 rdev->pm.power_state[state_index].type = 2046 POWER_STATE_TYPE_DEFAULT; 2047 rdev->pm.default_power_state_index = state_index; 2048 rdev->pm.power_state[state_index].default_clock_mode = 2049 &rdev->pm.power_state[state_index].clock_info[0]; 2050 } else if (state_index == 0) { 2051 rdev->pm.power_state[state_index].clock_info[0].flags |= 2052 RADEON_PM_MODE_NO_DISPLAY; 2053 } 2054 } 2055 2056 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev) 2057 { 2058 struct radeon_mode_info *mode_info = &rdev->mode_info; 2059 u32 misc, misc2 = 0; 2060 int num_modes = 0, i; 2061 int state_index = 0; 2062 struct radeon_i2c_bus_rec i2c_bus; 2063 union power_info *power_info; 2064 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2065 u16 data_offset; 2066 u8 frev, crev; 2067 2068 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2069 &frev, &crev, &data_offset)) 2070 return state_index; 2071 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2072 2073 /* add the i2c bus for thermal/fan chip */ 2074 if ((power_info->info.ucOverdriveThermalController > 0) && 2075 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) { 2076 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2077 thermal_controller_names[power_info->info.ucOverdriveThermalController], 2078 power_info->info.ucOverdriveControllerAddress >> 1); 2079 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine); 2080 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2081 if (rdev->pm.i2c_bus) { 2082 struct i2c_board_info info = { }; 2083 const char *name = thermal_controller_names[power_info->info. 2084 ucOverdriveThermalController]; 2085 info.addr = power_info->info.ucOverdriveControllerAddress >> 1; 2086 strlcpy(info.type, name, sizeof(info.type)); 2087 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2088 } 2089 } 2090 num_modes = power_info->info.ucNumOfPowerModeEntries; 2091 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK) 2092 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK; 2093 if (num_modes == 0) 2094 return state_index; 2095 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL); 2096 if (!rdev->pm.power_state) 2097 return state_index; 2098 /* last mode is usually default, array is low to high */ 2099 for (i = 0; i < num_modes; i++) { 2100 rdev->pm.power_state[state_index].clock_info = 2101 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); 2102 if (!rdev->pm.power_state[state_index].clock_info) 2103 return state_index; 2104 rdev->pm.power_state[state_index].num_clock_modes = 1; 2105 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2106 switch (frev) { 2107 case 1: 2108 rdev->pm.power_state[state_index].clock_info[0].mclk = 2109 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock); 2110 rdev->pm.power_state[state_index].clock_info[0].sclk = 2111 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock); 2112 /* skip invalid modes */ 2113 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2114 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2115 continue; 2116 rdev->pm.power_state[state_index].pcie_lanes = 2117 power_info->info.asPowerPlayInfo[i].ucNumPciELanes; 2118 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo); 2119 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2120 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2121 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2122 VOLTAGE_GPIO; 2123 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2124 radeon_lookup_gpio(rdev, 2125 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex); 2126 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2127 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2128 true; 2129 else 2130 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2131 false; 2132 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2133 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2134 VOLTAGE_VDDC; 2135 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2136 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex; 2137 } 2138 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2139 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0); 2140 state_index++; 2141 break; 2142 case 2: 2143 rdev->pm.power_state[state_index].clock_info[0].mclk = 2144 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock); 2145 rdev->pm.power_state[state_index].clock_info[0].sclk = 2146 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock); 2147 /* skip invalid modes */ 2148 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2149 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2150 continue; 2151 rdev->pm.power_state[state_index].pcie_lanes = 2152 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes; 2153 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo); 2154 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2); 2155 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2156 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2157 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2158 VOLTAGE_GPIO; 2159 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2160 radeon_lookup_gpio(rdev, 2161 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex); 2162 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2163 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2164 true; 2165 else 2166 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2167 false; 2168 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2169 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2170 VOLTAGE_VDDC; 2171 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2172 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex; 2173 } 2174 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2175 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); 2176 state_index++; 2177 break; 2178 case 3: 2179 rdev->pm.power_state[state_index].clock_info[0].mclk = 2180 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock); 2181 rdev->pm.power_state[state_index].clock_info[0].sclk = 2182 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock); 2183 /* skip invalid modes */ 2184 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2185 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2186 continue; 2187 rdev->pm.power_state[state_index].pcie_lanes = 2188 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes; 2189 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo); 2190 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2); 2191 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2192 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2193 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2194 VOLTAGE_GPIO; 2195 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2196 radeon_lookup_gpio(rdev, 2197 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex); 2198 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2199 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2200 true; 2201 else 2202 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2203 false; 2204 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2205 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2206 VOLTAGE_VDDC; 2207 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2208 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex; 2209 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) { 2210 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled = 2211 true; 2212 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id = 2213 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex; 2214 } 2215 } 2216 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2217 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); 2218 state_index++; 2219 break; 2220 } 2221 } 2222 /* last mode is usually default */ 2223 if (rdev->pm.default_power_state_index == -1) { 2224 rdev->pm.power_state[state_index - 1].type = 2225 POWER_STATE_TYPE_DEFAULT; 2226 rdev->pm.default_power_state_index = state_index - 1; 2227 rdev->pm.power_state[state_index - 1].default_clock_mode = 2228 &rdev->pm.power_state[state_index - 1].clock_info[0]; 2229 rdev->pm.power_state[state_index].flags &= 2230 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2231 rdev->pm.power_state[state_index].misc = 0; 2232 rdev->pm.power_state[state_index].misc2 = 0; 2233 } 2234 return state_index; 2235 } 2236 2237 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev, 2238 ATOM_PPLIB_THERMALCONTROLLER *controller) 2239 { 2240 struct radeon_i2c_bus_rec i2c_bus; 2241 2242 /* add the i2c bus for thermal/fan chip */ 2243 if (controller->ucType > 0) { 2244 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) { 2245 DRM_INFO("Internal thermal controller %s fan control\n", 2246 (controller->ucFanParameters & 2247 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2248 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX; 2249 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) { 2250 DRM_INFO("Internal thermal controller %s fan control\n", 2251 (controller->ucFanParameters & 2252 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2253 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770; 2254 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) { 2255 DRM_INFO("Internal thermal controller %s fan control\n", 2256 (controller->ucFanParameters & 2257 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2258 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN; 2259 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) { 2260 DRM_INFO("Internal thermal controller %s fan control\n", 2261 (controller->ucFanParameters & 2262 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2263 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO; 2264 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) { 2265 DRM_INFO("Internal thermal controller %s fan control\n", 2266 (controller->ucFanParameters & 2267 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2268 rdev->pm.int_thermal_type = THERMAL_TYPE_NI; 2269 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) { 2270 DRM_INFO("Internal thermal controller %s fan control\n", 2271 (controller->ucFanParameters & 2272 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2273 rdev->pm.int_thermal_type = THERMAL_TYPE_SI; 2274 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) { 2275 DRM_INFO("Internal thermal controller %s fan control\n", 2276 (controller->ucFanParameters & 2277 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2278 rdev->pm.int_thermal_type = THERMAL_TYPE_CI; 2279 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) { 2280 DRM_INFO("Internal thermal controller %s fan control\n", 2281 (controller->ucFanParameters & 2282 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2283 rdev->pm.int_thermal_type = THERMAL_TYPE_KV; 2284 } else if ((controller->ucType == 2285 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) || 2286 (controller->ucType == 2287 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) || 2288 (controller->ucType == 2289 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) { 2290 DRM_INFO("Special thermal controller config\n"); 2291 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) { 2292 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n", 2293 pp_lib_thermal_controller_names[controller->ucType], 2294 controller->ucI2cAddress >> 1, 2295 (controller->ucFanParameters & 2296 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2297 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine); 2298 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2299 if (rdev->pm.i2c_bus) { 2300 struct i2c_board_info info = { }; 2301 const char *name = pp_lib_thermal_controller_names[controller->ucType]; 2302 info.addr = controller->ucI2cAddress >> 1; 2303 strlcpy(info.type, name, sizeof(info.type)); 2304 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2305 } 2306 } else { 2307 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n", 2308 controller->ucType, 2309 controller->ucI2cAddress >> 1, 2310 (controller->ucFanParameters & 2311 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2312 } 2313 } 2314 } 2315 2316 void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 2317 u16 *vddc, u16 *vddci, u16 *mvdd) 2318 { 2319 struct radeon_mode_info *mode_info = &rdev->mode_info; 2320 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 2321 u8 frev, crev; 2322 u16 data_offset; 2323 union firmware_info *firmware_info; 2324 2325 *vddc = 0; 2326 *vddci = 0; 2327 *mvdd = 0; 2328 2329 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2330 &frev, &crev, &data_offset)) { 2331 firmware_info = 2332 (union firmware_info *)(mode_info->atom_context->bios + 2333 data_offset); 2334 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage); 2335 if ((frev == 2) && (crev >= 2)) { 2336 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage); 2337 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage); 2338 } 2339 } 2340 } 2341 2342 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev, 2343 int state_index, int mode_index, 2344 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info) 2345 { 2346 int j; 2347 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings); 2348 u32 misc2 = le16_to_cpu(non_clock_info->usClassification); 2349 u16 vddc, vddci, mvdd; 2350 2351 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 2352 2353 rdev->pm.power_state[state_index].misc = misc; 2354 rdev->pm.power_state[state_index].misc2 = misc2; 2355 rdev->pm.power_state[state_index].pcie_lanes = 2356 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> 2357 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 2358 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { 2359 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: 2360 rdev->pm.power_state[state_index].type = 2361 POWER_STATE_TYPE_BATTERY; 2362 break; 2363 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED: 2364 rdev->pm.power_state[state_index].type = 2365 POWER_STATE_TYPE_BALANCED; 2366 break; 2367 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: 2368 rdev->pm.power_state[state_index].type = 2369 POWER_STATE_TYPE_PERFORMANCE; 2370 break; 2371 case ATOM_PPLIB_CLASSIFICATION_UI_NONE: 2372 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) 2373 rdev->pm.power_state[state_index].type = 2374 POWER_STATE_TYPE_PERFORMANCE; 2375 break; 2376 } 2377 rdev->pm.power_state[state_index].flags = 0; 2378 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) 2379 rdev->pm.power_state[state_index].flags |= 2380 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2381 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) { 2382 rdev->pm.power_state[state_index].type = 2383 POWER_STATE_TYPE_DEFAULT; 2384 rdev->pm.default_power_state_index = state_index; 2385 rdev->pm.power_state[state_index].default_clock_mode = 2386 &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; 2387 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) { 2388 /* NI chips post without MC ucode, so default clocks are strobe mode only */ 2389 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk; 2390 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk; 2391 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage; 2392 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci; 2393 } else { 2394 u16 max_vddci = 0; 2395 2396 if (ASIC_IS_DCE4(rdev)) 2397 radeon_atom_get_max_voltage(rdev, 2398 SET_VOLTAGE_TYPE_ASIC_VDDCI, 2399 &max_vddci); 2400 /* patch the table values with the default sclk/mclk from firmware info */ 2401 for (j = 0; j < mode_index; j++) { 2402 rdev->pm.power_state[state_index].clock_info[j].mclk = 2403 rdev->clock.default_mclk; 2404 rdev->pm.power_state[state_index].clock_info[j].sclk = 2405 rdev->clock.default_sclk; 2406 if (vddc) 2407 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage = 2408 vddc; 2409 if (max_vddci) 2410 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci = 2411 max_vddci; 2412 } 2413 } 2414 } 2415 } 2416 2417 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev, 2418 int state_index, int mode_index, 2419 union pplib_clock_info *clock_info) 2420 { 2421 u32 sclk, mclk; 2422 u16 vddc; 2423 2424 if (rdev->flags & RADEON_IS_IGP) { 2425 if (rdev->family >= CHIP_PALM) { 2426 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); 2427 sclk |= clock_info->sumo.ucEngineClockHigh << 16; 2428 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2429 } else { 2430 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow); 2431 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; 2432 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2433 } 2434 } else if (rdev->family >= CHIP_BONAIRE) { 2435 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); 2436 sclk |= clock_info->ci.ucEngineClockHigh << 16; 2437 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); 2438 mclk |= clock_info->ci.ucMemoryClockHigh << 16; 2439 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2440 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2441 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2442 VOLTAGE_NONE; 2443 } else if (rdev->family >= CHIP_TAHITI) { 2444 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 2445 sclk |= clock_info->si.ucEngineClockHigh << 16; 2446 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 2447 mclk |= clock_info->si.ucMemoryClockHigh << 16; 2448 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2449 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2450 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2451 VOLTAGE_SW; 2452 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2453 le16_to_cpu(clock_info->si.usVDDC); 2454 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = 2455 le16_to_cpu(clock_info->si.usVDDCI); 2456 } else if (rdev->family >= CHIP_CEDAR) { 2457 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); 2458 sclk |= clock_info->evergreen.ucEngineClockHigh << 16; 2459 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow); 2460 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16; 2461 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2462 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2463 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2464 VOLTAGE_SW; 2465 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2466 le16_to_cpu(clock_info->evergreen.usVDDC); 2467 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = 2468 le16_to_cpu(clock_info->evergreen.usVDDCI); 2469 } else { 2470 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow); 2471 sclk |= clock_info->r600.ucEngineClockHigh << 16; 2472 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow); 2473 mclk |= clock_info->r600.ucMemoryClockHigh << 16; 2474 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2475 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2476 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2477 VOLTAGE_SW; 2478 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2479 le16_to_cpu(clock_info->r600.usVDDC); 2480 } 2481 2482 /* patch up vddc if necessary */ 2483 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) { 2484 case ATOM_VIRTUAL_VOLTAGE_ID0: 2485 case ATOM_VIRTUAL_VOLTAGE_ID1: 2486 case ATOM_VIRTUAL_VOLTAGE_ID2: 2487 case ATOM_VIRTUAL_VOLTAGE_ID3: 2488 case ATOM_VIRTUAL_VOLTAGE_ID4: 2489 case ATOM_VIRTUAL_VOLTAGE_ID5: 2490 case ATOM_VIRTUAL_VOLTAGE_ID6: 2491 case ATOM_VIRTUAL_VOLTAGE_ID7: 2492 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, 2493 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage, 2494 &vddc) == 0) 2495 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc; 2496 break; 2497 default: 2498 break; 2499 } 2500 2501 if (rdev->flags & RADEON_IS_IGP) { 2502 /* skip invalid modes */ 2503 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) 2504 return false; 2505 } else { 2506 /* skip invalid modes */ 2507 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || 2508 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) 2509 return false; 2510 } 2511 return true; 2512 } 2513 2514 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev) 2515 { 2516 struct radeon_mode_info *mode_info = &rdev->mode_info; 2517 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2518 union pplib_power_state *power_state; 2519 int i, j; 2520 int state_index = 0, mode_index = 0; 2521 union pplib_clock_info *clock_info; 2522 bool valid; 2523 union power_info *power_info; 2524 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2525 u16 data_offset; 2526 u8 frev, crev; 2527 2528 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2529 &frev, &crev, &data_offset)) 2530 return state_index; 2531 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2532 2533 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2534 if (power_info->pplib.ucNumStates == 0) 2535 return state_index; 2536 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2537 power_info->pplib.ucNumStates, GFP_KERNEL); 2538 if (!rdev->pm.power_state) 2539 return state_index; 2540 /* first mode is usually default, followed by low to high */ 2541 for (i = 0; i < power_info->pplib.ucNumStates; i++) { 2542 mode_index = 0; 2543 power_state = (union pplib_power_state *) 2544 (mode_info->atom_context->bios + data_offset + 2545 le16_to_cpu(power_info->pplib.usStateArrayOffset) + 2546 i * power_info->pplib.ucStateEntrySize); 2547 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2548 (mode_info->atom_context->bios + data_offset + 2549 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) + 2550 (power_state->v1.ucNonClockStateIndex * 2551 power_info->pplib.ucNonClockSize)); 2552 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) * 2553 ((power_info->pplib.ucStateEntrySize - 1) ? 2554 (power_info->pplib.ucStateEntrySize - 1) : 1), 2555 GFP_KERNEL); 2556 if (!rdev->pm.power_state[i].clock_info) 2557 return state_index; 2558 if (power_info->pplib.ucStateEntrySize - 1) { 2559 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) { 2560 clock_info = (union pplib_clock_info *) 2561 (mode_info->atom_context->bios + data_offset + 2562 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) + 2563 (power_state->v1.ucClockStateIndices[j] * 2564 power_info->pplib.ucClockInfoSize)); 2565 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2566 state_index, mode_index, 2567 clock_info); 2568 if (valid) 2569 mode_index++; 2570 } 2571 } else { 2572 rdev->pm.power_state[state_index].clock_info[0].mclk = 2573 rdev->clock.default_mclk; 2574 rdev->pm.power_state[state_index].clock_info[0].sclk = 2575 rdev->clock.default_sclk; 2576 mode_index++; 2577 } 2578 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2579 if (mode_index) { 2580 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, 2581 non_clock_info); 2582 state_index++; 2583 } 2584 } 2585 /* if multiple clock modes, mark the lowest as no display */ 2586 for (i = 0; i < state_index; i++) { 2587 if (rdev->pm.power_state[i].num_clock_modes > 1) 2588 rdev->pm.power_state[i].clock_info[0].flags |= 2589 RADEON_PM_MODE_NO_DISPLAY; 2590 } 2591 /* first mode is usually default */ 2592 if (rdev->pm.default_power_state_index == -1) { 2593 rdev->pm.power_state[0].type = 2594 POWER_STATE_TYPE_DEFAULT; 2595 rdev->pm.default_power_state_index = 0; 2596 rdev->pm.power_state[0].default_clock_mode = 2597 &rdev->pm.power_state[0].clock_info[0]; 2598 } 2599 return state_index; 2600 } 2601 2602 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev) 2603 { 2604 struct radeon_mode_info *mode_info = &rdev->mode_info; 2605 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2606 union pplib_power_state *power_state; 2607 int i, j, non_clock_array_index, clock_array_index; 2608 int state_index = 0, mode_index = 0; 2609 union pplib_clock_info *clock_info; 2610 struct _StateArray *state_array; 2611 struct _ClockInfoArray *clock_info_array; 2612 struct _NonClockInfoArray *non_clock_info_array; 2613 bool valid; 2614 union power_info *power_info; 2615 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2616 u16 data_offset; 2617 u8 frev, crev; 2618 u8 *power_state_offset; 2619 2620 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2621 &frev, &crev, &data_offset)) 2622 return state_index; 2623 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2624 2625 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2626 state_array = (struct _StateArray *) 2627 (mode_info->atom_context->bios + data_offset + 2628 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 2629 clock_info_array = (struct _ClockInfoArray *) 2630 (mode_info->atom_context->bios + data_offset + 2631 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 2632 non_clock_info_array = (struct _NonClockInfoArray *) 2633 (mode_info->atom_context->bios + data_offset + 2634 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 2635 if (state_array->ucNumEntries == 0) 2636 return state_index; 2637 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2638 state_array->ucNumEntries, GFP_KERNEL); 2639 if (!rdev->pm.power_state) 2640 return state_index; 2641 power_state_offset = (u8 *)state_array->states; 2642 for (i = 0; i < state_array->ucNumEntries; i++) { 2643 mode_index = 0; 2644 power_state = (union pplib_power_state *)power_state_offset; 2645 non_clock_array_index = power_state->v2.nonClockInfoIndex; 2646 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2647 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 2648 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) * 2649 (power_state->v2.ucNumDPMLevels ? 2650 power_state->v2.ucNumDPMLevels : 1), 2651 GFP_KERNEL); 2652 if (!rdev->pm.power_state[i].clock_info) 2653 return state_index; 2654 if (power_state->v2.ucNumDPMLevels) { 2655 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 2656 clock_array_index = power_state->v2.clockInfoIndex[j]; 2657 clock_info = (union pplib_clock_info *) 2658 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 2659 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2660 state_index, mode_index, 2661 clock_info); 2662 if (valid) 2663 mode_index++; 2664 } 2665 } else { 2666 rdev->pm.power_state[state_index].clock_info[0].mclk = 2667 rdev->clock.default_mclk; 2668 rdev->pm.power_state[state_index].clock_info[0].sclk = 2669 rdev->clock.default_sclk; 2670 mode_index++; 2671 } 2672 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2673 if (mode_index) { 2674 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, 2675 non_clock_info); 2676 state_index++; 2677 } 2678 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 2679 } 2680 /* if multiple clock modes, mark the lowest as no display */ 2681 for (i = 0; i < state_index; i++) { 2682 if (rdev->pm.power_state[i].num_clock_modes > 1) 2683 rdev->pm.power_state[i].clock_info[0].flags |= 2684 RADEON_PM_MODE_NO_DISPLAY; 2685 } 2686 /* first mode is usually default */ 2687 if (rdev->pm.default_power_state_index == -1) { 2688 rdev->pm.power_state[0].type = 2689 POWER_STATE_TYPE_DEFAULT; 2690 rdev->pm.default_power_state_index = 0; 2691 rdev->pm.power_state[0].default_clock_mode = 2692 &rdev->pm.power_state[0].clock_info[0]; 2693 } 2694 return state_index; 2695 } 2696 2697 void radeon_atombios_get_power_modes(struct radeon_device *rdev) 2698 { 2699 struct radeon_mode_info *mode_info = &rdev->mode_info; 2700 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2701 u16 data_offset; 2702 u8 frev, crev; 2703 int state_index = 0; 2704 2705 rdev->pm.default_power_state_index = -1; 2706 2707 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2708 &frev, &crev, &data_offset)) { 2709 switch (frev) { 2710 case 1: 2711 case 2: 2712 case 3: 2713 state_index = radeon_atombios_parse_power_table_1_3(rdev); 2714 break; 2715 case 4: 2716 case 5: 2717 state_index = radeon_atombios_parse_power_table_4_5(rdev); 2718 break; 2719 case 6: 2720 state_index = radeon_atombios_parse_power_table_6(rdev); 2721 break; 2722 default: 2723 break; 2724 } 2725 } 2726 2727 if (state_index == 0) { 2728 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL); 2729 if (rdev->pm.power_state) { 2730 rdev->pm.power_state[0].clock_info = 2731 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); 2732 if (rdev->pm.power_state[0].clock_info) { 2733 /* add the default mode */ 2734 rdev->pm.power_state[state_index].type = 2735 POWER_STATE_TYPE_DEFAULT; 2736 rdev->pm.power_state[state_index].num_clock_modes = 1; 2737 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 2738 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2739 rdev->pm.power_state[state_index].default_clock_mode = 2740 &rdev->pm.power_state[state_index].clock_info[0]; 2741 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2742 rdev->pm.power_state[state_index].pcie_lanes = 16; 2743 rdev->pm.default_power_state_index = state_index; 2744 rdev->pm.power_state[state_index].flags = 0; 2745 state_index++; 2746 } 2747 } 2748 } 2749 2750 rdev->pm.num_power_states = state_index; 2751 2752 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2753 rdev->pm.current_clock_mode_index = 0; 2754 if (rdev->pm.default_power_state_index >= 0) 2755 rdev->pm.current_vddc = 2756 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 2757 else 2758 rdev->pm.current_vddc = 0; 2759 } 2760 2761 union get_clock_dividers { 2762 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1; 2763 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2; 2764 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; 2765 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4; 2766 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; 2767 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in; 2768 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out; 2769 }; 2770 2771 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 2772 u8 clock_type, 2773 u32 clock, 2774 bool strobe_mode, 2775 struct atom_clock_dividers *dividers) 2776 { 2777 union get_clock_dividers args; 2778 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL); 2779 u8 frev, crev; 2780 2781 memset(&args, 0, sizeof(args)); 2782 memset(dividers, 0, sizeof(struct atom_clock_dividers)); 2783 2784 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2785 return -EINVAL; 2786 2787 switch (crev) { 2788 case 1: 2789 /* r4xx, r5xx */ 2790 args.v1.ucAction = clock_type; 2791 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */ 2792 2793 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2794 2795 dividers->post_div = args.v1.ucPostDiv; 2796 dividers->fb_div = args.v1.ucFbDiv; 2797 dividers->enable_post_div = true; 2798 break; 2799 case 2: 2800 case 3: 2801 case 5: 2802 /* r6xx, r7xx, evergreen, ni, si */ 2803 if (rdev->family <= CHIP_RV770) { 2804 args.v2.ucAction = clock_type; 2805 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */ 2806 2807 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2808 2809 dividers->post_div = args.v2.ucPostDiv; 2810 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); 2811 dividers->ref_div = args.v2.ucAction; 2812 if (rdev->family == CHIP_RV770) { 2813 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ? 2814 true : false; 2815 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0; 2816 } else 2817 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false; 2818 } else { 2819 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { 2820 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); 2821 2822 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2823 2824 dividers->post_div = args.v3.ucPostDiv; 2825 dividers->enable_post_div = (args.v3.ucCntlFlag & 2826 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 2827 dividers->enable_dithen = (args.v3.ucCntlFlag & 2828 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 2829 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); 2830 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); 2831 dividers->ref_div = args.v3.ucRefDiv; 2832 dividers->vco_mode = (args.v3.ucCntlFlag & 2833 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 2834 } else { 2835 /* for SI we use ComputeMemoryClockParam for memory plls */ 2836 if (rdev->family >= CHIP_TAHITI) 2837 return -EINVAL; 2838 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); 2839 if (strobe_mode) 2840 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN; 2841 2842 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2843 2844 dividers->post_div = args.v5.ucPostDiv; 2845 dividers->enable_post_div = (args.v5.ucCntlFlag & 2846 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 2847 dividers->enable_dithen = (args.v5.ucCntlFlag & 2848 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 2849 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv); 2850 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac); 2851 dividers->ref_div = args.v5.ucRefDiv; 2852 dividers->vco_mode = (args.v5.ucCntlFlag & 2853 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 2854 } 2855 } 2856 break; 2857 case 4: 2858 /* fusion */ 2859 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */ 2860 2861 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2862 2863 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; 2864 dividers->real_clock = le32_to_cpu(args.v4.ulClock); 2865 break; 2866 case 6: 2867 /* CI */ 2868 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */ 2869 args.v6_in.ulClock.ulComputeClockFlag = clock_type; 2870 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ 2871 2872 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2873 2874 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv); 2875 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac); 2876 dividers->ref_div = args.v6_out.ucPllRefDiv; 2877 dividers->post_div = args.v6_out.ucPllPostDiv; 2878 dividers->flags = args.v6_out.ucPllCntlFlag; 2879 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock); 2880 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; 2881 break; 2882 default: 2883 return -EINVAL; 2884 } 2885 return 0; 2886 } 2887 2888 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 2889 u32 clock, 2890 bool strobe_mode, 2891 struct atom_mpll_param *mpll_param) 2892 { 2893 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args; 2894 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam); 2895 u8 frev, crev; 2896 2897 memset(&args, 0, sizeof(args)); 2898 memset(mpll_param, 0, sizeof(struct atom_mpll_param)); 2899 2900 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2901 return -EINVAL; 2902 2903 switch (frev) { 2904 case 2: 2905 switch (crev) { 2906 case 1: 2907 /* SI */ 2908 args.ulClock = cpu_to_le32(clock); /* 10 khz */ 2909 args.ucInputFlag = 0; 2910 if (strobe_mode) 2911 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN; 2912 2913 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2914 2915 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac); 2916 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv); 2917 mpll_param->post_div = args.ucPostDiv; 2918 mpll_param->dll_speed = args.ucDllSpeed; 2919 mpll_param->bwcntl = args.ucBWCntl; 2920 mpll_param->vco_mode = 2921 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK); 2922 mpll_param->yclk_sel = 2923 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0; 2924 mpll_param->qdr = 2925 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0; 2926 mpll_param->half_rate = 2927 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0; 2928 break; 2929 default: 2930 return -EINVAL; 2931 } 2932 break; 2933 default: 2934 return -EINVAL; 2935 } 2936 return 0; 2937 } 2938 2939 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) 2940 { 2941 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args; 2942 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating); 2943 2944 args.ucEnable = enable; 2945 2946 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2947 } 2948 2949 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev) 2950 { 2951 GET_ENGINE_CLOCK_PS_ALLOCATION args; 2952 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); 2953 2954 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2955 return le32_to_cpu(args.ulReturnEngineClock); 2956 } 2957 2958 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev) 2959 { 2960 GET_MEMORY_CLOCK_PS_ALLOCATION args; 2961 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); 2962 2963 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2964 return le32_to_cpu(args.ulReturnMemoryClock); 2965 } 2966 2967 void radeon_atom_set_engine_clock(struct radeon_device *rdev, 2968 uint32_t eng_clock) 2969 { 2970 SET_ENGINE_CLOCK_PS_ALLOCATION args; 2971 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); 2972 2973 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */ 2974 2975 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2976 } 2977 2978 void radeon_atom_set_memory_clock(struct radeon_device *rdev, 2979 uint32_t mem_clock) 2980 { 2981 SET_MEMORY_CLOCK_PS_ALLOCATION args; 2982 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); 2983 2984 if (rdev->flags & RADEON_IS_IGP) 2985 return; 2986 2987 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */ 2988 2989 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2990 } 2991 2992 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 2993 u32 eng_clock, u32 mem_clock) 2994 { 2995 SET_ENGINE_CLOCK_PS_ALLOCATION args; 2996 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 2997 u32 tmp; 2998 2999 memset(&args, 0, sizeof(args)); 3000 3001 tmp = eng_clock & SET_CLOCK_FREQ_MASK; 3002 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24); 3003 3004 args.ulTargetEngineClock = cpu_to_le32(tmp); 3005 if (mem_clock) 3006 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK); 3007 3008 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3009 } 3010 3011 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 3012 u32 mem_clock) 3013 { 3014 u32 args; 3015 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 3016 3017 args = cpu_to_le32(mem_clock); /* 10 khz */ 3018 3019 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3020 } 3021 3022 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 3023 u32 mem_clock) 3024 { 3025 SET_MEMORY_CLOCK_PS_ALLOCATION args; 3026 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 3027 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24); 3028 3029 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */ 3030 3031 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3032 } 3033 3034 union set_voltage { 3035 struct _SET_VOLTAGE_PS_ALLOCATION alloc; 3036 struct _SET_VOLTAGE_PARAMETERS v1; 3037 struct _SET_VOLTAGE_PARAMETERS_V2 v2; 3038 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; 3039 }; 3040 3041 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type) 3042 { 3043 union set_voltage args; 3044 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3045 u8 frev, crev, volt_index = voltage_level; 3046 3047 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3048 return; 3049 3050 /* 0xff01 is a flag rather then an actual voltage */ 3051 if (voltage_level == 0xff01) 3052 return; 3053 3054 switch (crev) { 3055 case 1: 3056 args.v1.ucVoltageType = voltage_type; 3057 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE; 3058 args.v1.ucVoltageIndex = volt_index; 3059 break; 3060 case 2: 3061 args.v2.ucVoltageType = voltage_type; 3062 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE; 3063 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3064 break; 3065 case 3: 3066 args.v3.ucVoltageType = voltage_type; 3067 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE; 3068 args.v3.usVoltageLevel = cpu_to_le16(voltage_level); 3069 break; 3070 default: 3071 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3072 return; 3073 } 3074 3075 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3076 } 3077 3078 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 3079 u16 voltage_id, u16 *voltage) 3080 { 3081 union set_voltage args; 3082 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3083 u8 frev, crev; 3084 3085 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3086 return -EINVAL; 3087 3088 switch (crev) { 3089 case 1: 3090 return -EINVAL; 3091 case 2: 3092 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE; 3093 args.v2.ucVoltageMode = 0; 3094 args.v2.usVoltageLevel = 0; 3095 3096 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3097 3098 *voltage = le16_to_cpu(args.v2.usVoltageLevel); 3099 break; 3100 case 3: 3101 args.v3.ucVoltageType = voltage_type; 3102 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL; 3103 args.v3.usVoltageLevel = cpu_to_le16(voltage_id); 3104 3105 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3106 3107 *voltage = le16_to_cpu(args.v3.usVoltageLevel); 3108 break; 3109 default: 3110 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3111 return -EINVAL; 3112 } 3113 3114 return 0; 3115 } 3116 3117 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 3118 u16 *voltage, 3119 u16 leakage_idx) 3120 { 3121 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage); 3122 } 3123 3124 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 3125 u16 *leakage_id) 3126 { 3127 union set_voltage args; 3128 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3129 u8 frev, crev; 3130 3131 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3132 return -EINVAL; 3133 3134 switch (crev) { 3135 case 3: 3136 case 4: 3137 args.v3.ucVoltageType = 0; 3138 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID; 3139 args.v3.usVoltageLevel = 0; 3140 3141 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3142 3143 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel); 3144 break; 3145 default: 3146 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3147 return -EINVAL; 3148 } 3149 3150 return 0; 3151 } 3152 3153 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 3154 u16 *vddc, u16 *vddci, 3155 u16 virtual_voltage_id, 3156 u16 vbios_voltage_id) 3157 { 3158 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo); 3159 u8 frev, crev; 3160 u16 data_offset, size; 3161 int i, j; 3162 ATOM_ASIC_PROFILING_INFO_V2_1 *profile; 3163 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf; 3164 3165 *vddc = 0; 3166 *vddci = 0; 3167 3168 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3169 &frev, &crev, &data_offset)) 3170 return -EINVAL; 3171 3172 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *) 3173 (rdev->mode_info.atom_context->bios + data_offset); 3174 3175 switch (frev) { 3176 case 1: 3177 return -EINVAL; 3178 case 2: 3179 switch (crev) { 3180 case 1: 3181 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1)) 3182 return -EINVAL; 3183 leakage_bin = (u16 *) 3184 (rdev->mode_info.atom_context->bios + data_offset + 3185 le16_to_cpu(profile->usLeakageBinArrayOffset)); 3186 vddc_id_buf = (u16 *) 3187 (rdev->mode_info.atom_context->bios + data_offset + 3188 le16_to_cpu(profile->usElbVDDC_IdArrayOffset)); 3189 vddc_buf = (u16 *) 3190 (rdev->mode_info.atom_context->bios + data_offset + 3191 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset)); 3192 vddci_id_buf = (u16 *) 3193 (rdev->mode_info.atom_context->bios + data_offset + 3194 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset)); 3195 vddci_buf = (u16 *) 3196 (rdev->mode_info.atom_context->bios + data_offset + 3197 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset)); 3198 3199 if (profile->ucElbVDDC_Num > 0) { 3200 for (i = 0; i < profile->ucElbVDDC_Num; i++) { 3201 if (vddc_id_buf[i] == virtual_voltage_id) { 3202 for (j = 0; j < profile->ucLeakageBinNum; j++) { 3203 if (vbios_voltage_id <= leakage_bin[j]) { 3204 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i]; 3205 break; 3206 } 3207 } 3208 break; 3209 } 3210 } 3211 } 3212 if (profile->ucElbVDDCI_Num > 0) { 3213 for (i = 0; i < profile->ucElbVDDCI_Num; i++) { 3214 if (vddci_id_buf[i] == virtual_voltage_id) { 3215 for (j = 0; j < profile->ucLeakageBinNum; j++) { 3216 if (vbios_voltage_id <= leakage_bin[j]) { 3217 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i]; 3218 break; 3219 } 3220 } 3221 break; 3222 } 3223 } 3224 } 3225 break; 3226 default: 3227 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3228 return -EINVAL; 3229 } 3230 break; 3231 default: 3232 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3233 return -EINVAL; 3234 } 3235 3236 return 0; 3237 } 3238 3239 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 3240 u16 voltage_level, u8 voltage_type, 3241 u32 *gpio_value, u32 *gpio_mask) 3242 { 3243 union set_voltage args; 3244 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3245 u8 frev, crev; 3246 3247 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3248 return -EINVAL; 3249 3250 switch (crev) { 3251 case 1: 3252 return -EINVAL; 3253 case 2: 3254 args.v2.ucVoltageType = voltage_type; 3255 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK; 3256 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3257 3258 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3259 3260 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2); 3261 3262 args.v2.ucVoltageType = voltage_type; 3263 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL; 3264 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3265 3266 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3267 3268 *gpio_value = le32_to_cpu(*(u32 *)&args.v2); 3269 break; 3270 default: 3271 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3272 return -EINVAL; 3273 } 3274 3275 return 0; 3276 } 3277 3278 union voltage_object_info { 3279 struct _ATOM_VOLTAGE_OBJECT_INFO v1; 3280 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2; 3281 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; 3282 }; 3283 3284 union voltage_object { 3285 struct _ATOM_VOLTAGE_OBJECT v1; 3286 struct _ATOM_VOLTAGE_OBJECT_V2 v2; 3287 union _ATOM_VOLTAGE_OBJECT_V3 v3; 3288 }; 3289 3290 static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1, 3291 u8 voltage_type) 3292 { 3293 u32 size = le16_to_cpu(v1->sHeader.usStructureSize); 3294 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]); 3295 u8 *start = (u8 *)v1; 3296 3297 while (offset < size) { 3298 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset); 3299 if (vo->ucVoltageType == voltage_type) 3300 return vo; 3301 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) + 3302 vo->asFormula.ucNumOfVoltageEntries; 3303 } 3304 return NULL; 3305 } 3306 3307 static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2, 3308 u8 voltage_type) 3309 { 3310 u32 size = le16_to_cpu(v2->sHeader.usStructureSize); 3311 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]); 3312 u8 *start = (u8*)v2; 3313 3314 while (offset < size) { 3315 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset); 3316 if (vo->ucVoltageType == voltage_type) 3317 return vo; 3318 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) + 3319 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY)); 3320 } 3321 return NULL; 3322 } 3323 3324 static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3, 3325 u8 voltage_type, u8 voltage_mode) 3326 { 3327 u32 size = le16_to_cpu(v3->sHeader.usStructureSize); 3328 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]); 3329 u8 *start = (u8*)v3; 3330 3331 while (offset < size) { 3332 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset); 3333 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) && 3334 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode)) 3335 return vo; 3336 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize); 3337 } 3338 return NULL; 3339 } 3340 3341 bool 3342 radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 3343 u8 voltage_type, u8 voltage_mode) 3344 { 3345 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3346 u8 frev, crev; 3347 u16 data_offset, size; 3348 union voltage_object_info *voltage_info; 3349 union voltage_object *voltage_object = NULL; 3350 3351 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3352 &frev, &crev, &data_offset)) { 3353 voltage_info = (union voltage_object_info *) 3354 (rdev->mode_info.atom_context->bios + data_offset); 3355 3356 switch (frev) { 3357 case 1: 3358 case 2: 3359 switch (crev) { 3360 case 1: 3361 voltage_object = (union voltage_object *) 3362 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3363 if (voltage_object && 3364 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO)) 3365 return true; 3366 break; 3367 case 2: 3368 voltage_object = (union voltage_object *) 3369 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3370 if (voltage_object && 3371 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO)) 3372 return true; 3373 break; 3374 default: 3375 DRM_ERROR("unknown voltage object table\n"); 3376 return false; 3377 } 3378 break; 3379 case 3: 3380 switch (crev) { 3381 case 1: 3382 if (atom_lookup_voltage_object_v3(&voltage_info->v3, 3383 voltage_type, voltage_mode)) 3384 return true; 3385 break; 3386 default: 3387 DRM_ERROR("unknown voltage object table\n"); 3388 return false; 3389 } 3390 break; 3391 default: 3392 DRM_ERROR("unknown voltage object table\n"); 3393 return false; 3394 } 3395 3396 } 3397 return false; 3398 } 3399 3400 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 3401 u8 voltage_type, u16 *max_voltage) 3402 { 3403 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3404 u8 frev, crev; 3405 u16 data_offset, size; 3406 union voltage_object_info *voltage_info; 3407 union voltage_object *voltage_object = NULL; 3408 3409 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3410 &frev, &crev, &data_offset)) { 3411 voltage_info = (union voltage_object_info *) 3412 (rdev->mode_info.atom_context->bios + data_offset); 3413 3414 switch (crev) { 3415 case 1: 3416 voltage_object = (union voltage_object *) 3417 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3418 if (voltage_object) { 3419 ATOM_VOLTAGE_FORMULA *formula = 3420 &voltage_object->v1.asFormula; 3421 if (formula->ucFlag & 1) 3422 *max_voltage = 3423 le16_to_cpu(formula->usVoltageBaseLevel) + 3424 formula->ucNumOfVoltageEntries / 2 * 3425 le16_to_cpu(formula->usVoltageStep); 3426 else 3427 *max_voltage = 3428 le16_to_cpu(formula->usVoltageBaseLevel) + 3429 (formula->ucNumOfVoltageEntries - 1) * 3430 le16_to_cpu(formula->usVoltageStep); 3431 return 0; 3432 } 3433 break; 3434 case 2: 3435 voltage_object = (union voltage_object *) 3436 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3437 if (voltage_object) { 3438 ATOM_VOLTAGE_FORMULA_V2 *formula = 3439 &voltage_object->v2.asFormula; 3440 if (formula->ucNumOfVoltageEntries) { 3441 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *) 3442 ((u8 *)&formula->asVIDAdjustEntries[0] + 3443 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1))); 3444 *max_voltage = 3445 le16_to_cpu(lut->usVoltageValue); 3446 return 0; 3447 } 3448 } 3449 break; 3450 default: 3451 DRM_ERROR("unknown voltage object table\n"); 3452 return -EINVAL; 3453 } 3454 3455 } 3456 return -EINVAL; 3457 } 3458 3459 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 3460 u8 voltage_type, u16 *min_voltage) 3461 { 3462 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3463 u8 frev, crev; 3464 u16 data_offset, size; 3465 union voltage_object_info *voltage_info; 3466 union voltage_object *voltage_object = NULL; 3467 3468 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3469 &frev, &crev, &data_offset)) { 3470 voltage_info = (union voltage_object_info *) 3471 (rdev->mode_info.atom_context->bios + data_offset); 3472 3473 switch (crev) { 3474 case 1: 3475 voltage_object = (union voltage_object *) 3476 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3477 if (voltage_object) { 3478 ATOM_VOLTAGE_FORMULA *formula = 3479 &voltage_object->v1.asFormula; 3480 *min_voltage = 3481 le16_to_cpu(formula->usVoltageBaseLevel); 3482 return 0; 3483 } 3484 break; 3485 case 2: 3486 voltage_object = (union voltage_object *) 3487 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3488 if (voltage_object) { 3489 ATOM_VOLTAGE_FORMULA_V2 *formula = 3490 &voltage_object->v2.asFormula; 3491 if (formula->ucNumOfVoltageEntries) { 3492 *min_voltage = 3493 le16_to_cpu(formula->asVIDAdjustEntries[ 3494 0 3495 ].usVoltageValue); 3496 return 0; 3497 } 3498 } 3499 break; 3500 default: 3501 DRM_ERROR("unknown voltage object table\n"); 3502 return -EINVAL; 3503 } 3504 3505 } 3506 return -EINVAL; 3507 } 3508 3509 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 3510 u8 voltage_type, u16 *voltage_step) 3511 { 3512 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3513 u8 frev, crev; 3514 u16 data_offset, size; 3515 union voltage_object_info *voltage_info; 3516 union voltage_object *voltage_object = NULL; 3517 3518 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3519 &frev, &crev, &data_offset)) { 3520 voltage_info = (union voltage_object_info *) 3521 (rdev->mode_info.atom_context->bios + data_offset); 3522 3523 switch (crev) { 3524 case 1: 3525 voltage_object = (union voltage_object *) 3526 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3527 if (voltage_object) { 3528 ATOM_VOLTAGE_FORMULA *formula = 3529 &voltage_object->v1.asFormula; 3530 if (formula->ucFlag & 1) 3531 *voltage_step = 3532 (le16_to_cpu(formula->usVoltageStep) + 1) / 2; 3533 else 3534 *voltage_step = 3535 le16_to_cpu(formula->usVoltageStep); 3536 return 0; 3537 } 3538 break; 3539 case 2: 3540 return -EINVAL; 3541 default: 3542 DRM_ERROR("unknown voltage object table\n"); 3543 return -EINVAL; 3544 } 3545 3546 } 3547 return -EINVAL; 3548 } 3549 3550 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 3551 u8 voltage_type, 3552 u16 nominal_voltage, 3553 u16 *true_voltage) 3554 { 3555 u16 min_voltage, max_voltage, voltage_step; 3556 3557 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage)) 3558 return -EINVAL; 3559 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage)) 3560 return -EINVAL; 3561 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step)) 3562 return -EINVAL; 3563 3564 if (nominal_voltage <= min_voltage) 3565 *true_voltage = min_voltage; 3566 else if (nominal_voltage >= max_voltage) 3567 *true_voltage = max_voltage; 3568 else 3569 *true_voltage = min_voltage + 3570 ((nominal_voltage - min_voltage) / voltage_step) * 3571 voltage_step; 3572 3573 return 0; 3574 } 3575 3576 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 3577 u8 voltage_type, u8 voltage_mode, 3578 struct atom_voltage_table *voltage_table) 3579 { 3580 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3581 u8 frev, crev; 3582 u16 data_offset, size; 3583 int i, ret; 3584 union voltage_object_info *voltage_info; 3585 union voltage_object *voltage_object = NULL; 3586 3587 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3588 &frev, &crev, &data_offset)) { 3589 voltage_info = (union voltage_object_info *) 3590 (rdev->mode_info.atom_context->bios + data_offset); 3591 3592 switch (frev) { 3593 case 1: 3594 case 2: 3595 switch (crev) { 3596 case 1: 3597 DRM_ERROR("old table version %d, %d\n", frev, crev); 3598 return -EINVAL; 3599 case 2: 3600 voltage_object = (union voltage_object *) 3601 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3602 if (voltage_object) { 3603 ATOM_VOLTAGE_FORMULA_V2 *formula = 3604 &voltage_object->v2.asFormula; 3605 VOLTAGE_LUT_ENTRY *lut; 3606 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES) 3607 return -EINVAL; 3608 lut = &formula->asVIDAdjustEntries[0]; 3609 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) { 3610 voltage_table->entries[i].value = 3611 le16_to_cpu(lut->usVoltageValue); 3612 ret = radeon_atom_get_voltage_gpio_settings(rdev, 3613 voltage_table->entries[i].value, 3614 voltage_type, 3615 &voltage_table->entries[i].smio_low, 3616 &voltage_table->mask_low); 3617 if (ret) 3618 return ret; 3619 lut = (VOLTAGE_LUT_ENTRY *) 3620 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY)); 3621 } 3622 voltage_table->count = formula->ucNumOfVoltageEntries; 3623 return 0; 3624 } 3625 break; 3626 default: 3627 DRM_ERROR("unknown voltage object table\n"); 3628 return -EINVAL; 3629 } 3630 break; 3631 case 3: 3632 switch (crev) { 3633 case 1: 3634 voltage_object = (union voltage_object *) 3635 atom_lookup_voltage_object_v3(&voltage_info->v3, 3636 voltage_type, voltage_mode); 3637 if (voltage_object) { 3638 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio = 3639 &voltage_object->v3.asGpioVoltageObj; 3640 VOLTAGE_LUT_ENTRY_V2 *lut; 3641 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES) 3642 return -EINVAL; 3643 lut = &gpio->asVolGpioLut[0]; 3644 for (i = 0; i < gpio->ucGpioEntryNum; i++) { 3645 voltage_table->entries[i].value = 3646 le16_to_cpu(lut->usVoltageValue); 3647 voltage_table->entries[i].smio_low = 3648 le32_to_cpu(lut->ulVoltageId); 3649 lut = (VOLTAGE_LUT_ENTRY_V2 *) 3650 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2)); 3651 } 3652 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal); 3653 voltage_table->count = gpio->ucGpioEntryNum; 3654 voltage_table->phase_delay = gpio->ucPhaseDelay; 3655 return 0; 3656 } 3657 break; 3658 default: 3659 DRM_ERROR("unknown voltage object table\n"); 3660 return -EINVAL; 3661 } 3662 break; 3663 default: 3664 DRM_ERROR("unknown voltage object table\n"); 3665 return -EINVAL; 3666 } 3667 } 3668 return -EINVAL; 3669 } 3670 3671 union vram_info { 3672 struct _ATOM_VRAM_INFO_V3 v1_3; 3673 struct _ATOM_VRAM_INFO_V4 v1_4; 3674 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; 3675 }; 3676 3677 int radeon_atom_get_memory_info(struct radeon_device *rdev, 3678 u8 module_index, struct atom_memory_info *mem_info) 3679 { 3680 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3681 u8 frev, crev, i; 3682 u16 data_offset, size; 3683 union vram_info *vram_info; 3684 3685 memset(mem_info, 0, sizeof(struct atom_memory_info)); 3686 3687 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3688 &frev, &crev, &data_offset)) { 3689 vram_info = (union vram_info *) 3690 (rdev->mode_info.atom_context->bios + data_offset); 3691 switch (frev) { 3692 case 1: 3693 switch (crev) { 3694 case 3: 3695 /* r6xx */ 3696 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) { 3697 ATOM_VRAM_MODULE_V3 *vram_module = 3698 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo; 3699 3700 for (i = 0; i < module_index; i++) { 3701 if (le16_to_cpu(vram_module->usSize) == 0) 3702 return -EINVAL; 3703 vram_module = (ATOM_VRAM_MODULE_V3 *) 3704 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize)); 3705 } 3706 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf; 3707 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0; 3708 } else 3709 return -EINVAL; 3710 break; 3711 case 4: 3712 /* r7xx, evergreen */ 3713 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) { 3714 ATOM_VRAM_MODULE_V4 *vram_module = 3715 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo; 3716 3717 for (i = 0; i < module_index; i++) { 3718 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3719 return -EINVAL; 3720 vram_module = (ATOM_VRAM_MODULE_V4 *) 3721 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3722 } 3723 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf; 3724 mem_info->mem_type = vram_module->ucMemoryType & 0xf0; 3725 } else 3726 return -EINVAL; 3727 break; 3728 default: 3729 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3730 return -EINVAL; 3731 } 3732 break; 3733 case 2: 3734 switch (crev) { 3735 case 1: 3736 /* ni */ 3737 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { 3738 ATOM_VRAM_MODULE_V7 *vram_module = 3739 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo; 3740 3741 for (i = 0; i < module_index; i++) { 3742 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3743 return -EINVAL; 3744 vram_module = (ATOM_VRAM_MODULE_V7 *) 3745 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3746 } 3747 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf; 3748 mem_info->mem_type = vram_module->ucMemoryType & 0xf0; 3749 } else 3750 return -EINVAL; 3751 break; 3752 default: 3753 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3754 return -EINVAL; 3755 } 3756 break; 3757 default: 3758 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3759 return -EINVAL; 3760 } 3761 return 0; 3762 } 3763 return -EINVAL; 3764 } 3765 3766 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 3767 bool gddr5, u8 module_index, 3768 struct atom_memory_clock_range_table *mclk_range_table) 3769 { 3770 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3771 u8 frev, crev, i; 3772 u16 data_offset, size; 3773 union vram_info *vram_info; 3774 u32 mem_timing_size = gddr5 ? 3775 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT); 3776 3777 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table)); 3778 3779 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3780 &frev, &crev, &data_offset)) { 3781 vram_info = (union vram_info *) 3782 (rdev->mode_info.atom_context->bios + data_offset); 3783 switch (frev) { 3784 case 1: 3785 switch (crev) { 3786 case 3: 3787 DRM_ERROR("old table version %d, %d\n", frev, crev); 3788 return -EINVAL; 3789 case 4: 3790 /* r7xx, evergreen */ 3791 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) { 3792 ATOM_VRAM_MODULE_V4 *vram_module = 3793 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo; 3794 ATOM_MEMORY_TIMING_FORMAT *format; 3795 3796 for (i = 0; i < module_index; i++) { 3797 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3798 return -EINVAL; 3799 vram_module = (ATOM_VRAM_MODULE_V4 *) 3800 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3801 } 3802 mclk_range_table->num_entries = (u8) 3803 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) / 3804 mem_timing_size); 3805 format = &vram_module->asMemTiming[0]; 3806 for (i = 0; i < mclk_range_table->num_entries; i++) { 3807 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange); 3808 format = (ATOM_MEMORY_TIMING_FORMAT *) 3809 ((u8 *)format + mem_timing_size); 3810 } 3811 } else 3812 return -EINVAL; 3813 break; 3814 default: 3815 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3816 return -EINVAL; 3817 } 3818 break; 3819 case 2: 3820 DRM_ERROR("new table version %d, %d\n", frev, crev); 3821 return -EINVAL; 3822 default: 3823 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3824 return -EINVAL; 3825 } 3826 return 0; 3827 } 3828 return -EINVAL; 3829 } 3830 3831 #define MEM_ID_MASK 0xff000000 3832 #define MEM_ID_SHIFT 24 3833 #define CLOCK_RANGE_MASK 0x00ffffff 3834 #define CLOCK_RANGE_SHIFT 0 3835 #define LOW_NIBBLE_MASK 0xf 3836 #define DATA_EQU_PREV 0 3837 #define DATA_FROM_TABLE 4 3838 3839 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 3840 u8 module_index, 3841 struct atom_mc_reg_table *reg_table) 3842 { 3843 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3844 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0; 3845 u32 i = 0, j; 3846 u16 data_offset, size; 3847 union vram_info *vram_info; 3848 3849 memset(reg_table, 0, sizeof(struct atom_mc_reg_table)); 3850 3851 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3852 &frev, &crev, &data_offset)) { 3853 vram_info = (union vram_info *) 3854 (rdev->mode_info.atom_context->bios + data_offset); 3855 switch (frev) { 3856 case 1: 3857 DRM_ERROR("old table version %d, %d\n", frev, crev); 3858 return -EINVAL; 3859 case 2: 3860 switch (crev) { 3861 case 1: 3862 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { 3863 ATOM_INIT_REG_BLOCK *reg_block = 3864 (ATOM_INIT_REG_BLOCK *) 3865 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); 3866 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = 3867 (ATOM_MEMORY_SETTING_DATA_BLOCK *) 3868 ((u8 *)reg_block + (2 * sizeof(u16)) + 3869 le16_to_cpu(reg_block->usRegIndexTblSize)); 3870 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0]; 3871 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) / 3872 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1; 3873 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE) 3874 return -EINVAL; 3875 while (i < num_entries) { 3876 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER) 3877 break; 3878 reg_table->mc_reg_address[i].s1 = 3879 (u16)(le16_to_cpu(format->usRegIndex)); 3880 reg_table->mc_reg_address[i].pre_reg_data = 3881 (u8)(format->ucPreRegDataLength); 3882 i++; 3883 format = (ATOM_INIT_REG_INDEX_FORMAT *) 3884 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT)); 3885 } 3886 reg_table->last = i; 3887 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && 3888 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) { 3889 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) 3890 >> MEM_ID_SHIFT); 3891 if (module_index == t_mem_id) { 3892 reg_table->mc_reg_table_entry[num_ranges].mclk_max = 3893 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) 3894 >> CLOCK_RANGE_SHIFT); 3895 for (i = 0, j = 1; i < reg_table->last; i++) { 3896 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { 3897 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 3898 (u32)le32_to_cpu(*((u32 *)reg_data + j)); 3899 j++; 3900 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { 3901 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 3902 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1]; 3903 } 3904 } 3905 num_ranges++; 3906 } 3907 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) 3908 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); 3909 } 3910 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) 3911 return -EINVAL; 3912 reg_table->num_entries = num_ranges; 3913 } else 3914 return -EINVAL; 3915 break; 3916 default: 3917 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3918 return -EINVAL; 3919 } 3920 break; 3921 default: 3922 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3923 return -EINVAL; 3924 } 3925 return 0; 3926 } 3927 return -EINVAL; 3928 } 3929 3930 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) 3931 { 3932 struct radeon_device *rdev = dev->dev_private; 3933 uint32_t bios_2_scratch, bios_6_scratch; 3934 3935 if (rdev->family >= CHIP_R600) { 3936 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 3937 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 3938 } else { 3939 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 3940 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3941 } 3942 3943 /* let the bios control the backlight */ 3944 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; 3945 3946 /* tell the bios not to handle mode switching */ 3947 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; 3948 3949 /* clear the vbios dpms state */ 3950 if (ASIC_IS_DCE4(rdev)) 3951 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE; 3952 3953 if (rdev->family >= CHIP_R600) { 3954 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 3955 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 3956 } else { 3957 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 3958 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3959 } 3960 3961 } 3962 3963 void radeon_save_bios_scratch_regs(struct radeon_device *rdev) 3964 { 3965 uint32_t scratch_reg; 3966 int i; 3967 3968 if (rdev->family >= CHIP_R600) 3969 scratch_reg = R600_BIOS_0_SCRATCH; 3970 else 3971 scratch_reg = RADEON_BIOS_0_SCRATCH; 3972 3973 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) 3974 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4)); 3975 } 3976 3977 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev) 3978 { 3979 uint32_t scratch_reg; 3980 int i; 3981 3982 if (rdev->family >= CHIP_R600) 3983 scratch_reg = R600_BIOS_0_SCRATCH; 3984 else 3985 scratch_reg = RADEON_BIOS_0_SCRATCH; 3986 3987 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) 3988 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]); 3989 } 3990 3991 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) 3992 { 3993 struct drm_device *dev = encoder->dev; 3994 struct radeon_device *rdev = dev->dev_private; 3995 uint32_t bios_6_scratch; 3996 3997 if (rdev->family >= CHIP_R600) 3998 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 3999 else 4000 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 4001 4002 if (lock) { 4003 bios_6_scratch |= ATOM_S6_CRITICAL_STATE; 4004 bios_6_scratch &= ~ATOM_S6_ACC_MODE; 4005 } else { 4006 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; 4007 bios_6_scratch |= ATOM_S6_ACC_MODE; 4008 } 4009 4010 if (rdev->family >= CHIP_R600) 4011 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 4012 else 4013 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 4014 } 4015 4016 /* at some point we may want to break this out into individual functions */ 4017 void 4018 radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 4019 struct drm_encoder *encoder, 4020 bool connected) 4021 { 4022 struct drm_device *dev = connector->dev; 4023 struct radeon_device *rdev = dev->dev_private; 4024 struct radeon_connector *radeon_connector = 4025 to_radeon_connector(connector); 4026 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4027 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch; 4028 4029 if (rdev->family >= CHIP_R600) { 4030 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 4031 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 4032 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 4033 } else { 4034 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 4035 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 4036 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 4037 } 4038 4039 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 4040 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 4041 if (connected) { 4042 DRM_DEBUG_KMS("TV1 connected\n"); 4043 bios_3_scratch |= ATOM_S3_TV1_ACTIVE; 4044 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1; 4045 } else { 4046 DRM_DEBUG_KMS("TV1 disconnected\n"); 4047 bios_0_scratch &= ~ATOM_S0_TV1_MASK; 4048 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; 4049 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1; 4050 } 4051 } 4052 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) && 4053 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) { 4054 if (connected) { 4055 DRM_DEBUG_KMS("CV connected\n"); 4056 bios_3_scratch |= ATOM_S3_CV_ACTIVE; 4057 bios_6_scratch |= ATOM_S6_ACC_REQ_CV; 4058 } else { 4059 DRM_DEBUG_KMS("CV disconnected\n"); 4060 bios_0_scratch &= ~ATOM_S0_CV_MASK; 4061 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; 4062 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV; 4063 } 4064 } 4065 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 4066 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 4067 if (connected) { 4068 DRM_DEBUG_KMS("LCD1 connected\n"); 4069 bios_0_scratch |= ATOM_S0_LCD1; 4070 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; 4071 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; 4072 } else { 4073 DRM_DEBUG_KMS("LCD1 disconnected\n"); 4074 bios_0_scratch &= ~ATOM_S0_LCD1; 4075 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; 4076 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; 4077 } 4078 } 4079 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 4080 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 4081 if (connected) { 4082 DRM_DEBUG_KMS("CRT1 connected\n"); 4083 bios_0_scratch |= ATOM_S0_CRT1_COLOR; 4084 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; 4085 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; 4086 } else { 4087 DRM_DEBUG_KMS("CRT1 disconnected\n"); 4088 bios_0_scratch &= ~ATOM_S0_CRT1_MASK; 4089 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; 4090 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; 4091 } 4092 } 4093 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 4094 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 4095 if (connected) { 4096 DRM_DEBUG_KMS("CRT2 connected\n"); 4097 bios_0_scratch |= ATOM_S0_CRT2_COLOR; 4098 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; 4099 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; 4100 } else { 4101 DRM_DEBUG_KMS("CRT2 disconnected\n"); 4102 bios_0_scratch &= ~ATOM_S0_CRT2_MASK; 4103 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; 4104 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; 4105 } 4106 } 4107 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 4108 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 4109 if (connected) { 4110 DRM_DEBUG_KMS("DFP1 connected\n"); 4111 bios_0_scratch |= ATOM_S0_DFP1; 4112 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; 4113 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; 4114 } else { 4115 DRM_DEBUG_KMS("DFP1 disconnected\n"); 4116 bios_0_scratch &= ~ATOM_S0_DFP1; 4117 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; 4118 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; 4119 } 4120 } 4121 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 4122 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 4123 if (connected) { 4124 DRM_DEBUG_KMS("DFP2 connected\n"); 4125 bios_0_scratch |= ATOM_S0_DFP2; 4126 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; 4127 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; 4128 } else { 4129 DRM_DEBUG_KMS("DFP2 disconnected\n"); 4130 bios_0_scratch &= ~ATOM_S0_DFP2; 4131 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; 4132 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; 4133 } 4134 } 4135 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && 4136 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { 4137 if (connected) { 4138 DRM_DEBUG_KMS("DFP3 connected\n"); 4139 bios_0_scratch |= ATOM_S0_DFP3; 4140 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; 4141 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; 4142 } else { 4143 DRM_DEBUG_KMS("DFP3 disconnected\n"); 4144 bios_0_scratch &= ~ATOM_S0_DFP3; 4145 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; 4146 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; 4147 } 4148 } 4149 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && 4150 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { 4151 if (connected) { 4152 DRM_DEBUG_KMS("DFP4 connected\n"); 4153 bios_0_scratch |= ATOM_S0_DFP4; 4154 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; 4155 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; 4156 } else { 4157 DRM_DEBUG_KMS("DFP4 disconnected\n"); 4158 bios_0_scratch &= ~ATOM_S0_DFP4; 4159 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; 4160 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; 4161 } 4162 } 4163 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && 4164 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { 4165 if (connected) { 4166 DRM_DEBUG_KMS("DFP5 connected\n"); 4167 bios_0_scratch |= ATOM_S0_DFP5; 4168 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; 4169 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; 4170 } else { 4171 DRM_DEBUG_KMS("DFP5 disconnected\n"); 4172 bios_0_scratch &= ~ATOM_S0_DFP5; 4173 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; 4174 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; 4175 } 4176 } 4177 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) && 4178 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) { 4179 if (connected) { 4180 DRM_DEBUG_KMS("DFP6 connected\n"); 4181 bios_0_scratch |= ATOM_S0_DFP6; 4182 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE; 4183 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6; 4184 } else { 4185 DRM_DEBUG_KMS("DFP6 disconnected\n"); 4186 bios_0_scratch &= ~ATOM_S0_DFP6; 4187 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE; 4188 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6; 4189 } 4190 } 4191 4192 if (rdev->family >= CHIP_R600) { 4193 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); 4194 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 4195 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 4196 } else { 4197 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 4198 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 4199 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 4200 } 4201 } 4202 4203 void 4204 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 4205 { 4206 struct drm_device *dev = encoder->dev; 4207 struct radeon_device *rdev = dev->dev_private; 4208 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4209 uint32_t bios_3_scratch; 4210 4211 if (ASIC_IS_DCE4(rdev)) 4212 return; 4213 4214 if (rdev->family >= CHIP_R600) 4215 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 4216 else 4217 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 4218 4219 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 4220 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE; 4221 bios_3_scratch |= (crtc << 18); 4222 } 4223 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 4224 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE; 4225 bios_3_scratch |= (crtc << 24); 4226 } 4227 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 4228 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE; 4229 bios_3_scratch |= (crtc << 16); 4230 } 4231 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 4232 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE; 4233 bios_3_scratch |= (crtc << 20); 4234 } 4235 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 4236 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE; 4237 bios_3_scratch |= (crtc << 17); 4238 } 4239 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 4240 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE; 4241 bios_3_scratch |= (crtc << 19); 4242 } 4243 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 4244 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE; 4245 bios_3_scratch |= (crtc << 23); 4246 } 4247 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 4248 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE; 4249 bios_3_scratch |= (crtc << 25); 4250 } 4251 4252 if (rdev->family >= CHIP_R600) 4253 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 4254 else 4255 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 4256 } 4257 4258 void 4259 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 4260 { 4261 struct drm_device *dev = encoder->dev; 4262 struct radeon_device *rdev = dev->dev_private; 4263 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4264 uint32_t bios_2_scratch; 4265 4266 if (ASIC_IS_DCE4(rdev)) 4267 return; 4268 4269 if (rdev->family >= CHIP_R600) 4270 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 4271 else 4272 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 4273 4274 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 4275 if (on) 4276 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE; 4277 else 4278 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE; 4279 } 4280 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 4281 if (on) 4282 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE; 4283 else 4284 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE; 4285 } 4286 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 4287 if (on) 4288 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE; 4289 else 4290 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE; 4291 } 4292 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 4293 if (on) 4294 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE; 4295 else 4296 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE; 4297 } 4298 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 4299 if (on) 4300 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE; 4301 else 4302 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE; 4303 } 4304 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 4305 if (on) 4306 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE; 4307 else 4308 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE; 4309 } 4310 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 4311 if (on) 4312 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE; 4313 else 4314 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE; 4315 } 4316 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 4317 if (on) 4318 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE; 4319 else 4320 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE; 4321 } 4322 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) { 4323 if (on) 4324 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE; 4325 else 4326 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE; 4327 } 4328 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) { 4329 if (on) 4330 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE; 4331 else 4332 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE; 4333 } 4334 4335 if (rdev->family >= CHIP_R600) 4336 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 4337 else 4338 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 4339 } 4340