1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <linux/pci.h> 28 29 #include <drm/drm_device.h> 30 #include <drm/radeon_drm.h> 31 32 #include "radeon.h" 33 34 #include "atom.h" 35 #include "atom-bits.h" 36 #include "radeon_asic.h" 37 #include "radeon_atombios.h" 38 #include "radeon_legacy_encoders.h" 39 40 union atom_supported_devices { 41 struct _ATOM_SUPPORTED_DEVICES_INFO info; 42 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2; 43 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1; 44 }; 45 46 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev, 47 ATOM_GPIO_I2C_ASSIGMENT *gpio, 48 u8 index) 49 { 50 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */ 51 if ((rdev->family == CHIP_R420) || 52 (rdev->family == CHIP_R423) || 53 (rdev->family == CHIP_RV410)) { 54 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) || 55 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) || 56 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) { 57 gpio->ucClkMaskShift = 0x19; 58 gpio->ucDataMaskShift = 0x18; 59 } 60 } 61 62 /* some evergreen boards have bad data for this entry */ 63 if (ASIC_IS_DCE4(rdev)) { 64 if ((index == 7) && 65 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) && 66 (gpio->sucI2cId.ucAccess == 0)) { 67 gpio->sucI2cId.ucAccess = 0x97; 68 gpio->ucDataMaskShift = 8; 69 gpio->ucDataEnShift = 8; 70 gpio->ucDataY_Shift = 8; 71 gpio->ucDataA_Shift = 8; 72 } 73 } 74 75 /* some DCE3 boards have bad data for this entry */ 76 if (ASIC_IS_DCE3(rdev)) { 77 if ((index == 4) && 78 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) && 79 (gpio->sucI2cId.ucAccess == 0x94)) 80 gpio->sucI2cId.ucAccess = 0x14; 81 } 82 } 83 84 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio) 85 { 86 struct radeon_i2c_bus_rec i2c; 87 88 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 89 90 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; 91 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; 92 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4; 93 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4; 94 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4; 95 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4; 96 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4; 97 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4; 98 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); 99 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); 100 i2c.en_clk_mask = (1 << gpio->ucClkEnShift); 101 i2c.en_data_mask = (1 << gpio->ucDataEnShift); 102 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); 103 i2c.y_data_mask = (1 << gpio->ucDataY_Shift); 104 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); 105 i2c.a_data_mask = (1 << gpio->ucDataA_Shift); 106 107 if (gpio->sucI2cId.sbfAccess.bfHW_Capable) 108 i2c.hw_capable = true; 109 else 110 i2c.hw_capable = false; 111 112 if (gpio->sucI2cId.ucAccess == 0xa0) 113 i2c.mm_i2c = true; 114 else 115 i2c.mm_i2c = false; 116 117 i2c.i2c_id = gpio->sucI2cId.ucAccess; 118 119 if (i2c.mask_clk_reg) 120 i2c.valid = true; 121 else 122 i2c.valid = false; 123 124 return i2c; 125 } 126 127 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev, 128 uint8_t id) 129 { 130 struct atom_context *ctx = rdev->mode_info.atom_context; 131 ATOM_GPIO_I2C_ASSIGMENT *gpio; 132 struct radeon_i2c_bus_rec i2c; 133 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 134 struct _ATOM_GPIO_I2C_INFO *i2c_info; 135 uint16_t data_offset, size; 136 int i, num_indices; 137 138 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 139 i2c.valid = false; 140 141 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 142 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 143 144 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 145 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 146 147 gpio = &i2c_info->asGPIO_Info[0]; 148 for (i = 0; i < num_indices; i++) { 149 150 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); 151 152 if (gpio->sucI2cId.ucAccess == id) { 153 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); 154 break; 155 } 156 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 157 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 158 } 159 } 160 161 return i2c; 162 } 163 164 void radeon_atombios_i2c_init(struct radeon_device *rdev) 165 { 166 struct atom_context *ctx = rdev->mode_info.atom_context; 167 ATOM_GPIO_I2C_ASSIGMENT *gpio; 168 struct radeon_i2c_bus_rec i2c; 169 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 170 struct _ATOM_GPIO_I2C_INFO *i2c_info; 171 uint16_t data_offset, size; 172 int i, num_indices; 173 char stmp[32]; 174 175 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 176 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 177 178 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 179 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 180 181 gpio = &i2c_info->asGPIO_Info[0]; 182 for (i = 0; i < num_indices; i++) { 183 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); 184 185 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); 186 187 if (i2c.valid) { 188 sprintf(stmp, "0x%x", i2c.i2c_id); 189 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp); 190 } 191 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 192 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 193 } 194 } 195 } 196 197 struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev, 198 u8 id) 199 { 200 struct atom_context *ctx = rdev->mode_info.atom_context; 201 struct radeon_gpio_rec gpio; 202 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); 203 struct _ATOM_GPIO_PIN_LUT *gpio_info; 204 ATOM_GPIO_PIN_ASSIGNMENT *pin; 205 u16 data_offset, size; 206 int i, num_indices; 207 208 memset(&gpio, 0, sizeof(struct radeon_gpio_rec)); 209 gpio.valid = false; 210 211 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 212 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset); 213 214 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 215 sizeof(ATOM_GPIO_PIN_ASSIGNMENT); 216 217 pin = gpio_info->asGPIO_Pin; 218 for (i = 0; i < num_indices; i++) { 219 if (id == pin->ucGPIO_ID) { 220 gpio.id = pin->ucGPIO_ID; 221 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4; 222 gpio.shift = pin->ucGpioPinBitShift; 223 gpio.mask = (1 << pin->ucGpioPinBitShift); 224 gpio.valid = true; 225 break; 226 } 227 pin = (ATOM_GPIO_PIN_ASSIGNMENT *) 228 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT)); 229 } 230 } 231 232 return gpio; 233 } 234 235 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev, 236 struct radeon_gpio_rec *gpio) 237 { 238 struct radeon_hpd hpd; 239 u32 reg; 240 241 memset(&hpd, 0, sizeof(struct radeon_hpd)); 242 243 if (ASIC_IS_DCE6(rdev)) 244 reg = SI_DC_GPIO_HPD_A; 245 else if (ASIC_IS_DCE4(rdev)) 246 reg = EVERGREEN_DC_GPIO_HPD_A; 247 else 248 reg = AVIVO_DC_GPIO_HPD_A; 249 250 hpd.gpio = *gpio; 251 if (gpio->reg == reg) { 252 switch(gpio->mask) { 253 case (1 << 0): 254 hpd.hpd = RADEON_HPD_1; 255 break; 256 case (1 << 8): 257 hpd.hpd = RADEON_HPD_2; 258 break; 259 case (1 << 16): 260 hpd.hpd = RADEON_HPD_3; 261 break; 262 case (1 << 24): 263 hpd.hpd = RADEON_HPD_4; 264 break; 265 case (1 << 26): 266 hpd.hpd = RADEON_HPD_5; 267 break; 268 case (1 << 28): 269 hpd.hpd = RADEON_HPD_6; 270 break; 271 default: 272 hpd.hpd = RADEON_HPD_NONE; 273 break; 274 } 275 } else 276 hpd.hpd = RADEON_HPD_NONE; 277 return hpd; 278 } 279 280 static bool radeon_atom_apply_quirks(struct drm_device *dev, 281 uint32_t supported_device, 282 int *connector_type, 283 struct radeon_i2c_bus_rec *i2c_bus, 284 uint16_t *line_mux, 285 struct radeon_hpd *hpd) 286 { 287 struct pci_dev *pdev = to_pci_dev(dev->dev); 288 289 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ 290 if ((pdev->device == 0x791e) && 291 (pdev->subsystem_vendor == 0x1043) && 292 (pdev->subsystem_device == 0x826d)) { 293 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && 294 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 295 *connector_type = DRM_MODE_CONNECTOR_DVID; 296 } 297 298 /* Asrock RS600 board lists the DVI port as HDMI */ 299 if ((pdev->device == 0x7941) && 300 (pdev->subsystem_vendor == 0x1849) && 301 (pdev->subsystem_device == 0x7941)) { 302 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && 303 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 304 *connector_type = DRM_MODE_CONNECTOR_DVID; 305 } 306 307 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */ 308 if ((pdev->device == 0x796e) && 309 (pdev->subsystem_vendor == 0x1462) && 310 (pdev->subsystem_device == 0x7302)) { 311 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) || 312 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 313 return false; 314 } 315 316 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */ 317 if ((pdev->device == 0x7941) && 318 (pdev->subsystem_vendor == 0x147b) && 319 (pdev->subsystem_device == 0x2412)) { 320 if (*connector_type == DRM_MODE_CONNECTOR_DVII) 321 return false; 322 } 323 324 /* Falcon NW laptop lists vga ddc line for LVDS */ 325 if ((pdev->device == 0x5653) && 326 (pdev->subsystem_vendor == 0x1462) && 327 (pdev->subsystem_device == 0x0291)) { 328 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) { 329 i2c_bus->valid = false; 330 *line_mux = 53; 331 } 332 } 333 334 /* HIS X1300 is DVI+VGA, not DVI+DVI */ 335 if ((pdev->device == 0x7146) && 336 (pdev->subsystem_vendor == 0x17af) && 337 (pdev->subsystem_device == 0x2058)) { 338 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) 339 return false; 340 } 341 342 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */ 343 if ((pdev->device == 0x7142) && 344 (pdev->subsystem_vendor == 0x1458) && 345 (pdev->subsystem_device == 0x2134)) { 346 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) 347 return false; 348 } 349 350 351 /* Funky macbooks */ 352 if ((pdev->device == 0x71C5) && 353 (pdev->subsystem_vendor == 0x106b) && 354 (pdev->subsystem_device == 0x0080)) { 355 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) || 356 (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) 357 return false; 358 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT) 359 *line_mux = 0x90; 360 } 361 362 /* mac rv630, rv730, others */ 363 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) && 364 (*connector_type == DRM_MODE_CONNECTOR_DVII)) { 365 *connector_type = DRM_MODE_CONNECTOR_9PinDIN; 366 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1; 367 } 368 369 /* ASUS HD 3600 XT board lists the DVI port as HDMI */ 370 if ((pdev->device == 0x9598) && 371 (pdev->subsystem_vendor == 0x1043) && 372 (pdev->subsystem_device == 0x01da)) { 373 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 374 *connector_type = DRM_MODE_CONNECTOR_DVII; 375 } 376 } 377 378 /* ASUS HD 3600 board lists the DVI port as HDMI */ 379 if ((pdev->device == 0x9598) && 380 (pdev->subsystem_vendor == 0x1043) && 381 (pdev->subsystem_device == 0x01e4)) { 382 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 383 *connector_type = DRM_MODE_CONNECTOR_DVII; 384 } 385 } 386 387 /* ASUS HD 3450 board lists the DVI port as HDMI */ 388 if ((pdev->device == 0x95C5) && 389 (pdev->subsystem_vendor == 0x1043) && 390 (pdev->subsystem_device == 0x01e2)) { 391 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 392 *connector_type = DRM_MODE_CONNECTOR_DVII; 393 } 394 } 395 396 /* some BIOSes seem to report DAC on HDMI - usually this is a board with 397 * HDMI + VGA reporting as HDMI 398 */ 399 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 400 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { 401 *connector_type = DRM_MODE_CONNECTOR_VGA; 402 *line_mux = 0; 403 } 404 } 405 406 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port 407 * on the laptop and a DVI port on the docking station and 408 * both share the same encoder, hpd pin, and ddc line. 409 * So while the bios table is technically correct, 410 * we drop the DVI port here since xrandr has no concept of 411 * encoders and will try and drive both connectors 412 * with different crtcs which isn't possible on the hardware 413 * side and leaves no crtcs for LVDS or VGA. 414 */ 415 if (((pdev->device == 0x95c4) || (pdev->device == 0x9591)) && 416 (pdev->subsystem_vendor == 0x1025) && 417 (pdev->subsystem_device == 0x013c)) { 418 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) && 419 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) { 420 /* actually it's a DVI-D port not DVI-I */ 421 *connector_type = DRM_MODE_CONNECTOR_DVID; 422 return false; 423 } 424 } 425 426 /* XFX Pine Group device rv730 reports no VGA DDC lines 427 * even though they are wired up to record 0x93 428 */ 429 if ((pdev->device == 0x9498) && 430 (pdev->subsystem_vendor == 0x1682) && 431 (pdev->subsystem_device == 0x2452) && 432 (i2c_bus->valid == false) && 433 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) { 434 struct radeon_device *rdev = dev->dev_private; 435 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93); 436 } 437 438 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */ 439 if (((pdev->device == 0x9802) || 440 (pdev->device == 0x9805) || 441 (pdev->device == 0x9806)) && 442 (pdev->subsystem_vendor == 0x1734) && 443 (pdev->subsystem_device == 0x11bd)) { 444 if (*connector_type == DRM_MODE_CONNECTOR_VGA) { 445 *connector_type = DRM_MODE_CONNECTOR_DVII; 446 *line_mux = 0x3103; 447 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) { 448 *connector_type = DRM_MODE_CONNECTOR_DVII; 449 } 450 } 451 452 return true; 453 } 454 455 static const int supported_devices_connector_convert[] = { 456 DRM_MODE_CONNECTOR_Unknown, 457 DRM_MODE_CONNECTOR_VGA, 458 DRM_MODE_CONNECTOR_DVII, 459 DRM_MODE_CONNECTOR_DVID, 460 DRM_MODE_CONNECTOR_DVIA, 461 DRM_MODE_CONNECTOR_SVIDEO, 462 DRM_MODE_CONNECTOR_Composite, 463 DRM_MODE_CONNECTOR_LVDS, 464 DRM_MODE_CONNECTOR_Unknown, 465 DRM_MODE_CONNECTOR_Unknown, 466 DRM_MODE_CONNECTOR_HDMIA, 467 DRM_MODE_CONNECTOR_HDMIB, 468 DRM_MODE_CONNECTOR_Unknown, 469 DRM_MODE_CONNECTOR_Unknown, 470 DRM_MODE_CONNECTOR_9PinDIN, 471 DRM_MODE_CONNECTOR_DisplayPort 472 }; 473 474 static const uint16_t supported_devices_connector_object_id_convert[] = { 475 CONNECTOR_OBJECT_ID_NONE, 476 CONNECTOR_OBJECT_ID_VGA, 477 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */ 478 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */ 479 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */ 480 CONNECTOR_OBJECT_ID_COMPOSITE, 481 CONNECTOR_OBJECT_ID_SVIDEO, 482 CONNECTOR_OBJECT_ID_LVDS, 483 CONNECTOR_OBJECT_ID_9PIN_DIN, 484 CONNECTOR_OBJECT_ID_9PIN_DIN, 485 CONNECTOR_OBJECT_ID_DISPLAYPORT, 486 CONNECTOR_OBJECT_ID_HDMI_TYPE_A, 487 CONNECTOR_OBJECT_ID_HDMI_TYPE_B, 488 CONNECTOR_OBJECT_ID_SVIDEO 489 }; 490 491 static const int object_connector_convert[] = { 492 DRM_MODE_CONNECTOR_Unknown, 493 DRM_MODE_CONNECTOR_DVII, 494 DRM_MODE_CONNECTOR_DVII, 495 DRM_MODE_CONNECTOR_DVID, 496 DRM_MODE_CONNECTOR_DVID, 497 DRM_MODE_CONNECTOR_VGA, 498 DRM_MODE_CONNECTOR_Composite, 499 DRM_MODE_CONNECTOR_SVIDEO, 500 DRM_MODE_CONNECTOR_Unknown, 501 DRM_MODE_CONNECTOR_Unknown, 502 DRM_MODE_CONNECTOR_9PinDIN, 503 DRM_MODE_CONNECTOR_Unknown, 504 DRM_MODE_CONNECTOR_HDMIA, 505 DRM_MODE_CONNECTOR_HDMIB, 506 DRM_MODE_CONNECTOR_LVDS, 507 DRM_MODE_CONNECTOR_9PinDIN, 508 DRM_MODE_CONNECTOR_Unknown, 509 DRM_MODE_CONNECTOR_Unknown, 510 DRM_MODE_CONNECTOR_Unknown, 511 DRM_MODE_CONNECTOR_DisplayPort, 512 DRM_MODE_CONNECTOR_eDP, 513 DRM_MODE_CONNECTOR_Unknown 514 }; 515 516 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) 517 { 518 struct radeon_device *rdev = dev->dev_private; 519 struct radeon_mode_info *mode_info = &rdev->mode_info; 520 struct atom_context *ctx = mode_info->atom_context; 521 int index = GetIndexIntoMasterTable(DATA, Object_Header); 522 u16 size, data_offset; 523 u8 frev, crev; 524 ATOM_CONNECTOR_OBJECT_TABLE *con_obj; 525 ATOM_ENCODER_OBJECT_TABLE *enc_obj; 526 ATOM_OBJECT_TABLE *router_obj; 527 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; 528 ATOM_OBJECT_HEADER *obj_header; 529 int i, j, k, path_size, device_support; 530 int connector_type; 531 u16 igp_lane_info, conn_id, connector_object_id; 532 struct radeon_i2c_bus_rec ddc_bus; 533 struct radeon_router router; 534 struct radeon_gpio_rec gpio; 535 struct radeon_hpd hpd; 536 537 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) 538 return false; 539 540 if (crev < 2) 541 return false; 542 543 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); 544 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) 545 (ctx->bios + data_offset + 546 le16_to_cpu(obj_header->usDisplayPathTableOffset)); 547 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) 548 (ctx->bios + data_offset + 549 le16_to_cpu(obj_header->usConnectorObjectTableOffset)); 550 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *) 551 (ctx->bios + data_offset + 552 le16_to_cpu(obj_header->usEncoderObjectTableOffset)); 553 router_obj = (ATOM_OBJECT_TABLE *) 554 (ctx->bios + data_offset + 555 le16_to_cpu(obj_header->usRouterObjectTableOffset)); 556 device_support = le16_to_cpu(obj_header->usDeviceSupport); 557 558 path_size = 0; 559 for (i = 0; i < path_obj->ucNumOfDispPath; i++) { 560 uint8_t *addr = (uint8_t *) path_obj->asDispPath; 561 ATOM_DISPLAY_OBJECT_PATH *path; 562 addr += path_size; 563 path = (ATOM_DISPLAY_OBJECT_PATH *) addr; 564 path_size += le16_to_cpu(path->usSize); 565 566 if (device_support & le16_to_cpu(path->usDeviceTag)) { 567 uint8_t con_obj_id, con_obj_num; 568 569 con_obj_id = 570 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) 571 >> OBJECT_ID_SHIFT; 572 con_obj_num = 573 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) 574 >> ENUM_ID_SHIFT; 575 576 /* TODO CV support */ 577 if (le16_to_cpu(path->usDeviceTag) == 578 ATOM_DEVICE_CV_SUPPORT) 579 continue; 580 581 /* IGP chips */ 582 if ((rdev->flags & RADEON_IS_IGP) && 583 (con_obj_id == 584 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { 585 uint16_t igp_offset = 0; 586 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj; 587 588 index = 589 GetIndexIntoMasterTable(DATA, 590 IntegratedSystemInfo); 591 592 if (atom_parse_data_header(ctx, index, &size, &frev, 593 &crev, &igp_offset)) { 594 595 if (crev >= 2) { 596 igp_obj = 597 (ATOM_INTEGRATED_SYSTEM_INFO_V2 598 *) (ctx->bios + igp_offset); 599 600 if (igp_obj) { 601 uint32_t slot_config, ct; 602 603 if (con_obj_num == 1) 604 slot_config = 605 igp_obj-> 606 ulDDISlot1Config; 607 else 608 slot_config = 609 igp_obj-> 610 ulDDISlot2Config; 611 612 ct = (slot_config >> 16) & 0xff; 613 connector_type = 614 object_connector_convert 615 [ct]; 616 connector_object_id = ct; 617 igp_lane_info = 618 slot_config & 0xffff; 619 } else 620 continue; 621 } else 622 continue; 623 } else { 624 igp_lane_info = 0; 625 connector_type = 626 object_connector_convert[con_obj_id]; 627 connector_object_id = con_obj_id; 628 } 629 } else { 630 igp_lane_info = 0; 631 connector_type = 632 object_connector_convert[con_obj_id]; 633 connector_object_id = con_obj_id; 634 } 635 636 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 637 continue; 638 639 router.ddc_valid = false; 640 router.cd_valid = false; 641 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) { 642 uint8_t grph_obj_type = 643 (le16_to_cpu(path->usGraphicObjIds[j]) & 644 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 645 646 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { 647 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) { 648 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID); 649 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) { 650 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 651 (ctx->bios + data_offset + 652 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); 653 ATOM_ENCODER_CAP_RECORD *cap_record; 654 u16 caps = 0; 655 656 while (record->ucRecordSize > 0 && 657 record->ucRecordType > 0 && 658 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 659 switch (record->ucRecordType) { 660 case ATOM_ENCODER_CAP_RECORD_TYPE: 661 cap_record =(ATOM_ENCODER_CAP_RECORD *) 662 record; 663 caps = le16_to_cpu(cap_record->usEncoderCap); 664 break; 665 } 666 record = (ATOM_COMMON_RECORD_HEADER *) 667 ((char *)record + record->ucRecordSize); 668 } 669 radeon_add_atom_encoder(dev, 670 encoder_obj, 671 le16_to_cpu 672 (path-> 673 usDeviceTag), 674 caps); 675 } 676 } 677 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) { 678 for (k = 0; k < router_obj->ucNumberOfObjects; k++) { 679 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); 680 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) { 681 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 682 (ctx->bios + data_offset + 683 le16_to_cpu(router_obj->asObjects[k].usRecordOffset)); 684 ATOM_I2C_RECORD *i2c_record; 685 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 686 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path; 687 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path; 688 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table = 689 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) 690 (ctx->bios + data_offset + 691 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); 692 u8 *num_dst_objs = (u8 *) 693 ((u8 *)router_src_dst_table + 1 + 694 (router_src_dst_table->ucNumberOfSrc * 2)); 695 u16 *dst_objs = (u16 *)(num_dst_objs + 1); 696 int enum_id; 697 698 router.router_id = router_obj_id; 699 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) { 700 if (le16_to_cpu(path->usConnObjectId) == 701 le16_to_cpu(dst_objs[enum_id])) 702 break; 703 } 704 705 while (record->ucRecordSize > 0 && 706 record->ucRecordType > 0 && 707 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 708 switch (record->ucRecordType) { 709 case ATOM_I2C_RECORD_TYPE: 710 i2c_record = 711 (ATOM_I2C_RECORD *) 712 record; 713 i2c_config = 714 (ATOM_I2C_ID_CONFIG_ACCESS *) 715 &i2c_record->sucI2cId; 716 router.i2c_info = 717 radeon_lookup_i2c_gpio(rdev, 718 i2c_config-> 719 ucAccess); 720 router.i2c_addr = i2c_record->ucI2CAddr >> 1; 721 break; 722 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE: 723 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *) 724 record; 725 router.ddc_valid = true; 726 router.ddc_mux_type = ddc_path->ucMuxType; 727 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin; 728 router.ddc_mux_state = ddc_path->ucMuxState[enum_id]; 729 break; 730 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE: 731 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *) 732 record; 733 router.cd_valid = true; 734 router.cd_mux_type = cd_path->ucMuxType; 735 router.cd_mux_control_pin = cd_path->ucMuxControlPin; 736 router.cd_mux_state = cd_path->ucMuxState[enum_id]; 737 break; 738 } 739 record = (ATOM_COMMON_RECORD_HEADER *) 740 ((char *)record + record->ucRecordSize); 741 } 742 } 743 } 744 } 745 } 746 747 /* look up gpio for ddc, hpd */ 748 ddc_bus.valid = false; 749 hpd.hpd = RADEON_HPD_NONE; 750 if ((le16_to_cpu(path->usDeviceTag) & 751 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { 752 for (j = 0; j < con_obj->ucNumberOfObjects; j++) { 753 if (le16_to_cpu(path->usConnObjectId) == 754 le16_to_cpu(con_obj->asObjects[j]. 755 usObjectID)) { 756 ATOM_COMMON_RECORD_HEADER 757 *record = 758 (ATOM_COMMON_RECORD_HEADER 759 *) 760 (ctx->bios + data_offset + 761 le16_to_cpu(con_obj-> 762 asObjects[j]. 763 usRecordOffset)); 764 ATOM_I2C_RECORD *i2c_record; 765 ATOM_HPD_INT_RECORD *hpd_record; 766 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 767 768 while (record->ucRecordSize > 0 && 769 record->ucRecordType > 0 && 770 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 771 switch (record->ucRecordType) { 772 case ATOM_I2C_RECORD_TYPE: 773 i2c_record = 774 (ATOM_I2C_RECORD *) 775 record; 776 i2c_config = 777 (ATOM_I2C_ID_CONFIG_ACCESS *) 778 &i2c_record->sucI2cId; 779 ddc_bus = radeon_lookup_i2c_gpio(rdev, 780 i2c_config-> 781 ucAccess); 782 break; 783 case ATOM_HPD_INT_RECORD_TYPE: 784 hpd_record = 785 (ATOM_HPD_INT_RECORD *) 786 record; 787 gpio = radeon_atombios_lookup_gpio(rdev, 788 hpd_record->ucHPDIntGPIOID); 789 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio); 790 hpd.plugged_state = hpd_record->ucPlugged_PinState; 791 break; 792 } 793 record = 794 (ATOM_COMMON_RECORD_HEADER 795 *) ((char *)record 796 + 797 record-> 798 ucRecordSize); 799 } 800 break; 801 } 802 } 803 } 804 805 /* needed for aux chan transactions */ 806 ddc_bus.hpd = hpd.hpd; 807 808 conn_id = le16_to_cpu(path->usConnObjectId); 809 810 if (!radeon_atom_apply_quirks 811 (dev, le16_to_cpu(path->usDeviceTag), &connector_type, 812 &ddc_bus, &conn_id, &hpd)) 813 continue; 814 815 radeon_add_atom_connector(dev, 816 conn_id, 817 le16_to_cpu(path-> 818 usDeviceTag), 819 connector_type, &ddc_bus, 820 igp_lane_info, 821 connector_object_id, 822 &hpd, 823 &router); 824 825 } 826 } 827 828 radeon_link_encoder_connector(dev); 829 return true; 830 } 831 832 static uint16_t atombios_get_connector_object_id(struct drm_device *dev, 833 int connector_type, 834 uint16_t devices) 835 { 836 struct radeon_device *rdev = dev->dev_private; 837 838 if (rdev->flags & RADEON_IS_IGP) { 839 return supported_devices_connector_object_id_convert 840 [connector_type]; 841 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) || 842 (connector_type == DRM_MODE_CONNECTOR_DVID)) && 843 (devices & ATOM_DEVICE_DFP2_SUPPORT)) { 844 struct radeon_mode_info *mode_info = &rdev->mode_info; 845 struct atom_context *ctx = mode_info->atom_context; 846 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info); 847 uint16_t size, data_offset; 848 uint8_t frev, crev; 849 ATOM_XTMDS_INFO *xtmds; 850 851 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) { 852 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset); 853 854 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) { 855 if (connector_type == DRM_MODE_CONNECTOR_DVII) 856 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 857 else 858 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 859 } else { 860 if (connector_type == DRM_MODE_CONNECTOR_DVII) 861 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 862 else 863 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 864 } 865 } else 866 return supported_devices_connector_object_id_convert 867 [connector_type]; 868 } else { 869 return supported_devices_connector_object_id_convert 870 [connector_type]; 871 } 872 } 873 874 struct bios_connector { 875 bool valid; 876 uint16_t line_mux; 877 uint16_t devices; 878 int connector_type; 879 struct radeon_i2c_bus_rec ddc_bus; 880 struct radeon_hpd hpd; 881 }; 882 883 bool radeon_get_atom_connector_info_from_supported_devices_table(struct 884 drm_device 885 *dev) 886 { 887 struct radeon_device *rdev = dev->dev_private; 888 struct radeon_mode_info *mode_info = &rdev->mode_info; 889 struct atom_context *ctx = mode_info->atom_context; 890 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo); 891 uint16_t size, data_offset; 892 uint8_t frev, crev; 893 uint16_t device_support; 894 uint8_t dac; 895 union atom_supported_devices *supported_devices; 896 int i, j, max_device; 897 struct bios_connector *bios_connectors; 898 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE; 899 struct radeon_router router; 900 901 router.ddc_valid = false; 902 router.cd_valid = false; 903 904 bios_connectors = kzalloc(bc_size, GFP_KERNEL); 905 if (!bios_connectors) 906 return false; 907 908 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, 909 &data_offset)) { 910 kfree(bios_connectors); 911 return false; 912 } 913 914 supported_devices = 915 (union atom_supported_devices *)(ctx->bios + data_offset); 916 917 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport); 918 919 if (frev > 1) 920 max_device = ATOM_MAX_SUPPORTED_DEVICE; 921 else 922 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO; 923 924 for (i = 0; i < max_device; i++) { 925 ATOM_CONNECTOR_INFO_I2C ci; 926 927 if (frev > 1) 928 ci = supported_devices->info_2d1.asConnInfo[i]; 929 else 930 ci = supported_devices->info.asConnInfo[i]; 931 932 bios_connectors[i].valid = false; 933 934 if (!(device_support & (1 << i))) { 935 continue; 936 } 937 938 if (i == ATOM_DEVICE_CV_INDEX) { 939 DRM_DEBUG_KMS("Skipping Component Video\n"); 940 continue; 941 } 942 943 bios_connectors[i].connector_type = 944 supported_devices_connector_convert[ci.sucConnectorInfo. 945 sbfAccess. 946 bfConnectorType]; 947 948 if (bios_connectors[i].connector_type == 949 DRM_MODE_CONNECTOR_Unknown) 950 continue; 951 952 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; 953 954 bios_connectors[i].line_mux = 955 ci.sucI2cId.ucAccess; 956 957 /* give tv unique connector ids */ 958 if (i == ATOM_DEVICE_TV1_INDEX) { 959 bios_connectors[i].ddc_bus.valid = false; 960 bios_connectors[i].line_mux = 50; 961 } else if (i == ATOM_DEVICE_TV2_INDEX) { 962 bios_connectors[i].ddc_bus.valid = false; 963 bios_connectors[i].line_mux = 51; 964 } else if (i == ATOM_DEVICE_CV_INDEX) { 965 bios_connectors[i].ddc_bus.valid = false; 966 bios_connectors[i].line_mux = 52; 967 } else 968 bios_connectors[i].ddc_bus = 969 radeon_lookup_i2c_gpio(rdev, 970 bios_connectors[i].line_mux); 971 972 if ((crev > 1) && (frev > 1)) { 973 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap; 974 switch (isb) { 975 case 0x4: 976 bios_connectors[i].hpd.hpd = RADEON_HPD_1; 977 break; 978 case 0xa: 979 bios_connectors[i].hpd.hpd = RADEON_HPD_2; 980 break; 981 default: 982 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; 983 break; 984 } 985 } else { 986 if (i == ATOM_DEVICE_DFP1_INDEX) 987 bios_connectors[i].hpd.hpd = RADEON_HPD_1; 988 else if (i == ATOM_DEVICE_DFP2_INDEX) 989 bios_connectors[i].hpd.hpd = RADEON_HPD_2; 990 else 991 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; 992 } 993 994 /* Always set the connector type to VGA for CRT1/CRT2. if they are 995 * shared with a DVI port, we'll pick up the DVI connector when we 996 * merge the outputs. Some bioses incorrectly list VGA ports as DVI. 997 */ 998 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) 999 bios_connectors[i].connector_type = 1000 DRM_MODE_CONNECTOR_VGA; 1001 1002 if (!radeon_atom_apply_quirks 1003 (dev, (1 << i), &bios_connectors[i].connector_type, 1004 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux, 1005 &bios_connectors[i].hpd)) 1006 continue; 1007 1008 bios_connectors[i].valid = true; 1009 bios_connectors[i].devices = (1 << i); 1010 1011 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) 1012 radeon_add_atom_encoder(dev, 1013 radeon_get_encoder_enum(dev, 1014 (1 << i), 1015 dac), 1016 (1 << i), 1017 0); 1018 else 1019 radeon_add_legacy_encoder(dev, 1020 radeon_get_encoder_enum(dev, 1021 (1 << i), 1022 dac), 1023 (1 << i)); 1024 } 1025 1026 /* combine shared connectors */ 1027 for (i = 0; i < max_device; i++) { 1028 if (bios_connectors[i].valid) { 1029 for (j = 0; j < max_device; j++) { 1030 if (bios_connectors[j].valid && (i != j)) { 1031 if (bios_connectors[i].line_mux == 1032 bios_connectors[j].line_mux) { 1033 /* make sure not to combine LVDS */ 1034 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1035 bios_connectors[i].line_mux = 53; 1036 bios_connectors[i].ddc_bus.valid = false; 1037 continue; 1038 } 1039 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1040 bios_connectors[j].line_mux = 53; 1041 bios_connectors[j].ddc_bus.valid = false; 1042 continue; 1043 } 1044 /* combine analog and digital for DVI-I */ 1045 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 1046 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) || 1047 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 1048 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) { 1049 bios_connectors[i].devices |= 1050 bios_connectors[j].devices; 1051 bios_connectors[i].connector_type = 1052 DRM_MODE_CONNECTOR_DVII; 1053 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) 1054 bios_connectors[i].hpd = 1055 bios_connectors[j].hpd; 1056 bios_connectors[j].valid = false; 1057 } 1058 } 1059 } 1060 } 1061 } 1062 } 1063 1064 /* add the connectors */ 1065 for (i = 0; i < max_device; i++) { 1066 if (bios_connectors[i].valid) { 1067 uint16_t connector_object_id = 1068 atombios_get_connector_object_id(dev, 1069 bios_connectors[i].connector_type, 1070 bios_connectors[i].devices); 1071 radeon_add_atom_connector(dev, 1072 bios_connectors[i].line_mux, 1073 bios_connectors[i].devices, 1074 bios_connectors[i]. 1075 connector_type, 1076 &bios_connectors[i].ddc_bus, 1077 0, 1078 connector_object_id, 1079 &bios_connectors[i].hpd, 1080 &router); 1081 } 1082 } 1083 1084 radeon_link_encoder_connector(dev); 1085 1086 kfree(bios_connectors); 1087 return true; 1088 } 1089 1090 union firmware_info { 1091 ATOM_FIRMWARE_INFO info; 1092 ATOM_FIRMWARE_INFO_V1_2 info_12; 1093 ATOM_FIRMWARE_INFO_V1_3 info_13; 1094 ATOM_FIRMWARE_INFO_V1_4 info_14; 1095 ATOM_FIRMWARE_INFO_V2_1 info_21; 1096 ATOM_FIRMWARE_INFO_V2_2 info_22; 1097 }; 1098 1099 union igp_info { 1100 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 1101 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 1102 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; 1103 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; 1104 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; 1105 }; 1106 1107 static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev) 1108 { 1109 struct radeon_mode_info *mode_info = &rdev->mode_info; 1110 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1111 union igp_info *igp_info; 1112 u8 frev, crev; 1113 u16 data_offset; 1114 1115 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1116 &frev, &crev, &data_offset)) { 1117 igp_info = (union igp_info *)(mode_info->atom_context->bios + 1118 data_offset); 1119 rdev->clock.vco_freq = 1120 le32_to_cpu(igp_info->info_6.ulDentistVCOFreq); 1121 } 1122 } 1123 1124 bool radeon_atom_get_clock_info(struct drm_device *dev) 1125 { 1126 struct radeon_device *rdev = dev->dev_private; 1127 struct radeon_mode_info *mode_info = &rdev->mode_info; 1128 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 1129 union firmware_info *firmware_info; 1130 uint8_t frev, crev; 1131 struct radeon_pll *p1pll = &rdev->clock.p1pll; 1132 struct radeon_pll *p2pll = &rdev->clock.p2pll; 1133 struct radeon_pll *dcpll = &rdev->clock.dcpll; 1134 struct radeon_pll *spll = &rdev->clock.spll; 1135 struct radeon_pll *mpll = &rdev->clock.mpll; 1136 uint16_t data_offset; 1137 1138 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1139 &frev, &crev, &data_offset)) { 1140 firmware_info = 1141 (union firmware_info *)(mode_info->atom_context->bios + 1142 data_offset); 1143 /* pixel clocks */ 1144 p1pll->reference_freq = 1145 le16_to_cpu(firmware_info->info.usReferenceClock); 1146 p1pll->reference_div = 0; 1147 1148 if ((frev < 2) && (crev < 2)) 1149 p1pll->pll_out_min = 1150 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); 1151 else 1152 p1pll->pll_out_min = 1153 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); 1154 p1pll->pll_out_max = 1155 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); 1156 1157 if (((frev < 2) && (crev >= 4)) || (frev >= 2)) { 1158 p1pll->lcd_pll_out_min = 1159 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100; 1160 if (p1pll->lcd_pll_out_min == 0) 1161 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 1162 p1pll->lcd_pll_out_max = 1163 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100; 1164 if (p1pll->lcd_pll_out_max == 0) 1165 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 1166 } else { 1167 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 1168 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 1169 } 1170 1171 if (p1pll->pll_out_min == 0) { 1172 if (ASIC_IS_AVIVO(rdev)) 1173 p1pll->pll_out_min = 64800; 1174 else 1175 p1pll->pll_out_min = 20000; 1176 } 1177 1178 p1pll->pll_in_min = 1179 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); 1180 p1pll->pll_in_max = 1181 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); 1182 1183 *p2pll = *p1pll; 1184 1185 /* system clock */ 1186 if (ASIC_IS_DCE4(rdev)) 1187 spll->reference_freq = 1188 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock); 1189 else 1190 spll->reference_freq = 1191 le16_to_cpu(firmware_info->info.usReferenceClock); 1192 spll->reference_div = 0; 1193 1194 spll->pll_out_min = 1195 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); 1196 spll->pll_out_max = 1197 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); 1198 1199 /* ??? */ 1200 if (spll->pll_out_min == 0) { 1201 if (ASIC_IS_AVIVO(rdev)) 1202 spll->pll_out_min = 64800; 1203 else 1204 spll->pll_out_min = 20000; 1205 } 1206 1207 spll->pll_in_min = 1208 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); 1209 spll->pll_in_max = 1210 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); 1211 1212 /* memory clock */ 1213 if (ASIC_IS_DCE4(rdev)) 1214 mpll->reference_freq = 1215 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock); 1216 else 1217 mpll->reference_freq = 1218 le16_to_cpu(firmware_info->info.usReferenceClock); 1219 mpll->reference_div = 0; 1220 1221 mpll->pll_out_min = 1222 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); 1223 mpll->pll_out_max = 1224 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); 1225 1226 /* ??? */ 1227 if (mpll->pll_out_min == 0) { 1228 if (ASIC_IS_AVIVO(rdev)) 1229 mpll->pll_out_min = 64800; 1230 else 1231 mpll->pll_out_min = 20000; 1232 } 1233 1234 mpll->pll_in_min = 1235 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); 1236 mpll->pll_in_max = 1237 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); 1238 1239 rdev->clock.default_sclk = 1240 le32_to_cpu(firmware_info->info.ulDefaultEngineClock); 1241 rdev->clock.default_mclk = 1242 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); 1243 1244 if (ASIC_IS_DCE4(rdev)) { 1245 rdev->clock.default_dispclk = 1246 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); 1247 if (rdev->clock.default_dispclk == 0) { 1248 if (ASIC_IS_DCE6(rdev)) 1249 rdev->clock.default_dispclk = 60000; /* 600 Mhz */ 1250 else if (ASIC_IS_DCE5(rdev)) 1251 rdev->clock.default_dispclk = 54000; /* 540 Mhz */ 1252 else 1253 rdev->clock.default_dispclk = 60000; /* 600 Mhz */ 1254 } 1255 /* set a reasonable default for DP */ 1256 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) { 1257 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n", 1258 rdev->clock.default_dispclk / 100); 1259 rdev->clock.default_dispclk = 60000; 1260 } 1261 rdev->clock.dp_extclk = 1262 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); 1263 rdev->clock.current_dispclk = rdev->clock.default_dispclk; 1264 } 1265 *dcpll = *p1pll; 1266 1267 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock); 1268 if (rdev->clock.max_pixel_clock == 0) 1269 rdev->clock.max_pixel_clock = 40000; 1270 1271 /* not technically a clock, but... */ 1272 rdev->mode_info.firmware_flags = 1273 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess); 1274 1275 if (ASIC_IS_DCE8(rdev)) 1276 rdev->clock.vco_freq = 1277 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq); 1278 else if (ASIC_IS_DCE5(rdev)) 1279 rdev->clock.vco_freq = rdev->clock.current_dispclk; 1280 else if (ASIC_IS_DCE41(rdev)) 1281 radeon_atombios_get_dentist_vco_freq(rdev); 1282 else 1283 rdev->clock.vco_freq = rdev->clock.current_dispclk; 1284 1285 if (rdev->clock.vco_freq == 0) 1286 rdev->clock.vco_freq = 360000; /* 3.6 GHz */ 1287 1288 return true; 1289 } 1290 1291 return false; 1292 } 1293 1294 bool radeon_atombios_sideport_present(struct radeon_device *rdev) 1295 { 1296 struct radeon_mode_info *mode_info = &rdev->mode_info; 1297 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1298 union igp_info *igp_info; 1299 u8 frev, crev; 1300 u16 data_offset; 1301 1302 /* sideport is AMD only */ 1303 if (rdev->family == CHIP_RS600) 1304 return false; 1305 1306 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1307 &frev, &crev, &data_offset)) { 1308 igp_info = (union igp_info *)(mode_info->atom_context->bios + 1309 data_offset); 1310 switch (crev) { 1311 case 1: 1312 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock)) 1313 return true; 1314 break; 1315 case 2: 1316 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock)) 1317 return true; 1318 break; 1319 default: 1320 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 1321 break; 1322 } 1323 } 1324 return false; 1325 } 1326 1327 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 1328 struct radeon_encoder_int_tmds *tmds) 1329 { 1330 struct drm_device *dev = encoder->base.dev; 1331 struct radeon_device *rdev = dev->dev_private; 1332 struct radeon_mode_info *mode_info = &rdev->mode_info; 1333 int index = GetIndexIntoMasterTable(DATA, TMDS_Info); 1334 uint16_t data_offset; 1335 struct _ATOM_TMDS_INFO *tmds_info; 1336 uint8_t frev, crev; 1337 uint16_t maxfreq; 1338 int i; 1339 1340 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1341 &frev, &crev, &data_offset)) { 1342 tmds_info = 1343 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios + 1344 data_offset); 1345 1346 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); 1347 for (i = 0; i < 4; i++) { 1348 tmds->tmds_pll[i].freq = 1349 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency); 1350 tmds->tmds_pll[i].value = 1351 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f; 1352 tmds->tmds_pll[i].value |= 1353 (tmds_info->asMiscInfo[i]. 1354 ucPLL_VCO_Gain & 0x3f) << 6; 1355 tmds->tmds_pll[i].value |= 1356 (tmds_info->asMiscInfo[i]. 1357 ucPLL_DutyCycle & 0xf) << 12; 1358 tmds->tmds_pll[i].value |= 1359 (tmds_info->asMiscInfo[i]. 1360 ucPLL_VoltageSwing & 0xf) << 16; 1361 1362 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n", 1363 tmds->tmds_pll[i].freq, 1364 tmds->tmds_pll[i].value); 1365 1366 if (maxfreq == tmds->tmds_pll[i].freq) { 1367 tmds->tmds_pll[i].freq = 0xffffffff; 1368 break; 1369 } 1370 } 1371 return true; 1372 } 1373 return false; 1374 } 1375 1376 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 1377 struct radeon_atom_ss *ss, 1378 int id) 1379 { 1380 struct radeon_mode_info *mode_info = &rdev->mode_info; 1381 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info); 1382 uint16_t data_offset, size; 1383 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info; 1384 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign; 1385 uint8_t frev, crev; 1386 int i, num_indices; 1387 1388 memset(ss, 0, sizeof(struct radeon_atom_ss)); 1389 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1390 &frev, &crev, &data_offset)) { 1391 ss_info = 1392 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset); 1393 1394 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1395 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT); 1396 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *) 1397 ((u8 *)&ss_info->asSS_Info[0]); 1398 for (i = 0; i < num_indices; i++) { 1399 if (ss_assign->ucSS_Id == id) { 1400 ss->percentage = 1401 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage); 1402 ss->type = ss_assign->ucSpreadSpectrumType; 1403 ss->step = ss_assign->ucSS_Step; 1404 ss->delay = ss_assign->ucSS_Delay; 1405 ss->range = ss_assign->ucSS_Range; 1406 ss->refdiv = ss_assign->ucRecommendedRef_Div; 1407 return true; 1408 } 1409 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *) 1410 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT)); 1411 } 1412 } 1413 return false; 1414 } 1415 1416 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev, 1417 struct radeon_atom_ss *ss, 1418 int id) 1419 { 1420 struct radeon_mode_info *mode_info = &rdev->mode_info; 1421 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1422 u16 data_offset, size; 1423 union igp_info *igp_info; 1424 u8 frev, crev; 1425 u16 percentage = 0, rate = 0; 1426 1427 /* get any igp specific overrides */ 1428 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1429 &frev, &crev, &data_offset)) { 1430 igp_info = (union igp_info *) 1431 (mode_info->atom_context->bios + data_offset); 1432 switch (crev) { 1433 case 6: 1434 switch (id) { 1435 case ASIC_INTERNAL_SS_ON_TMDS: 1436 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage); 1437 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz); 1438 break; 1439 case ASIC_INTERNAL_SS_ON_HDMI: 1440 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage); 1441 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz); 1442 break; 1443 case ASIC_INTERNAL_SS_ON_LVDS: 1444 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage); 1445 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz); 1446 break; 1447 } 1448 break; 1449 case 7: 1450 switch (id) { 1451 case ASIC_INTERNAL_SS_ON_TMDS: 1452 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage); 1453 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz); 1454 break; 1455 case ASIC_INTERNAL_SS_ON_HDMI: 1456 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage); 1457 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz); 1458 break; 1459 case ASIC_INTERNAL_SS_ON_LVDS: 1460 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage); 1461 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz); 1462 break; 1463 } 1464 break; 1465 case 8: 1466 switch (id) { 1467 case ASIC_INTERNAL_SS_ON_TMDS: 1468 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage); 1469 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz); 1470 break; 1471 case ASIC_INTERNAL_SS_ON_HDMI: 1472 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage); 1473 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz); 1474 break; 1475 case ASIC_INTERNAL_SS_ON_LVDS: 1476 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage); 1477 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz); 1478 break; 1479 } 1480 break; 1481 default: 1482 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 1483 break; 1484 } 1485 if (percentage) 1486 ss->percentage = percentage; 1487 if (rate) 1488 ss->rate = rate; 1489 } 1490 } 1491 1492 union asic_ss_info { 1493 struct _ATOM_ASIC_INTERNAL_SS_INFO info; 1494 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2; 1495 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3; 1496 }; 1497 1498 union asic_ss_assignment { 1499 struct _ATOM_ASIC_SS_ASSIGNMENT v1; 1500 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2; 1501 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3; 1502 }; 1503 1504 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 1505 struct radeon_atom_ss *ss, 1506 int id, u32 clock) 1507 { 1508 struct radeon_mode_info *mode_info = &rdev->mode_info; 1509 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 1510 uint16_t data_offset, size; 1511 union asic_ss_info *ss_info; 1512 union asic_ss_assignment *ss_assign; 1513 uint8_t frev, crev; 1514 int i, num_indices; 1515 1516 if (id == ASIC_INTERNAL_MEMORY_SS) { 1517 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT)) 1518 return false; 1519 } 1520 if (id == ASIC_INTERNAL_ENGINE_SS) { 1521 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT)) 1522 return false; 1523 } 1524 1525 memset(ss, 0, sizeof(struct radeon_atom_ss)); 1526 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1527 &frev, &crev, &data_offset)) { 1528 1529 ss_info = 1530 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset); 1531 1532 switch (frev) { 1533 case 1: 1534 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1535 sizeof(ATOM_ASIC_SS_ASSIGNMENT); 1536 1537 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]); 1538 for (i = 0; i < num_indices; i++) { 1539 if ((ss_assign->v1.ucClockIndication == id) && 1540 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) { 1541 ss->percentage = 1542 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage); 1543 ss->type = ss_assign->v1.ucSpreadSpectrumMode; 1544 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz); 1545 ss->percentage_divider = 100; 1546 return true; 1547 } 1548 ss_assign = (union asic_ss_assignment *) 1549 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT)); 1550 } 1551 break; 1552 case 2: 1553 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1554 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); 1555 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]); 1556 for (i = 0; i < num_indices; i++) { 1557 if ((ss_assign->v2.ucClockIndication == id) && 1558 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) { 1559 ss->percentage = 1560 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage); 1561 ss->type = ss_assign->v2.ucSpreadSpectrumMode; 1562 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz); 1563 ss->percentage_divider = 100; 1564 if ((crev == 2) && 1565 ((id == ASIC_INTERNAL_ENGINE_SS) || 1566 (id == ASIC_INTERNAL_MEMORY_SS))) 1567 ss->rate /= 100; 1568 return true; 1569 } 1570 ss_assign = (union asic_ss_assignment *) 1571 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2)); 1572 } 1573 break; 1574 case 3: 1575 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1576 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); 1577 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]); 1578 for (i = 0; i < num_indices; i++) { 1579 if ((ss_assign->v3.ucClockIndication == id) && 1580 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) { 1581 ss->percentage = 1582 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage); 1583 ss->type = ss_assign->v3.ucSpreadSpectrumMode; 1584 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz); 1585 if (ss_assign->v3.ucSpreadSpectrumMode & 1586 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK) 1587 ss->percentage_divider = 1000; 1588 else 1589 ss->percentage_divider = 100; 1590 if ((id == ASIC_INTERNAL_ENGINE_SS) || 1591 (id == ASIC_INTERNAL_MEMORY_SS)) 1592 ss->rate /= 100; 1593 if (rdev->flags & RADEON_IS_IGP) 1594 radeon_atombios_get_igp_ss_overrides(rdev, ss, id); 1595 return true; 1596 } 1597 ss_assign = (union asic_ss_assignment *) 1598 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3)); 1599 } 1600 break; 1601 default: 1602 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev); 1603 break; 1604 } 1605 1606 } 1607 return false; 1608 } 1609 1610 union lvds_info { 1611 struct _ATOM_LVDS_INFO info; 1612 struct _ATOM_LVDS_INFO_V12 info_12; 1613 }; 1614 1615 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct 1616 radeon_encoder 1617 *encoder) 1618 { 1619 struct drm_device *dev = encoder->base.dev; 1620 struct radeon_device *rdev = dev->dev_private; 1621 struct radeon_mode_info *mode_info = &rdev->mode_info; 1622 int index = GetIndexIntoMasterTable(DATA, LVDS_Info); 1623 uint16_t data_offset, misc; 1624 union lvds_info *lvds_info; 1625 uint8_t frev, crev; 1626 struct radeon_encoder_atom_dig *lvds = NULL; 1627 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1628 1629 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1630 &frev, &crev, &data_offset)) { 1631 lvds_info = 1632 (union lvds_info *)(mode_info->atom_context->bios + data_offset); 1633 lvds = 1634 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 1635 1636 if (!lvds) 1637 return NULL; 1638 1639 lvds->native_mode.clock = 1640 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; 1641 lvds->native_mode.hdisplay = 1642 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); 1643 lvds->native_mode.vdisplay = 1644 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); 1645 lvds->native_mode.htotal = lvds->native_mode.hdisplay + 1646 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); 1647 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + 1648 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); 1649 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + 1650 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); 1651 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + 1652 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); 1653 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + 1654 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset); 1655 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + 1656 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); 1657 lvds->panel_pwr_delay = 1658 le16_to_cpu(lvds_info->info.usOffDelayInMs); 1659 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc; 1660 1661 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess); 1662 if (misc & ATOM_VSYNC_POLARITY) 1663 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC; 1664 if (misc & ATOM_HSYNC_POLARITY) 1665 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC; 1666 if (misc & ATOM_COMPOSITESYNC) 1667 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC; 1668 if (misc & ATOM_INTERLACE) 1669 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE; 1670 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1671 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; 1672 1673 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize); 1674 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize); 1675 1676 /* set crtc values */ 1677 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1678 1679 lvds->lcd_ss_id = lvds_info->info.ucSS_Id; 1680 1681 encoder->native_mode = lvds->native_mode; 1682 1683 if (encoder_enum == 2) 1684 lvds->linkb = true; 1685 else 1686 lvds->linkb = false; 1687 1688 /* parse the lcd record table */ 1689 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) { 1690 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record; 1691 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record; 1692 bool bad_record = false; 1693 u8 *record; 1694 1695 if ((frev == 1) && (crev < 2)) 1696 /* absolute */ 1697 record = (u8 *)(mode_info->atom_context->bios + 1698 le16_to_cpu(lvds_info->info.usModePatchTableOffset)); 1699 else 1700 /* relative */ 1701 record = (u8 *)(mode_info->atom_context->bios + 1702 data_offset + 1703 le16_to_cpu(lvds_info->info.usModePatchTableOffset)); 1704 while (*record != ATOM_RECORD_END_TYPE) { 1705 switch (*record) { 1706 case LCD_MODE_PATCH_RECORD_MODE_TYPE: 1707 record += sizeof(ATOM_PATCH_RECORD_MODE); 1708 break; 1709 case LCD_RTS_RECORD_TYPE: 1710 record += sizeof(ATOM_LCD_RTS_RECORD); 1711 break; 1712 case LCD_CAP_RECORD_TYPE: 1713 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP); 1714 break; 1715 case LCD_FAKE_EDID_PATCH_RECORD_TYPE: 1716 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record; 1717 if (fake_edid_record->ucFakeEDIDLength) { 1718 struct edid *edid; 1719 int edid_size; 1720 1721 if (fake_edid_record->ucFakeEDIDLength == 128) 1722 edid_size = fake_edid_record->ucFakeEDIDLength; 1723 else 1724 edid_size = fake_edid_record->ucFakeEDIDLength * 128; 1725 edid = kmemdup(&fake_edid_record->ucFakeEDIDString[0], 1726 edid_size, GFP_KERNEL); 1727 if (edid) { 1728 if (drm_edid_is_valid(edid)) { 1729 rdev->mode_info.bios_hardcoded_edid = edid; 1730 rdev->mode_info.bios_hardcoded_edid_size = edid_size; 1731 } else { 1732 kfree(edid); 1733 } 1734 } 1735 record += struct_size(fake_edid_record, 1736 ucFakeEDIDString, 1737 edid_size); 1738 } else { 1739 /* empty fake edid record must be 3 bytes long */ 1740 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + 1; 1741 } 1742 break; 1743 case LCD_PANEL_RESOLUTION_RECORD_TYPE: 1744 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record; 1745 lvds->native_mode.width_mm = panel_res_record->usHSize; 1746 lvds->native_mode.height_mm = panel_res_record->usVSize; 1747 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD); 1748 break; 1749 default: 1750 DRM_ERROR("Bad LCD record %d\n", *record); 1751 bad_record = true; 1752 break; 1753 } 1754 if (bad_record) 1755 break; 1756 } 1757 } 1758 } 1759 return lvds; 1760 } 1761 1762 struct radeon_encoder_primary_dac * 1763 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) 1764 { 1765 struct drm_device *dev = encoder->base.dev; 1766 struct radeon_device *rdev = dev->dev_private; 1767 struct radeon_mode_info *mode_info = &rdev->mode_info; 1768 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 1769 uint16_t data_offset; 1770 struct _COMPASSIONATE_DATA *dac_info; 1771 uint8_t frev, crev; 1772 uint8_t bg, dac; 1773 struct radeon_encoder_primary_dac *p_dac = NULL; 1774 1775 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1776 &frev, &crev, &data_offset)) { 1777 dac_info = (struct _COMPASSIONATE_DATA *) 1778 (mode_info->atom_context->bios + data_offset); 1779 1780 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL); 1781 1782 if (!p_dac) 1783 return NULL; 1784 1785 bg = dac_info->ucDAC1_BG_Adjustment; 1786 dac = dac_info->ucDAC1_DAC_Adjustment; 1787 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 1788 1789 } 1790 return p_dac; 1791 } 1792 1793 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 1794 struct drm_display_mode *mode) 1795 { 1796 struct radeon_mode_info *mode_info = &rdev->mode_info; 1797 ATOM_ANALOG_TV_INFO *tv_info; 1798 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; 1799 ATOM_DTD_FORMAT *dtd_timings; 1800 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1801 u8 frev, crev; 1802 u16 data_offset, misc; 1803 1804 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL, 1805 &frev, &crev, &data_offset)) 1806 return false; 1807 1808 switch (crev) { 1809 case 1: 1810 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); 1811 if (index >= MAX_SUPPORTED_TV_TIMING) 1812 return false; 1813 1814 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); 1815 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); 1816 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); 1817 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) + 1818 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); 1819 1820 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); 1821 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); 1822 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); 1823 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) + 1824 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); 1825 1826 mode->flags = 0; 1827 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess); 1828 if (misc & ATOM_VSYNC_POLARITY) 1829 mode->flags |= DRM_MODE_FLAG_NVSYNC; 1830 if (misc & ATOM_HSYNC_POLARITY) 1831 mode->flags |= DRM_MODE_FLAG_NHSYNC; 1832 if (misc & ATOM_COMPOSITESYNC) 1833 mode->flags |= DRM_MODE_FLAG_CSYNC; 1834 if (misc & ATOM_INTERLACE) 1835 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1836 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1837 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1838 1839 mode->crtc_clock = mode->clock = 1840 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; 1841 1842 if (index == 1) { 1843 /* PAL timings appear to have wrong values for totals */ 1844 mode->crtc_htotal -= 1; 1845 mode->crtc_vtotal -= 1; 1846 } 1847 break; 1848 case 2: 1849 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset); 1850 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2) 1851 return false; 1852 1853 dtd_timings = &tv_info_v1_2->aModeTimings[index]; 1854 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) + 1855 le16_to_cpu(dtd_timings->usHBlanking_Time); 1856 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive); 1857 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) + 1858 le16_to_cpu(dtd_timings->usHSyncOffset); 1859 mode->crtc_hsync_end = mode->crtc_hsync_start + 1860 le16_to_cpu(dtd_timings->usHSyncWidth); 1861 1862 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) + 1863 le16_to_cpu(dtd_timings->usVBlanking_Time); 1864 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive); 1865 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) + 1866 le16_to_cpu(dtd_timings->usVSyncOffset); 1867 mode->crtc_vsync_end = mode->crtc_vsync_start + 1868 le16_to_cpu(dtd_timings->usVSyncWidth); 1869 1870 mode->flags = 0; 1871 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); 1872 if (misc & ATOM_VSYNC_POLARITY) 1873 mode->flags |= DRM_MODE_FLAG_NVSYNC; 1874 if (misc & ATOM_HSYNC_POLARITY) 1875 mode->flags |= DRM_MODE_FLAG_NHSYNC; 1876 if (misc & ATOM_COMPOSITESYNC) 1877 mode->flags |= DRM_MODE_FLAG_CSYNC; 1878 if (misc & ATOM_INTERLACE) 1879 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1880 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1881 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1882 1883 mode->crtc_clock = mode->clock = 1884 le16_to_cpu(dtd_timings->usPixClk) * 10; 1885 break; 1886 } 1887 return true; 1888 } 1889 1890 enum radeon_tv_std 1891 radeon_atombios_get_tv_info(struct radeon_device *rdev) 1892 { 1893 struct radeon_mode_info *mode_info = &rdev->mode_info; 1894 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1895 uint16_t data_offset; 1896 uint8_t frev, crev; 1897 struct _ATOM_ANALOG_TV_INFO *tv_info; 1898 enum radeon_tv_std tv_std = TV_STD_NTSC; 1899 1900 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1901 &frev, &crev, &data_offset)) { 1902 1903 tv_info = (struct _ATOM_ANALOG_TV_INFO *) 1904 (mode_info->atom_context->bios + data_offset); 1905 1906 switch (tv_info->ucTV_BootUpDefaultStandard) { 1907 case ATOM_TV_NTSC: 1908 tv_std = TV_STD_NTSC; 1909 DRM_DEBUG_KMS("Default TV standard: NTSC\n"); 1910 break; 1911 case ATOM_TV_NTSCJ: 1912 tv_std = TV_STD_NTSC_J; 1913 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); 1914 break; 1915 case ATOM_TV_PAL: 1916 tv_std = TV_STD_PAL; 1917 DRM_DEBUG_KMS("Default TV standard: PAL\n"); 1918 break; 1919 case ATOM_TV_PALM: 1920 tv_std = TV_STD_PAL_M; 1921 DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); 1922 break; 1923 case ATOM_TV_PALN: 1924 tv_std = TV_STD_PAL_N; 1925 DRM_DEBUG_KMS("Default TV standard: PAL-N\n"); 1926 break; 1927 case ATOM_TV_PALCN: 1928 tv_std = TV_STD_PAL_CN; 1929 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n"); 1930 break; 1931 case ATOM_TV_PAL60: 1932 tv_std = TV_STD_PAL_60; 1933 DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); 1934 break; 1935 case ATOM_TV_SECAM: 1936 tv_std = TV_STD_SECAM; 1937 DRM_DEBUG_KMS("Default TV standard: SECAM\n"); 1938 break; 1939 default: 1940 tv_std = TV_STD_NTSC; 1941 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n"); 1942 break; 1943 } 1944 } 1945 return tv_std; 1946 } 1947 1948 struct radeon_encoder_tv_dac * 1949 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) 1950 { 1951 struct drm_device *dev = encoder->base.dev; 1952 struct radeon_device *rdev = dev->dev_private; 1953 struct radeon_mode_info *mode_info = &rdev->mode_info; 1954 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 1955 uint16_t data_offset; 1956 struct _COMPASSIONATE_DATA *dac_info; 1957 uint8_t frev, crev; 1958 uint8_t bg, dac; 1959 struct radeon_encoder_tv_dac *tv_dac = NULL; 1960 1961 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1962 &frev, &crev, &data_offset)) { 1963 1964 dac_info = (struct _COMPASSIONATE_DATA *) 1965 (mode_info->atom_context->bios + data_offset); 1966 1967 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 1968 1969 if (!tv_dac) 1970 return NULL; 1971 1972 bg = dac_info->ucDAC2_CRT2_BG_Adjustment; 1973 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment; 1974 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1975 1976 bg = dac_info->ucDAC2_PAL_BG_Adjustment; 1977 dac = dac_info->ucDAC2_PAL_DAC_Adjustment; 1978 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1979 1980 bg = dac_info->ucDAC2_NTSC_BG_Adjustment; 1981 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment; 1982 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1983 1984 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev); 1985 } 1986 return tv_dac; 1987 } 1988 1989 static const char *thermal_controller_names[] = { 1990 "NONE", 1991 "lm63", 1992 "adm1032", 1993 "adm1030", 1994 "max6649", 1995 "lm63", /* lm64 */ 1996 "f75375", 1997 "asc7xxx", 1998 }; 1999 2000 static const char *pp_lib_thermal_controller_names[] = { 2001 "NONE", 2002 "lm63", 2003 "adm1032", 2004 "adm1030", 2005 "max6649", 2006 "lm63", /* lm64 */ 2007 "f75375", 2008 "RV6xx", 2009 "RV770", 2010 "adt7473", 2011 "NONE", 2012 "External GPIO", 2013 "Evergreen", 2014 "emc2103", 2015 "Sumo", 2016 "Northern Islands", 2017 "Southern Islands", 2018 "lm96163", 2019 "Sea Islands", 2020 }; 2021 2022 union power_info { 2023 struct _ATOM_POWERPLAY_INFO info; 2024 struct _ATOM_POWERPLAY_INFO_V2 info_2; 2025 struct _ATOM_POWERPLAY_INFO_V3 info_3; 2026 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 2027 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 2028 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 2029 }; 2030 2031 union pplib_clock_info { 2032 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 2033 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 2034 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 2035 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 2036 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 2037 struct _ATOM_PPLIB_CI_CLOCK_INFO ci; 2038 }; 2039 2040 union pplib_power_state { 2041 struct _ATOM_PPLIB_STATE v1; 2042 struct _ATOM_PPLIB_STATE_V2 v2; 2043 }; 2044 2045 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev, 2046 int state_index, 2047 u32 misc, u32 misc2) 2048 { 2049 rdev->pm.power_state[state_index].misc = misc; 2050 rdev->pm.power_state[state_index].misc2 = misc2; 2051 /* order matters! */ 2052 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) 2053 rdev->pm.power_state[state_index].type = 2054 POWER_STATE_TYPE_POWERSAVE; 2055 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE) 2056 rdev->pm.power_state[state_index].type = 2057 POWER_STATE_TYPE_BATTERY; 2058 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE) 2059 rdev->pm.power_state[state_index].type = 2060 POWER_STATE_TYPE_BATTERY; 2061 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) 2062 rdev->pm.power_state[state_index].type = 2063 POWER_STATE_TYPE_BALANCED; 2064 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) { 2065 rdev->pm.power_state[state_index].type = 2066 POWER_STATE_TYPE_PERFORMANCE; 2067 rdev->pm.power_state[state_index].flags &= 2068 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2069 } 2070 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE) 2071 rdev->pm.power_state[state_index].type = 2072 POWER_STATE_TYPE_BALANCED; 2073 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { 2074 rdev->pm.power_state[state_index].type = 2075 POWER_STATE_TYPE_DEFAULT; 2076 rdev->pm.default_power_state_index = state_index; 2077 rdev->pm.power_state[state_index].default_clock_mode = 2078 &rdev->pm.power_state[state_index].clock_info[0]; 2079 } else if (state_index == 0) { 2080 rdev->pm.power_state[state_index].clock_info[0].flags |= 2081 RADEON_PM_MODE_NO_DISPLAY; 2082 } 2083 } 2084 2085 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev) 2086 { 2087 struct radeon_mode_info *mode_info = &rdev->mode_info; 2088 u32 misc, misc2 = 0; 2089 int num_modes = 0, i; 2090 int state_index = 0; 2091 struct radeon_i2c_bus_rec i2c_bus; 2092 union power_info *power_info; 2093 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2094 u16 data_offset; 2095 u8 frev, crev; 2096 2097 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2098 &frev, &crev, &data_offset)) 2099 return state_index; 2100 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2101 2102 /* add the i2c bus for thermal/fan chip */ 2103 if ((power_info->info.ucOverdriveThermalController > 0) && 2104 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) { 2105 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2106 thermal_controller_names[power_info->info.ucOverdriveThermalController], 2107 power_info->info.ucOverdriveControllerAddress >> 1); 2108 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine); 2109 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2110 if (rdev->pm.i2c_bus) { 2111 struct i2c_board_info info = { }; 2112 const char *name = thermal_controller_names[power_info->info. 2113 ucOverdriveThermalController]; 2114 info.addr = power_info->info.ucOverdriveControllerAddress >> 1; 2115 strscpy(info.type, name, sizeof(info.type)); 2116 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info); 2117 } 2118 } 2119 num_modes = power_info->info.ucNumOfPowerModeEntries; 2120 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK) 2121 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK; 2122 if (num_modes == 0) 2123 return state_index; 2124 rdev->pm.power_state = kcalloc(num_modes, 2125 sizeof(struct radeon_power_state), 2126 GFP_KERNEL); 2127 if (!rdev->pm.power_state) 2128 return state_index; 2129 /* last mode is usually default, array is low to high */ 2130 for (i = 0; i < num_modes; i++) { 2131 /* avoid memory leaks from invalid modes or unknown frev. */ 2132 if (!rdev->pm.power_state[state_index].clock_info) { 2133 rdev->pm.power_state[state_index].clock_info = 2134 kzalloc(sizeof(struct radeon_pm_clock_info), 2135 GFP_KERNEL); 2136 } 2137 if (!rdev->pm.power_state[state_index].clock_info) 2138 goto out; 2139 rdev->pm.power_state[state_index].num_clock_modes = 1; 2140 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2141 switch (frev) { 2142 case 1: 2143 rdev->pm.power_state[state_index].clock_info[0].mclk = 2144 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock); 2145 rdev->pm.power_state[state_index].clock_info[0].sclk = 2146 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock); 2147 /* skip invalid modes */ 2148 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2149 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2150 continue; 2151 rdev->pm.power_state[state_index].pcie_lanes = 2152 power_info->info.asPowerPlayInfo[i].ucNumPciELanes; 2153 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo); 2154 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2155 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2156 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2157 VOLTAGE_GPIO; 2158 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2159 radeon_atombios_lookup_gpio(rdev, 2160 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex); 2161 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2162 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2163 true; 2164 else 2165 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2166 false; 2167 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2168 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2169 VOLTAGE_VDDC; 2170 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2171 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex; 2172 } 2173 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2174 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0); 2175 state_index++; 2176 break; 2177 case 2: 2178 rdev->pm.power_state[state_index].clock_info[0].mclk = 2179 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock); 2180 rdev->pm.power_state[state_index].clock_info[0].sclk = 2181 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock); 2182 /* skip invalid modes */ 2183 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2184 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2185 continue; 2186 rdev->pm.power_state[state_index].pcie_lanes = 2187 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes; 2188 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo); 2189 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2); 2190 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2191 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2192 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2193 VOLTAGE_GPIO; 2194 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2195 radeon_atombios_lookup_gpio(rdev, 2196 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex); 2197 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2198 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2199 true; 2200 else 2201 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2202 false; 2203 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2204 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2205 VOLTAGE_VDDC; 2206 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2207 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex; 2208 } 2209 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2210 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); 2211 state_index++; 2212 break; 2213 case 3: 2214 rdev->pm.power_state[state_index].clock_info[0].mclk = 2215 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock); 2216 rdev->pm.power_state[state_index].clock_info[0].sclk = 2217 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock); 2218 /* skip invalid modes */ 2219 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2220 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2221 continue; 2222 rdev->pm.power_state[state_index].pcie_lanes = 2223 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes; 2224 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo); 2225 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2); 2226 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2227 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2228 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2229 VOLTAGE_GPIO; 2230 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2231 radeon_atombios_lookup_gpio(rdev, 2232 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex); 2233 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2234 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2235 true; 2236 else 2237 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2238 false; 2239 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2240 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2241 VOLTAGE_VDDC; 2242 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2243 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex; 2244 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) { 2245 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled = 2246 true; 2247 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id = 2248 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex; 2249 } 2250 } 2251 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2252 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); 2253 state_index++; 2254 break; 2255 } 2256 } 2257 out: 2258 /* free any unused clock_info allocation. */ 2259 if (state_index && state_index < num_modes) { 2260 kfree(rdev->pm.power_state[state_index].clock_info); 2261 rdev->pm.power_state[state_index].clock_info = NULL; 2262 } 2263 2264 /* last mode is usually default */ 2265 if (state_index && rdev->pm.default_power_state_index == -1) { 2266 rdev->pm.power_state[state_index - 1].type = 2267 POWER_STATE_TYPE_DEFAULT; 2268 rdev->pm.default_power_state_index = state_index - 1; 2269 rdev->pm.power_state[state_index - 1].default_clock_mode = 2270 &rdev->pm.power_state[state_index - 1].clock_info[0]; 2271 rdev->pm.power_state[state_index - 1].flags &= 2272 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2273 rdev->pm.power_state[state_index - 1].misc = 0; 2274 rdev->pm.power_state[state_index - 1].misc2 = 0; 2275 } 2276 return state_index; 2277 } 2278 2279 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev, 2280 ATOM_PPLIB_THERMALCONTROLLER *controller) 2281 { 2282 struct radeon_i2c_bus_rec i2c_bus; 2283 2284 /* add the i2c bus for thermal/fan chip */ 2285 if (controller->ucType > 0) { 2286 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN) 2287 rdev->pm.no_fan = true; 2288 rdev->pm.fan_pulses_per_revolution = 2289 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK; 2290 if (rdev->pm.fan_pulses_per_revolution) { 2291 rdev->pm.fan_min_rpm = controller->ucFanMinRPM; 2292 rdev->pm.fan_max_rpm = controller->ucFanMaxRPM; 2293 } 2294 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) { 2295 DRM_INFO("Internal thermal controller %s fan control\n", 2296 (controller->ucFanParameters & 2297 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2298 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX; 2299 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) { 2300 DRM_INFO("Internal thermal controller %s fan control\n", 2301 (controller->ucFanParameters & 2302 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2303 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770; 2304 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) { 2305 DRM_INFO("Internal thermal controller %s fan control\n", 2306 (controller->ucFanParameters & 2307 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2308 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN; 2309 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) { 2310 DRM_INFO("Internal thermal controller %s fan control\n", 2311 (controller->ucFanParameters & 2312 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2313 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO; 2314 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) { 2315 DRM_INFO("Internal thermal controller %s fan control\n", 2316 (controller->ucFanParameters & 2317 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2318 rdev->pm.int_thermal_type = THERMAL_TYPE_NI; 2319 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) { 2320 DRM_INFO("Internal thermal controller %s fan control\n", 2321 (controller->ucFanParameters & 2322 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2323 rdev->pm.int_thermal_type = THERMAL_TYPE_SI; 2324 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) { 2325 DRM_INFO("Internal thermal controller %s fan control\n", 2326 (controller->ucFanParameters & 2327 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2328 rdev->pm.int_thermal_type = THERMAL_TYPE_CI; 2329 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) { 2330 DRM_INFO("Internal thermal controller %s fan control\n", 2331 (controller->ucFanParameters & 2332 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2333 rdev->pm.int_thermal_type = THERMAL_TYPE_KV; 2334 } else if (controller->ucType == 2335 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) { 2336 DRM_INFO("External GPIO thermal controller %s fan control\n", 2337 (controller->ucFanParameters & 2338 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2339 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO; 2340 } else if (controller->ucType == 2341 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) { 2342 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n", 2343 (controller->ucFanParameters & 2344 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2345 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL; 2346 } else if (controller->ucType == 2347 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) { 2348 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n", 2349 (controller->ucFanParameters & 2350 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2351 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL; 2352 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) { 2353 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n", 2354 pp_lib_thermal_controller_names[controller->ucType], 2355 controller->ucI2cAddress >> 1, 2356 (controller->ucFanParameters & 2357 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2358 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL; 2359 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine); 2360 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2361 if (rdev->pm.i2c_bus) { 2362 struct i2c_board_info info = { }; 2363 const char *name = pp_lib_thermal_controller_names[controller->ucType]; 2364 info.addr = controller->ucI2cAddress >> 1; 2365 strscpy(info.type, name, sizeof(info.type)); 2366 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info); 2367 } 2368 } else { 2369 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n", 2370 controller->ucType, 2371 controller->ucI2cAddress >> 1, 2372 (controller->ucFanParameters & 2373 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2374 } 2375 } 2376 } 2377 2378 void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 2379 u16 *vddc, u16 *vddci, u16 *mvdd) 2380 { 2381 struct radeon_mode_info *mode_info = &rdev->mode_info; 2382 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 2383 u8 frev, crev; 2384 u16 data_offset; 2385 union firmware_info *firmware_info; 2386 2387 *vddc = 0; 2388 *vddci = 0; 2389 *mvdd = 0; 2390 2391 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2392 &frev, &crev, &data_offset)) { 2393 firmware_info = 2394 (union firmware_info *)(mode_info->atom_context->bios + 2395 data_offset); 2396 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage); 2397 if ((frev == 2) && (crev >= 2)) { 2398 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage); 2399 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage); 2400 } 2401 } 2402 } 2403 2404 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev, 2405 int state_index, int mode_index, 2406 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info) 2407 { 2408 int j; 2409 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings); 2410 u32 misc2 = le16_to_cpu(non_clock_info->usClassification); 2411 u16 vddc, vddci, mvdd; 2412 2413 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 2414 2415 rdev->pm.power_state[state_index].misc = misc; 2416 rdev->pm.power_state[state_index].misc2 = misc2; 2417 rdev->pm.power_state[state_index].pcie_lanes = 2418 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> 2419 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 2420 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { 2421 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: 2422 rdev->pm.power_state[state_index].type = 2423 POWER_STATE_TYPE_BATTERY; 2424 break; 2425 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED: 2426 rdev->pm.power_state[state_index].type = 2427 POWER_STATE_TYPE_BALANCED; 2428 break; 2429 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: 2430 rdev->pm.power_state[state_index].type = 2431 POWER_STATE_TYPE_PERFORMANCE; 2432 break; 2433 case ATOM_PPLIB_CLASSIFICATION_UI_NONE: 2434 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) 2435 rdev->pm.power_state[state_index].type = 2436 POWER_STATE_TYPE_PERFORMANCE; 2437 break; 2438 } 2439 rdev->pm.power_state[state_index].flags = 0; 2440 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) 2441 rdev->pm.power_state[state_index].flags |= 2442 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2443 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) { 2444 rdev->pm.power_state[state_index].type = 2445 POWER_STATE_TYPE_DEFAULT; 2446 rdev->pm.default_power_state_index = state_index; 2447 rdev->pm.power_state[state_index].default_clock_mode = 2448 &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; 2449 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) { 2450 /* NI chips post without MC ucode, so default clocks are strobe mode only */ 2451 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk; 2452 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk; 2453 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage; 2454 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci; 2455 } else { 2456 u16 max_vddci = 0; 2457 2458 if (ASIC_IS_DCE4(rdev)) 2459 radeon_atom_get_max_voltage(rdev, 2460 SET_VOLTAGE_TYPE_ASIC_VDDCI, 2461 &max_vddci); 2462 /* patch the table values with the default sclk/mclk from firmware info */ 2463 for (j = 0; j < mode_index; j++) { 2464 rdev->pm.power_state[state_index].clock_info[j].mclk = 2465 rdev->clock.default_mclk; 2466 rdev->pm.power_state[state_index].clock_info[j].sclk = 2467 rdev->clock.default_sclk; 2468 if (vddc) 2469 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage = 2470 vddc; 2471 if (max_vddci) 2472 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci = 2473 max_vddci; 2474 } 2475 } 2476 } 2477 } 2478 2479 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev, 2480 int state_index, int mode_index, 2481 union pplib_clock_info *clock_info) 2482 { 2483 u32 sclk, mclk; 2484 u16 vddc; 2485 2486 if (rdev->flags & RADEON_IS_IGP) { 2487 if (rdev->family >= CHIP_PALM) { 2488 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); 2489 sclk |= clock_info->sumo.ucEngineClockHigh << 16; 2490 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2491 } else { 2492 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow); 2493 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; 2494 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2495 } 2496 } else if (rdev->family >= CHIP_BONAIRE) { 2497 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); 2498 sclk |= clock_info->ci.ucEngineClockHigh << 16; 2499 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); 2500 mclk |= clock_info->ci.ucMemoryClockHigh << 16; 2501 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2502 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2503 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2504 VOLTAGE_NONE; 2505 } else if (rdev->family >= CHIP_TAHITI) { 2506 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 2507 sclk |= clock_info->si.ucEngineClockHigh << 16; 2508 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 2509 mclk |= clock_info->si.ucMemoryClockHigh << 16; 2510 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2511 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2512 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2513 VOLTAGE_SW; 2514 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2515 le16_to_cpu(clock_info->si.usVDDC); 2516 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = 2517 le16_to_cpu(clock_info->si.usVDDCI); 2518 } else if (rdev->family >= CHIP_CEDAR) { 2519 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); 2520 sclk |= clock_info->evergreen.ucEngineClockHigh << 16; 2521 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow); 2522 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16; 2523 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2524 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2525 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2526 VOLTAGE_SW; 2527 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2528 le16_to_cpu(clock_info->evergreen.usVDDC); 2529 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = 2530 le16_to_cpu(clock_info->evergreen.usVDDCI); 2531 } else { 2532 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow); 2533 sclk |= clock_info->r600.ucEngineClockHigh << 16; 2534 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow); 2535 mclk |= clock_info->r600.ucMemoryClockHigh << 16; 2536 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2537 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2538 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2539 VOLTAGE_SW; 2540 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2541 le16_to_cpu(clock_info->r600.usVDDC); 2542 } 2543 2544 /* patch up vddc if necessary */ 2545 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) { 2546 case ATOM_VIRTUAL_VOLTAGE_ID0: 2547 case ATOM_VIRTUAL_VOLTAGE_ID1: 2548 case ATOM_VIRTUAL_VOLTAGE_ID2: 2549 case ATOM_VIRTUAL_VOLTAGE_ID3: 2550 case ATOM_VIRTUAL_VOLTAGE_ID4: 2551 case ATOM_VIRTUAL_VOLTAGE_ID5: 2552 case ATOM_VIRTUAL_VOLTAGE_ID6: 2553 case ATOM_VIRTUAL_VOLTAGE_ID7: 2554 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, 2555 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage, 2556 &vddc) == 0) 2557 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc; 2558 break; 2559 default: 2560 break; 2561 } 2562 2563 if (rdev->flags & RADEON_IS_IGP) { 2564 /* skip invalid modes */ 2565 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) 2566 return false; 2567 } else { 2568 /* skip invalid modes */ 2569 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || 2570 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) 2571 return false; 2572 } 2573 return true; 2574 } 2575 2576 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev) 2577 { 2578 struct radeon_mode_info *mode_info = &rdev->mode_info; 2579 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2580 union pplib_power_state *power_state; 2581 int i, j; 2582 int state_index = 0, mode_index = 0; 2583 union pplib_clock_info *clock_info; 2584 bool valid; 2585 union power_info *power_info; 2586 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2587 u16 data_offset; 2588 u8 frev, crev; 2589 2590 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2591 &frev, &crev, &data_offset)) 2592 return state_index; 2593 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2594 2595 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2596 if (power_info->pplib.ucNumStates == 0) 2597 return state_index; 2598 rdev->pm.power_state = kcalloc(power_info->pplib.ucNumStates, 2599 sizeof(struct radeon_power_state), 2600 GFP_KERNEL); 2601 if (!rdev->pm.power_state) 2602 return state_index; 2603 /* first mode is usually default, followed by low to high */ 2604 for (i = 0; i < power_info->pplib.ucNumStates; i++) { 2605 mode_index = 0; 2606 power_state = (union pplib_power_state *) 2607 (mode_info->atom_context->bios + data_offset + 2608 le16_to_cpu(power_info->pplib.usStateArrayOffset) + 2609 i * power_info->pplib.ucStateEntrySize); 2610 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2611 (mode_info->atom_context->bios + data_offset + 2612 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) + 2613 (power_state->v1.ucNonClockStateIndex * 2614 power_info->pplib.ucNonClockSize)); 2615 rdev->pm.power_state[i].clock_info = 2616 kcalloc((power_info->pplib.ucStateEntrySize - 1) ? 2617 (power_info->pplib.ucStateEntrySize - 1) : 1, 2618 sizeof(struct radeon_pm_clock_info), 2619 GFP_KERNEL); 2620 if (!rdev->pm.power_state[i].clock_info) 2621 return state_index; 2622 if (power_info->pplib.ucStateEntrySize - 1) { 2623 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) { 2624 clock_info = (union pplib_clock_info *) 2625 (mode_info->atom_context->bios + data_offset + 2626 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) + 2627 (power_state->v1.ucClockStateIndices[j] * 2628 power_info->pplib.ucClockInfoSize)); 2629 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2630 state_index, mode_index, 2631 clock_info); 2632 if (valid) 2633 mode_index++; 2634 } 2635 } else { 2636 rdev->pm.power_state[state_index].clock_info[0].mclk = 2637 rdev->clock.default_mclk; 2638 rdev->pm.power_state[state_index].clock_info[0].sclk = 2639 rdev->clock.default_sclk; 2640 mode_index++; 2641 } 2642 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2643 if (mode_index) { 2644 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, 2645 non_clock_info); 2646 state_index++; 2647 } 2648 } 2649 /* if multiple clock modes, mark the lowest as no display */ 2650 for (i = 0; i < state_index; i++) { 2651 if (rdev->pm.power_state[i].num_clock_modes > 1) 2652 rdev->pm.power_state[i].clock_info[0].flags |= 2653 RADEON_PM_MODE_NO_DISPLAY; 2654 } 2655 /* first mode is usually default */ 2656 if (rdev->pm.default_power_state_index == -1) { 2657 rdev->pm.power_state[0].type = 2658 POWER_STATE_TYPE_DEFAULT; 2659 rdev->pm.default_power_state_index = 0; 2660 rdev->pm.power_state[0].default_clock_mode = 2661 &rdev->pm.power_state[0].clock_info[0]; 2662 } 2663 return state_index; 2664 } 2665 2666 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev) 2667 { 2668 struct radeon_mode_info *mode_info = &rdev->mode_info; 2669 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2670 union pplib_power_state *power_state; 2671 int i, j, non_clock_array_index, clock_array_index; 2672 int state_index = 0, mode_index = 0; 2673 union pplib_clock_info *clock_info; 2674 struct _StateArray *state_array; 2675 struct _ClockInfoArray *clock_info_array; 2676 struct _NonClockInfoArray *non_clock_info_array; 2677 bool valid; 2678 union power_info *power_info; 2679 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2680 u16 data_offset; 2681 u8 frev, crev; 2682 u8 *power_state_offset; 2683 2684 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2685 &frev, &crev, &data_offset)) 2686 return state_index; 2687 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2688 2689 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2690 state_array = (struct _StateArray *) 2691 (mode_info->atom_context->bios + data_offset + 2692 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 2693 clock_info_array = (struct _ClockInfoArray *) 2694 (mode_info->atom_context->bios + data_offset + 2695 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 2696 non_clock_info_array = (struct _NonClockInfoArray *) 2697 (mode_info->atom_context->bios + data_offset + 2698 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 2699 if (state_array->ucNumEntries == 0) 2700 return state_index; 2701 rdev->pm.power_state = kcalloc(state_array->ucNumEntries, 2702 sizeof(struct radeon_power_state), 2703 GFP_KERNEL); 2704 if (!rdev->pm.power_state) 2705 return state_index; 2706 power_state_offset = (u8 *)state_array->states; 2707 for (i = 0; i < state_array->ucNumEntries; i++) { 2708 mode_index = 0; 2709 power_state = (union pplib_power_state *)power_state_offset; 2710 non_clock_array_index = power_state->v2.nonClockInfoIndex; 2711 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2712 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 2713 rdev->pm.power_state[i].clock_info = 2714 kcalloc(power_state->v2.ucNumDPMLevels ? 2715 power_state->v2.ucNumDPMLevels : 1, 2716 sizeof(struct radeon_pm_clock_info), 2717 GFP_KERNEL); 2718 if (!rdev->pm.power_state[i].clock_info) 2719 return state_index; 2720 if (power_state->v2.ucNumDPMLevels) { 2721 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 2722 clock_array_index = power_state->v2.clockInfoIndex[j]; 2723 clock_info = (union pplib_clock_info *) 2724 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 2725 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2726 state_index, mode_index, 2727 clock_info); 2728 if (valid) 2729 mode_index++; 2730 } 2731 } else { 2732 rdev->pm.power_state[state_index].clock_info[0].mclk = 2733 rdev->clock.default_mclk; 2734 rdev->pm.power_state[state_index].clock_info[0].sclk = 2735 rdev->clock.default_sclk; 2736 mode_index++; 2737 } 2738 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2739 if (mode_index) { 2740 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, 2741 non_clock_info); 2742 state_index++; 2743 } 2744 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 2745 } 2746 /* if multiple clock modes, mark the lowest as no display */ 2747 for (i = 0; i < state_index; i++) { 2748 if (rdev->pm.power_state[i].num_clock_modes > 1) 2749 rdev->pm.power_state[i].clock_info[0].flags |= 2750 RADEON_PM_MODE_NO_DISPLAY; 2751 } 2752 /* first mode is usually default */ 2753 if (rdev->pm.default_power_state_index == -1) { 2754 rdev->pm.power_state[0].type = 2755 POWER_STATE_TYPE_DEFAULT; 2756 rdev->pm.default_power_state_index = 0; 2757 rdev->pm.power_state[0].default_clock_mode = 2758 &rdev->pm.power_state[0].clock_info[0]; 2759 } 2760 return state_index; 2761 } 2762 2763 void radeon_atombios_get_power_modes(struct radeon_device *rdev) 2764 { 2765 struct radeon_mode_info *mode_info = &rdev->mode_info; 2766 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2767 u16 data_offset; 2768 u8 frev, crev; 2769 int state_index = 0; 2770 2771 rdev->pm.default_power_state_index = -1; 2772 2773 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2774 &frev, &crev, &data_offset)) { 2775 switch (frev) { 2776 case 1: 2777 case 2: 2778 case 3: 2779 state_index = radeon_atombios_parse_power_table_1_3(rdev); 2780 break; 2781 case 4: 2782 case 5: 2783 state_index = radeon_atombios_parse_power_table_4_5(rdev); 2784 break; 2785 case 6: 2786 state_index = radeon_atombios_parse_power_table_6(rdev); 2787 break; 2788 default: 2789 break; 2790 } 2791 } 2792 2793 if (state_index == 0) { 2794 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL); 2795 if (rdev->pm.power_state) { 2796 rdev->pm.power_state[0].clock_info = 2797 kcalloc(1, 2798 sizeof(struct radeon_pm_clock_info), 2799 GFP_KERNEL); 2800 if (rdev->pm.power_state[0].clock_info) { 2801 /* add the default mode */ 2802 rdev->pm.power_state[state_index].type = 2803 POWER_STATE_TYPE_DEFAULT; 2804 rdev->pm.power_state[state_index].num_clock_modes = 1; 2805 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 2806 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2807 rdev->pm.power_state[state_index].default_clock_mode = 2808 &rdev->pm.power_state[state_index].clock_info[0]; 2809 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2810 rdev->pm.power_state[state_index].pcie_lanes = 16; 2811 rdev->pm.default_power_state_index = state_index; 2812 rdev->pm.power_state[state_index].flags = 0; 2813 state_index++; 2814 } 2815 } 2816 } 2817 2818 rdev->pm.num_power_states = state_index; 2819 2820 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2821 rdev->pm.current_clock_mode_index = 0; 2822 if (rdev->pm.default_power_state_index >= 0) 2823 rdev->pm.current_vddc = 2824 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 2825 else 2826 rdev->pm.current_vddc = 0; 2827 } 2828 2829 union get_clock_dividers { 2830 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1; 2831 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2; 2832 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; 2833 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4; 2834 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; 2835 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in; 2836 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out; 2837 }; 2838 2839 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 2840 u8 clock_type, 2841 u32 clock, 2842 bool strobe_mode, 2843 struct atom_clock_dividers *dividers) 2844 { 2845 union get_clock_dividers args; 2846 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL); 2847 u8 frev, crev; 2848 2849 memset(&args, 0, sizeof(args)); 2850 memset(dividers, 0, sizeof(struct atom_clock_dividers)); 2851 2852 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2853 return -EINVAL; 2854 2855 switch (crev) { 2856 case 1: 2857 /* r4xx, r5xx */ 2858 args.v1.ucAction = clock_type; 2859 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */ 2860 2861 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2862 2863 dividers->post_div = args.v1.ucPostDiv; 2864 dividers->fb_div = args.v1.ucFbDiv; 2865 dividers->enable_post_div = true; 2866 break; 2867 case 2: 2868 case 3: 2869 case 5: 2870 /* r6xx, r7xx, evergreen, ni, si */ 2871 if (rdev->family <= CHIP_RV770) { 2872 args.v2.ucAction = clock_type; 2873 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */ 2874 2875 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2876 2877 dividers->post_div = args.v2.ucPostDiv; 2878 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); 2879 dividers->ref_div = args.v2.ucAction; 2880 if (rdev->family == CHIP_RV770) { 2881 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ? 2882 true : false; 2883 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0; 2884 } else 2885 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false; 2886 } else { 2887 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { 2888 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); 2889 2890 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2891 2892 dividers->post_div = args.v3.ucPostDiv; 2893 dividers->enable_post_div = (args.v3.ucCntlFlag & 2894 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 2895 dividers->enable_dithen = (args.v3.ucCntlFlag & 2896 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 2897 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); 2898 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); 2899 dividers->ref_div = args.v3.ucRefDiv; 2900 dividers->vco_mode = (args.v3.ucCntlFlag & 2901 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 2902 } else { 2903 /* for SI we use ComputeMemoryClockParam for memory plls */ 2904 if (rdev->family >= CHIP_TAHITI) 2905 return -EINVAL; 2906 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); 2907 if (strobe_mode) 2908 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN; 2909 2910 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2911 2912 dividers->post_div = args.v5.ucPostDiv; 2913 dividers->enable_post_div = (args.v5.ucCntlFlag & 2914 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 2915 dividers->enable_dithen = (args.v5.ucCntlFlag & 2916 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 2917 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv); 2918 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac); 2919 dividers->ref_div = args.v5.ucRefDiv; 2920 dividers->vco_mode = (args.v5.ucCntlFlag & 2921 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 2922 } 2923 } 2924 break; 2925 case 4: 2926 /* fusion */ 2927 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */ 2928 2929 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2930 2931 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; 2932 dividers->real_clock = le32_to_cpu(args.v4.ulClock); 2933 break; 2934 case 6: 2935 /* CI */ 2936 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */ 2937 args.v6_in.ulClock.ulComputeClockFlag = clock_type; 2938 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ 2939 2940 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2941 2942 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv); 2943 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac); 2944 dividers->ref_div = args.v6_out.ucPllRefDiv; 2945 dividers->post_div = args.v6_out.ucPllPostDiv; 2946 dividers->flags = args.v6_out.ucPllCntlFlag; 2947 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock); 2948 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; 2949 break; 2950 default: 2951 return -EINVAL; 2952 } 2953 return 0; 2954 } 2955 2956 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 2957 u32 clock, 2958 bool strobe_mode, 2959 struct atom_mpll_param *mpll_param) 2960 { 2961 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args; 2962 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam); 2963 u8 frev, crev; 2964 2965 memset(&args, 0, sizeof(args)); 2966 memset(mpll_param, 0, sizeof(struct atom_mpll_param)); 2967 2968 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2969 return -EINVAL; 2970 2971 switch (frev) { 2972 case 2: 2973 switch (crev) { 2974 case 1: 2975 /* SI */ 2976 args.ulClock = cpu_to_le32(clock); /* 10 khz */ 2977 args.ucInputFlag = 0; 2978 if (strobe_mode) 2979 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN; 2980 2981 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2982 2983 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac); 2984 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv); 2985 mpll_param->post_div = args.ucPostDiv; 2986 mpll_param->dll_speed = args.ucDllSpeed; 2987 mpll_param->bwcntl = args.ucBWCntl; 2988 mpll_param->vco_mode = 2989 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK); 2990 mpll_param->yclk_sel = 2991 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0; 2992 mpll_param->qdr = 2993 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0; 2994 mpll_param->half_rate = 2995 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0; 2996 break; 2997 default: 2998 return -EINVAL; 2999 } 3000 break; 3001 default: 3002 return -EINVAL; 3003 } 3004 return 0; 3005 } 3006 3007 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) 3008 { 3009 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args; 3010 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating); 3011 3012 args.ucEnable = enable; 3013 3014 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3015 } 3016 3017 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev) 3018 { 3019 GET_ENGINE_CLOCK_PS_ALLOCATION args; 3020 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); 3021 3022 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3023 return le32_to_cpu(args.ulReturnEngineClock); 3024 } 3025 3026 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev) 3027 { 3028 GET_MEMORY_CLOCK_PS_ALLOCATION args; 3029 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); 3030 3031 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3032 return le32_to_cpu(args.ulReturnMemoryClock); 3033 } 3034 3035 void radeon_atom_set_engine_clock(struct radeon_device *rdev, 3036 uint32_t eng_clock) 3037 { 3038 SET_ENGINE_CLOCK_PS_ALLOCATION args; 3039 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); 3040 3041 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */ 3042 3043 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3044 } 3045 3046 void radeon_atom_set_memory_clock(struct radeon_device *rdev, 3047 uint32_t mem_clock) 3048 { 3049 SET_MEMORY_CLOCK_PS_ALLOCATION args; 3050 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); 3051 3052 if (rdev->flags & RADEON_IS_IGP) 3053 return; 3054 3055 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */ 3056 3057 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3058 } 3059 3060 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 3061 u32 eng_clock, u32 mem_clock) 3062 { 3063 SET_ENGINE_CLOCK_PS_ALLOCATION args; 3064 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 3065 u32 tmp; 3066 3067 memset(&args, 0, sizeof(args)); 3068 3069 tmp = eng_clock & SET_CLOCK_FREQ_MASK; 3070 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24); 3071 3072 args.ulTargetEngineClock = cpu_to_le32(tmp); 3073 if (mem_clock) 3074 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK); 3075 3076 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3077 } 3078 3079 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 3080 u32 mem_clock) 3081 { 3082 u32 args; 3083 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 3084 3085 args = cpu_to_le32(mem_clock); /* 10 khz */ 3086 3087 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3088 } 3089 3090 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 3091 u32 mem_clock) 3092 { 3093 SET_MEMORY_CLOCK_PS_ALLOCATION args; 3094 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 3095 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24); 3096 3097 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */ 3098 3099 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3100 } 3101 3102 union set_voltage { 3103 struct _SET_VOLTAGE_PS_ALLOCATION alloc; 3104 struct _SET_VOLTAGE_PARAMETERS v1; 3105 struct _SET_VOLTAGE_PARAMETERS_V2 v2; 3106 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; 3107 }; 3108 3109 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type) 3110 { 3111 union set_voltage args; 3112 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3113 u8 frev, crev, volt_index = voltage_level; 3114 3115 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3116 return; 3117 3118 /* 0xff01 is a flag rather then an actual voltage */ 3119 if (voltage_level == 0xff01) 3120 return; 3121 3122 switch (crev) { 3123 case 1: 3124 args.v1.ucVoltageType = voltage_type; 3125 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE; 3126 args.v1.ucVoltageIndex = volt_index; 3127 break; 3128 case 2: 3129 args.v2.ucVoltageType = voltage_type; 3130 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE; 3131 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3132 break; 3133 case 3: 3134 args.v3.ucVoltageType = voltage_type; 3135 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE; 3136 args.v3.usVoltageLevel = cpu_to_le16(voltage_level); 3137 break; 3138 default: 3139 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3140 return; 3141 } 3142 3143 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3144 } 3145 3146 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 3147 u16 voltage_id, u16 *voltage) 3148 { 3149 union set_voltage args; 3150 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3151 u8 frev, crev; 3152 3153 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3154 return -EINVAL; 3155 3156 switch (crev) { 3157 case 1: 3158 return -EINVAL; 3159 case 2: 3160 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE; 3161 args.v2.ucVoltageMode = 0; 3162 args.v2.usVoltageLevel = 0; 3163 3164 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3165 3166 *voltage = le16_to_cpu(args.v2.usVoltageLevel); 3167 break; 3168 case 3: 3169 args.v3.ucVoltageType = voltage_type; 3170 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL; 3171 args.v3.usVoltageLevel = cpu_to_le16(voltage_id); 3172 3173 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3174 3175 *voltage = le16_to_cpu(args.v3.usVoltageLevel); 3176 break; 3177 default: 3178 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3179 return -EINVAL; 3180 } 3181 3182 return 0; 3183 } 3184 3185 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 3186 u16 *voltage, 3187 u16 leakage_idx) 3188 { 3189 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage); 3190 } 3191 3192 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 3193 u16 *leakage_id) 3194 { 3195 union set_voltage args; 3196 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3197 u8 frev, crev; 3198 3199 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3200 return -EINVAL; 3201 3202 switch (crev) { 3203 case 3: 3204 case 4: 3205 args.v3.ucVoltageType = 0; 3206 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID; 3207 args.v3.usVoltageLevel = 0; 3208 3209 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3210 3211 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel); 3212 break; 3213 default: 3214 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3215 return -EINVAL; 3216 } 3217 3218 return 0; 3219 } 3220 3221 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 3222 u16 *vddc, u16 *vddci, 3223 u16 virtual_voltage_id, 3224 u16 vbios_voltage_id) 3225 { 3226 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo); 3227 u8 frev, crev; 3228 u16 data_offset, size; 3229 int i, j; 3230 ATOM_ASIC_PROFILING_INFO_V2_1 *profile; 3231 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf; 3232 3233 *vddc = 0; 3234 *vddci = 0; 3235 3236 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3237 &frev, &crev, &data_offset)) 3238 return -EINVAL; 3239 3240 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *) 3241 (rdev->mode_info.atom_context->bios + data_offset); 3242 3243 switch (frev) { 3244 case 1: 3245 return -EINVAL; 3246 case 2: 3247 switch (crev) { 3248 case 1: 3249 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1)) 3250 return -EINVAL; 3251 leakage_bin = (u16 *) 3252 (rdev->mode_info.atom_context->bios + data_offset + 3253 le16_to_cpu(profile->usLeakageBinArrayOffset)); 3254 vddc_id_buf = (u16 *) 3255 (rdev->mode_info.atom_context->bios + data_offset + 3256 le16_to_cpu(profile->usElbVDDC_IdArrayOffset)); 3257 vddc_buf = (u16 *) 3258 (rdev->mode_info.atom_context->bios + data_offset + 3259 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset)); 3260 vddci_id_buf = (u16 *) 3261 (rdev->mode_info.atom_context->bios + data_offset + 3262 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset)); 3263 vddci_buf = (u16 *) 3264 (rdev->mode_info.atom_context->bios + data_offset + 3265 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset)); 3266 3267 if (profile->ucElbVDDC_Num > 0) { 3268 for (i = 0; i < profile->ucElbVDDC_Num; i++) { 3269 if (vddc_id_buf[i] == virtual_voltage_id) { 3270 for (j = 0; j < profile->ucLeakageBinNum; j++) { 3271 if (vbios_voltage_id <= leakage_bin[j]) { 3272 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i]; 3273 break; 3274 } 3275 } 3276 break; 3277 } 3278 } 3279 } 3280 if (profile->ucElbVDDCI_Num > 0) { 3281 for (i = 0; i < profile->ucElbVDDCI_Num; i++) { 3282 if (vddci_id_buf[i] == virtual_voltage_id) { 3283 for (j = 0; j < profile->ucLeakageBinNum; j++) { 3284 if (vbios_voltage_id <= leakage_bin[j]) { 3285 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i]; 3286 break; 3287 } 3288 } 3289 break; 3290 } 3291 } 3292 } 3293 break; 3294 default: 3295 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3296 return -EINVAL; 3297 } 3298 break; 3299 default: 3300 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3301 return -EINVAL; 3302 } 3303 3304 return 0; 3305 } 3306 3307 union get_voltage_info { 3308 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in; 3309 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out; 3310 }; 3311 3312 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 3313 u16 virtual_voltage_id, 3314 u16 *voltage) 3315 { 3316 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo); 3317 u32 entry_id; 3318 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; 3319 union get_voltage_info args; 3320 3321 for (entry_id = 0; entry_id < count; entry_id++) { 3322 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == 3323 virtual_voltage_id) 3324 break; 3325 } 3326 3327 if (entry_id >= count) 3328 return -EINVAL; 3329 3330 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC; 3331 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE; 3332 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id); 3333 args.in.ulSCLKFreq = 3334 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); 3335 3336 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3337 3338 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel); 3339 3340 return 0; 3341 } 3342 3343 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 3344 u16 voltage_level, u8 voltage_type, 3345 u32 *gpio_value, u32 *gpio_mask) 3346 { 3347 union set_voltage args; 3348 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3349 u8 frev, crev; 3350 3351 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3352 return -EINVAL; 3353 3354 switch (crev) { 3355 case 1: 3356 return -EINVAL; 3357 case 2: 3358 args.v2.ucVoltageType = voltage_type; 3359 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK; 3360 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3361 3362 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3363 3364 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2); 3365 3366 args.v2.ucVoltageType = voltage_type; 3367 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL; 3368 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3369 3370 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3371 3372 *gpio_value = le32_to_cpu(*(u32 *)&args.v2); 3373 break; 3374 default: 3375 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3376 return -EINVAL; 3377 } 3378 3379 return 0; 3380 } 3381 3382 union voltage_object_info { 3383 struct _ATOM_VOLTAGE_OBJECT_INFO v1; 3384 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2; 3385 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; 3386 }; 3387 3388 union voltage_object { 3389 struct _ATOM_VOLTAGE_OBJECT v1; 3390 struct _ATOM_VOLTAGE_OBJECT_V2 v2; 3391 union _ATOM_VOLTAGE_OBJECT_V3 v3; 3392 }; 3393 3394 static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1, 3395 u8 voltage_type) 3396 { 3397 u32 size = le16_to_cpu(v1->sHeader.usStructureSize); 3398 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]); 3399 u8 *start = (u8 *)v1; 3400 3401 while (offset < size) { 3402 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset); 3403 if (vo->ucVoltageType == voltage_type) 3404 return vo; 3405 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) + 3406 vo->asFormula.ucNumOfVoltageEntries; 3407 } 3408 return NULL; 3409 } 3410 3411 static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2, 3412 u8 voltage_type) 3413 { 3414 u32 size = le16_to_cpu(v2->sHeader.usStructureSize); 3415 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]); 3416 u8 *start = (u8 *)v2; 3417 3418 while (offset < size) { 3419 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset); 3420 if (vo->ucVoltageType == voltage_type) 3421 return vo; 3422 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) + 3423 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY)); 3424 } 3425 return NULL; 3426 } 3427 3428 static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3, 3429 u8 voltage_type, u8 voltage_mode) 3430 { 3431 u32 size = le16_to_cpu(v3->sHeader.usStructureSize); 3432 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]); 3433 u8 *start = (u8 *)v3; 3434 3435 while (offset < size) { 3436 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset); 3437 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) && 3438 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode)) 3439 return vo; 3440 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize); 3441 } 3442 return NULL; 3443 } 3444 3445 bool 3446 radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 3447 u8 voltage_type, u8 voltage_mode) 3448 { 3449 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3450 u8 frev, crev; 3451 u16 data_offset, size; 3452 union voltage_object_info *voltage_info; 3453 union voltage_object *voltage_object = NULL; 3454 3455 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3456 &frev, &crev, &data_offset)) { 3457 voltage_info = (union voltage_object_info *) 3458 (rdev->mode_info.atom_context->bios + data_offset); 3459 3460 switch (frev) { 3461 case 1: 3462 case 2: 3463 switch (crev) { 3464 case 1: 3465 voltage_object = (union voltage_object *) 3466 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3467 if (voltage_object && 3468 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO)) 3469 return true; 3470 break; 3471 case 2: 3472 voltage_object = (union voltage_object *) 3473 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3474 if (voltage_object && 3475 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO)) 3476 return true; 3477 break; 3478 default: 3479 DRM_ERROR("unknown voltage object table\n"); 3480 return false; 3481 } 3482 break; 3483 case 3: 3484 switch (crev) { 3485 case 1: 3486 if (atom_lookup_voltage_object_v3(&voltage_info->v3, 3487 voltage_type, voltage_mode)) 3488 return true; 3489 break; 3490 default: 3491 DRM_ERROR("unknown voltage object table\n"); 3492 return false; 3493 } 3494 break; 3495 default: 3496 DRM_ERROR("unknown voltage object table\n"); 3497 return false; 3498 } 3499 3500 } 3501 return false; 3502 } 3503 3504 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 3505 u8 voltage_type, 3506 u8 *svd_gpio_id, u8 *svc_gpio_id) 3507 { 3508 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3509 u8 frev, crev; 3510 u16 data_offset, size; 3511 union voltage_object_info *voltage_info; 3512 union voltage_object *voltage_object = NULL; 3513 3514 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3515 &frev, &crev, &data_offset)) { 3516 voltage_info = (union voltage_object_info *) 3517 (rdev->mode_info.atom_context->bios + data_offset); 3518 3519 switch (frev) { 3520 case 3: 3521 switch (crev) { 3522 case 1: 3523 voltage_object = (union voltage_object *) 3524 atom_lookup_voltage_object_v3(&voltage_info->v3, 3525 voltage_type, 3526 VOLTAGE_OBJ_SVID2); 3527 if (voltage_object) { 3528 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId; 3529 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId; 3530 } else { 3531 return -EINVAL; 3532 } 3533 break; 3534 default: 3535 DRM_ERROR("unknown voltage object table\n"); 3536 return -EINVAL; 3537 } 3538 break; 3539 default: 3540 DRM_ERROR("unknown voltage object table\n"); 3541 return -EINVAL; 3542 } 3543 3544 } 3545 return 0; 3546 } 3547 3548 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 3549 u8 voltage_type, u16 *max_voltage) 3550 { 3551 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3552 u8 frev, crev; 3553 u16 data_offset, size; 3554 union voltage_object_info *voltage_info; 3555 union voltage_object *voltage_object = NULL; 3556 3557 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3558 &frev, &crev, &data_offset)) { 3559 voltage_info = (union voltage_object_info *) 3560 (rdev->mode_info.atom_context->bios + data_offset); 3561 3562 switch (crev) { 3563 case 1: 3564 voltage_object = (union voltage_object *) 3565 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3566 if (voltage_object) { 3567 ATOM_VOLTAGE_FORMULA *formula = 3568 &voltage_object->v1.asFormula; 3569 if (formula->ucFlag & 1) 3570 *max_voltage = 3571 le16_to_cpu(formula->usVoltageBaseLevel) + 3572 formula->ucNumOfVoltageEntries / 2 * 3573 le16_to_cpu(formula->usVoltageStep); 3574 else 3575 *max_voltage = 3576 le16_to_cpu(formula->usVoltageBaseLevel) + 3577 (formula->ucNumOfVoltageEntries - 1) * 3578 le16_to_cpu(formula->usVoltageStep); 3579 return 0; 3580 } 3581 break; 3582 case 2: 3583 voltage_object = (union voltage_object *) 3584 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3585 if (voltage_object) { 3586 ATOM_VOLTAGE_FORMULA_V2 *formula = 3587 &voltage_object->v2.asFormula; 3588 if (formula->ucNumOfVoltageEntries) { 3589 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *) 3590 ((u8 *)&formula->asVIDAdjustEntries[0] + 3591 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1))); 3592 *max_voltage = 3593 le16_to_cpu(lut->usVoltageValue); 3594 return 0; 3595 } 3596 } 3597 break; 3598 default: 3599 DRM_ERROR("unknown voltage object table\n"); 3600 return -EINVAL; 3601 } 3602 3603 } 3604 return -EINVAL; 3605 } 3606 3607 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 3608 u8 voltage_type, u16 *min_voltage) 3609 { 3610 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3611 u8 frev, crev; 3612 u16 data_offset, size; 3613 union voltage_object_info *voltage_info; 3614 union voltage_object *voltage_object = NULL; 3615 3616 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3617 &frev, &crev, &data_offset)) { 3618 voltage_info = (union voltage_object_info *) 3619 (rdev->mode_info.atom_context->bios + data_offset); 3620 3621 switch (crev) { 3622 case 1: 3623 voltage_object = (union voltage_object *) 3624 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3625 if (voltage_object) { 3626 ATOM_VOLTAGE_FORMULA *formula = 3627 &voltage_object->v1.asFormula; 3628 *min_voltage = 3629 le16_to_cpu(formula->usVoltageBaseLevel); 3630 return 0; 3631 } 3632 break; 3633 case 2: 3634 voltage_object = (union voltage_object *) 3635 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3636 if (voltage_object) { 3637 ATOM_VOLTAGE_FORMULA_V2 *formula = 3638 &voltage_object->v2.asFormula; 3639 if (formula->ucNumOfVoltageEntries) { 3640 *min_voltage = 3641 le16_to_cpu(formula->asVIDAdjustEntries[ 3642 0 3643 ].usVoltageValue); 3644 return 0; 3645 } 3646 } 3647 break; 3648 default: 3649 DRM_ERROR("unknown voltage object table\n"); 3650 return -EINVAL; 3651 } 3652 3653 } 3654 return -EINVAL; 3655 } 3656 3657 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 3658 u8 voltage_type, u16 *voltage_step) 3659 { 3660 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3661 u8 frev, crev; 3662 u16 data_offset, size; 3663 union voltage_object_info *voltage_info; 3664 union voltage_object *voltage_object = NULL; 3665 3666 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3667 &frev, &crev, &data_offset)) { 3668 voltage_info = (union voltage_object_info *) 3669 (rdev->mode_info.atom_context->bios + data_offset); 3670 3671 switch (crev) { 3672 case 1: 3673 voltage_object = (union voltage_object *) 3674 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3675 if (voltage_object) { 3676 ATOM_VOLTAGE_FORMULA *formula = 3677 &voltage_object->v1.asFormula; 3678 if (formula->ucFlag & 1) 3679 *voltage_step = 3680 (le16_to_cpu(formula->usVoltageStep) + 1) / 2; 3681 else 3682 *voltage_step = 3683 le16_to_cpu(formula->usVoltageStep); 3684 return 0; 3685 } 3686 break; 3687 case 2: 3688 return -EINVAL; 3689 default: 3690 DRM_ERROR("unknown voltage object table\n"); 3691 return -EINVAL; 3692 } 3693 3694 } 3695 return -EINVAL; 3696 } 3697 3698 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 3699 u8 voltage_type, 3700 u16 nominal_voltage, 3701 u16 *true_voltage) 3702 { 3703 u16 min_voltage, max_voltage, voltage_step; 3704 3705 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage)) 3706 return -EINVAL; 3707 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage)) 3708 return -EINVAL; 3709 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step)) 3710 return -EINVAL; 3711 3712 if (nominal_voltage <= min_voltage) 3713 *true_voltage = min_voltage; 3714 else if (nominal_voltage >= max_voltage) 3715 *true_voltage = max_voltage; 3716 else 3717 *true_voltage = min_voltage + 3718 ((nominal_voltage - min_voltage) / voltage_step) * 3719 voltage_step; 3720 3721 return 0; 3722 } 3723 3724 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 3725 u8 voltage_type, u8 voltage_mode, 3726 struct atom_voltage_table *voltage_table) 3727 { 3728 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3729 u8 frev, crev; 3730 u16 data_offset, size; 3731 int i, ret; 3732 union voltage_object_info *voltage_info; 3733 union voltage_object *voltage_object = NULL; 3734 3735 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3736 &frev, &crev, &data_offset)) { 3737 voltage_info = (union voltage_object_info *) 3738 (rdev->mode_info.atom_context->bios + data_offset); 3739 3740 switch (frev) { 3741 case 1: 3742 case 2: 3743 switch (crev) { 3744 case 1: 3745 DRM_ERROR("old table version %d, %d\n", frev, crev); 3746 return -EINVAL; 3747 case 2: 3748 voltage_object = (union voltage_object *) 3749 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3750 if (voltage_object) { 3751 ATOM_VOLTAGE_FORMULA_V2 *formula = 3752 &voltage_object->v2.asFormula; 3753 VOLTAGE_LUT_ENTRY *lut; 3754 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES) 3755 return -EINVAL; 3756 lut = &formula->asVIDAdjustEntries[0]; 3757 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) { 3758 voltage_table->entries[i].value = 3759 le16_to_cpu(lut->usVoltageValue); 3760 ret = radeon_atom_get_voltage_gpio_settings(rdev, 3761 voltage_table->entries[i].value, 3762 voltage_type, 3763 &voltage_table->entries[i].smio_low, 3764 &voltage_table->mask_low); 3765 if (ret) 3766 return ret; 3767 lut = (VOLTAGE_LUT_ENTRY *) 3768 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY)); 3769 } 3770 voltage_table->count = formula->ucNumOfVoltageEntries; 3771 return 0; 3772 } 3773 break; 3774 default: 3775 DRM_ERROR("unknown voltage object table\n"); 3776 return -EINVAL; 3777 } 3778 break; 3779 case 3: 3780 switch (crev) { 3781 case 1: 3782 voltage_object = (union voltage_object *) 3783 atom_lookup_voltage_object_v3(&voltage_info->v3, 3784 voltage_type, voltage_mode); 3785 if (voltage_object) { 3786 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio = 3787 &voltage_object->v3.asGpioVoltageObj; 3788 VOLTAGE_LUT_ENTRY_V2 *lut; 3789 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES) 3790 return -EINVAL; 3791 lut = &gpio->asVolGpioLut[0]; 3792 for (i = 0; i < gpio->ucGpioEntryNum; i++) { 3793 voltage_table->entries[i].value = 3794 le16_to_cpu(lut->usVoltageValue); 3795 voltage_table->entries[i].smio_low = 3796 le32_to_cpu(lut->ulVoltageId); 3797 lut = (VOLTAGE_LUT_ENTRY_V2 *) 3798 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2)); 3799 } 3800 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal); 3801 voltage_table->count = gpio->ucGpioEntryNum; 3802 voltage_table->phase_delay = gpio->ucPhaseDelay; 3803 return 0; 3804 } 3805 break; 3806 default: 3807 DRM_ERROR("unknown voltage object table\n"); 3808 return -EINVAL; 3809 } 3810 break; 3811 default: 3812 DRM_ERROR("unknown voltage object table\n"); 3813 return -EINVAL; 3814 } 3815 } 3816 return -EINVAL; 3817 } 3818 3819 union vram_info { 3820 struct _ATOM_VRAM_INFO_V3 v1_3; 3821 struct _ATOM_VRAM_INFO_V4 v1_4; 3822 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; 3823 }; 3824 3825 int radeon_atom_get_memory_info(struct radeon_device *rdev, 3826 u8 module_index, struct atom_memory_info *mem_info) 3827 { 3828 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3829 u8 frev, crev, i; 3830 u16 data_offset, size; 3831 union vram_info *vram_info; 3832 3833 memset(mem_info, 0, sizeof(struct atom_memory_info)); 3834 3835 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3836 &frev, &crev, &data_offset)) { 3837 vram_info = (union vram_info *) 3838 (rdev->mode_info.atom_context->bios + data_offset); 3839 switch (frev) { 3840 case 1: 3841 switch (crev) { 3842 case 3: 3843 /* r6xx */ 3844 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) { 3845 ATOM_VRAM_MODULE_V3 *vram_module = 3846 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo; 3847 3848 for (i = 0; i < module_index; i++) { 3849 if (le16_to_cpu(vram_module->usSize) == 0) 3850 return -EINVAL; 3851 vram_module = (ATOM_VRAM_MODULE_V3 *) 3852 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize)); 3853 } 3854 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf; 3855 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0; 3856 } else 3857 return -EINVAL; 3858 break; 3859 case 4: 3860 /* r7xx, evergreen */ 3861 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) { 3862 ATOM_VRAM_MODULE_V4 *vram_module = 3863 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo; 3864 3865 for (i = 0; i < module_index; i++) { 3866 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3867 return -EINVAL; 3868 vram_module = (ATOM_VRAM_MODULE_V4 *) 3869 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3870 } 3871 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf; 3872 mem_info->mem_type = vram_module->ucMemoryType & 0xf0; 3873 } else 3874 return -EINVAL; 3875 break; 3876 default: 3877 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3878 return -EINVAL; 3879 } 3880 break; 3881 case 2: 3882 switch (crev) { 3883 case 1: 3884 /* ni */ 3885 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { 3886 ATOM_VRAM_MODULE_V7 *vram_module = 3887 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo; 3888 3889 for (i = 0; i < module_index; i++) { 3890 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3891 return -EINVAL; 3892 vram_module = (ATOM_VRAM_MODULE_V7 *) 3893 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3894 } 3895 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf; 3896 mem_info->mem_type = vram_module->ucMemoryType & 0xf0; 3897 } else 3898 return -EINVAL; 3899 break; 3900 default: 3901 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3902 return -EINVAL; 3903 } 3904 break; 3905 default: 3906 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3907 return -EINVAL; 3908 } 3909 return 0; 3910 } 3911 return -EINVAL; 3912 } 3913 3914 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 3915 bool gddr5, u8 module_index, 3916 struct atom_memory_clock_range_table *mclk_range_table) 3917 { 3918 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3919 u8 frev, crev, i; 3920 u16 data_offset, size; 3921 union vram_info *vram_info; 3922 u32 mem_timing_size = gddr5 ? 3923 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT); 3924 3925 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table)); 3926 3927 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3928 &frev, &crev, &data_offset)) { 3929 vram_info = (union vram_info *) 3930 (rdev->mode_info.atom_context->bios + data_offset); 3931 switch (frev) { 3932 case 1: 3933 switch (crev) { 3934 case 3: 3935 DRM_ERROR("old table version %d, %d\n", frev, crev); 3936 return -EINVAL; 3937 case 4: 3938 /* r7xx, evergreen */ 3939 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) { 3940 ATOM_VRAM_MODULE_V4 *vram_module = 3941 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo; 3942 ATOM_MEMORY_TIMING_FORMAT *format; 3943 3944 for (i = 0; i < module_index; i++) { 3945 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3946 return -EINVAL; 3947 vram_module = (ATOM_VRAM_MODULE_V4 *) 3948 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3949 } 3950 mclk_range_table->num_entries = (u8) 3951 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) / 3952 mem_timing_size); 3953 format = &vram_module->asMemTiming[0]; 3954 for (i = 0; i < mclk_range_table->num_entries; i++) { 3955 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange); 3956 format = (ATOM_MEMORY_TIMING_FORMAT *) 3957 ((u8 *)format + mem_timing_size); 3958 } 3959 } else 3960 return -EINVAL; 3961 break; 3962 default: 3963 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3964 return -EINVAL; 3965 } 3966 break; 3967 case 2: 3968 DRM_ERROR("new table version %d, %d\n", frev, crev); 3969 return -EINVAL; 3970 default: 3971 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3972 return -EINVAL; 3973 } 3974 return 0; 3975 } 3976 return -EINVAL; 3977 } 3978 3979 #define MEM_ID_MASK 0xff000000 3980 #define MEM_ID_SHIFT 24 3981 #define CLOCK_RANGE_MASK 0x00ffffff 3982 #define CLOCK_RANGE_SHIFT 0 3983 #define LOW_NIBBLE_MASK 0xf 3984 #define DATA_EQU_PREV 0 3985 #define DATA_FROM_TABLE 4 3986 3987 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 3988 u8 module_index, 3989 struct atom_mc_reg_table *reg_table) 3990 { 3991 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3992 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0; 3993 u32 i = 0, j; 3994 u16 data_offset, size; 3995 union vram_info *vram_info; 3996 3997 memset(reg_table, 0, sizeof(struct atom_mc_reg_table)); 3998 3999 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 4000 &frev, &crev, &data_offset)) { 4001 vram_info = (union vram_info *) 4002 (rdev->mode_info.atom_context->bios + data_offset); 4003 switch (frev) { 4004 case 1: 4005 DRM_ERROR("old table version %d, %d\n", frev, crev); 4006 return -EINVAL; 4007 case 2: 4008 switch (crev) { 4009 case 1: 4010 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { 4011 ATOM_INIT_REG_BLOCK *reg_block = 4012 (ATOM_INIT_REG_BLOCK *) 4013 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); 4014 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = 4015 (ATOM_MEMORY_SETTING_DATA_BLOCK *) 4016 ((u8 *)reg_block + (2 * sizeof(u16)) + 4017 le16_to_cpu(reg_block->usRegIndexTblSize)); 4018 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0]; 4019 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) / 4020 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1; 4021 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE) 4022 return -EINVAL; 4023 while (i < num_entries) { 4024 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER) 4025 break; 4026 reg_table->mc_reg_address[i].s1 = 4027 (u16)(le16_to_cpu(format->usRegIndex)); 4028 reg_table->mc_reg_address[i].pre_reg_data = 4029 (u8)(format->ucPreRegDataLength); 4030 i++; 4031 format = (ATOM_INIT_REG_INDEX_FORMAT *) 4032 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT)); 4033 } 4034 reg_table->last = i; 4035 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && 4036 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) { 4037 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) 4038 >> MEM_ID_SHIFT); 4039 if (module_index == t_mem_id) { 4040 reg_table->mc_reg_table_entry[num_ranges].mclk_max = 4041 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) 4042 >> CLOCK_RANGE_SHIFT); 4043 for (i = 0, j = 1; i < reg_table->last; i++) { 4044 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { 4045 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 4046 (u32)le32_to_cpu(*((u32 *)reg_data + j)); 4047 j++; 4048 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { 4049 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 4050 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1]; 4051 } 4052 } 4053 num_ranges++; 4054 } 4055 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) 4056 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); 4057 } 4058 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) 4059 return -EINVAL; 4060 reg_table->num_entries = num_ranges; 4061 } else 4062 return -EINVAL; 4063 break; 4064 default: 4065 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 4066 return -EINVAL; 4067 } 4068 break; 4069 default: 4070 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 4071 return -EINVAL; 4072 } 4073 return 0; 4074 } 4075 return -EINVAL; 4076 } 4077 4078 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) 4079 { 4080 struct radeon_device *rdev = dev->dev_private; 4081 uint32_t bios_2_scratch, bios_6_scratch; 4082 4083 if (rdev->family >= CHIP_R600) { 4084 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 4085 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 4086 } else { 4087 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 4088 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 4089 } 4090 4091 /* let the bios control the backlight */ 4092 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; 4093 4094 /* tell the bios not to handle mode switching */ 4095 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; 4096 4097 /* clear the vbios dpms state */ 4098 if (ASIC_IS_DCE4(rdev)) 4099 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE; 4100 4101 if (rdev->family >= CHIP_R600) { 4102 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 4103 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 4104 } else { 4105 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 4106 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 4107 } 4108 4109 } 4110 4111 void radeon_save_bios_scratch_regs(struct radeon_device *rdev) 4112 { 4113 uint32_t scratch_reg; 4114 int i; 4115 4116 if (rdev->family >= CHIP_R600) 4117 scratch_reg = R600_BIOS_0_SCRATCH; 4118 else 4119 scratch_reg = RADEON_BIOS_0_SCRATCH; 4120 4121 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) 4122 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4)); 4123 } 4124 4125 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev) 4126 { 4127 uint32_t scratch_reg; 4128 int i; 4129 4130 if (rdev->family >= CHIP_R600) 4131 scratch_reg = R600_BIOS_0_SCRATCH; 4132 else 4133 scratch_reg = RADEON_BIOS_0_SCRATCH; 4134 4135 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) 4136 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]); 4137 } 4138 4139 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) 4140 { 4141 struct drm_device *dev = encoder->dev; 4142 struct radeon_device *rdev = dev->dev_private; 4143 uint32_t bios_6_scratch; 4144 4145 if (rdev->family >= CHIP_R600) 4146 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 4147 else 4148 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 4149 4150 if (lock) { 4151 bios_6_scratch |= ATOM_S6_CRITICAL_STATE; 4152 bios_6_scratch &= ~ATOM_S6_ACC_MODE; 4153 } else { 4154 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; 4155 bios_6_scratch |= ATOM_S6_ACC_MODE; 4156 } 4157 4158 if (rdev->family >= CHIP_R600) 4159 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 4160 else 4161 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 4162 } 4163 4164 /* at some point we may want to break this out into individual functions */ 4165 void 4166 radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 4167 struct drm_encoder *encoder, 4168 bool connected) 4169 { 4170 struct drm_device *dev = connector->dev; 4171 struct radeon_device *rdev = dev->dev_private; 4172 struct radeon_connector *radeon_connector = 4173 to_radeon_connector(connector); 4174 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4175 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch; 4176 4177 if (rdev->family >= CHIP_R600) { 4178 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 4179 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 4180 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 4181 } else { 4182 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 4183 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 4184 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 4185 } 4186 4187 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 4188 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 4189 if (connected) { 4190 DRM_DEBUG_KMS("TV1 connected\n"); 4191 bios_3_scratch |= ATOM_S3_TV1_ACTIVE; 4192 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1; 4193 } else { 4194 DRM_DEBUG_KMS("TV1 disconnected\n"); 4195 bios_0_scratch &= ~ATOM_S0_TV1_MASK; 4196 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; 4197 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1; 4198 } 4199 } 4200 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) && 4201 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) { 4202 if (connected) { 4203 DRM_DEBUG_KMS("CV connected\n"); 4204 bios_3_scratch |= ATOM_S3_CV_ACTIVE; 4205 bios_6_scratch |= ATOM_S6_ACC_REQ_CV; 4206 } else { 4207 DRM_DEBUG_KMS("CV disconnected\n"); 4208 bios_0_scratch &= ~ATOM_S0_CV_MASK; 4209 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; 4210 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV; 4211 } 4212 } 4213 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 4214 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 4215 if (connected) { 4216 DRM_DEBUG_KMS("LCD1 connected\n"); 4217 bios_0_scratch |= ATOM_S0_LCD1; 4218 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; 4219 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; 4220 } else { 4221 DRM_DEBUG_KMS("LCD1 disconnected\n"); 4222 bios_0_scratch &= ~ATOM_S0_LCD1; 4223 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; 4224 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; 4225 } 4226 } 4227 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 4228 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 4229 if (connected) { 4230 DRM_DEBUG_KMS("CRT1 connected\n"); 4231 bios_0_scratch |= ATOM_S0_CRT1_COLOR; 4232 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; 4233 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; 4234 } else { 4235 DRM_DEBUG_KMS("CRT1 disconnected\n"); 4236 bios_0_scratch &= ~ATOM_S0_CRT1_MASK; 4237 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; 4238 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; 4239 } 4240 } 4241 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 4242 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 4243 if (connected) { 4244 DRM_DEBUG_KMS("CRT2 connected\n"); 4245 bios_0_scratch |= ATOM_S0_CRT2_COLOR; 4246 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; 4247 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; 4248 } else { 4249 DRM_DEBUG_KMS("CRT2 disconnected\n"); 4250 bios_0_scratch &= ~ATOM_S0_CRT2_MASK; 4251 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; 4252 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; 4253 } 4254 } 4255 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 4256 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 4257 if (connected) { 4258 DRM_DEBUG_KMS("DFP1 connected\n"); 4259 bios_0_scratch |= ATOM_S0_DFP1; 4260 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; 4261 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; 4262 } else { 4263 DRM_DEBUG_KMS("DFP1 disconnected\n"); 4264 bios_0_scratch &= ~ATOM_S0_DFP1; 4265 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; 4266 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; 4267 } 4268 } 4269 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 4270 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 4271 if (connected) { 4272 DRM_DEBUG_KMS("DFP2 connected\n"); 4273 bios_0_scratch |= ATOM_S0_DFP2; 4274 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; 4275 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; 4276 } else { 4277 DRM_DEBUG_KMS("DFP2 disconnected\n"); 4278 bios_0_scratch &= ~ATOM_S0_DFP2; 4279 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; 4280 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; 4281 } 4282 } 4283 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && 4284 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { 4285 if (connected) { 4286 DRM_DEBUG_KMS("DFP3 connected\n"); 4287 bios_0_scratch |= ATOM_S0_DFP3; 4288 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; 4289 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; 4290 } else { 4291 DRM_DEBUG_KMS("DFP3 disconnected\n"); 4292 bios_0_scratch &= ~ATOM_S0_DFP3; 4293 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; 4294 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; 4295 } 4296 } 4297 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && 4298 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { 4299 if (connected) { 4300 DRM_DEBUG_KMS("DFP4 connected\n"); 4301 bios_0_scratch |= ATOM_S0_DFP4; 4302 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; 4303 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; 4304 } else { 4305 DRM_DEBUG_KMS("DFP4 disconnected\n"); 4306 bios_0_scratch &= ~ATOM_S0_DFP4; 4307 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; 4308 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; 4309 } 4310 } 4311 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && 4312 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { 4313 if (connected) { 4314 DRM_DEBUG_KMS("DFP5 connected\n"); 4315 bios_0_scratch |= ATOM_S0_DFP5; 4316 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; 4317 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; 4318 } else { 4319 DRM_DEBUG_KMS("DFP5 disconnected\n"); 4320 bios_0_scratch &= ~ATOM_S0_DFP5; 4321 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; 4322 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; 4323 } 4324 } 4325 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) && 4326 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) { 4327 if (connected) { 4328 DRM_DEBUG_KMS("DFP6 connected\n"); 4329 bios_0_scratch |= ATOM_S0_DFP6; 4330 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE; 4331 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6; 4332 } else { 4333 DRM_DEBUG_KMS("DFP6 disconnected\n"); 4334 bios_0_scratch &= ~ATOM_S0_DFP6; 4335 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE; 4336 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6; 4337 } 4338 } 4339 4340 if (rdev->family >= CHIP_R600) { 4341 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); 4342 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 4343 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 4344 } else { 4345 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 4346 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 4347 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 4348 } 4349 } 4350 4351 void 4352 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 4353 { 4354 struct drm_device *dev = encoder->dev; 4355 struct radeon_device *rdev = dev->dev_private; 4356 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4357 uint32_t bios_3_scratch; 4358 4359 if (ASIC_IS_DCE4(rdev)) 4360 return; 4361 4362 if (rdev->family >= CHIP_R600) 4363 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 4364 else 4365 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 4366 4367 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 4368 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE; 4369 bios_3_scratch |= (crtc << 18); 4370 } 4371 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 4372 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE; 4373 bios_3_scratch |= (crtc << 24); 4374 } 4375 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 4376 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE; 4377 bios_3_scratch |= (crtc << 16); 4378 } 4379 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 4380 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE; 4381 bios_3_scratch |= (crtc << 20); 4382 } 4383 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 4384 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE; 4385 bios_3_scratch |= (crtc << 17); 4386 } 4387 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 4388 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE; 4389 bios_3_scratch |= (crtc << 19); 4390 } 4391 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 4392 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE; 4393 bios_3_scratch |= (crtc << 23); 4394 } 4395 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 4396 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE; 4397 bios_3_scratch |= (crtc << 25); 4398 } 4399 4400 if (rdev->family >= CHIP_R600) 4401 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 4402 else 4403 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 4404 } 4405 4406 void 4407 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 4408 { 4409 struct drm_device *dev = encoder->dev; 4410 struct radeon_device *rdev = dev->dev_private; 4411 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4412 uint32_t bios_2_scratch; 4413 4414 if (ASIC_IS_DCE4(rdev)) 4415 return; 4416 4417 if (rdev->family >= CHIP_R600) 4418 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 4419 else 4420 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 4421 4422 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 4423 if (on) 4424 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE; 4425 else 4426 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE; 4427 } 4428 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 4429 if (on) 4430 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE; 4431 else 4432 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE; 4433 } 4434 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 4435 if (on) 4436 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE; 4437 else 4438 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE; 4439 } 4440 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 4441 if (on) 4442 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE; 4443 else 4444 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE; 4445 } 4446 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 4447 if (on) 4448 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE; 4449 else 4450 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE; 4451 } 4452 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 4453 if (on) 4454 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE; 4455 else 4456 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE; 4457 } 4458 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 4459 if (on) 4460 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE; 4461 else 4462 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE; 4463 } 4464 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 4465 if (on) 4466 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE; 4467 else 4468 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE; 4469 } 4470 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) { 4471 if (on) 4472 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE; 4473 else 4474 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE; 4475 } 4476 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) { 4477 if (on) 4478 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE; 4479 else 4480 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE; 4481 } 4482 4483 if (rdev->family >= CHIP_R600) 4484 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 4485 else 4486 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 4487 } 4488