1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_ASIC_H__ 29 #define __RADEON_ASIC_H__ 30 31 /* 32 * common functions 33 */ 34 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); 35 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 36 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); 37 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 38 39 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); 40 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 41 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); 42 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); 43 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 44 45 /* 46 * r100,rv100,rs100,rv200,rs200 47 */ 48 struct r100_mc_save { 49 u32 GENMO_WT; 50 u32 CRTC_EXT_CNTL; 51 u32 CRTC_GEN_CNTL; 52 u32 CRTC2_GEN_CNTL; 53 u32 CUR_OFFSET; 54 u32 CUR2_OFFSET; 55 }; 56 int r100_init(struct radeon_device *rdev); 57 void r100_fini(struct radeon_device *rdev); 58 int r100_suspend(struct radeon_device *rdev); 59 int r100_resume(struct radeon_device *rdev); 60 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); 61 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 62 void r100_vga_set_state(struct radeon_device *rdev, bool state); 63 bool r100_gpu_is_lockup(struct radeon_device *rdev); 64 int r100_asic_reset(struct radeon_device *rdev); 65 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); 66 void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 67 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 68 void r100_cp_commit(struct radeon_device *rdev); 69 void r100_ring_start(struct radeon_device *rdev); 70 int r100_irq_set(struct radeon_device *rdev); 71 int r100_irq_process(struct radeon_device *rdev); 72 void r100_fence_ring_emit(struct radeon_device *rdev, 73 struct radeon_fence *fence); 74 int r100_cs_parse(struct radeon_cs_parser *p); 75 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 76 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); 77 int r100_copy_blit(struct radeon_device *rdev, 78 uint64_t src_offset, 79 uint64_t dst_offset, 80 unsigned num_pages, 81 struct radeon_fence *fence); 82 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 83 uint32_t tiling_flags, uint32_t pitch, 84 uint32_t offset, uint32_t obj_size); 85 void r100_clear_surface_reg(struct radeon_device *rdev, int reg); 86 void r100_bandwidth_update(struct radeon_device *rdev); 87 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 88 int r100_ring_test(struct radeon_device *rdev); 89 void r100_hpd_init(struct radeon_device *rdev); 90 void r100_hpd_fini(struct radeon_device *rdev); 91 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 92 void r100_hpd_set_polarity(struct radeon_device *rdev, 93 enum radeon_hpd_id hpd); 94 int r100_debugfs_rbbm_init(struct radeon_device *rdev); 95 int r100_debugfs_cp_init(struct radeon_device *rdev); 96 void r100_cp_disable(struct radeon_device *rdev); 97 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 98 void r100_cp_fini(struct radeon_device *rdev); 99 int r100_pci_gart_init(struct radeon_device *rdev); 100 void r100_pci_gart_fini(struct radeon_device *rdev); 101 int r100_pci_gart_enable(struct radeon_device *rdev); 102 void r100_pci_gart_disable(struct radeon_device *rdev); 103 int r100_debugfs_mc_info_init(struct radeon_device *rdev); 104 int r100_gui_wait_for_idle(struct radeon_device *rdev); 105 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, 106 struct radeon_cp *cp); 107 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, 108 struct r100_gpu_lockup *lockup, 109 struct radeon_cp *cp); 110 void r100_ib_fini(struct radeon_device *rdev); 111 int r100_ib_init(struct radeon_device *rdev); 112 void r100_irq_disable(struct radeon_device *rdev); 113 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); 114 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); 115 void r100_vram_init_sizes(struct radeon_device *rdev); 116 int r100_cp_reset(struct radeon_device *rdev); 117 void r100_vga_render_disable(struct radeon_device *rdev); 118 void r100_restore_sanity(struct radeon_device *rdev); 119 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 120 struct radeon_cs_packet *pkt, 121 struct radeon_bo *robj); 122 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 123 struct radeon_cs_packet *pkt, 124 const unsigned *auth, unsigned n, 125 radeon_packet0_check_t check); 126 int r100_cs_packet_parse(struct radeon_cs_parser *p, 127 struct radeon_cs_packet *pkt, 128 unsigned idx); 129 void r100_enable_bm(struct radeon_device *rdev); 130 void r100_set_common_regs(struct radeon_device *rdev); 131 void r100_bm_disable(struct radeon_device *rdev); 132 extern bool r100_gui_idle(struct radeon_device *rdev); 133 extern void r100_pm_misc(struct radeon_device *rdev); 134 extern void r100_pm_prepare(struct radeon_device *rdev); 135 extern void r100_pm_finish(struct radeon_device *rdev); 136 extern void r100_pm_init_profile(struct radeon_device *rdev); 137 extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); 138 extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc); 139 extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 140 extern void r100_post_page_flip(struct radeon_device *rdev, int crtc); 141 142 /* 143 * r200,rv250,rs300,rv280 144 */ 145 extern int r200_copy_dma(struct radeon_device *rdev, 146 uint64_t src_offset, 147 uint64_t dst_offset, 148 unsigned num_pages, 149 struct radeon_fence *fence); 150 void r200_set_safe_registers(struct radeon_device *rdev); 151 152 /* 153 * r300,r350,rv350,rv380 154 */ 155 extern int r300_init(struct radeon_device *rdev); 156 extern void r300_fini(struct radeon_device *rdev); 157 extern int r300_suspend(struct radeon_device *rdev); 158 extern int r300_resume(struct radeon_device *rdev); 159 extern bool r300_gpu_is_lockup(struct radeon_device *rdev); 160 extern int r300_asic_reset(struct radeon_device *rdev); 161 extern void r300_ring_start(struct radeon_device *rdev); 162 extern void r300_fence_ring_emit(struct radeon_device *rdev, 163 struct radeon_fence *fence); 164 extern int r300_cs_parse(struct radeon_cs_parser *p); 165 extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); 166 extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 167 extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); 168 extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 169 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); 170 extern int rv370_get_pcie_lanes(struct radeon_device *rdev); 171 extern void r300_set_reg_safe(struct radeon_device *rdev); 172 extern void r300_mc_program(struct radeon_device *rdev); 173 extern void r300_mc_init(struct radeon_device *rdev); 174 extern void r300_clock_startup(struct radeon_device *rdev); 175 extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 176 extern int rv370_pcie_gart_init(struct radeon_device *rdev); 177 extern void rv370_pcie_gart_fini(struct radeon_device *rdev); 178 extern int rv370_pcie_gart_enable(struct radeon_device *rdev); 179 extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 180 181 /* 182 * r420,r423,rv410 183 */ 184 extern int r420_init(struct radeon_device *rdev); 185 extern void r420_fini(struct radeon_device *rdev); 186 extern int r420_suspend(struct radeon_device *rdev); 187 extern int r420_resume(struct radeon_device *rdev); 188 extern void r420_pm_init_profile(struct radeon_device *rdev); 189 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 190 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 191 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 192 extern void r420_pipes_init(struct radeon_device *rdev); 193 194 /* 195 * rs400,rs480 196 */ 197 extern int rs400_init(struct radeon_device *rdev); 198 extern void rs400_fini(struct radeon_device *rdev); 199 extern int rs400_suspend(struct radeon_device *rdev); 200 extern int rs400_resume(struct radeon_device *rdev); 201 void rs400_gart_tlb_flush(struct radeon_device *rdev); 202 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 203 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); 204 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 205 int rs400_gart_init(struct radeon_device *rdev); 206 int rs400_gart_enable(struct radeon_device *rdev); 207 void rs400_gart_adjust_size(struct radeon_device *rdev); 208 void rs400_gart_disable(struct radeon_device *rdev); 209 void rs400_gart_fini(struct radeon_device *rdev); 210 211 212 /* 213 * rs600. 214 */ 215 extern int rs600_asic_reset(struct radeon_device *rdev); 216 extern int rs600_init(struct radeon_device *rdev); 217 extern void rs600_fini(struct radeon_device *rdev); 218 extern int rs600_suspend(struct radeon_device *rdev); 219 extern int rs600_resume(struct radeon_device *rdev); 220 int rs600_irq_set(struct radeon_device *rdev); 221 int rs600_irq_process(struct radeon_device *rdev); 222 void rs600_irq_disable(struct radeon_device *rdev); 223 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); 224 void rs600_gart_tlb_flush(struct radeon_device *rdev); 225 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 226 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); 227 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 228 void rs600_bandwidth_update(struct radeon_device *rdev); 229 void rs600_hpd_init(struct radeon_device *rdev); 230 void rs600_hpd_fini(struct radeon_device *rdev); 231 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 232 void rs600_hpd_set_polarity(struct radeon_device *rdev, 233 enum radeon_hpd_id hpd); 234 extern void rs600_pm_misc(struct radeon_device *rdev); 235 extern void rs600_pm_prepare(struct radeon_device *rdev); 236 extern void rs600_pm_finish(struct radeon_device *rdev); 237 extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc); 238 extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 239 extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc); 240 void rs600_set_safe_registers(struct radeon_device *rdev); 241 242 243 /* 244 * rs690,rs740 245 */ 246 int rs690_init(struct radeon_device *rdev); 247 void rs690_fini(struct radeon_device *rdev); 248 int rs690_resume(struct radeon_device *rdev); 249 int rs690_suspend(struct radeon_device *rdev); 250 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); 251 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 252 void rs690_bandwidth_update(struct radeon_device *rdev); 253 void rs690_line_buffer_adjust(struct radeon_device *rdev, 254 struct drm_display_mode *mode1, 255 struct drm_display_mode *mode2); 256 257 /* 258 * rv515 259 */ 260 struct rv515_mc_save { 261 u32 d1vga_control; 262 u32 d2vga_control; 263 u32 vga_render_control; 264 u32 vga_hdp_control; 265 u32 d1crtc_control; 266 u32 d2crtc_control; 267 }; 268 int rv515_init(struct radeon_device *rdev); 269 void rv515_fini(struct radeon_device *rdev); 270 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); 271 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 272 void rv515_ring_start(struct radeon_device *rdev); 273 uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg); 274 void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 275 void rv515_bandwidth_update(struct radeon_device *rdev); 276 int rv515_resume(struct radeon_device *rdev); 277 int rv515_suspend(struct radeon_device *rdev); 278 void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 279 void rv515_vga_render_disable(struct radeon_device *rdev); 280 void rv515_set_safe_registers(struct radeon_device *rdev); 281 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); 282 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); 283 void rv515_clock_startup(struct radeon_device *rdev); 284 void rv515_debugfs(struct radeon_device *rdev); 285 286 287 /* 288 * r520,rv530,rv560,rv570,r580 289 */ 290 int r520_init(struct radeon_device *rdev); 291 int r520_resume(struct radeon_device *rdev); 292 293 /* 294 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 295 */ 296 int r600_init(struct radeon_device *rdev); 297 void r600_fini(struct radeon_device *rdev); 298 int r600_suspend(struct radeon_device *rdev); 299 int r600_resume(struct radeon_device *rdev); 300 void r600_vga_set_state(struct radeon_device *rdev, bool state); 301 int r600_wb_init(struct radeon_device *rdev); 302 void r600_wb_fini(struct radeon_device *rdev); 303 void r600_cp_commit(struct radeon_device *rdev); 304 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 305 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 306 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 307 int r600_cs_parse(struct radeon_cs_parser *p); 308 void r600_fence_ring_emit(struct radeon_device *rdev, 309 struct radeon_fence *fence); 310 int r600_irq_process(struct radeon_device *rdev); 311 int r600_irq_set(struct radeon_device *rdev); 312 bool r600_gpu_is_lockup(struct radeon_device *rdev); 313 int r600_asic_reset(struct radeon_device *rdev); 314 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 315 uint32_t tiling_flags, uint32_t pitch, 316 uint32_t offset, uint32_t obj_size); 317 void r600_clear_surface_reg(struct radeon_device *rdev, int reg); 318 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 319 int r600_ring_test(struct radeon_device *rdev); 320 int r600_copy_blit(struct radeon_device *rdev, 321 uint64_t src_offset, uint64_t dst_offset, 322 unsigned num_pages, struct radeon_fence *fence); 323 void r600_hpd_init(struct radeon_device *rdev); 324 void r600_hpd_fini(struct radeon_device *rdev); 325 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 326 void r600_hpd_set_polarity(struct radeon_device *rdev, 327 enum radeon_hpd_id hpd); 328 extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo); 329 extern bool r600_gui_idle(struct radeon_device *rdev); 330 extern void r600_pm_misc(struct radeon_device *rdev); 331 extern void r600_pm_init_profile(struct radeon_device *rdev); 332 extern void rs780_pm_init_profile(struct radeon_device *rdev); 333 extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); 334 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); 335 extern int r600_get_pcie_lanes(struct radeon_device *rdev); 336 337 /* 338 * rv770,rv730,rv710,rv740 339 */ 340 int rv770_init(struct radeon_device *rdev); 341 void rv770_fini(struct radeon_device *rdev); 342 int rv770_suspend(struct radeon_device *rdev); 343 int rv770_resume(struct radeon_device *rdev); 344 extern void rv770_pm_misc(struct radeon_device *rdev); 345 extern u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 346 347 /* 348 * evergreen 349 */ 350 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); 351 int evergreen_init(struct radeon_device *rdev); 352 void evergreen_fini(struct radeon_device *rdev); 353 int evergreen_suspend(struct radeon_device *rdev); 354 int evergreen_resume(struct radeon_device *rdev); 355 bool evergreen_gpu_is_lockup(struct radeon_device *rdev); 356 int evergreen_asic_reset(struct radeon_device *rdev); 357 void evergreen_bandwidth_update(struct radeon_device *rdev); 358 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 359 int evergreen_copy_blit(struct radeon_device *rdev, 360 uint64_t src_offset, uint64_t dst_offset, 361 unsigned num_pages, struct radeon_fence *fence); 362 void evergreen_hpd_init(struct radeon_device *rdev); 363 void evergreen_hpd_fini(struct radeon_device *rdev); 364 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 365 void evergreen_hpd_set_polarity(struct radeon_device *rdev, 366 enum radeon_hpd_id hpd); 367 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); 368 int evergreen_irq_set(struct radeon_device *rdev); 369 int evergreen_irq_process(struct radeon_device *rdev); 370 extern int evergreen_cs_parse(struct radeon_cs_parser *p); 371 extern void evergreen_pm_misc(struct radeon_device *rdev); 372 extern void evergreen_pm_prepare(struct radeon_device *rdev); 373 extern void evergreen_pm_finish(struct radeon_device *rdev); 374 extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc); 375 extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 376 extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); 377 378 #endif 379