1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_ASIC_H__ 29 #define __RADEON_ASIC_H__ 30 31 /* 32 * common functions 33 */ 34 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); 35 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 36 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); 37 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 38 39 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); 40 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 41 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); 42 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); 43 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 44 45 void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 46 u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder); 47 void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 48 u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder); 49 50 u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev, 51 struct radeon_ring *ring); 52 u32 radeon_ring_generic_get_wptr(struct radeon_device *rdev, 53 struct radeon_ring *ring); 54 void radeon_ring_generic_set_wptr(struct radeon_device *rdev, 55 struct radeon_ring *ring); 56 57 /* 58 * r100,rv100,rs100,rv200,rs200 59 */ 60 struct r100_mc_save { 61 u32 GENMO_WT; 62 u32 CRTC_EXT_CNTL; 63 u32 CRTC_GEN_CNTL; 64 u32 CRTC2_GEN_CNTL; 65 u32 CUR_OFFSET; 66 u32 CUR2_OFFSET; 67 }; 68 int r100_init(struct radeon_device *rdev); 69 void r100_fini(struct radeon_device *rdev); 70 int r100_suspend(struct radeon_device *rdev); 71 int r100_resume(struct radeon_device *rdev); 72 void r100_vga_set_state(struct radeon_device *rdev, bool state); 73 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 74 int r100_asic_reset(struct radeon_device *rdev); 75 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); 76 void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 77 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 78 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 79 int r100_irq_set(struct radeon_device *rdev); 80 int r100_irq_process(struct radeon_device *rdev); 81 void r100_fence_ring_emit(struct radeon_device *rdev, 82 struct radeon_fence *fence); 83 void r100_semaphore_ring_emit(struct radeon_device *rdev, 84 struct radeon_ring *cp, 85 struct radeon_semaphore *semaphore, 86 bool emit_wait); 87 int r100_cs_parse(struct radeon_cs_parser *p); 88 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 89 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); 90 int r100_copy_blit(struct radeon_device *rdev, 91 uint64_t src_offset, 92 uint64_t dst_offset, 93 unsigned num_gpu_pages, 94 struct radeon_fence **fence); 95 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 96 uint32_t tiling_flags, uint32_t pitch, 97 uint32_t offset, uint32_t obj_size); 98 void r100_clear_surface_reg(struct radeon_device *rdev, int reg); 99 void r100_bandwidth_update(struct radeon_device *rdev); 100 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 101 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 102 void r100_hpd_init(struct radeon_device *rdev); 103 void r100_hpd_fini(struct radeon_device *rdev); 104 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 105 void r100_hpd_set_polarity(struct radeon_device *rdev, 106 enum radeon_hpd_id hpd); 107 int r100_debugfs_rbbm_init(struct radeon_device *rdev); 108 int r100_debugfs_cp_init(struct radeon_device *rdev); 109 void r100_cp_disable(struct radeon_device *rdev); 110 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 111 void r100_cp_fini(struct radeon_device *rdev); 112 int r100_pci_gart_init(struct radeon_device *rdev); 113 void r100_pci_gart_fini(struct radeon_device *rdev); 114 int r100_pci_gart_enable(struct radeon_device *rdev); 115 void r100_pci_gart_disable(struct radeon_device *rdev); 116 int r100_debugfs_mc_info_init(struct radeon_device *rdev); 117 int r100_gui_wait_for_idle(struct radeon_device *rdev); 118 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 119 void r100_irq_disable(struct radeon_device *rdev); 120 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); 121 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); 122 void r100_vram_init_sizes(struct radeon_device *rdev); 123 int r100_cp_reset(struct radeon_device *rdev); 124 void r100_vga_render_disable(struct radeon_device *rdev); 125 void r100_restore_sanity(struct radeon_device *rdev); 126 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 127 struct radeon_cs_packet *pkt, 128 struct radeon_bo *robj); 129 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 130 struct radeon_cs_packet *pkt, 131 const unsigned *auth, unsigned n, 132 radeon_packet0_check_t check); 133 int r100_cs_packet_parse(struct radeon_cs_parser *p, 134 struct radeon_cs_packet *pkt, 135 unsigned idx); 136 void r100_enable_bm(struct radeon_device *rdev); 137 void r100_set_common_regs(struct radeon_device *rdev); 138 void r100_bm_disable(struct radeon_device *rdev); 139 extern bool r100_gui_idle(struct radeon_device *rdev); 140 extern void r100_pm_misc(struct radeon_device *rdev); 141 extern void r100_pm_prepare(struct radeon_device *rdev); 142 extern void r100_pm_finish(struct radeon_device *rdev); 143 extern void r100_pm_init_profile(struct radeon_device *rdev); 144 extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); 145 extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc); 146 extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 147 extern void r100_post_page_flip(struct radeon_device *rdev, int crtc); 148 extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); 149 extern int r100_mc_wait_for_idle(struct radeon_device *rdev); 150 151 /* 152 * r200,rv250,rs300,rv280 153 */ 154 extern int r200_copy_dma(struct radeon_device *rdev, 155 uint64_t src_offset, 156 uint64_t dst_offset, 157 unsigned num_gpu_pages, 158 struct radeon_fence **fence); 159 void r200_set_safe_registers(struct radeon_device *rdev); 160 161 /* 162 * r300,r350,rv350,rv380 163 */ 164 extern int r300_init(struct radeon_device *rdev); 165 extern void r300_fini(struct radeon_device *rdev); 166 extern int r300_suspend(struct radeon_device *rdev); 167 extern int r300_resume(struct radeon_device *rdev); 168 extern int r300_asic_reset(struct radeon_device *rdev); 169 extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 170 extern void r300_fence_ring_emit(struct radeon_device *rdev, 171 struct radeon_fence *fence); 172 extern int r300_cs_parse(struct radeon_cs_parser *p); 173 extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); 174 extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 175 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); 176 extern int rv370_get_pcie_lanes(struct radeon_device *rdev); 177 extern void r300_set_reg_safe(struct radeon_device *rdev); 178 extern void r300_mc_program(struct radeon_device *rdev); 179 extern void r300_mc_init(struct radeon_device *rdev); 180 extern void r300_clock_startup(struct radeon_device *rdev); 181 extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 182 extern int rv370_pcie_gart_init(struct radeon_device *rdev); 183 extern void rv370_pcie_gart_fini(struct radeon_device *rdev); 184 extern int rv370_pcie_gart_enable(struct radeon_device *rdev); 185 extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 186 extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 187 188 /* 189 * r420,r423,rv410 190 */ 191 extern int r420_init(struct radeon_device *rdev); 192 extern void r420_fini(struct radeon_device *rdev); 193 extern int r420_suspend(struct radeon_device *rdev); 194 extern int r420_resume(struct radeon_device *rdev); 195 extern void r420_pm_init_profile(struct radeon_device *rdev); 196 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 197 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 198 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 199 extern void r420_pipes_init(struct radeon_device *rdev); 200 201 /* 202 * rs400,rs480 203 */ 204 extern int rs400_init(struct radeon_device *rdev); 205 extern void rs400_fini(struct radeon_device *rdev); 206 extern int rs400_suspend(struct radeon_device *rdev); 207 extern int rs400_resume(struct radeon_device *rdev); 208 void rs400_gart_tlb_flush(struct radeon_device *rdev); 209 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 210 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); 211 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 212 int rs400_gart_init(struct radeon_device *rdev); 213 int rs400_gart_enable(struct radeon_device *rdev); 214 void rs400_gart_adjust_size(struct radeon_device *rdev); 215 void rs400_gart_disable(struct radeon_device *rdev); 216 void rs400_gart_fini(struct radeon_device *rdev); 217 extern int rs400_mc_wait_for_idle(struct radeon_device *rdev); 218 219 /* 220 * rs600. 221 */ 222 extern int rs600_asic_reset(struct radeon_device *rdev); 223 extern int rs600_init(struct radeon_device *rdev); 224 extern void rs600_fini(struct radeon_device *rdev); 225 extern int rs600_suspend(struct radeon_device *rdev); 226 extern int rs600_resume(struct radeon_device *rdev); 227 int rs600_irq_set(struct radeon_device *rdev); 228 int rs600_irq_process(struct radeon_device *rdev); 229 void rs600_irq_disable(struct radeon_device *rdev); 230 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); 231 void rs600_gart_tlb_flush(struct radeon_device *rdev); 232 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 233 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); 234 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 235 void rs600_bandwidth_update(struct radeon_device *rdev); 236 void rs600_hpd_init(struct radeon_device *rdev); 237 void rs600_hpd_fini(struct radeon_device *rdev); 238 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 239 void rs600_hpd_set_polarity(struct radeon_device *rdev, 240 enum radeon_hpd_id hpd); 241 extern void rs600_pm_misc(struct radeon_device *rdev); 242 extern void rs600_pm_prepare(struct radeon_device *rdev); 243 extern void rs600_pm_finish(struct radeon_device *rdev); 244 extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc); 245 extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 246 extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc); 247 void rs600_set_safe_registers(struct radeon_device *rdev); 248 extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc); 249 extern int rs600_mc_wait_for_idle(struct radeon_device *rdev); 250 251 /* 252 * rs690,rs740 253 */ 254 int rs690_init(struct radeon_device *rdev); 255 void rs690_fini(struct radeon_device *rdev); 256 int rs690_resume(struct radeon_device *rdev); 257 int rs690_suspend(struct radeon_device *rdev); 258 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); 259 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 260 void rs690_bandwidth_update(struct radeon_device *rdev); 261 void rs690_line_buffer_adjust(struct radeon_device *rdev, 262 struct drm_display_mode *mode1, 263 struct drm_display_mode *mode2); 264 extern int rs690_mc_wait_for_idle(struct radeon_device *rdev); 265 266 /* 267 * rv515 268 */ 269 struct rv515_mc_save { 270 u32 vga_render_control; 271 u32 vga_hdp_control; 272 bool crtc_enabled[2]; 273 }; 274 275 int rv515_init(struct radeon_device *rdev); 276 void rv515_fini(struct radeon_device *rdev); 277 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); 278 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 279 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 280 void rv515_bandwidth_update(struct radeon_device *rdev); 281 int rv515_resume(struct radeon_device *rdev); 282 int rv515_suspend(struct radeon_device *rdev); 283 void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 284 void rv515_vga_render_disable(struct radeon_device *rdev); 285 void rv515_set_safe_registers(struct radeon_device *rdev); 286 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); 287 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); 288 void rv515_clock_startup(struct radeon_device *rdev); 289 void rv515_debugfs(struct radeon_device *rdev); 290 int rv515_mc_wait_for_idle(struct radeon_device *rdev); 291 292 /* 293 * r520,rv530,rv560,rv570,r580 294 */ 295 int r520_init(struct radeon_device *rdev); 296 int r520_resume(struct radeon_device *rdev); 297 int r520_mc_wait_for_idle(struct radeon_device *rdev); 298 299 /* 300 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 301 */ 302 int r600_init(struct radeon_device *rdev); 303 void r600_fini(struct radeon_device *rdev); 304 int r600_suspend(struct radeon_device *rdev); 305 int r600_resume(struct radeon_device *rdev); 306 void r600_vga_set_state(struct radeon_device *rdev, bool state); 307 int r600_wb_init(struct radeon_device *rdev); 308 void r600_wb_fini(struct radeon_device *rdev); 309 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 310 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 311 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 312 int r600_cs_parse(struct radeon_cs_parser *p); 313 int r600_dma_cs_parse(struct radeon_cs_parser *p); 314 void r600_fence_ring_emit(struct radeon_device *rdev, 315 struct radeon_fence *fence); 316 void r600_semaphore_ring_emit(struct radeon_device *rdev, 317 struct radeon_ring *cp, 318 struct radeon_semaphore *semaphore, 319 bool emit_wait); 320 void r600_dma_fence_ring_emit(struct radeon_device *rdev, 321 struct radeon_fence *fence); 322 void r600_dma_semaphore_ring_emit(struct radeon_device *rdev, 323 struct radeon_ring *ring, 324 struct radeon_semaphore *semaphore, 325 bool emit_wait); 326 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 327 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 328 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 329 int r600_asic_reset(struct radeon_device *rdev); 330 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 331 uint32_t tiling_flags, uint32_t pitch, 332 uint32_t offset, uint32_t obj_size); 333 void r600_clear_surface_reg(struct radeon_device *rdev, int reg); 334 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 335 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 336 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 337 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 338 int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 339 int r600_copy_cpdma(struct radeon_device *rdev, 340 uint64_t src_offset, uint64_t dst_offset, 341 unsigned num_gpu_pages, struct radeon_fence **fence); 342 int r600_copy_dma(struct radeon_device *rdev, 343 uint64_t src_offset, uint64_t dst_offset, 344 unsigned num_gpu_pages, struct radeon_fence **fence); 345 void r600_hpd_init(struct radeon_device *rdev); 346 void r600_hpd_fini(struct radeon_device *rdev); 347 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 348 void r600_hpd_set_polarity(struct radeon_device *rdev, 349 enum radeon_hpd_id hpd); 350 extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo); 351 extern bool r600_gui_idle(struct radeon_device *rdev); 352 extern void r600_pm_misc(struct radeon_device *rdev); 353 extern void r600_pm_init_profile(struct radeon_device *rdev); 354 extern void rs780_pm_init_profile(struct radeon_device *rdev); 355 extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg); 356 extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 357 extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); 358 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); 359 extern int r600_get_pcie_lanes(struct radeon_device *rdev); 360 bool r600_card_posted(struct radeon_device *rdev); 361 void r600_cp_stop(struct radeon_device *rdev); 362 int r600_cp_start(struct radeon_device *rdev); 363 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); 364 int r600_cp_resume(struct radeon_device *rdev); 365 void r600_cp_fini(struct radeon_device *rdev); 366 int r600_count_pipe_bits(uint32_t val); 367 int r600_mc_wait_for_idle(struct radeon_device *rdev); 368 int r600_pcie_gart_init(struct radeon_device *rdev); 369 void r600_scratch_init(struct radeon_device *rdev); 370 int r600_init_microcode(struct radeon_device *rdev); 371 /* r600 irq */ 372 int r600_irq_process(struct radeon_device *rdev); 373 int r600_irq_init(struct radeon_device *rdev); 374 void r600_irq_fini(struct radeon_device *rdev); 375 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 376 int r600_irq_set(struct radeon_device *rdev); 377 void r600_irq_suspend(struct radeon_device *rdev); 378 void r600_disable_interrupts(struct radeon_device *rdev); 379 void r600_rlc_stop(struct radeon_device *rdev); 380 /* r600 audio */ 381 int r600_audio_init(struct radeon_device *rdev); 382 struct r600_audio_pin r600_audio_status(struct radeon_device *rdev); 383 void r600_audio_fini(struct radeon_device *rdev); 384 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); 385 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); 386 void r600_hdmi_enable(struct drm_encoder *encoder, bool enable); 387 void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 388 int r600_mc_wait_for_idle(struct radeon_device *rdev); 389 u32 r600_get_xclk(struct radeon_device *rdev); 390 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev); 391 int rv6xx_get_temp(struct radeon_device *rdev); 392 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 393 int r600_dpm_pre_set_power_state(struct radeon_device *rdev); 394 void r600_dpm_post_set_power_state(struct radeon_device *rdev); 395 /* r600 dma */ 396 uint32_t r600_dma_get_rptr(struct radeon_device *rdev, 397 struct radeon_ring *ring); 398 uint32_t r600_dma_get_wptr(struct radeon_device *rdev, 399 struct radeon_ring *ring); 400 void r600_dma_set_wptr(struct radeon_device *rdev, 401 struct radeon_ring *ring); 402 /* rv6xx dpm */ 403 int rv6xx_dpm_init(struct radeon_device *rdev); 404 int rv6xx_dpm_enable(struct radeon_device *rdev); 405 void rv6xx_dpm_disable(struct radeon_device *rdev); 406 int rv6xx_dpm_set_power_state(struct radeon_device *rdev); 407 void rv6xx_setup_asic(struct radeon_device *rdev); 408 void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev); 409 void rv6xx_dpm_fini(struct radeon_device *rdev); 410 u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low); 411 u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low); 412 void rv6xx_dpm_print_power_state(struct radeon_device *rdev, 413 struct radeon_ps *ps); 414 void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 415 struct seq_file *m); 416 int rv6xx_dpm_force_performance_level(struct radeon_device *rdev, 417 enum radeon_dpm_forced_level level); 418 /* rs780 dpm */ 419 int rs780_dpm_init(struct radeon_device *rdev); 420 int rs780_dpm_enable(struct radeon_device *rdev); 421 void rs780_dpm_disable(struct radeon_device *rdev); 422 int rs780_dpm_set_power_state(struct radeon_device *rdev); 423 void rs780_dpm_setup_asic(struct radeon_device *rdev); 424 void rs780_dpm_display_configuration_changed(struct radeon_device *rdev); 425 void rs780_dpm_fini(struct radeon_device *rdev); 426 u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low); 427 u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low); 428 void rs780_dpm_print_power_state(struct radeon_device *rdev, 429 struct radeon_ps *ps); 430 void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 431 struct seq_file *m); 432 int rs780_dpm_force_performance_level(struct radeon_device *rdev, 433 enum radeon_dpm_forced_level level); 434 435 /* 436 * rv770,rv730,rv710,rv740 437 */ 438 int rv770_init(struct radeon_device *rdev); 439 void rv770_fini(struct radeon_device *rdev); 440 int rv770_suspend(struct radeon_device *rdev); 441 int rv770_resume(struct radeon_device *rdev); 442 void rv770_pm_misc(struct radeon_device *rdev); 443 u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 444 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 445 void r700_cp_stop(struct radeon_device *rdev); 446 void r700_cp_fini(struct radeon_device *rdev); 447 int rv770_copy_dma(struct radeon_device *rdev, 448 uint64_t src_offset, uint64_t dst_offset, 449 unsigned num_gpu_pages, 450 struct radeon_fence **fence); 451 u32 rv770_get_xclk(struct radeon_device *rdev); 452 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 453 int rv770_get_temp(struct radeon_device *rdev); 454 /* rv7xx pm */ 455 int rv770_dpm_init(struct radeon_device *rdev); 456 int rv770_dpm_enable(struct radeon_device *rdev); 457 void rv770_dpm_disable(struct radeon_device *rdev); 458 int rv770_dpm_set_power_state(struct radeon_device *rdev); 459 void rv770_dpm_setup_asic(struct radeon_device *rdev); 460 void rv770_dpm_display_configuration_changed(struct radeon_device *rdev); 461 void rv770_dpm_fini(struct radeon_device *rdev); 462 u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low); 463 u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low); 464 void rv770_dpm_print_power_state(struct radeon_device *rdev, 465 struct radeon_ps *ps); 466 void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 467 struct seq_file *m); 468 int rv770_dpm_force_performance_level(struct radeon_device *rdev, 469 enum radeon_dpm_forced_level level); 470 bool rv770_dpm_vblank_too_short(struct radeon_device *rdev); 471 472 /* 473 * evergreen 474 */ 475 struct evergreen_mc_save { 476 u32 vga_render_control; 477 u32 vga_hdp_control; 478 bool crtc_enabled[RADEON_MAX_CRTCS]; 479 }; 480 481 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); 482 int evergreen_init(struct radeon_device *rdev); 483 void evergreen_fini(struct radeon_device *rdev); 484 int evergreen_suspend(struct radeon_device *rdev); 485 int evergreen_resume(struct radeon_device *rdev); 486 bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 487 bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 488 int evergreen_asic_reset(struct radeon_device *rdev); 489 void evergreen_bandwidth_update(struct radeon_device *rdev); 490 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 491 void evergreen_hpd_init(struct radeon_device *rdev); 492 void evergreen_hpd_fini(struct radeon_device *rdev); 493 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 494 void evergreen_hpd_set_polarity(struct radeon_device *rdev, 495 enum radeon_hpd_id hpd); 496 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); 497 int evergreen_irq_set(struct radeon_device *rdev); 498 int evergreen_irq_process(struct radeon_device *rdev); 499 extern int evergreen_cs_parse(struct radeon_cs_parser *p); 500 extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p); 501 extern void evergreen_pm_misc(struct radeon_device *rdev); 502 extern void evergreen_pm_prepare(struct radeon_device *rdev); 503 extern void evergreen_pm_finish(struct radeon_device *rdev); 504 extern void sumo_pm_init_profile(struct radeon_device *rdev); 505 extern void btc_pm_init_profile(struct radeon_device *rdev); 506 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 507 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 508 extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc); 509 extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 510 extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); 511 extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); 512 void evergreen_disable_interrupt_state(struct radeon_device *rdev); 513 int evergreen_mc_wait_for_idle(struct radeon_device *rdev); 514 void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, 515 struct radeon_fence *fence); 516 void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, 517 struct radeon_ib *ib); 518 int evergreen_copy_dma(struct radeon_device *rdev, 519 uint64_t src_offset, uint64_t dst_offset, 520 unsigned num_gpu_pages, 521 struct radeon_fence **fence); 522 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable); 523 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 524 int evergreen_get_temp(struct radeon_device *rdev); 525 int sumo_get_temp(struct radeon_device *rdev); 526 int tn_get_temp(struct radeon_device *rdev); 527 int cypress_dpm_init(struct radeon_device *rdev); 528 void cypress_dpm_setup_asic(struct radeon_device *rdev); 529 int cypress_dpm_enable(struct radeon_device *rdev); 530 void cypress_dpm_disable(struct radeon_device *rdev); 531 int cypress_dpm_set_power_state(struct radeon_device *rdev); 532 void cypress_dpm_display_configuration_changed(struct radeon_device *rdev); 533 void cypress_dpm_fini(struct radeon_device *rdev); 534 bool cypress_dpm_vblank_too_short(struct radeon_device *rdev); 535 int btc_dpm_init(struct radeon_device *rdev); 536 void btc_dpm_setup_asic(struct radeon_device *rdev); 537 int btc_dpm_enable(struct radeon_device *rdev); 538 void btc_dpm_disable(struct radeon_device *rdev); 539 int btc_dpm_pre_set_power_state(struct radeon_device *rdev); 540 int btc_dpm_set_power_state(struct radeon_device *rdev); 541 void btc_dpm_post_set_power_state(struct radeon_device *rdev); 542 void btc_dpm_fini(struct radeon_device *rdev); 543 u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low); 544 u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low); 545 bool btc_dpm_vblank_too_short(struct radeon_device *rdev); 546 int sumo_dpm_init(struct radeon_device *rdev); 547 int sumo_dpm_enable(struct radeon_device *rdev); 548 void sumo_dpm_disable(struct radeon_device *rdev); 549 int sumo_dpm_pre_set_power_state(struct radeon_device *rdev); 550 int sumo_dpm_set_power_state(struct radeon_device *rdev); 551 void sumo_dpm_post_set_power_state(struct radeon_device *rdev); 552 void sumo_dpm_setup_asic(struct radeon_device *rdev); 553 void sumo_dpm_display_configuration_changed(struct radeon_device *rdev); 554 void sumo_dpm_fini(struct radeon_device *rdev); 555 u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low); 556 u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low); 557 void sumo_dpm_print_power_state(struct radeon_device *rdev, 558 struct radeon_ps *ps); 559 void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 560 struct seq_file *m); 561 int sumo_dpm_force_performance_level(struct radeon_device *rdev, 562 enum radeon_dpm_forced_level level); 563 564 /* 565 * cayman 566 */ 567 void cayman_fence_ring_emit(struct radeon_device *rdev, 568 struct radeon_fence *fence); 569 void cayman_uvd_semaphore_emit(struct radeon_device *rdev, 570 struct radeon_ring *ring, 571 struct radeon_semaphore *semaphore, 572 bool emit_wait); 573 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); 574 int cayman_init(struct radeon_device *rdev); 575 void cayman_fini(struct radeon_device *rdev); 576 int cayman_suspend(struct radeon_device *rdev); 577 int cayman_resume(struct radeon_device *rdev); 578 int cayman_asic_reset(struct radeon_device *rdev); 579 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 580 int cayman_vm_init(struct radeon_device *rdev); 581 void cayman_vm_fini(struct radeon_device *rdev); 582 void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 583 uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); 584 void cayman_vm_set_page(struct radeon_device *rdev, 585 struct radeon_ib *ib, 586 uint64_t pe, 587 uint64_t addr, unsigned count, 588 uint32_t incr, uint32_t flags); 589 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 590 int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 591 void cayman_dma_ring_ib_execute(struct radeon_device *rdev, 592 struct radeon_ib *ib); 593 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 594 bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 595 void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 596 597 int ni_dpm_init(struct radeon_device *rdev); 598 void ni_dpm_setup_asic(struct radeon_device *rdev); 599 int ni_dpm_enable(struct radeon_device *rdev); 600 void ni_dpm_disable(struct radeon_device *rdev); 601 int ni_dpm_pre_set_power_state(struct radeon_device *rdev); 602 int ni_dpm_set_power_state(struct radeon_device *rdev); 603 void ni_dpm_post_set_power_state(struct radeon_device *rdev); 604 void ni_dpm_fini(struct radeon_device *rdev); 605 u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low); 606 u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low); 607 void ni_dpm_print_power_state(struct radeon_device *rdev, 608 struct radeon_ps *ps); 609 void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 610 struct seq_file *m); 611 int ni_dpm_force_performance_level(struct radeon_device *rdev, 612 enum radeon_dpm_forced_level level); 613 bool ni_dpm_vblank_too_short(struct radeon_device *rdev); 614 int trinity_dpm_init(struct radeon_device *rdev); 615 int trinity_dpm_enable(struct radeon_device *rdev); 616 void trinity_dpm_disable(struct radeon_device *rdev); 617 int trinity_dpm_pre_set_power_state(struct radeon_device *rdev); 618 int trinity_dpm_set_power_state(struct radeon_device *rdev); 619 void trinity_dpm_post_set_power_state(struct radeon_device *rdev); 620 void trinity_dpm_setup_asic(struct radeon_device *rdev); 621 void trinity_dpm_display_configuration_changed(struct radeon_device *rdev); 622 void trinity_dpm_fini(struct radeon_device *rdev); 623 u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low); 624 u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low); 625 void trinity_dpm_print_power_state(struct radeon_device *rdev, 626 struct radeon_ps *ps); 627 void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 628 struct seq_file *m); 629 int trinity_dpm_force_performance_level(struct radeon_device *rdev, 630 enum radeon_dpm_forced_level level); 631 void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable); 632 633 /* DCE6 - SI */ 634 void dce6_bandwidth_update(struct radeon_device *rdev); 635 int dce6_audio_init(struct radeon_device *rdev); 636 void dce6_audio_fini(struct radeon_device *rdev); 637 638 /* 639 * si 640 */ 641 void si_fence_ring_emit(struct radeon_device *rdev, 642 struct radeon_fence *fence); 643 void si_pcie_gart_tlb_flush(struct radeon_device *rdev); 644 int si_init(struct radeon_device *rdev); 645 void si_fini(struct radeon_device *rdev); 646 int si_suspend(struct radeon_device *rdev); 647 int si_resume(struct radeon_device *rdev); 648 bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 649 bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 650 int si_asic_reset(struct radeon_device *rdev); 651 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 652 int si_irq_set(struct radeon_device *rdev); 653 int si_irq_process(struct radeon_device *rdev); 654 int si_vm_init(struct radeon_device *rdev); 655 void si_vm_fini(struct radeon_device *rdev); 656 void si_vm_set_page(struct radeon_device *rdev, 657 struct radeon_ib *ib, 658 uint64_t pe, 659 uint64_t addr, unsigned count, 660 uint32_t incr, uint32_t flags); 661 void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 662 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 663 int si_copy_dma(struct radeon_device *rdev, 664 uint64_t src_offset, uint64_t dst_offset, 665 unsigned num_gpu_pages, 666 struct radeon_fence **fence); 667 void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 668 u32 si_get_xclk(struct radeon_device *rdev); 669 uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev); 670 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 671 int si_get_temp(struct radeon_device *rdev); 672 int si_dpm_init(struct radeon_device *rdev); 673 void si_dpm_setup_asic(struct radeon_device *rdev); 674 int si_dpm_enable(struct radeon_device *rdev); 675 void si_dpm_disable(struct radeon_device *rdev); 676 int si_dpm_pre_set_power_state(struct radeon_device *rdev); 677 int si_dpm_set_power_state(struct radeon_device *rdev); 678 void si_dpm_post_set_power_state(struct radeon_device *rdev); 679 void si_dpm_fini(struct radeon_device *rdev); 680 void si_dpm_display_configuration_changed(struct radeon_device *rdev); 681 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 682 struct seq_file *m); 683 int si_dpm_force_performance_level(struct radeon_device *rdev, 684 enum radeon_dpm_forced_level level); 685 686 /* DCE8 - CIK */ 687 void dce8_bandwidth_update(struct radeon_device *rdev); 688 689 /* 690 * cik 691 */ 692 uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev); 693 u32 cik_get_xclk(struct radeon_device *rdev); 694 uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 695 void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 696 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 697 void cik_sdma_fence_ring_emit(struct radeon_device *rdev, 698 struct radeon_fence *fence); 699 void cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, 700 struct radeon_ring *ring, 701 struct radeon_semaphore *semaphore, 702 bool emit_wait); 703 void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 704 int cik_copy_dma(struct radeon_device *rdev, 705 uint64_t src_offset, uint64_t dst_offset, 706 unsigned num_gpu_pages, 707 struct radeon_fence **fence); 708 int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 709 int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 710 bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 711 void cik_fence_gfx_ring_emit(struct radeon_device *rdev, 712 struct radeon_fence *fence); 713 void cik_fence_compute_ring_emit(struct radeon_device *rdev, 714 struct radeon_fence *fence); 715 void cik_semaphore_ring_emit(struct radeon_device *rdev, 716 struct radeon_ring *cp, 717 struct radeon_semaphore *semaphore, 718 bool emit_wait); 719 void cik_pcie_gart_tlb_flush(struct radeon_device *rdev); 720 int cik_init(struct radeon_device *rdev); 721 void cik_fini(struct radeon_device *rdev); 722 int cik_suspend(struct radeon_device *rdev); 723 int cik_resume(struct radeon_device *rdev); 724 bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 725 int cik_asic_reset(struct radeon_device *rdev); 726 void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 727 int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 728 int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 729 int cik_irq_set(struct radeon_device *rdev); 730 int cik_irq_process(struct radeon_device *rdev); 731 int cik_vm_init(struct radeon_device *rdev); 732 void cik_vm_fini(struct radeon_device *rdev); 733 void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 734 void cik_vm_set_page(struct radeon_device *rdev, 735 struct radeon_ib *ib, 736 uint64_t pe, 737 uint64_t addr, unsigned count, 738 uint32_t incr, uint32_t flags); 739 void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 740 int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 741 u32 cik_compute_ring_get_rptr(struct radeon_device *rdev, 742 struct radeon_ring *ring); 743 u32 cik_compute_ring_get_wptr(struct radeon_device *rdev, 744 struct radeon_ring *ring); 745 void cik_compute_ring_set_wptr(struct radeon_device *rdev, 746 struct radeon_ring *ring); 747 int ci_get_temp(struct radeon_device *rdev); 748 int kv_get_temp(struct radeon_device *rdev); 749 750 int ci_dpm_init(struct radeon_device *rdev); 751 int ci_dpm_enable(struct radeon_device *rdev); 752 void ci_dpm_disable(struct radeon_device *rdev); 753 int ci_dpm_pre_set_power_state(struct radeon_device *rdev); 754 int ci_dpm_set_power_state(struct radeon_device *rdev); 755 void ci_dpm_post_set_power_state(struct radeon_device *rdev); 756 void ci_dpm_setup_asic(struct radeon_device *rdev); 757 void ci_dpm_display_configuration_changed(struct radeon_device *rdev); 758 void ci_dpm_fini(struct radeon_device *rdev); 759 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low); 760 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low); 761 void ci_dpm_print_power_state(struct radeon_device *rdev, 762 struct radeon_ps *ps); 763 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 764 struct seq_file *m); 765 int ci_dpm_force_performance_level(struct radeon_device *rdev, 766 enum radeon_dpm_forced_level level); 767 bool ci_dpm_vblank_too_short(struct radeon_device *rdev); 768 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate); 769 770 int kv_dpm_init(struct radeon_device *rdev); 771 int kv_dpm_enable(struct radeon_device *rdev); 772 void kv_dpm_disable(struct radeon_device *rdev); 773 int kv_dpm_pre_set_power_state(struct radeon_device *rdev); 774 int kv_dpm_set_power_state(struct radeon_device *rdev); 775 void kv_dpm_post_set_power_state(struct radeon_device *rdev); 776 void kv_dpm_setup_asic(struct radeon_device *rdev); 777 void kv_dpm_display_configuration_changed(struct radeon_device *rdev); 778 void kv_dpm_fini(struct radeon_device *rdev); 779 u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low); 780 u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low); 781 void kv_dpm_print_power_state(struct radeon_device *rdev, 782 struct radeon_ps *ps); 783 void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 784 struct seq_file *m); 785 int kv_dpm_force_performance_level(struct radeon_device *rdev, 786 enum radeon_dpm_forced_level level); 787 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate); 788 void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable); 789 790 /* uvd v1.0 */ 791 uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev, 792 struct radeon_ring *ring); 793 uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev, 794 struct radeon_ring *ring); 795 void uvd_v1_0_set_wptr(struct radeon_device *rdev, 796 struct radeon_ring *ring); 797 798 int uvd_v1_0_init(struct radeon_device *rdev); 799 void uvd_v1_0_fini(struct radeon_device *rdev); 800 int uvd_v1_0_start(struct radeon_device *rdev); 801 void uvd_v1_0_stop(struct radeon_device *rdev); 802 803 int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 804 int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 805 void uvd_v1_0_semaphore_emit(struct radeon_device *rdev, 806 struct radeon_ring *ring, 807 struct radeon_semaphore *semaphore, 808 bool emit_wait); 809 void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 810 811 /* uvd v2.2 */ 812 int uvd_v2_2_resume(struct radeon_device *rdev); 813 void uvd_v2_2_fence_emit(struct radeon_device *rdev, 814 struct radeon_fence *fence); 815 816 /* uvd v3.1 */ 817 void uvd_v3_1_semaphore_emit(struct radeon_device *rdev, 818 struct radeon_ring *ring, 819 struct radeon_semaphore *semaphore, 820 bool emit_wait); 821 822 /* uvd v4.2 */ 823 int uvd_v4_2_resume(struct radeon_device *rdev); 824 825 #endif 826