1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/console.h> 30 #include <drm/drmP.h> 31 #include <drm/drm_crtc_helper.h> 32 #include <drm/radeon_drm.h> 33 #include <linux/vgaarb.h> 34 #include <linux/vga_switcheroo.h> 35 #include "radeon_reg.h" 36 #include "radeon.h" 37 #include "radeon_asic.h" 38 #include "atom.h" 39 40 /* 41 * Registers accessors functions. 42 */ 43 /** 44 * radeon_invalid_rreg - dummy reg read function 45 * 46 * @rdev: radeon device pointer 47 * @reg: offset of register 48 * 49 * Dummy register read function. Used for register blocks 50 * that certain asics don't have (all asics). 51 * Returns the value in the register. 52 */ 53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) 54 { 55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); 56 BUG_ON(1); 57 return 0; 58 } 59 60 /** 61 * radeon_invalid_wreg - dummy reg write function 62 * 63 * @rdev: radeon device pointer 64 * @reg: offset of register 65 * @v: value to write to the register 66 * 67 * Dummy register read function. Used for register blocks 68 * that certain asics don't have (all asics). 69 */ 70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 71 { 72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", 73 reg, v); 74 BUG_ON(1); 75 } 76 77 /** 78 * radeon_register_accessor_init - sets up the register accessor callbacks 79 * 80 * @rdev: radeon device pointer 81 * 82 * Sets up the register accessor callbacks for various register 83 * apertures. Not all asics have all apertures (all asics). 84 */ 85 static void radeon_register_accessor_init(struct radeon_device *rdev) 86 { 87 rdev->mc_rreg = &radeon_invalid_rreg; 88 rdev->mc_wreg = &radeon_invalid_wreg; 89 rdev->pll_rreg = &radeon_invalid_rreg; 90 rdev->pll_wreg = &radeon_invalid_wreg; 91 rdev->pciep_rreg = &radeon_invalid_rreg; 92 rdev->pciep_wreg = &radeon_invalid_wreg; 93 94 /* Don't change order as we are overridding accessor. */ 95 if (rdev->family < CHIP_RV515) { 96 rdev->pcie_reg_mask = 0xff; 97 } else { 98 rdev->pcie_reg_mask = 0x7ff; 99 } 100 /* FIXME: not sure here */ 101 if (rdev->family <= CHIP_R580) { 102 rdev->pll_rreg = &r100_pll_rreg; 103 rdev->pll_wreg = &r100_pll_wreg; 104 } 105 if (rdev->family >= CHIP_R420) { 106 rdev->mc_rreg = &r420_mc_rreg; 107 rdev->mc_wreg = &r420_mc_wreg; 108 } 109 if (rdev->family >= CHIP_RV515) { 110 rdev->mc_rreg = &rv515_mc_rreg; 111 rdev->mc_wreg = &rv515_mc_wreg; 112 } 113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { 114 rdev->mc_rreg = &rs400_mc_rreg; 115 rdev->mc_wreg = &rs400_mc_wreg; 116 } 117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 118 rdev->mc_rreg = &rs690_mc_rreg; 119 rdev->mc_wreg = &rs690_mc_wreg; 120 } 121 if (rdev->family == CHIP_RS600) { 122 rdev->mc_rreg = &rs600_mc_rreg; 123 rdev->mc_wreg = &rs600_mc_wreg; 124 } 125 if (rdev->family >= CHIP_R600) { 126 rdev->pciep_rreg = &r600_pciep_rreg; 127 rdev->pciep_wreg = &r600_pciep_wreg; 128 } 129 } 130 131 132 /* helper to disable agp */ 133 /** 134 * radeon_agp_disable - AGP disable helper function 135 * 136 * @rdev: radeon device pointer 137 * 138 * Removes AGP flags and changes the gart callbacks on AGP 139 * cards when using the internal gart rather than AGP (all asics). 140 */ 141 void radeon_agp_disable(struct radeon_device *rdev) 142 { 143 rdev->flags &= ~RADEON_IS_AGP; 144 if (rdev->family >= CHIP_R600) { 145 DRM_INFO("Forcing AGP to PCIE mode\n"); 146 rdev->flags |= RADEON_IS_PCIE; 147 } else if (rdev->family >= CHIP_RV515 || 148 rdev->family == CHIP_RV380 || 149 rdev->family == CHIP_RV410 || 150 rdev->family == CHIP_R423) { 151 DRM_INFO("Forcing AGP to PCIE mode\n"); 152 rdev->flags |= RADEON_IS_PCIE; 153 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 154 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 155 } else { 156 DRM_INFO("Forcing AGP to PCI mode\n"); 157 rdev->flags |= RADEON_IS_PCI; 158 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 159 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 160 } 161 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 162 } 163 164 /* 165 * ASIC 166 */ 167 static struct radeon_asic r100_asic = { 168 .init = &r100_init, 169 .fini = &r100_fini, 170 .suspend = &r100_suspend, 171 .resume = &r100_resume, 172 .vga_set_state = &r100_vga_set_state, 173 .asic_reset = &r100_asic_reset, 174 .ioctl_wait_idle = NULL, 175 .gui_idle = &r100_gui_idle, 176 .mc_wait_for_idle = &r100_mc_wait_for_idle, 177 .gart = { 178 .tlb_flush = &r100_pci_gart_tlb_flush, 179 .set_page = &r100_pci_gart_set_page, 180 }, 181 .ring = { 182 [RADEON_RING_TYPE_GFX_INDEX] = { 183 .ib_execute = &r100_ring_ib_execute, 184 .emit_fence = &r100_fence_ring_emit, 185 .emit_semaphore = &r100_semaphore_ring_emit, 186 .cs_parse = &r100_cs_parse, 187 .ring_start = &r100_ring_start, 188 .ring_test = &r100_ring_test, 189 .ib_test = &r100_ib_test, 190 .is_lockup = &r100_gpu_is_lockup, 191 } 192 }, 193 .irq = { 194 .set = &r100_irq_set, 195 .process = &r100_irq_process, 196 }, 197 .display = { 198 .bandwidth_update = &r100_bandwidth_update, 199 .get_vblank_counter = &r100_get_vblank_counter, 200 .wait_for_vblank = &r100_wait_for_vblank, 201 .set_backlight_level = &radeon_legacy_set_backlight_level, 202 .get_backlight_level = &radeon_legacy_get_backlight_level, 203 }, 204 .copy = { 205 .blit = &r100_copy_blit, 206 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 207 .dma = NULL, 208 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 209 .copy = &r100_copy_blit, 210 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 211 }, 212 .surface = { 213 .set_reg = r100_set_surface_reg, 214 .clear_reg = r100_clear_surface_reg, 215 }, 216 .hpd = { 217 .init = &r100_hpd_init, 218 .fini = &r100_hpd_fini, 219 .sense = &r100_hpd_sense, 220 .set_polarity = &r100_hpd_set_polarity, 221 }, 222 .pm = { 223 .misc = &r100_pm_misc, 224 .prepare = &r100_pm_prepare, 225 .finish = &r100_pm_finish, 226 .init_profile = &r100_pm_init_profile, 227 .get_dynpm_state = &r100_pm_get_dynpm_state, 228 .get_engine_clock = &radeon_legacy_get_engine_clock, 229 .set_engine_clock = &radeon_legacy_set_engine_clock, 230 .get_memory_clock = &radeon_legacy_get_memory_clock, 231 .set_memory_clock = NULL, 232 .get_pcie_lanes = NULL, 233 .set_pcie_lanes = NULL, 234 .set_clock_gating = &radeon_legacy_set_clock_gating, 235 }, 236 .pflip = { 237 .pre_page_flip = &r100_pre_page_flip, 238 .page_flip = &r100_page_flip, 239 .post_page_flip = &r100_post_page_flip, 240 }, 241 }; 242 243 static struct radeon_asic r200_asic = { 244 .init = &r100_init, 245 .fini = &r100_fini, 246 .suspend = &r100_suspend, 247 .resume = &r100_resume, 248 .vga_set_state = &r100_vga_set_state, 249 .asic_reset = &r100_asic_reset, 250 .ioctl_wait_idle = NULL, 251 .gui_idle = &r100_gui_idle, 252 .mc_wait_for_idle = &r100_mc_wait_for_idle, 253 .gart = { 254 .tlb_flush = &r100_pci_gart_tlb_flush, 255 .set_page = &r100_pci_gart_set_page, 256 }, 257 .ring = { 258 [RADEON_RING_TYPE_GFX_INDEX] = { 259 .ib_execute = &r100_ring_ib_execute, 260 .emit_fence = &r100_fence_ring_emit, 261 .emit_semaphore = &r100_semaphore_ring_emit, 262 .cs_parse = &r100_cs_parse, 263 .ring_start = &r100_ring_start, 264 .ring_test = &r100_ring_test, 265 .ib_test = &r100_ib_test, 266 .is_lockup = &r100_gpu_is_lockup, 267 } 268 }, 269 .irq = { 270 .set = &r100_irq_set, 271 .process = &r100_irq_process, 272 }, 273 .display = { 274 .bandwidth_update = &r100_bandwidth_update, 275 .get_vblank_counter = &r100_get_vblank_counter, 276 .wait_for_vblank = &r100_wait_for_vblank, 277 .set_backlight_level = &radeon_legacy_set_backlight_level, 278 .get_backlight_level = &radeon_legacy_get_backlight_level, 279 }, 280 .copy = { 281 .blit = &r100_copy_blit, 282 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 283 .dma = &r200_copy_dma, 284 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 285 .copy = &r100_copy_blit, 286 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 287 }, 288 .surface = { 289 .set_reg = r100_set_surface_reg, 290 .clear_reg = r100_clear_surface_reg, 291 }, 292 .hpd = { 293 .init = &r100_hpd_init, 294 .fini = &r100_hpd_fini, 295 .sense = &r100_hpd_sense, 296 .set_polarity = &r100_hpd_set_polarity, 297 }, 298 .pm = { 299 .misc = &r100_pm_misc, 300 .prepare = &r100_pm_prepare, 301 .finish = &r100_pm_finish, 302 .init_profile = &r100_pm_init_profile, 303 .get_dynpm_state = &r100_pm_get_dynpm_state, 304 .get_engine_clock = &radeon_legacy_get_engine_clock, 305 .set_engine_clock = &radeon_legacy_set_engine_clock, 306 .get_memory_clock = &radeon_legacy_get_memory_clock, 307 .set_memory_clock = NULL, 308 .get_pcie_lanes = NULL, 309 .set_pcie_lanes = NULL, 310 .set_clock_gating = &radeon_legacy_set_clock_gating, 311 }, 312 .pflip = { 313 .pre_page_flip = &r100_pre_page_flip, 314 .page_flip = &r100_page_flip, 315 .post_page_flip = &r100_post_page_flip, 316 }, 317 }; 318 319 static struct radeon_asic r300_asic = { 320 .init = &r300_init, 321 .fini = &r300_fini, 322 .suspend = &r300_suspend, 323 .resume = &r300_resume, 324 .vga_set_state = &r100_vga_set_state, 325 .asic_reset = &r300_asic_reset, 326 .ioctl_wait_idle = NULL, 327 .gui_idle = &r100_gui_idle, 328 .mc_wait_for_idle = &r300_mc_wait_for_idle, 329 .gart = { 330 .tlb_flush = &r100_pci_gart_tlb_flush, 331 .set_page = &r100_pci_gart_set_page, 332 }, 333 .ring = { 334 [RADEON_RING_TYPE_GFX_INDEX] = { 335 .ib_execute = &r100_ring_ib_execute, 336 .emit_fence = &r300_fence_ring_emit, 337 .emit_semaphore = &r100_semaphore_ring_emit, 338 .cs_parse = &r300_cs_parse, 339 .ring_start = &r300_ring_start, 340 .ring_test = &r100_ring_test, 341 .ib_test = &r100_ib_test, 342 .is_lockup = &r100_gpu_is_lockup, 343 } 344 }, 345 .irq = { 346 .set = &r100_irq_set, 347 .process = &r100_irq_process, 348 }, 349 .display = { 350 .bandwidth_update = &r100_bandwidth_update, 351 .get_vblank_counter = &r100_get_vblank_counter, 352 .wait_for_vblank = &r100_wait_for_vblank, 353 .set_backlight_level = &radeon_legacy_set_backlight_level, 354 .get_backlight_level = &radeon_legacy_get_backlight_level, 355 }, 356 .copy = { 357 .blit = &r100_copy_blit, 358 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 359 .dma = &r200_copy_dma, 360 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 361 .copy = &r100_copy_blit, 362 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 363 }, 364 .surface = { 365 .set_reg = r100_set_surface_reg, 366 .clear_reg = r100_clear_surface_reg, 367 }, 368 .hpd = { 369 .init = &r100_hpd_init, 370 .fini = &r100_hpd_fini, 371 .sense = &r100_hpd_sense, 372 .set_polarity = &r100_hpd_set_polarity, 373 }, 374 .pm = { 375 .misc = &r100_pm_misc, 376 .prepare = &r100_pm_prepare, 377 .finish = &r100_pm_finish, 378 .init_profile = &r100_pm_init_profile, 379 .get_dynpm_state = &r100_pm_get_dynpm_state, 380 .get_engine_clock = &radeon_legacy_get_engine_clock, 381 .set_engine_clock = &radeon_legacy_set_engine_clock, 382 .get_memory_clock = &radeon_legacy_get_memory_clock, 383 .set_memory_clock = NULL, 384 .get_pcie_lanes = &rv370_get_pcie_lanes, 385 .set_pcie_lanes = &rv370_set_pcie_lanes, 386 .set_clock_gating = &radeon_legacy_set_clock_gating, 387 }, 388 .pflip = { 389 .pre_page_flip = &r100_pre_page_flip, 390 .page_flip = &r100_page_flip, 391 .post_page_flip = &r100_post_page_flip, 392 }, 393 }; 394 395 static struct radeon_asic r300_asic_pcie = { 396 .init = &r300_init, 397 .fini = &r300_fini, 398 .suspend = &r300_suspend, 399 .resume = &r300_resume, 400 .vga_set_state = &r100_vga_set_state, 401 .asic_reset = &r300_asic_reset, 402 .ioctl_wait_idle = NULL, 403 .gui_idle = &r100_gui_idle, 404 .mc_wait_for_idle = &r300_mc_wait_for_idle, 405 .gart = { 406 .tlb_flush = &rv370_pcie_gart_tlb_flush, 407 .set_page = &rv370_pcie_gart_set_page, 408 }, 409 .ring = { 410 [RADEON_RING_TYPE_GFX_INDEX] = { 411 .ib_execute = &r100_ring_ib_execute, 412 .emit_fence = &r300_fence_ring_emit, 413 .emit_semaphore = &r100_semaphore_ring_emit, 414 .cs_parse = &r300_cs_parse, 415 .ring_start = &r300_ring_start, 416 .ring_test = &r100_ring_test, 417 .ib_test = &r100_ib_test, 418 .is_lockup = &r100_gpu_is_lockup, 419 } 420 }, 421 .irq = { 422 .set = &r100_irq_set, 423 .process = &r100_irq_process, 424 }, 425 .display = { 426 .bandwidth_update = &r100_bandwidth_update, 427 .get_vblank_counter = &r100_get_vblank_counter, 428 .wait_for_vblank = &r100_wait_for_vblank, 429 .set_backlight_level = &radeon_legacy_set_backlight_level, 430 .get_backlight_level = &radeon_legacy_get_backlight_level, 431 }, 432 .copy = { 433 .blit = &r100_copy_blit, 434 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 435 .dma = &r200_copy_dma, 436 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 437 .copy = &r100_copy_blit, 438 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 439 }, 440 .surface = { 441 .set_reg = r100_set_surface_reg, 442 .clear_reg = r100_clear_surface_reg, 443 }, 444 .hpd = { 445 .init = &r100_hpd_init, 446 .fini = &r100_hpd_fini, 447 .sense = &r100_hpd_sense, 448 .set_polarity = &r100_hpd_set_polarity, 449 }, 450 .pm = { 451 .misc = &r100_pm_misc, 452 .prepare = &r100_pm_prepare, 453 .finish = &r100_pm_finish, 454 .init_profile = &r100_pm_init_profile, 455 .get_dynpm_state = &r100_pm_get_dynpm_state, 456 .get_engine_clock = &radeon_legacy_get_engine_clock, 457 .set_engine_clock = &radeon_legacy_set_engine_clock, 458 .get_memory_clock = &radeon_legacy_get_memory_clock, 459 .set_memory_clock = NULL, 460 .get_pcie_lanes = &rv370_get_pcie_lanes, 461 .set_pcie_lanes = &rv370_set_pcie_lanes, 462 .set_clock_gating = &radeon_legacy_set_clock_gating, 463 }, 464 .pflip = { 465 .pre_page_flip = &r100_pre_page_flip, 466 .page_flip = &r100_page_flip, 467 .post_page_flip = &r100_post_page_flip, 468 }, 469 }; 470 471 static struct radeon_asic r420_asic = { 472 .init = &r420_init, 473 .fini = &r420_fini, 474 .suspend = &r420_suspend, 475 .resume = &r420_resume, 476 .vga_set_state = &r100_vga_set_state, 477 .asic_reset = &r300_asic_reset, 478 .ioctl_wait_idle = NULL, 479 .gui_idle = &r100_gui_idle, 480 .mc_wait_for_idle = &r300_mc_wait_for_idle, 481 .gart = { 482 .tlb_flush = &rv370_pcie_gart_tlb_flush, 483 .set_page = &rv370_pcie_gart_set_page, 484 }, 485 .ring = { 486 [RADEON_RING_TYPE_GFX_INDEX] = { 487 .ib_execute = &r100_ring_ib_execute, 488 .emit_fence = &r300_fence_ring_emit, 489 .emit_semaphore = &r100_semaphore_ring_emit, 490 .cs_parse = &r300_cs_parse, 491 .ring_start = &r300_ring_start, 492 .ring_test = &r100_ring_test, 493 .ib_test = &r100_ib_test, 494 .is_lockup = &r100_gpu_is_lockup, 495 } 496 }, 497 .irq = { 498 .set = &r100_irq_set, 499 .process = &r100_irq_process, 500 }, 501 .display = { 502 .bandwidth_update = &r100_bandwidth_update, 503 .get_vblank_counter = &r100_get_vblank_counter, 504 .wait_for_vblank = &r100_wait_for_vblank, 505 .set_backlight_level = &atombios_set_backlight_level, 506 .get_backlight_level = &atombios_get_backlight_level, 507 }, 508 .copy = { 509 .blit = &r100_copy_blit, 510 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 511 .dma = &r200_copy_dma, 512 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 513 .copy = &r100_copy_blit, 514 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 515 }, 516 .surface = { 517 .set_reg = r100_set_surface_reg, 518 .clear_reg = r100_clear_surface_reg, 519 }, 520 .hpd = { 521 .init = &r100_hpd_init, 522 .fini = &r100_hpd_fini, 523 .sense = &r100_hpd_sense, 524 .set_polarity = &r100_hpd_set_polarity, 525 }, 526 .pm = { 527 .misc = &r100_pm_misc, 528 .prepare = &r100_pm_prepare, 529 .finish = &r100_pm_finish, 530 .init_profile = &r420_pm_init_profile, 531 .get_dynpm_state = &r100_pm_get_dynpm_state, 532 .get_engine_clock = &radeon_atom_get_engine_clock, 533 .set_engine_clock = &radeon_atom_set_engine_clock, 534 .get_memory_clock = &radeon_atom_get_memory_clock, 535 .set_memory_clock = &radeon_atom_set_memory_clock, 536 .get_pcie_lanes = &rv370_get_pcie_lanes, 537 .set_pcie_lanes = &rv370_set_pcie_lanes, 538 .set_clock_gating = &radeon_atom_set_clock_gating, 539 }, 540 .pflip = { 541 .pre_page_flip = &r100_pre_page_flip, 542 .page_flip = &r100_page_flip, 543 .post_page_flip = &r100_post_page_flip, 544 }, 545 }; 546 547 static struct radeon_asic rs400_asic = { 548 .init = &rs400_init, 549 .fini = &rs400_fini, 550 .suspend = &rs400_suspend, 551 .resume = &rs400_resume, 552 .vga_set_state = &r100_vga_set_state, 553 .asic_reset = &r300_asic_reset, 554 .ioctl_wait_idle = NULL, 555 .gui_idle = &r100_gui_idle, 556 .mc_wait_for_idle = &rs400_mc_wait_for_idle, 557 .gart = { 558 .tlb_flush = &rs400_gart_tlb_flush, 559 .set_page = &rs400_gart_set_page, 560 }, 561 .ring = { 562 [RADEON_RING_TYPE_GFX_INDEX] = { 563 .ib_execute = &r100_ring_ib_execute, 564 .emit_fence = &r300_fence_ring_emit, 565 .emit_semaphore = &r100_semaphore_ring_emit, 566 .cs_parse = &r300_cs_parse, 567 .ring_start = &r300_ring_start, 568 .ring_test = &r100_ring_test, 569 .ib_test = &r100_ib_test, 570 .is_lockup = &r100_gpu_is_lockup, 571 } 572 }, 573 .irq = { 574 .set = &r100_irq_set, 575 .process = &r100_irq_process, 576 }, 577 .display = { 578 .bandwidth_update = &r100_bandwidth_update, 579 .get_vblank_counter = &r100_get_vblank_counter, 580 .wait_for_vblank = &r100_wait_for_vblank, 581 .set_backlight_level = &radeon_legacy_set_backlight_level, 582 .get_backlight_level = &radeon_legacy_get_backlight_level, 583 }, 584 .copy = { 585 .blit = &r100_copy_blit, 586 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 587 .dma = &r200_copy_dma, 588 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 589 .copy = &r100_copy_blit, 590 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 591 }, 592 .surface = { 593 .set_reg = r100_set_surface_reg, 594 .clear_reg = r100_clear_surface_reg, 595 }, 596 .hpd = { 597 .init = &r100_hpd_init, 598 .fini = &r100_hpd_fini, 599 .sense = &r100_hpd_sense, 600 .set_polarity = &r100_hpd_set_polarity, 601 }, 602 .pm = { 603 .misc = &r100_pm_misc, 604 .prepare = &r100_pm_prepare, 605 .finish = &r100_pm_finish, 606 .init_profile = &r100_pm_init_profile, 607 .get_dynpm_state = &r100_pm_get_dynpm_state, 608 .get_engine_clock = &radeon_legacy_get_engine_clock, 609 .set_engine_clock = &radeon_legacy_set_engine_clock, 610 .get_memory_clock = &radeon_legacy_get_memory_clock, 611 .set_memory_clock = NULL, 612 .get_pcie_lanes = NULL, 613 .set_pcie_lanes = NULL, 614 .set_clock_gating = &radeon_legacy_set_clock_gating, 615 }, 616 .pflip = { 617 .pre_page_flip = &r100_pre_page_flip, 618 .page_flip = &r100_page_flip, 619 .post_page_flip = &r100_post_page_flip, 620 }, 621 }; 622 623 static struct radeon_asic rs600_asic = { 624 .init = &rs600_init, 625 .fini = &rs600_fini, 626 .suspend = &rs600_suspend, 627 .resume = &rs600_resume, 628 .vga_set_state = &r100_vga_set_state, 629 .asic_reset = &rs600_asic_reset, 630 .ioctl_wait_idle = NULL, 631 .gui_idle = &r100_gui_idle, 632 .mc_wait_for_idle = &rs600_mc_wait_for_idle, 633 .gart = { 634 .tlb_flush = &rs600_gart_tlb_flush, 635 .set_page = &rs600_gart_set_page, 636 }, 637 .ring = { 638 [RADEON_RING_TYPE_GFX_INDEX] = { 639 .ib_execute = &r100_ring_ib_execute, 640 .emit_fence = &r300_fence_ring_emit, 641 .emit_semaphore = &r100_semaphore_ring_emit, 642 .cs_parse = &r300_cs_parse, 643 .ring_start = &r300_ring_start, 644 .ring_test = &r100_ring_test, 645 .ib_test = &r100_ib_test, 646 .is_lockup = &r100_gpu_is_lockup, 647 } 648 }, 649 .irq = { 650 .set = &rs600_irq_set, 651 .process = &rs600_irq_process, 652 }, 653 .display = { 654 .bandwidth_update = &rs600_bandwidth_update, 655 .get_vblank_counter = &rs600_get_vblank_counter, 656 .wait_for_vblank = &avivo_wait_for_vblank, 657 .set_backlight_level = &atombios_set_backlight_level, 658 .get_backlight_level = &atombios_get_backlight_level, 659 .hdmi_enable = &r600_hdmi_enable, 660 .hdmi_setmode = &r600_hdmi_setmode, 661 }, 662 .copy = { 663 .blit = &r100_copy_blit, 664 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 665 .dma = &r200_copy_dma, 666 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 667 .copy = &r100_copy_blit, 668 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 669 }, 670 .surface = { 671 .set_reg = r100_set_surface_reg, 672 .clear_reg = r100_clear_surface_reg, 673 }, 674 .hpd = { 675 .init = &rs600_hpd_init, 676 .fini = &rs600_hpd_fini, 677 .sense = &rs600_hpd_sense, 678 .set_polarity = &rs600_hpd_set_polarity, 679 }, 680 .pm = { 681 .misc = &rs600_pm_misc, 682 .prepare = &rs600_pm_prepare, 683 .finish = &rs600_pm_finish, 684 .init_profile = &r420_pm_init_profile, 685 .get_dynpm_state = &r100_pm_get_dynpm_state, 686 .get_engine_clock = &radeon_atom_get_engine_clock, 687 .set_engine_clock = &radeon_atom_set_engine_clock, 688 .get_memory_clock = &radeon_atom_get_memory_clock, 689 .set_memory_clock = &radeon_atom_set_memory_clock, 690 .get_pcie_lanes = NULL, 691 .set_pcie_lanes = NULL, 692 .set_clock_gating = &radeon_atom_set_clock_gating, 693 }, 694 .pflip = { 695 .pre_page_flip = &rs600_pre_page_flip, 696 .page_flip = &rs600_page_flip, 697 .post_page_flip = &rs600_post_page_flip, 698 }, 699 }; 700 701 static struct radeon_asic rs690_asic = { 702 .init = &rs690_init, 703 .fini = &rs690_fini, 704 .suspend = &rs690_suspend, 705 .resume = &rs690_resume, 706 .vga_set_state = &r100_vga_set_state, 707 .asic_reset = &rs600_asic_reset, 708 .ioctl_wait_idle = NULL, 709 .gui_idle = &r100_gui_idle, 710 .mc_wait_for_idle = &rs690_mc_wait_for_idle, 711 .gart = { 712 .tlb_flush = &rs400_gart_tlb_flush, 713 .set_page = &rs400_gart_set_page, 714 }, 715 .ring = { 716 [RADEON_RING_TYPE_GFX_INDEX] = { 717 .ib_execute = &r100_ring_ib_execute, 718 .emit_fence = &r300_fence_ring_emit, 719 .emit_semaphore = &r100_semaphore_ring_emit, 720 .cs_parse = &r300_cs_parse, 721 .ring_start = &r300_ring_start, 722 .ring_test = &r100_ring_test, 723 .ib_test = &r100_ib_test, 724 .is_lockup = &r100_gpu_is_lockup, 725 } 726 }, 727 .irq = { 728 .set = &rs600_irq_set, 729 .process = &rs600_irq_process, 730 }, 731 .display = { 732 .get_vblank_counter = &rs600_get_vblank_counter, 733 .bandwidth_update = &rs690_bandwidth_update, 734 .wait_for_vblank = &avivo_wait_for_vblank, 735 .set_backlight_level = &atombios_set_backlight_level, 736 .get_backlight_level = &atombios_get_backlight_level, 737 .hdmi_enable = &r600_hdmi_enable, 738 .hdmi_setmode = &r600_hdmi_setmode, 739 }, 740 .copy = { 741 .blit = &r100_copy_blit, 742 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 743 .dma = &r200_copy_dma, 744 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 745 .copy = &r200_copy_dma, 746 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 747 }, 748 .surface = { 749 .set_reg = r100_set_surface_reg, 750 .clear_reg = r100_clear_surface_reg, 751 }, 752 .hpd = { 753 .init = &rs600_hpd_init, 754 .fini = &rs600_hpd_fini, 755 .sense = &rs600_hpd_sense, 756 .set_polarity = &rs600_hpd_set_polarity, 757 }, 758 .pm = { 759 .misc = &rs600_pm_misc, 760 .prepare = &rs600_pm_prepare, 761 .finish = &rs600_pm_finish, 762 .init_profile = &r420_pm_init_profile, 763 .get_dynpm_state = &r100_pm_get_dynpm_state, 764 .get_engine_clock = &radeon_atom_get_engine_clock, 765 .set_engine_clock = &radeon_atom_set_engine_clock, 766 .get_memory_clock = &radeon_atom_get_memory_clock, 767 .set_memory_clock = &radeon_atom_set_memory_clock, 768 .get_pcie_lanes = NULL, 769 .set_pcie_lanes = NULL, 770 .set_clock_gating = &radeon_atom_set_clock_gating, 771 }, 772 .pflip = { 773 .pre_page_flip = &rs600_pre_page_flip, 774 .page_flip = &rs600_page_flip, 775 .post_page_flip = &rs600_post_page_flip, 776 }, 777 }; 778 779 static struct radeon_asic rv515_asic = { 780 .init = &rv515_init, 781 .fini = &rv515_fini, 782 .suspend = &rv515_suspend, 783 .resume = &rv515_resume, 784 .vga_set_state = &r100_vga_set_state, 785 .asic_reset = &rs600_asic_reset, 786 .ioctl_wait_idle = NULL, 787 .gui_idle = &r100_gui_idle, 788 .mc_wait_for_idle = &rv515_mc_wait_for_idle, 789 .gart = { 790 .tlb_flush = &rv370_pcie_gart_tlb_flush, 791 .set_page = &rv370_pcie_gart_set_page, 792 }, 793 .ring = { 794 [RADEON_RING_TYPE_GFX_INDEX] = { 795 .ib_execute = &r100_ring_ib_execute, 796 .emit_fence = &r300_fence_ring_emit, 797 .emit_semaphore = &r100_semaphore_ring_emit, 798 .cs_parse = &r300_cs_parse, 799 .ring_start = &rv515_ring_start, 800 .ring_test = &r100_ring_test, 801 .ib_test = &r100_ib_test, 802 .is_lockup = &r100_gpu_is_lockup, 803 } 804 }, 805 .irq = { 806 .set = &rs600_irq_set, 807 .process = &rs600_irq_process, 808 }, 809 .display = { 810 .get_vblank_counter = &rs600_get_vblank_counter, 811 .bandwidth_update = &rv515_bandwidth_update, 812 .wait_for_vblank = &avivo_wait_for_vblank, 813 .set_backlight_level = &atombios_set_backlight_level, 814 .get_backlight_level = &atombios_get_backlight_level, 815 }, 816 .copy = { 817 .blit = &r100_copy_blit, 818 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 819 .dma = &r200_copy_dma, 820 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 821 .copy = &r100_copy_blit, 822 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 823 }, 824 .surface = { 825 .set_reg = r100_set_surface_reg, 826 .clear_reg = r100_clear_surface_reg, 827 }, 828 .hpd = { 829 .init = &rs600_hpd_init, 830 .fini = &rs600_hpd_fini, 831 .sense = &rs600_hpd_sense, 832 .set_polarity = &rs600_hpd_set_polarity, 833 }, 834 .pm = { 835 .misc = &rs600_pm_misc, 836 .prepare = &rs600_pm_prepare, 837 .finish = &rs600_pm_finish, 838 .init_profile = &r420_pm_init_profile, 839 .get_dynpm_state = &r100_pm_get_dynpm_state, 840 .get_engine_clock = &radeon_atom_get_engine_clock, 841 .set_engine_clock = &radeon_atom_set_engine_clock, 842 .get_memory_clock = &radeon_atom_get_memory_clock, 843 .set_memory_clock = &radeon_atom_set_memory_clock, 844 .get_pcie_lanes = &rv370_get_pcie_lanes, 845 .set_pcie_lanes = &rv370_set_pcie_lanes, 846 .set_clock_gating = &radeon_atom_set_clock_gating, 847 }, 848 .pflip = { 849 .pre_page_flip = &rs600_pre_page_flip, 850 .page_flip = &rs600_page_flip, 851 .post_page_flip = &rs600_post_page_flip, 852 }, 853 }; 854 855 static struct radeon_asic r520_asic = { 856 .init = &r520_init, 857 .fini = &rv515_fini, 858 .suspend = &rv515_suspend, 859 .resume = &r520_resume, 860 .vga_set_state = &r100_vga_set_state, 861 .asic_reset = &rs600_asic_reset, 862 .ioctl_wait_idle = NULL, 863 .gui_idle = &r100_gui_idle, 864 .mc_wait_for_idle = &r520_mc_wait_for_idle, 865 .gart = { 866 .tlb_flush = &rv370_pcie_gart_tlb_flush, 867 .set_page = &rv370_pcie_gart_set_page, 868 }, 869 .ring = { 870 [RADEON_RING_TYPE_GFX_INDEX] = { 871 .ib_execute = &r100_ring_ib_execute, 872 .emit_fence = &r300_fence_ring_emit, 873 .emit_semaphore = &r100_semaphore_ring_emit, 874 .cs_parse = &r300_cs_parse, 875 .ring_start = &rv515_ring_start, 876 .ring_test = &r100_ring_test, 877 .ib_test = &r100_ib_test, 878 .is_lockup = &r100_gpu_is_lockup, 879 } 880 }, 881 .irq = { 882 .set = &rs600_irq_set, 883 .process = &rs600_irq_process, 884 }, 885 .display = { 886 .bandwidth_update = &rv515_bandwidth_update, 887 .get_vblank_counter = &rs600_get_vblank_counter, 888 .wait_for_vblank = &avivo_wait_for_vblank, 889 .set_backlight_level = &atombios_set_backlight_level, 890 .get_backlight_level = &atombios_get_backlight_level, 891 }, 892 .copy = { 893 .blit = &r100_copy_blit, 894 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 895 .dma = &r200_copy_dma, 896 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 897 .copy = &r100_copy_blit, 898 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 899 }, 900 .surface = { 901 .set_reg = r100_set_surface_reg, 902 .clear_reg = r100_clear_surface_reg, 903 }, 904 .hpd = { 905 .init = &rs600_hpd_init, 906 .fini = &rs600_hpd_fini, 907 .sense = &rs600_hpd_sense, 908 .set_polarity = &rs600_hpd_set_polarity, 909 }, 910 .pm = { 911 .misc = &rs600_pm_misc, 912 .prepare = &rs600_pm_prepare, 913 .finish = &rs600_pm_finish, 914 .init_profile = &r420_pm_init_profile, 915 .get_dynpm_state = &r100_pm_get_dynpm_state, 916 .get_engine_clock = &radeon_atom_get_engine_clock, 917 .set_engine_clock = &radeon_atom_set_engine_clock, 918 .get_memory_clock = &radeon_atom_get_memory_clock, 919 .set_memory_clock = &radeon_atom_set_memory_clock, 920 .get_pcie_lanes = &rv370_get_pcie_lanes, 921 .set_pcie_lanes = &rv370_set_pcie_lanes, 922 .set_clock_gating = &radeon_atom_set_clock_gating, 923 }, 924 .pflip = { 925 .pre_page_flip = &rs600_pre_page_flip, 926 .page_flip = &rs600_page_flip, 927 .post_page_flip = &rs600_post_page_flip, 928 }, 929 }; 930 931 static struct radeon_asic r600_asic = { 932 .init = &r600_init, 933 .fini = &r600_fini, 934 .suspend = &r600_suspend, 935 .resume = &r600_resume, 936 .vga_set_state = &r600_vga_set_state, 937 .asic_reset = &r600_asic_reset, 938 .ioctl_wait_idle = r600_ioctl_wait_idle, 939 .gui_idle = &r600_gui_idle, 940 .mc_wait_for_idle = &r600_mc_wait_for_idle, 941 .get_xclk = &r600_get_xclk, 942 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 943 .gart = { 944 .tlb_flush = &r600_pcie_gart_tlb_flush, 945 .set_page = &rs600_gart_set_page, 946 }, 947 .ring = { 948 [RADEON_RING_TYPE_GFX_INDEX] = { 949 .ib_execute = &r600_ring_ib_execute, 950 .emit_fence = &r600_fence_ring_emit, 951 .emit_semaphore = &r600_semaphore_ring_emit, 952 .cs_parse = &r600_cs_parse, 953 .ring_test = &r600_ring_test, 954 .ib_test = &r600_ib_test, 955 .is_lockup = &r600_gfx_is_lockup, 956 }, 957 [R600_RING_TYPE_DMA_INDEX] = { 958 .ib_execute = &r600_dma_ring_ib_execute, 959 .emit_fence = &r600_dma_fence_ring_emit, 960 .emit_semaphore = &r600_dma_semaphore_ring_emit, 961 .cs_parse = &r600_dma_cs_parse, 962 .ring_test = &r600_dma_ring_test, 963 .ib_test = &r600_dma_ib_test, 964 .is_lockup = &r600_dma_is_lockup, 965 } 966 }, 967 .irq = { 968 .set = &r600_irq_set, 969 .process = &r600_irq_process, 970 }, 971 .display = { 972 .bandwidth_update = &rv515_bandwidth_update, 973 .get_vblank_counter = &rs600_get_vblank_counter, 974 .wait_for_vblank = &avivo_wait_for_vblank, 975 .set_backlight_level = &atombios_set_backlight_level, 976 .get_backlight_level = &atombios_get_backlight_level, 977 .hdmi_enable = &r600_hdmi_enable, 978 .hdmi_setmode = &r600_hdmi_setmode, 979 }, 980 .copy = { 981 .blit = &r600_copy_blit, 982 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 983 .dma = &r600_copy_dma, 984 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 985 .copy = &r600_copy_dma, 986 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 987 }, 988 .surface = { 989 .set_reg = r600_set_surface_reg, 990 .clear_reg = r600_clear_surface_reg, 991 }, 992 .hpd = { 993 .init = &r600_hpd_init, 994 .fini = &r600_hpd_fini, 995 .sense = &r600_hpd_sense, 996 .set_polarity = &r600_hpd_set_polarity, 997 }, 998 .pm = { 999 .misc = &r600_pm_misc, 1000 .prepare = &rs600_pm_prepare, 1001 .finish = &rs600_pm_finish, 1002 .init_profile = &r600_pm_init_profile, 1003 .get_dynpm_state = &r600_pm_get_dynpm_state, 1004 .get_engine_clock = &radeon_atom_get_engine_clock, 1005 .set_engine_clock = &radeon_atom_set_engine_clock, 1006 .get_memory_clock = &radeon_atom_get_memory_clock, 1007 .set_memory_clock = &radeon_atom_set_memory_clock, 1008 .get_pcie_lanes = &r600_get_pcie_lanes, 1009 .set_pcie_lanes = &r600_set_pcie_lanes, 1010 .set_clock_gating = NULL, 1011 }, 1012 .pflip = { 1013 .pre_page_flip = &rs600_pre_page_flip, 1014 .page_flip = &rs600_page_flip, 1015 .post_page_flip = &rs600_post_page_flip, 1016 }, 1017 }; 1018 1019 static struct radeon_asic rs780_asic = { 1020 .init = &r600_init, 1021 .fini = &r600_fini, 1022 .suspend = &r600_suspend, 1023 .resume = &r600_resume, 1024 .vga_set_state = &r600_vga_set_state, 1025 .asic_reset = &r600_asic_reset, 1026 .ioctl_wait_idle = r600_ioctl_wait_idle, 1027 .gui_idle = &r600_gui_idle, 1028 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1029 .get_xclk = &r600_get_xclk, 1030 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1031 .gart = { 1032 .tlb_flush = &r600_pcie_gart_tlb_flush, 1033 .set_page = &rs600_gart_set_page, 1034 }, 1035 .ring = { 1036 [RADEON_RING_TYPE_GFX_INDEX] = { 1037 .ib_execute = &r600_ring_ib_execute, 1038 .emit_fence = &r600_fence_ring_emit, 1039 .emit_semaphore = &r600_semaphore_ring_emit, 1040 .cs_parse = &r600_cs_parse, 1041 .ring_test = &r600_ring_test, 1042 .ib_test = &r600_ib_test, 1043 .is_lockup = &r600_gfx_is_lockup, 1044 }, 1045 [R600_RING_TYPE_DMA_INDEX] = { 1046 .ib_execute = &r600_dma_ring_ib_execute, 1047 .emit_fence = &r600_dma_fence_ring_emit, 1048 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1049 .cs_parse = &r600_dma_cs_parse, 1050 .ring_test = &r600_dma_ring_test, 1051 .ib_test = &r600_dma_ib_test, 1052 .is_lockup = &r600_dma_is_lockup, 1053 } 1054 }, 1055 .irq = { 1056 .set = &r600_irq_set, 1057 .process = &r600_irq_process, 1058 }, 1059 .display = { 1060 .bandwidth_update = &rs690_bandwidth_update, 1061 .get_vblank_counter = &rs600_get_vblank_counter, 1062 .wait_for_vblank = &avivo_wait_for_vblank, 1063 .set_backlight_level = &atombios_set_backlight_level, 1064 .get_backlight_level = &atombios_get_backlight_level, 1065 .hdmi_enable = &r600_hdmi_enable, 1066 .hdmi_setmode = &r600_hdmi_setmode, 1067 }, 1068 .copy = { 1069 .blit = &r600_copy_blit, 1070 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1071 .dma = &r600_copy_dma, 1072 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1073 .copy = &r600_copy_dma, 1074 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1075 }, 1076 .surface = { 1077 .set_reg = r600_set_surface_reg, 1078 .clear_reg = r600_clear_surface_reg, 1079 }, 1080 .hpd = { 1081 .init = &r600_hpd_init, 1082 .fini = &r600_hpd_fini, 1083 .sense = &r600_hpd_sense, 1084 .set_polarity = &r600_hpd_set_polarity, 1085 }, 1086 .pm = { 1087 .misc = &r600_pm_misc, 1088 .prepare = &rs600_pm_prepare, 1089 .finish = &rs600_pm_finish, 1090 .init_profile = &rs780_pm_init_profile, 1091 .get_dynpm_state = &r600_pm_get_dynpm_state, 1092 .get_engine_clock = &radeon_atom_get_engine_clock, 1093 .set_engine_clock = &radeon_atom_set_engine_clock, 1094 .get_memory_clock = NULL, 1095 .set_memory_clock = NULL, 1096 .get_pcie_lanes = NULL, 1097 .set_pcie_lanes = NULL, 1098 .set_clock_gating = NULL, 1099 }, 1100 .pflip = { 1101 .pre_page_flip = &rs600_pre_page_flip, 1102 .page_flip = &rs600_page_flip, 1103 .post_page_flip = &rs600_post_page_flip, 1104 }, 1105 }; 1106 1107 static struct radeon_asic rv770_asic = { 1108 .init = &rv770_init, 1109 .fini = &rv770_fini, 1110 .suspend = &rv770_suspend, 1111 .resume = &rv770_resume, 1112 .asic_reset = &r600_asic_reset, 1113 .vga_set_state = &r600_vga_set_state, 1114 .ioctl_wait_idle = r600_ioctl_wait_idle, 1115 .gui_idle = &r600_gui_idle, 1116 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1117 .get_xclk = &rv770_get_xclk, 1118 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1119 .gart = { 1120 .tlb_flush = &r600_pcie_gart_tlb_flush, 1121 .set_page = &rs600_gart_set_page, 1122 }, 1123 .ring = { 1124 [RADEON_RING_TYPE_GFX_INDEX] = { 1125 .ib_execute = &r600_ring_ib_execute, 1126 .emit_fence = &r600_fence_ring_emit, 1127 .emit_semaphore = &r600_semaphore_ring_emit, 1128 .cs_parse = &r600_cs_parse, 1129 .ring_test = &r600_ring_test, 1130 .ib_test = &r600_ib_test, 1131 .is_lockup = &r600_gfx_is_lockup, 1132 }, 1133 [R600_RING_TYPE_DMA_INDEX] = { 1134 .ib_execute = &r600_dma_ring_ib_execute, 1135 .emit_fence = &r600_dma_fence_ring_emit, 1136 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1137 .cs_parse = &r600_dma_cs_parse, 1138 .ring_test = &r600_dma_ring_test, 1139 .ib_test = &r600_dma_ib_test, 1140 .is_lockup = &r600_dma_is_lockup, 1141 }, 1142 [R600_RING_TYPE_UVD_INDEX] = { 1143 .ib_execute = &r600_uvd_ib_execute, 1144 .emit_fence = &r600_uvd_fence_emit, 1145 .emit_semaphore = &r600_uvd_semaphore_emit, 1146 .cs_parse = &radeon_uvd_cs_parse, 1147 .ring_test = &r600_uvd_ring_test, 1148 .ib_test = &r600_uvd_ib_test, 1149 .is_lockup = &radeon_ring_test_lockup, 1150 } 1151 }, 1152 .irq = { 1153 .set = &r600_irq_set, 1154 .process = &r600_irq_process, 1155 }, 1156 .display = { 1157 .bandwidth_update = &rv515_bandwidth_update, 1158 .get_vblank_counter = &rs600_get_vblank_counter, 1159 .wait_for_vblank = &avivo_wait_for_vblank, 1160 .set_backlight_level = &atombios_set_backlight_level, 1161 .get_backlight_level = &atombios_get_backlight_level, 1162 .hdmi_enable = &r600_hdmi_enable, 1163 .hdmi_setmode = &r600_hdmi_setmode, 1164 }, 1165 .copy = { 1166 .blit = &r600_copy_blit, 1167 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1168 .dma = &rv770_copy_dma, 1169 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1170 .copy = &rv770_copy_dma, 1171 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1172 }, 1173 .surface = { 1174 .set_reg = r600_set_surface_reg, 1175 .clear_reg = r600_clear_surface_reg, 1176 }, 1177 .hpd = { 1178 .init = &r600_hpd_init, 1179 .fini = &r600_hpd_fini, 1180 .sense = &r600_hpd_sense, 1181 .set_polarity = &r600_hpd_set_polarity, 1182 }, 1183 .pm = { 1184 .misc = &rv770_pm_misc, 1185 .prepare = &rs600_pm_prepare, 1186 .finish = &rs600_pm_finish, 1187 .init_profile = &r600_pm_init_profile, 1188 .get_dynpm_state = &r600_pm_get_dynpm_state, 1189 .get_engine_clock = &radeon_atom_get_engine_clock, 1190 .set_engine_clock = &radeon_atom_set_engine_clock, 1191 .get_memory_clock = &radeon_atom_get_memory_clock, 1192 .set_memory_clock = &radeon_atom_set_memory_clock, 1193 .get_pcie_lanes = &r600_get_pcie_lanes, 1194 .set_pcie_lanes = &r600_set_pcie_lanes, 1195 .set_clock_gating = &radeon_atom_set_clock_gating, 1196 .set_uvd_clocks = &rv770_set_uvd_clocks, 1197 }, 1198 .pflip = { 1199 .pre_page_flip = &rs600_pre_page_flip, 1200 .page_flip = &rv770_page_flip, 1201 .post_page_flip = &rs600_post_page_flip, 1202 }, 1203 }; 1204 1205 static struct radeon_asic evergreen_asic = { 1206 .init = &evergreen_init, 1207 .fini = &evergreen_fini, 1208 .suspend = &evergreen_suspend, 1209 .resume = &evergreen_resume, 1210 .asic_reset = &evergreen_asic_reset, 1211 .vga_set_state = &r600_vga_set_state, 1212 .ioctl_wait_idle = r600_ioctl_wait_idle, 1213 .gui_idle = &r600_gui_idle, 1214 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1215 .get_xclk = &rv770_get_xclk, 1216 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1217 .gart = { 1218 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1219 .set_page = &rs600_gart_set_page, 1220 }, 1221 .ring = { 1222 [RADEON_RING_TYPE_GFX_INDEX] = { 1223 .ib_execute = &evergreen_ring_ib_execute, 1224 .emit_fence = &r600_fence_ring_emit, 1225 .emit_semaphore = &r600_semaphore_ring_emit, 1226 .cs_parse = &evergreen_cs_parse, 1227 .ring_test = &r600_ring_test, 1228 .ib_test = &r600_ib_test, 1229 .is_lockup = &evergreen_gfx_is_lockup, 1230 }, 1231 [R600_RING_TYPE_DMA_INDEX] = { 1232 .ib_execute = &evergreen_dma_ring_ib_execute, 1233 .emit_fence = &evergreen_dma_fence_ring_emit, 1234 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1235 .cs_parse = &evergreen_dma_cs_parse, 1236 .ring_test = &r600_dma_ring_test, 1237 .ib_test = &r600_dma_ib_test, 1238 .is_lockup = &evergreen_dma_is_lockup, 1239 }, 1240 [R600_RING_TYPE_UVD_INDEX] = { 1241 .ib_execute = &r600_uvd_ib_execute, 1242 .emit_fence = &r600_uvd_fence_emit, 1243 .emit_semaphore = &r600_uvd_semaphore_emit, 1244 .cs_parse = &radeon_uvd_cs_parse, 1245 .ring_test = &r600_uvd_ring_test, 1246 .ib_test = &r600_uvd_ib_test, 1247 .is_lockup = &radeon_ring_test_lockup, 1248 } 1249 }, 1250 .irq = { 1251 .set = &evergreen_irq_set, 1252 .process = &evergreen_irq_process, 1253 }, 1254 .display = { 1255 .bandwidth_update = &evergreen_bandwidth_update, 1256 .get_vblank_counter = &evergreen_get_vblank_counter, 1257 .wait_for_vblank = &dce4_wait_for_vblank, 1258 .set_backlight_level = &atombios_set_backlight_level, 1259 .get_backlight_level = &atombios_get_backlight_level, 1260 .hdmi_enable = &evergreen_hdmi_enable, 1261 .hdmi_setmode = &evergreen_hdmi_setmode, 1262 }, 1263 .copy = { 1264 .blit = &r600_copy_blit, 1265 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1266 .dma = &evergreen_copy_dma, 1267 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1268 .copy = &evergreen_copy_dma, 1269 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1270 }, 1271 .surface = { 1272 .set_reg = r600_set_surface_reg, 1273 .clear_reg = r600_clear_surface_reg, 1274 }, 1275 .hpd = { 1276 .init = &evergreen_hpd_init, 1277 .fini = &evergreen_hpd_fini, 1278 .sense = &evergreen_hpd_sense, 1279 .set_polarity = &evergreen_hpd_set_polarity, 1280 }, 1281 .pm = { 1282 .misc = &evergreen_pm_misc, 1283 .prepare = &evergreen_pm_prepare, 1284 .finish = &evergreen_pm_finish, 1285 .init_profile = &r600_pm_init_profile, 1286 .get_dynpm_state = &r600_pm_get_dynpm_state, 1287 .get_engine_clock = &radeon_atom_get_engine_clock, 1288 .set_engine_clock = &radeon_atom_set_engine_clock, 1289 .get_memory_clock = &radeon_atom_get_memory_clock, 1290 .set_memory_clock = &radeon_atom_set_memory_clock, 1291 .get_pcie_lanes = &r600_get_pcie_lanes, 1292 .set_pcie_lanes = &r600_set_pcie_lanes, 1293 .set_clock_gating = NULL, 1294 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1295 }, 1296 .pflip = { 1297 .pre_page_flip = &evergreen_pre_page_flip, 1298 .page_flip = &evergreen_page_flip, 1299 .post_page_flip = &evergreen_post_page_flip, 1300 }, 1301 }; 1302 1303 static struct radeon_asic sumo_asic = { 1304 .init = &evergreen_init, 1305 .fini = &evergreen_fini, 1306 .suspend = &evergreen_suspend, 1307 .resume = &evergreen_resume, 1308 .asic_reset = &evergreen_asic_reset, 1309 .vga_set_state = &r600_vga_set_state, 1310 .ioctl_wait_idle = r600_ioctl_wait_idle, 1311 .gui_idle = &r600_gui_idle, 1312 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1313 .get_xclk = &r600_get_xclk, 1314 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1315 .gart = { 1316 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1317 .set_page = &rs600_gart_set_page, 1318 }, 1319 .ring = { 1320 [RADEON_RING_TYPE_GFX_INDEX] = { 1321 .ib_execute = &evergreen_ring_ib_execute, 1322 .emit_fence = &r600_fence_ring_emit, 1323 .emit_semaphore = &r600_semaphore_ring_emit, 1324 .cs_parse = &evergreen_cs_parse, 1325 .ring_test = &r600_ring_test, 1326 .ib_test = &r600_ib_test, 1327 .is_lockup = &evergreen_gfx_is_lockup, 1328 }, 1329 [R600_RING_TYPE_DMA_INDEX] = { 1330 .ib_execute = &evergreen_dma_ring_ib_execute, 1331 .emit_fence = &evergreen_dma_fence_ring_emit, 1332 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1333 .cs_parse = &evergreen_dma_cs_parse, 1334 .ring_test = &r600_dma_ring_test, 1335 .ib_test = &r600_dma_ib_test, 1336 .is_lockup = &evergreen_dma_is_lockup, 1337 }, 1338 [R600_RING_TYPE_UVD_INDEX] = { 1339 .ib_execute = &r600_uvd_ib_execute, 1340 .emit_fence = &r600_uvd_fence_emit, 1341 .emit_semaphore = &r600_uvd_semaphore_emit, 1342 .cs_parse = &radeon_uvd_cs_parse, 1343 .ring_test = &r600_uvd_ring_test, 1344 .ib_test = &r600_uvd_ib_test, 1345 .is_lockup = &radeon_ring_test_lockup, 1346 } 1347 }, 1348 .irq = { 1349 .set = &evergreen_irq_set, 1350 .process = &evergreen_irq_process, 1351 }, 1352 .display = { 1353 .bandwidth_update = &evergreen_bandwidth_update, 1354 .get_vblank_counter = &evergreen_get_vblank_counter, 1355 .wait_for_vblank = &dce4_wait_for_vblank, 1356 .set_backlight_level = &atombios_set_backlight_level, 1357 .get_backlight_level = &atombios_get_backlight_level, 1358 .hdmi_enable = &evergreen_hdmi_enable, 1359 .hdmi_setmode = &evergreen_hdmi_setmode, 1360 }, 1361 .copy = { 1362 .blit = &r600_copy_blit, 1363 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1364 .dma = &evergreen_copy_dma, 1365 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1366 .copy = &evergreen_copy_dma, 1367 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1368 }, 1369 .surface = { 1370 .set_reg = r600_set_surface_reg, 1371 .clear_reg = r600_clear_surface_reg, 1372 }, 1373 .hpd = { 1374 .init = &evergreen_hpd_init, 1375 .fini = &evergreen_hpd_fini, 1376 .sense = &evergreen_hpd_sense, 1377 .set_polarity = &evergreen_hpd_set_polarity, 1378 }, 1379 .pm = { 1380 .misc = &evergreen_pm_misc, 1381 .prepare = &evergreen_pm_prepare, 1382 .finish = &evergreen_pm_finish, 1383 .init_profile = &sumo_pm_init_profile, 1384 .get_dynpm_state = &r600_pm_get_dynpm_state, 1385 .get_engine_clock = &radeon_atom_get_engine_clock, 1386 .set_engine_clock = &radeon_atom_set_engine_clock, 1387 .get_memory_clock = NULL, 1388 .set_memory_clock = NULL, 1389 .get_pcie_lanes = NULL, 1390 .set_pcie_lanes = NULL, 1391 .set_clock_gating = NULL, 1392 .set_uvd_clocks = &sumo_set_uvd_clocks, 1393 }, 1394 .pflip = { 1395 .pre_page_flip = &evergreen_pre_page_flip, 1396 .page_flip = &evergreen_page_flip, 1397 .post_page_flip = &evergreen_post_page_flip, 1398 }, 1399 }; 1400 1401 static struct radeon_asic btc_asic = { 1402 .init = &evergreen_init, 1403 .fini = &evergreen_fini, 1404 .suspend = &evergreen_suspend, 1405 .resume = &evergreen_resume, 1406 .asic_reset = &evergreen_asic_reset, 1407 .vga_set_state = &r600_vga_set_state, 1408 .ioctl_wait_idle = r600_ioctl_wait_idle, 1409 .gui_idle = &r600_gui_idle, 1410 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1411 .get_xclk = &rv770_get_xclk, 1412 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1413 .gart = { 1414 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1415 .set_page = &rs600_gart_set_page, 1416 }, 1417 .ring = { 1418 [RADEON_RING_TYPE_GFX_INDEX] = { 1419 .ib_execute = &evergreen_ring_ib_execute, 1420 .emit_fence = &r600_fence_ring_emit, 1421 .emit_semaphore = &r600_semaphore_ring_emit, 1422 .cs_parse = &evergreen_cs_parse, 1423 .ring_test = &r600_ring_test, 1424 .ib_test = &r600_ib_test, 1425 .is_lockup = &evergreen_gfx_is_lockup, 1426 }, 1427 [R600_RING_TYPE_DMA_INDEX] = { 1428 .ib_execute = &evergreen_dma_ring_ib_execute, 1429 .emit_fence = &evergreen_dma_fence_ring_emit, 1430 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1431 .cs_parse = &evergreen_dma_cs_parse, 1432 .ring_test = &r600_dma_ring_test, 1433 .ib_test = &r600_dma_ib_test, 1434 .is_lockup = &evergreen_dma_is_lockup, 1435 }, 1436 [R600_RING_TYPE_UVD_INDEX] = { 1437 .ib_execute = &r600_uvd_ib_execute, 1438 .emit_fence = &r600_uvd_fence_emit, 1439 .emit_semaphore = &r600_uvd_semaphore_emit, 1440 .cs_parse = &radeon_uvd_cs_parse, 1441 .ring_test = &r600_uvd_ring_test, 1442 .ib_test = &r600_uvd_ib_test, 1443 .is_lockup = &radeon_ring_test_lockup, 1444 } 1445 }, 1446 .irq = { 1447 .set = &evergreen_irq_set, 1448 .process = &evergreen_irq_process, 1449 }, 1450 .display = { 1451 .bandwidth_update = &evergreen_bandwidth_update, 1452 .get_vblank_counter = &evergreen_get_vblank_counter, 1453 .wait_for_vblank = &dce4_wait_for_vblank, 1454 .set_backlight_level = &atombios_set_backlight_level, 1455 .get_backlight_level = &atombios_get_backlight_level, 1456 .hdmi_enable = &evergreen_hdmi_enable, 1457 .hdmi_setmode = &evergreen_hdmi_setmode, 1458 }, 1459 .copy = { 1460 .blit = &r600_copy_blit, 1461 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1462 .dma = &evergreen_copy_dma, 1463 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1464 .copy = &evergreen_copy_dma, 1465 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1466 }, 1467 .surface = { 1468 .set_reg = r600_set_surface_reg, 1469 .clear_reg = r600_clear_surface_reg, 1470 }, 1471 .hpd = { 1472 .init = &evergreen_hpd_init, 1473 .fini = &evergreen_hpd_fini, 1474 .sense = &evergreen_hpd_sense, 1475 .set_polarity = &evergreen_hpd_set_polarity, 1476 }, 1477 .pm = { 1478 .misc = &evergreen_pm_misc, 1479 .prepare = &evergreen_pm_prepare, 1480 .finish = &evergreen_pm_finish, 1481 .init_profile = &btc_pm_init_profile, 1482 .get_dynpm_state = &r600_pm_get_dynpm_state, 1483 .get_engine_clock = &radeon_atom_get_engine_clock, 1484 .set_engine_clock = &radeon_atom_set_engine_clock, 1485 .get_memory_clock = &radeon_atom_get_memory_clock, 1486 .set_memory_clock = &radeon_atom_set_memory_clock, 1487 .get_pcie_lanes = &r600_get_pcie_lanes, 1488 .set_pcie_lanes = &r600_set_pcie_lanes, 1489 .set_clock_gating = NULL, 1490 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1491 }, 1492 .pflip = { 1493 .pre_page_flip = &evergreen_pre_page_flip, 1494 .page_flip = &evergreen_page_flip, 1495 .post_page_flip = &evergreen_post_page_flip, 1496 }, 1497 }; 1498 1499 static struct radeon_asic cayman_asic = { 1500 .init = &cayman_init, 1501 .fini = &cayman_fini, 1502 .suspend = &cayman_suspend, 1503 .resume = &cayman_resume, 1504 .asic_reset = &cayman_asic_reset, 1505 .vga_set_state = &r600_vga_set_state, 1506 .ioctl_wait_idle = r600_ioctl_wait_idle, 1507 .gui_idle = &r600_gui_idle, 1508 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1509 .get_xclk = &rv770_get_xclk, 1510 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1511 .gart = { 1512 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1513 .set_page = &rs600_gart_set_page, 1514 }, 1515 .vm = { 1516 .init = &cayman_vm_init, 1517 .fini = &cayman_vm_fini, 1518 .pt_ring_index = R600_RING_TYPE_DMA_INDEX, 1519 .set_page = &cayman_vm_set_page, 1520 }, 1521 .ring = { 1522 [RADEON_RING_TYPE_GFX_INDEX] = { 1523 .ib_execute = &cayman_ring_ib_execute, 1524 .ib_parse = &evergreen_ib_parse, 1525 .emit_fence = &cayman_fence_ring_emit, 1526 .emit_semaphore = &r600_semaphore_ring_emit, 1527 .cs_parse = &evergreen_cs_parse, 1528 .ring_test = &r600_ring_test, 1529 .ib_test = &r600_ib_test, 1530 .is_lockup = &cayman_gfx_is_lockup, 1531 .vm_flush = &cayman_vm_flush, 1532 }, 1533 [CAYMAN_RING_TYPE_CP1_INDEX] = { 1534 .ib_execute = &cayman_ring_ib_execute, 1535 .ib_parse = &evergreen_ib_parse, 1536 .emit_fence = &cayman_fence_ring_emit, 1537 .emit_semaphore = &r600_semaphore_ring_emit, 1538 .cs_parse = &evergreen_cs_parse, 1539 .ring_test = &r600_ring_test, 1540 .ib_test = &r600_ib_test, 1541 .is_lockup = &cayman_gfx_is_lockup, 1542 .vm_flush = &cayman_vm_flush, 1543 }, 1544 [CAYMAN_RING_TYPE_CP2_INDEX] = { 1545 .ib_execute = &cayman_ring_ib_execute, 1546 .ib_parse = &evergreen_ib_parse, 1547 .emit_fence = &cayman_fence_ring_emit, 1548 .emit_semaphore = &r600_semaphore_ring_emit, 1549 .cs_parse = &evergreen_cs_parse, 1550 .ring_test = &r600_ring_test, 1551 .ib_test = &r600_ib_test, 1552 .is_lockup = &cayman_gfx_is_lockup, 1553 .vm_flush = &cayman_vm_flush, 1554 }, 1555 [R600_RING_TYPE_DMA_INDEX] = { 1556 .ib_execute = &cayman_dma_ring_ib_execute, 1557 .ib_parse = &evergreen_dma_ib_parse, 1558 .emit_fence = &evergreen_dma_fence_ring_emit, 1559 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1560 .cs_parse = &evergreen_dma_cs_parse, 1561 .ring_test = &r600_dma_ring_test, 1562 .ib_test = &r600_dma_ib_test, 1563 .is_lockup = &cayman_dma_is_lockup, 1564 .vm_flush = &cayman_dma_vm_flush, 1565 }, 1566 [CAYMAN_RING_TYPE_DMA1_INDEX] = { 1567 .ib_execute = &cayman_dma_ring_ib_execute, 1568 .ib_parse = &evergreen_dma_ib_parse, 1569 .emit_fence = &evergreen_dma_fence_ring_emit, 1570 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1571 .cs_parse = &evergreen_dma_cs_parse, 1572 .ring_test = &r600_dma_ring_test, 1573 .ib_test = &r600_dma_ib_test, 1574 .is_lockup = &cayman_dma_is_lockup, 1575 .vm_flush = &cayman_dma_vm_flush, 1576 }, 1577 [R600_RING_TYPE_UVD_INDEX] = { 1578 .ib_execute = &r600_uvd_ib_execute, 1579 .emit_fence = &r600_uvd_fence_emit, 1580 .emit_semaphore = &cayman_uvd_semaphore_emit, 1581 .cs_parse = &radeon_uvd_cs_parse, 1582 .ring_test = &r600_uvd_ring_test, 1583 .ib_test = &r600_uvd_ib_test, 1584 .is_lockup = &radeon_ring_test_lockup, 1585 } 1586 }, 1587 .irq = { 1588 .set = &evergreen_irq_set, 1589 .process = &evergreen_irq_process, 1590 }, 1591 .display = { 1592 .bandwidth_update = &evergreen_bandwidth_update, 1593 .get_vblank_counter = &evergreen_get_vblank_counter, 1594 .wait_for_vblank = &dce4_wait_for_vblank, 1595 .set_backlight_level = &atombios_set_backlight_level, 1596 .get_backlight_level = &atombios_get_backlight_level, 1597 .hdmi_enable = &evergreen_hdmi_enable, 1598 .hdmi_setmode = &evergreen_hdmi_setmode, 1599 }, 1600 .copy = { 1601 .blit = &r600_copy_blit, 1602 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1603 .dma = &evergreen_copy_dma, 1604 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1605 .copy = &evergreen_copy_dma, 1606 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1607 }, 1608 .surface = { 1609 .set_reg = r600_set_surface_reg, 1610 .clear_reg = r600_clear_surface_reg, 1611 }, 1612 .hpd = { 1613 .init = &evergreen_hpd_init, 1614 .fini = &evergreen_hpd_fini, 1615 .sense = &evergreen_hpd_sense, 1616 .set_polarity = &evergreen_hpd_set_polarity, 1617 }, 1618 .pm = { 1619 .misc = &evergreen_pm_misc, 1620 .prepare = &evergreen_pm_prepare, 1621 .finish = &evergreen_pm_finish, 1622 .init_profile = &btc_pm_init_profile, 1623 .get_dynpm_state = &r600_pm_get_dynpm_state, 1624 .get_engine_clock = &radeon_atom_get_engine_clock, 1625 .set_engine_clock = &radeon_atom_set_engine_clock, 1626 .get_memory_clock = &radeon_atom_get_memory_clock, 1627 .set_memory_clock = &radeon_atom_set_memory_clock, 1628 .get_pcie_lanes = &r600_get_pcie_lanes, 1629 .set_pcie_lanes = &r600_set_pcie_lanes, 1630 .set_clock_gating = NULL, 1631 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1632 }, 1633 .pflip = { 1634 .pre_page_flip = &evergreen_pre_page_flip, 1635 .page_flip = &evergreen_page_flip, 1636 .post_page_flip = &evergreen_post_page_flip, 1637 }, 1638 }; 1639 1640 static struct radeon_asic trinity_asic = { 1641 .init = &cayman_init, 1642 .fini = &cayman_fini, 1643 .suspend = &cayman_suspend, 1644 .resume = &cayman_resume, 1645 .asic_reset = &cayman_asic_reset, 1646 .vga_set_state = &r600_vga_set_state, 1647 .ioctl_wait_idle = r600_ioctl_wait_idle, 1648 .gui_idle = &r600_gui_idle, 1649 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1650 .get_xclk = &r600_get_xclk, 1651 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1652 .gart = { 1653 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1654 .set_page = &rs600_gart_set_page, 1655 }, 1656 .vm = { 1657 .init = &cayman_vm_init, 1658 .fini = &cayman_vm_fini, 1659 .pt_ring_index = R600_RING_TYPE_DMA_INDEX, 1660 .set_page = &cayman_vm_set_page, 1661 }, 1662 .ring = { 1663 [RADEON_RING_TYPE_GFX_INDEX] = { 1664 .ib_execute = &cayman_ring_ib_execute, 1665 .ib_parse = &evergreen_ib_parse, 1666 .emit_fence = &cayman_fence_ring_emit, 1667 .emit_semaphore = &r600_semaphore_ring_emit, 1668 .cs_parse = &evergreen_cs_parse, 1669 .ring_test = &r600_ring_test, 1670 .ib_test = &r600_ib_test, 1671 .is_lockup = &cayman_gfx_is_lockup, 1672 .vm_flush = &cayman_vm_flush, 1673 }, 1674 [CAYMAN_RING_TYPE_CP1_INDEX] = { 1675 .ib_execute = &cayman_ring_ib_execute, 1676 .ib_parse = &evergreen_ib_parse, 1677 .emit_fence = &cayman_fence_ring_emit, 1678 .emit_semaphore = &r600_semaphore_ring_emit, 1679 .cs_parse = &evergreen_cs_parse, 1680 .ring_test = &r600_ring_test, 1681 .ib_test = &r600_ib_test, 1682 .is_lockup = &cayman_gfx_is_lockup, 1683 .vm_flush = &cayman_vm_flush, 1684 }, 1685 [CAYMAN_RING_TYPE_CP2_INDEX] = { 1686 .ib_execute = &cayman_ring_ib_execute, 1687 .ib_parse = &evergreen_ib_parse, 1688 .emit_fence = &cayman_fence_ring_emit, 1689 .emit_semaphore = &r600_semaphore_ring_emit, 1690 .cs_parse = &evergreen_cs_parse, 1691 .ring_test = &r600_ring_test, 1692 .ib_test = &r600_ib_test, 1693 .is_lockup = &cayman_gfx_is_lockup, 1694 .vm_flush = &cayman_vm_flush, 1695 }, 1696 [R600_RING_TYPE_DMA_INDEX] = { 1697 .ib_execute = &cayman_dma_ring_ib_execute, 1698 .ib_parse = &evergreen_dma_ib_parse, 1699 .emit_fence = &evergreen_dma_fence_ring_emit, 1700 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1701 .cs_parse = &evergreen_dma_cs_parse, 1702 .ring_test = &r600_dma_ring_test, 1703 .ib_test = &r600_dma_ib_test, 1704 .is_lockup = &cayman_dma_is_lockup, 1705 .vm_flush = &cayman_dma_vm_flush, 1706 }, 1707 [CAYMAN_RING_TYPE_DMA1_INDEX] = { 1708 .ib_execute = &cayman_dma_ring_ib_execute, 1709 .ib_parse = &evergreen_dma_ib_parse, 1710 .emit_fence = &evergreen_dma_fence_ring_emit, 1711 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1712 .cs_parse = &evergreen_dma_cs_parse, 1713 .ring_test = &r600_dma_ring_test, 1714 .ib_test = &r600_dma_ib_test, 1715 .is_lockup = &cayman_dma_is_lockup, 1716 .vm_flush = &cayman_dma_vm_flush, 1717 }, 1718 [R600_RING_TYPE_UVD_INDEX] = { 1719 .ib_execute = &r600_uvd_ib_execute, 1720 .emit_fence = &r600_uvd_fence_emit, 1721 .emit_semaphore = &cayman_uvd_semaphore_emit, 1722 .cs_parse = &radeon_uvd_cs_parse, 1723 .ring_test = &r600_uvd_ring_test, 1724 .ib_test = &r600_uvd_ib_test, 1725 .is_lockup = &radeon_ring_test_lockup, 1726 } 1727 }, 1728 .irq = { 1729 .set = &evergreen_irq_set, 1730 .process = &evergreen_irq_process, 1731 }, 1732 .display = { 1733 .bandwidth_update = &dce6_bandwidth_update, 1734 .get_vblank_counter = &evergreen_get_vblank_counter, 1735 .wait_for_vblank = &dce4_wait_for_vblank, 1736 .set_backlight_level = &atombios_set_backlight_level, 1737 .get_backlight_level = &atombios_get_backlight_level, 1738 }, 1739 .copy = { 1740 .blit = &r600_copy_blit, 1741 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1742 .dma = &evergreen_copy_dma, 1743 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1744 .copy = &evergreen_copy_dma, 1745 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1746 }, 1747 .surface = { 1748 .set_reg = r600_set_surface_reg, 1749 .clear_reg = r600_clear_surface_reg, 1750 }, 1751 .hpd = { 1752 .init = &evergreen_hpd_init, 1753 .fini = &evergreen_hpd_fini, 1754 .sense = &evergreen_hpd_sense, 1755 .set_polarity = &evergreen_hpd_set_polarity, 1756 }, 1757 .pm = { 1758 .misc = &evergreen_pm_misc, 1759 .prepare = &evergreen_pm_prepare, 1760 .finish = &evergreen_pm_finish, 1761 .init_profile = &sumo_pm_init_profile, 1762 .get_dynpm_state = &r600_pm_get_dynpm_state, 1763 .get_engine_clock = &radeon_atom_get_engine_clock, 1764 .set_engine_clock = &radeon_atom_set_engine_clock, 1765 .get_memory_clock = NULL, 1766 .set_memory_clock = NULL, 1767 .get_pcie_lanes = NULL, 1768 .set_pcie_lanes = NULL, 1769 .set_clock_gating = NULL, 1770 .set_uvd_clocks = &sumo_set_uvd_clocks, 1771 }, 1772 .pflip = { 1773 .pre_page_flip = &evergreen_pre_page_flip, 1774 .page_flip = &evergreen_page_flip, 1775 .post_page_flip = &evergreen_post_page_flip, 1776 }, 1777 }; 1778 1779 static struct radeon_asic si_asic = { 1780 .init = &si_init, 1781 .fini = &si_fini, 1782 .suspend = &si_suspend, 1783 .resume = &si_resume, 1784 .asic_reset = &si_asic_reset, 1785 .vga_set_state = &r600_vga_set_state, 1786 .ioctl_wait_idle = r600_ioctl_wait_idle, 1787 .gui_idle = &r600_gui_idle, 1788 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1789 .get_xclk = &si_get_xclk, 1790 .get_gpu_clock_counter = &si_get_gpu_clock_counter, 1791 .gart = { 1792 .tlb_flush = &si_pcie_gart_tlb_flush, 1793 .set_page = &rs600_gart_set_page, 1794 }, 1795 .vm = { 1796 .init = &si_vm_init, 1797 .fini = &si_vm_fini, 1798 .pt_ring_index = R600_RING_TYPE_DMA_INDEX, 1799 .set_page = &si_vm_set_page, 1800 }, 1801 .ring = { 1802 [RADEON_RING_TYPE_GFX_INDEX] = { 1803 .ib_execute = &si_ring_ib_execute, 1804 .ib_parse = &si_ib_parse, 1805 .emit_fence = &si_fence_ring_emit, 1806 .emit_semaphore = &r600_semaphore_ring_emit, 1807 .cs_parse = NULL, 1808 .ring_test = &r600_ring_test, 1809 .ib_test = &r600_ib_test, 1810 .is_lockup = &si_gfx_is_lockup, 1811 .vm_flush = &si_vm_flush, 1812 }, 1813 [CAYMAN_RING_TYPE_CP1_INDEX] = { 1814 .ib_execute = &si_ring_ib_execute, 1815 .ib_parse = &si_ib_parse, 1816 .emit_fence = &si_fence_ring_emit, 1817 .emit_semaphore = &r600_semaphore_ring_emit, 1818 .cs_parse = NULL, 1819 .ring_test = &r600_ring_test, 1820 .ib_test = &r600_ib_test, 1821 .is_lockup = &si_gfx_is_lockup, 1822 .vm_flush = &si_vm_flush, 1823 }, 1824 [CAYMAN_RING_TYPE_CP2_INDEX] = { 1825 .ib_execute = &si_ring_ib_execute, 1826 .ib_parse = &si_ib_parse, 1827 .emit_fence = &si_fence_ring_emit, 1828 .emit_semaphore = &r600_semaphore_ring_emit, 1829 .cs_parse = NULL, 1830 .ring_test = &r600_ring_test, 1831 .ib_test = &r600_ib_test, 1832 .is_lockup = &si_gfx_is_lockup, 1833 .vm_flush = &si_vm_flush, 1834 }, 1835 [R600_RING_TYPE_DMA_INDEX] = { 1836 .ib_execute = &cayman_dma_ring_ib_execute, 1837 .ib_parse = &evergreen_dma_ib_parse, 1838 .emit_fence = &evergreen_dma_fence_ring_emit, 1839 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1840 .cs_parse = NULL, 1841 .ring_test = &r600_dma_ring_test, 1842 .ib_test = &r600_dma_ib_test, 1843 .is_lockup = &si_dma_is_lockup, 1844 .vm_flush = &si_dma_vm_flush, 1845 }, 1846 [CAYMAN_RING_TYPE_DMA1_INDEX] = { 1847 .ib_execute = &cayman_dma_ring_ib_execute, 1848 .ib_parse = &evergreen_dma_ib_parse, 1849 .emit_fence = &evergreen_dma_fence_ring_emit, 1850 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1851 .cs_parse = NULL, 1852 .ring_test = &r600_dma_ring_test, 1853 .ib_test = &r600_dma_ib_test, 1854 .is_lockup = &si_dma_is_lockup, 1855 .vm_flush = &si_dma_vm_flush, 1856 }, 1857 [R600_RING_TYPE_UVD_INDEX] = { 1858 .ib_execute = &r600_uvd_ib_execute, 1859 .emit_fence = &r600_uvd_fence_emit, 1860 .emit_semaphore = &cayman_uvd_semaphore_emit, 1861 .cs_parse = &radeon_uvd_cs_parse, 1862 .ring_test = &r600_uvd_ring_test, 1863 .ib_test = &r600_uvd_ib_test, 1864 .is_lockup = &radeon_ring_test_lockup, 1865 } 1866 }, 1867 .irq = { 1868 .set = &si_irq_set, 1869 .process = &si_irq_process, 1870 }, 1871 .display = { 1872 .bandwidth_update = &dce6_bandwidth_update, 1873 .get_vblank_counter = &evergreen_get_vblank_counter, 1874 .wait_for_vblank = &dce4_wait_for_vblank, 1875 .set_backlight_level = &atombios_set_backlight_level, 1876 .get_backlight_level = &atombios_get_backlight_level, 1877 }, 1878 .copy = { 1879 .blit = NULL, 1880 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1881 .dma = &si_copy_dma, 1882 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1883 .copy = &si_copy_dma, 1884 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1885 }, 1886 .surface = { 1887 .set_reg = r600_set_surface_reg, 1888 .clear_reg = r600_clear_surface_reg, 1889 }, 1890 .hpd = { 1891 .init = &evergreen_hpd_init, 1892 .fini = &evergreen_hpd_fini, 1893 .sense = &evergreen_hpd_sense, 1894 .set_polarity = &evergreen_hpd_set_polarity, 1895 }, 1896 .pm = { 1897 .misc = &evergreen_pm_misc, 1898 .prepare = &evergreen_pm_prepare, 1899 .finish = &evergreen_pm_finish, 1900 .init_profile = &sumo_pm_init_profile, 1901 .get_dynpm_state = &r600_pm_get_dynpm_state, 1902 .get_engine_clock = &radeon_atom_get_engine_clock, 1903 .set_engine_clock = &radeon_atom_set_engine_clock, 1904 .get_memory_clock = &radeon_atom_get_memory_clock, 1905 .set_memory_clock = &radeon_atom_set_memory_clock, 1906 .get_pcie_lanes = &r600_get_pcie_lanes, 1907 .set_pcie_lanes = &r600_set_pcie_lanes, 1908 .set_clock_gating = NULL, 1909 .set_uvd_clocks = &si_set_uvd_clocks, 1910 }, 1911 .pflip = { 1912 .pre_page_flip = &evergreen_pre_page_flip, 1913 .page_flip = &evergreen_page_flip, 1914 .post_page_flip = &evergreen_post_page_flip, 1915 }, 1916 }; 1917 1918 /** 1919 * radeon_asic_init - register asic specific callbacks 1920 * 1921 * @rdev: radeon device pointer 1922 * 1923 * Registers the appropriate asic specific callbacks for each 1924 * chip family. Also sets other asics specific info like the number 1925 * of crtcs and the register aperture accessors (all asics). 1926 * Returns 0 for success. 1927 */ 1928 int radeon_asic_init(struct radeon_device *rdev) 1929 { 1930 radeon_register_accessor_init(rdev); 1931 1932 /* set the number of crtcs */ 1933 if (rdev->flags & RADEON_SINGLE_CRTC) 1934 rdev->num_crtc = 1; 1935 else 1936 rdev->num_crtc = 2; 1937 1938 switch (rdev->family) { 1939 case CHIP_R100: 1940 case CHIP_RV100: 1941 case CHIP_RS100: 1942 case CHIP_RV200: 1943 case CHIP_RS200: 1944 rdev->asic = &r100_asic; 1945 break; 1946 case CHIP_R200: 1947 case CHIP_RV250: 1948 case CHIP_RS300: 1949 case CHIP_RV280: 1950 rdev->asic = &r200_asic; 1951 break; 1952 case CHIP_R300: 1953 case CHIP_R350: 1954 case CHIP_RV350: 1955 case CHIP_RV380: 1956 if (rdev->flags & RADEON_IS_PCIE) 1957 rdev->asic = &r300_asic_pcie; 1958 else 1959 rdev->asic = &r300_asic; 1960 break; 1961 case CHIP_R420: 1962 case CHIP_R423: 1963 case CHIP_RV410: 1964 rdev->asic = &r420_asic; 1965 /* handle macs */ 1966 if (rdev->bios == NULL) { 1967 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; 1968 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; 1969 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; 1970 rdev->asic->pm.set_memory_clock = NULL; 1971 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; 1972 } 1973 break; 1974 case CHIP_RS400: 1975 case CHIP_RS480: 1976 rdev->asic = &rs400_asic; 1977 break; 1978 case CHIP_RS600: 1979 rdev->asic = &rs600_asic; 1980 break; 1981 case CHIP_RS690: 1982 case CHIP_RS740: 1983 rdev->asic = &rs690_asic; 1984 break; 1985 case CHIP_RV515: 1986 rdev->asic = &rv515_asic; 1987 break; 1988 case CHIP_R520: 1989 case CHIP_RV530: 1990 case CHIP_RV560: 1991 case CHIP_RV570: 1992 case CHIP_R580: 1993 rdev->asic = &r520_asic; 1994 break; 1995 case CHIP_R600: 1996 case CHIP_RV610: 1997 case CHIP_RV630: 1998 case CHIP_RV620: 1999 case CHIP_RV635: 2000 case CHIP_RV670: 2001 rdev->asic = &r600_asic; 2002 break; 2003 case CHIP_RS780: 2004 case CHIP_RS880: 2005 rdev->asic = &rs780_asic; 2006 break; 2007 case CHIP_RV770: 2008 case CHIP_RV730: 2009 case CHIP_RV710: 2010 case CHIP_RV740: 2011 rdev->asic = &rv770_asic; 2012 break; 2013 case CHIP_CEDAR: 2014 case CHIP_REDWOOD: 2015 case CHIP_JUNIPER: 2016 case CHIP_CYPRESS: 2017 case CHIP_HEMLOCK: 2018 /* set num crtcs */ 2019 if (rdev->family == CHIP_CEDAR) 2020 rdev->num_crtc = 4; 2021 else 2022 rdev->num_crtc = 6; 2023 rdev->asic = &evergreen_asic; 2024 break; 2025 case CHIP_PALM: 2026 case CHIP_SUMO: 2027 case CHIP_SUMO2: 2028 rdev->asic = &sumo_asic; 2029 break; 2030 case CHIP_BARTS: 2031 case CHIP_TURKS: 2032 case CHIP_CAICOS: 2033 /* set num crtcs */ 2034 if (rdev->family == CHIP_CAICOS) 2035 rdev->num_crtc = 4; 2036 else 2037 rdev->num_crtc = 6; 2038 rdev->asic = &btc_asic; 2039 break; 2040 case CHIP_CAYMAN: 2041 rdev->asic = &cayman_asic; 2042 /* set num crtcs */ 2043 rdev->num_crtc = 6; 2044 break; 2045 case CHIP_ARUBA: 2046 rdev->asic = &trinity_asic; 2047 /* set num crtcs */ 2048 rdev->num_crtc = 4; 2049 break; 2050 case CHIP_TAHITI: 2051 case CHIP_PITCAIRN: 2052 case CHIP_VERDE: 2053 case CHIP_OLAND: 2054 rdev->asic = &si_asic; 2055 /* set num crtcs */ 2056 if (rdev->family == CHIP_OLAND) 2057 rdev->num_crtc = 2; 2058 else 2059 rdev->num_crtc = 6; 2060 break; 2061 default: 2062 /* FIXME: not supported yet */ 2063 return -EINVAL; 2064 } 2065 2066 if (rdev->flags & RADEON_IS_IGP) { 2067 rdev->asic->pm.get_memory_clock = NULL; 2068 rdev->asic->pm.set_memory_clock = NULL; 2069 } 2070 2071 return 0; 2072 } 2073 2074