1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/console.h> 30 #include <linux/vgaarb.h> 31 32 #include <drm/drm_crtc_helper.h> 33 #include <drm/drm_pci.h> 34 #include <drm/radeon_drm.h> 35 36 #include "atom.h" 37 #include "radeon.h" 38 #include "radeon_asic.h" 39 #include "radeon_reg.h" 40 41 /* 42 * Registers accessors functions. 43 */ 44 /** 45 * radeon_invalid_rreg - dummy reg read function 46 * 47 * @rdev: radeon device pointer 48 * @reg: offset of register 49 * 50 * Dummy register read function. Used for register blocks 51 * that certain asics don't have (all asics). 52 * Returns the value in the register. 53 */ 54 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) 55 { 56 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); 57 BUG_ON(1); 58 return 0; 59 } 60 61 /** 62 * radeon_invalid_wreg - dummy reg write function 63 * 64 * @rdev: radeon device pointer 65 * @reg: offset of register 66 * @v: value to write to the register 67 * 68 * Dummy register read function. Used for register blocks 69 * that certain asics don't have (all asics). 70 */ 71 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 72 { 73 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", 74 reg, v); 75 BUG_ON(1); 76 } 77 78 /** 79 * radeon_register_accessor_init - sets up the register accessor callbacks 80 * 81 * @rdev: radeon device pointer 82 * 83 * Sets up the register accessor callbacks for various register 84 * apertures. Not all asics have all apertures (all asics). 85 */ 86 static void radeon_register_accessor_init(struct radeon_device *rdev) 87 { 88 rdev->mc_rreg = &radeon_invalid_rreg; 89 rdev->mc_wreg = &radeon_invalid_wreg; 90 rdev->pll_rreg = &radeon_invalid_rreg; 91 rdev->pll_wreg = &radeon_invalid_wreg; 92 rdev->pciep_rreg = &radeon_invalid_rreg; 93 rdev->pciep_wreg = &radeon_invalid_wreg; 94 95 /* Don't change order as we are overridding accessor. */ 96 if (rdev->family < CHIP_RV515) { 97 rdev->pcie_reg_mask = 0xff; 98 } else { 99 rdev->pcie_reg_mask = 0x7ff; 100 } 101 /* FIXME: not sure here */ 102 if (rdev->family <= CHIP_R580) { 103 rdev->pll_rreg = &r100_pll_rreg; 104 rdev->pll_wreg = &r100_pll_wreg; 105 } 106 if (rdev->family >= CHIP_R420) { 107 rdev->mc_rreg = &r420_mc_rreg; 108 rdev->mc_wreg = &r420_mc_wreg; 109 } 110 if (rdev->family >= CHIP_RV515) { 111 rdev->mc_rreg = &rv515_mc_rreg; 112 rdev->mc_wreg = &rv515_mc_wreg; 113 } 114 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { 115 rdev->mc_rreg = &rs400_mc_rreg; 116 rdev->mc_wreg = &rs400_mc_wreg; 117 } 118 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 119 rdev->mc_rreg = &rs690_mc_rreg; 120 rdev->mc_wreg = &rs690_mc_wreg; 121 } 122 if (rdev->family == CHIP_RS600) { 123 rdev->mc_rreg = &rs600_mc_rreg; 124 rdev->mc_wreg = &rs600_mc_wreg; 125 } 126 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 127 rdev->mc_rreg = &rs780_mc_rreg; 128 rdev->mc_wreg = &rs780_mc_wreg; 129 } 130 131 if (rdev->family >= CHIP_BONAIRE) { 132 rdev->pciep_rreg = &cik_pciep_rreg; 133 rdev->pciep_wreg = &cik_pciep_wreg; 134 } else if (rdev->family >= CHIP_R600) { 135 rdev->pciep_rreg = &r600_pciep_rreg; 136 rdev->pciep_wreg = &r600_pciep_wreg; 137 } 138 } 139 140 static int radeon_invalid_get_allowed_info_register(struct radeon_device *rdev, 141 u32 reg, u32 *val) 142 { 143 return -EINVAL; 144 } 145 146 /* helper to disable agp */ 147 /** 148 * radeon_agp_disable - AGP disable helper function 149 * 150 * @rdev: radeon device pointer 151 * 152 * Removes AGP flags and changes the gart callbacks on AGP 153 * cards when using the internal gart rather than AGP (all asics). 154 */ 155 void radeon_agp_disable(struct radeon_device *rdev) 156 { 157 rdev->flags &= ~RADEON_IS_AGP; 158 if (rdev->family >= CHIP_R600) { 159 DRM_INFO("Forcing AGP to PCIE mode\n"); 160 rdev->flags |= RADEON_IS_PCIE; 161 } else if (rdev->family >= CHIP_RV515 || 162 rdev->family == CHIP_RV380 || 163 rdev->family == CHIP_RV410 || 164 rdev->family == CHIP_R423) { 165 DRM_INFO("Forcing AGP to PCIE mode\n"); 166 rdev->flags |= RADEON_IS_PCIE; 167 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 168 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; 169 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 170 } else { 171 DRM_INFO("Forcing AGP to PCI mode\n"); 172 rdev->flags |= RADEON_IS_PCI; 173 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 174 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; 175 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 176 } 177 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 178 } 179 180 /* 181 * ASIC 182 */ 183 184 static const struct radeon_asic_ring r100_gfx_ring = { 185 .ib_execute = &r100_ring_ib_execute, 186 .emit_fence = &r100_fence_ring_emit, 187 .emit_semaphore = &r100_semaphore_ring_emit, 188 .cs_parse = &r100_cs_parse, 189 .ring_start = &r100_ring_start, 190 .ring_test = &r100_ring_test, 191 .ib_test = &r100_ib_test, 192 .is_lockup = &r100_gpu_is_lockup, 193 .get_rptr = &r100_gfx_get_rptr, 194 .get_wptr = &r100_gfx_get_wptr, 195 .set_wptr = &r100_gfx_set_wptr, 196 }; 197 198 static struct radeon_asic r100_asic = { 199 .init = &r100_init, 200 .fini = &r100_fini, 201 .suspend = &r100_suspend, 202 .resume = &r100_resume, 203 .vga_set_state = &r100_vga_set_state, 204 .asic_reset = &r100_asic_reset, 205 .mmio_hdp_flush = NULL, 206 .gui_idle = &r100_gui_idle, 207 .mc_wait_for_idle = &r100_mc_wait_for_idle, 208 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 209 .gart = { 210 .tlb_flush = &r100_pci_gart_tlb_flush, 211 .get_page_entry = &r100_pci_gart_get_page_entry, 212 .set_page = &r100_pci_gart_set_page, 213 }, 214 .ring = { 215 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring 216 }, 217 .irq = { 218 .set = &r100_irq_set, 219 .process = &r100_irq_process, 220 }, 221 .display = { 222 .bandwidth_update = &r100_bandwidth_update, 223 .get_vblank_counter = &r100_get_vblank_counter, 224 .wait_for_vblank = &r100_wait_for_vblank, 225 .set_backlight_level = &radeon_legacy_set_backlight_level, 226 .get_backlight_level = &radeon_legacy_get_backlight_level, 227 }, 228 .copy = { 229 .blit = &r100_copy_blit, 230 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 231 .dma = NULL, 232 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 233 .copy = &r100_copy_blit, 234 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 235 }, 236 .surface = { 237 .set_reg = r100_set_surface_reg, 238 .clear_reg = r100_clear_surface_reg, 239 }, 240 .hpd = { 241 .init = &r100_hpd_init, 242 .fini = &r100_hpd_fini, 243 .sense = &r100_hpd_sense, 244 .set_polarity = &r100_hpd_set_polarity, 245 }, 246 .pm = { 247 .misc = &r100_pm_misc, 248 .prepare = &r100_pm_prepare, 249 .finish = &r100_pm_finish, 250 .init_profile = &r100_pm_init_profile, 251 .get_dynpm_state = &r100_pm_get_dynpm_state, 252 .get_engine_clock = &radeon_legacy_get_engine_clock, 253 .set_engine_clock = &radeon_legacy_set_engine_clock, 254 .get_memory_clock = &radeon_legacy_get_memory_clock, 255 .set_memory_clock = NULL, 256 .get_pcie_lanes = NULL, 257 .set_pcie_lanes = NULL, 258 .set_clock_gating = &radeon_legacy_set_clock_gating, 259 }, 260 .pflip = { 261 .page_flip = &r100_page_flip, 262 .page_flip_pending = &r100_page_flip_pending, 263 }, 264 }; 265 266 static struct radeon_asic r200_asic = { 267 .init = &r100_init, 268 .fini = &r100_fini, 269 .suspend = &r100_suspend, 270 .resume = &r100_resume, 271 .vga_set_state = &r100_vga_set_state, 272 .asic_reset = &r100_asic_reset, 273 .mmio_hdp_flush = NULL, 274 .gui_idle = &r100_gui_idle, 275 .mc_wait_for_idle = &r100_mc_wait_for_idle, 276 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 277 .gart = { 278 .tlb_flush = &r100_pci_gart_tlb_flush, 279 .get_page_entry = &r100_pci_gart_get_page_entry, 280 .set_page = &r100_pci_gart_set_page, 281 }, 282 .ring = { 283 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring 284 }, 285 .irq = { 286 .set = &r100_irq_set, 287 .process = &r100_irq_process, 288 }, 289 .display = { 290 .bandwidth_update = &r100_bandwidth_update, 291 .get_vblank_counter = &r100_get_vblank_counter, 292 .wait_for_vblank = &r100_wait_for_vblank, 293 .set_backlight_level = &radeon_legacy_set_backlight_level, 294 .get_backlight_level = &radeon_legacy_get_backlight_level, 295 }, 296 .copy = { 297 .blit = &r100_copy_blit, 298 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 299 .dma = &r200_copy_dma, 300 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 301 .copy = &r100_copy_blit, 302 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 303 }, 304 .surface = { 305 .set_reg = r100_set_surface_reg, 306 .clear_reg = r100_clear_surface_reg, 307 }, 308 .hpd = { 309 .init = &r100_hpd_init, 310 .fini = &r100_hpd_fini, 311 .sense = &r100_hpd_sense, 312 .set_polarity = &r100_hpd_set_polarity, 313 }, 314 .pm = { 315 .misc = &r100_pm_misc, 316 .prepare = &r100_pm_prepare, 317 .finish = &r100_pm_finish, 318 .init_profile = &r100_pm_init_profile, 319 .get_dynpm_state = &r100_pm_get_dynpm_state, 320 .get_engine_clock = &radeon_legacy_get_engine_clock, 321 .set_engine_clock = &radeon_legacy_set_engine_clock, 322 .get_memory_clock = &radeon_legacy_get_memory_clock, 323 .set_memory_clock = NULL, 324 .get_pcie_lanes = NULL, 325 .set_pcie_lanes = NULL, 326 .set_clock_gating = &radeon_legacy_set_clock_gating, 327 }, 328 .pflip = { 329 .page_flip = &r100_page_flip, 330 .page_flip_pending = &r100_page_flip_pending, 331 }, 332 }; 333 334 static const struct radeon_asic_ring r300_gfx_ring = { 335 .ib_execute = &r100_ring_ib_execute, 336 .emit_fence = &r300_fence_ring_emit, 337 .emit_semaphore = &r100_semaphore_ring_emit, 338 .cs_parse = &r300_cs_parse, 339 .ring_start = &r300_ring_start, 340 .ring_test = &r100_ring_test, 341 .ib_test = &r100_ib_test, 342 .is_lockup = &r100_gpu_is_lockup, 343 .get_rptr = &r100_gfx_get_rptr, 344 .get_wptr = &r100_gfx_get_wptr, 345 .set_wptr = &r100_gfx_set_wptr, 346 }; 347 348 static const struct radeon_asic_ring rv515_gfx_ring = { 349 .ib_execute = &r100_ring_ib_execute, 350 .emit_fence = &r300_fence_ring_emit, 351 .emit_semaphore = &r100_semaphore_ring_emit, 352 .cs_parse = &r300_cs_parse, 353 .ring_start = &rv515_ring_start, 354 .ring_test = &r100_ring_test, 355 .ib_test = &r100_ib_test, 356 .is_lockup = &r100_gpu_is_lockup, 357 .get_rptr = &r100_gfx_get_rptr, 358 .get_wptr = &r100_gfx_get_wptr, 359 .set_wptr = &r100_gfx_set_wptr, 360 }; 361 362 static struct radeon_asic r300_asic = { 363 .init = &r300_init, 364 .fini = &r300_fini, 365 .suspend = &r300_suspend, 366 .resume = &r300_resume, 367 .vga_set_state = &r100_vga_set_state, 368 .asic_reset = &r300_asic_reset, 369 .mmio_hdp_flush = NULL, 370 .gui_idle = &r100_gui_idle, 371 .mc_wait_for_idle = &r300_mc_wait_for_idle, 372 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 373 .gart = { 374 .tlb_flush = &r100_pci_gart_tlb_flush, 375 .get_page_entry = &r100_pci_gart_get_page_entry, 376 .set_page = &r100_pci_gart_set_page, 377 }, 378 .ring = { 379 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 380 }, 381 .irq = { 382 .set = &r100_irq_set, 383 .process = &r100_irq_process, 384 }, 385 .display = { 386 .bandwidth_update = &r100_bandwidth_update, 387 .get_vblank_counter = &r100_get_vblank_counter, 388 .wait_for_vblank = &r100_wait_for_vblank, 389 .set_backlight_level = &radeon_legacy_set_backlight_level, 390 .get_backlight_level = &radeon_legacy_get_backlight_level, 391 }, 392 .copy = { 393 .blit = &r100_copy_blit, 394 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 395 .dma = &r200_copy_dma, 396 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 397 .copy = &r100_copy_blit, 398 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 399 }, 400 .surface = { 401 .set_reg = r100_set_surface_reg, 402 .clear_reg = r100_clear_surface_reg, 403 }, 404 .hpd = { 405 .init = &r100_hpd_init, 406 .fini = &r100_hpd_fini, 407 .sense = &r100_hpd_sense, 408 .set_polarity = &r100_hpd_set_polarity, 409 }, 410 .pm = { 411 .misc = &r100_pm_misc, 412 .prepare = &r100_pm_prepare, 413 .finish = &r100_pm_finish, 414 .init_profile = &r100_pm_init_profile, 415 .get_dynpm_state = &r100_pm_get_dynpm_state, 416 .get_engine_clock = &radeon_legacy_get_engine_clock, 417 .set_engine_clock = &radeon_legacy_set_engine_clock, 418 .get_memory_clock = &radeon_legacy_get_memory_clock, 419 .set_memory_clock = NULL, 420 .get_pcie_lanes = &rv370_get_pcie_lanes, 421 .set_pcie_lanes = &rv370_set_pcie_lanes, 422 .set_clock_gating = &radeon_legacy_set_clock_gating, 423 }, 424 .pflip = { 425 .page_flip = &r100_page_flip, 426 .page_flip_pending = &r100_page_flip_pending, 427 }, 428 }; 429 430 static struct radeon_asic r300_asic_pcie = { 431 .init = &r300_init, 432 .fini = &r300_fini, 433 .suspend = &r300_suspend, 434 .resume = &r300_resume, 435 .vga_set_state = &r100_vga_set_state, 436 .asic_reset = &r300_asic_reset, 437 .mmio_hdp_flush = NULL, 438 .gui_idle = &r100_gui_idle, 439 .mc_wait_for_idle = &r300_mc_wait_for_idle, 440 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 441 .gart = { 442 .tlb_flush = &rv370_pcie_gart_tlb_flush, 443 .get_page_entry = &rv370_pcie_gart_get_page_entry, 444 .set_page = &rv370_pcie_gart_set_page, 445 }, 446 .ring = { 447 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 448 }, 449 .irq = { 450 .set = &r100_irq_set, 451 .process = &r100_irq_process, 452 }, 453 .display = { 454 .bandwidth_update = &r100_bandwidth_update, 455 .get_vblank_counter = &r100_get_vblank_counter, 456 .wait_for_vblank = &r100_wait_for_vblank, 457 .set_backlight_level = &radeon_legacy_set_backlight_level, 458 .get_backlight_level = &radeon_legacy_get_backlight_level, 459 }, 460 .copy = { 461 .blit = &r100_copy_blit, 462 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 463 .dma = &r200_copy_dma, 464 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 465 .copy = &r100_copy_blit, 466 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 467 }, 468 .surface = { 469 .set_reg = r100_set_surface_reg, 470 .clear_reg = r100_clear_surface_reg, 471 }, 472 .hpd = { 473 .init = &r100_hpd_init, 474 .fini = &r100_hpd_fini, 475 .sense = &r100_hpd_sense, 476 .set_polarity = &r100_hpd_set_polarity, 477 }, 478 .pm = { 479 .misc = &r100_pm_misc, 480 .prepare = &r100_pm_prepare, 481 .finish = &r100_pm_finish, 482 .init_profile = &r100_pm_init_profile, 483 .get_dynpm_state = &r100_pm_get_dynpm_state, 484 .get_engine_clock = &radeon_legacy_get_engine_clock, 485 .set_engine_clock = &radeon_legacy_set_engine_clock, 486 .get_memory_clock = &radeon_legacy_get_memory_clock, 487 .set_memory_clock = NULL, 488 .get_pcie_lanes = &rv370_get_pcie_lanes, 489 .set_pcie_lanes = &rv370_set_pcie_lanes, 490 .set_clock_gating = &radeon_legacy_set_clock_gating, 491 }, 492 .pflip = { 493 .page_flip = &r100_page_flip, 494 .page_flip_pending = &r100_page_flip_pending, 495 }, 496 }; 497 498 static struct radeon_asic r420_asic = { 499 .init = &r420_init, 500 .fini = &r420_fini, 501 .suspend = &r420_suspend, 502 .resume = &r420_resume, 503 .vga_set_state = &r100_vga_set_state, 504 .asic_reset = &r300_asic_reset, 505 .mmio_hdp_flush = NULL, 506 .gui_idle = &r100_gui_idle, 507 .mc_wait_for_idle = &r300_mc_wait_for_idle, 508 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 509 .gart = { 510 .tlb_flush = &rv370_pcie_gart_tlb_flush, 511 .get_page_entry = &rv370_pcie_gart_get_page_entry, 512 .set_page = &rv370_pcie_gart_set_page, 513 }, 514 .ring = { 515 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 516 }, 517 .irq = { 518 .set = &r100_irq_set, 519 .process = &r100_irq_process, 520 }, 521 .display = { 522 .bandwidth_update = &r100_bandwidth_update, 523 .get_vblank_counter = &r100_get_vblank_counter, 524 .wait_for_vblank = &r100_wait_for_vblank, 525 .set_backlight_level = &atombios_set_backlight_level, 526 .get_backlight_level = &atombios_get_backlight_level, 527 }, 528 .copy = { 529 .blit = &r100_copy_blit, 530 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 531 .dma = &r200_copy_dma, 532 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 533 .copy = &r100_copy_blit, 534 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 535 }, 536 .surface = { 537 .set_reg = r100_set_surface_reg, 538 .clear_reg = r100_clear_surface_reg, 539 }, 540 .hpd = { 541 .init = &r100_hpd_init, 542 .fini = &r100_hpd_fini, 543 .sense = &r100_hpd_sense, 544 .set_polarity = &r100_hpd_set_polarity, 545 }, 546 .pm = { 547 .misc = &r100_pm_misc, 548 .prepare = &r100_pm_prepare, 549 .finish = &r100_pm_finish, 550 .init_profile = &r420_pm_init_profile, 551 .get_dynpm_state = &r100_pm_get_dynpm_state, 552 .get_engine_clock = &radeon_atom_get_engine_clock, 553 .set_engine_clock = &radeon_atom_set_engine_clock, 554 .get_memory_clock = &radeon_atom_get_memory_clock, 555 .set_memory_clock = &radeon_atom_set_memory_clock, 556 .get_pcie_lanes = &rv370_get_pcie_lanes, 557 .set_pcie_lanes = &rv370_set_pcie_lanes, 558 .set_clock_gating = &radeon_atom_set_clock_gating, 559 }, 560 .pflip = { 561 .page_flip = &r100_page_flip, 562 .page_flip_pending = &r100_page_flip_pending, 563 }, 564 }; 565 566 static struct radeon_asic rs400_asic = { 567 .init = &rs400_init, 568 .fini = &rs400_fini, 569 .suspend = &rs400_suspend, 570 .resume = &rs400_resume, 571 .vga_set_state = &r100_vga_set_state, 572 .asic_reset = &r300_asic_reset, 573 .mmio_hdp_flush = NULL, 574 .gui_idle = &r100_gui_idle, 575 .mc_wait_for_idle = &rs400_mc_wait_for_idle, 576 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 577 .gart = { 578 .tlb_flush = &rs400_gart_tlb_flush, 579 .get_page_entry = &rs400_gart_get_page_entry, 580 .set_page = &rs400_gart_set_page, 581 }, 582 .ring = { 583 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 584 }, 585 .irq = { 586 .set = &r100_irq_set, 587 .process = &r100_irq_process, 588 }, 589 .display = { 590 .bandwidth_update = &r100_bandwidth_update, 591 .get_vblank_counter = &r100_get_vblank_counter, 592 .wait_for_vblank = &r100_wait_for_vblank, 593 .set_backlight_level = &radeon_legacy_set_backlight_level, 594 .get_backlight_level = &radeon_legacy_get_backlight_level, 595 }, 596 .copy = { 597 .blit = &r100_copy_blit, 598 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 599 .dma = &r200_copy_dma, 600 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 601 .copy = &r100_copy_blit, 602 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 603 }, 604 .surface = { 605 .set_reg = r100_set_surface_reg, 606 .clear_reg = r100_clear_surface_reg, 607 }, 608 .hpd = { 609 .init = &r100_hpd_init, 610 .fini = &r100_hpd_fini, 611 .sense = &r100_hpd_sense, 612 .set_polarity = &r100_hpd_set_polarity, 613 }, 614 .pm = { 615 .misc = &r100_pm_misc, 616 .prepare = &r100_pm_prepare, 617 .finish = &r100_pm_finish, 618 .init_profile = &r100_pm_init_profile, 619 .get_dynpm_state = &r100_pm_get_dynpm_state, 620 .get_engine_clock = &radeon_legacy_get_engine_clock, 621 .set_engine_clock = &radeon_legacy_set_engine_clock, 622 .get_memory_clock = &radeon_legacy_get_memory_clock, 623 .set_memory_clock = NULL, 624 .get_pcie_lanes = NULL, 625 .set_pcie_lanes = NULL, 626 .set_clock_gating = &radeon_legacy_set_clock_gating, 627 }, 628 .pflip = { 629 .page_flip = &r100_page_flip, 630 .page_flip_pending = &r100_page_flip_pending, 631 }, 632 }; 633 634 static struct radeon_asic rs600_asic = { 635 .init = &rs600_init, 636 .fini = &rs600_fini, 637 .suspend = &rs600_suspend, 638 .resume = &rs600_resume, 639 .vga_set_state = &r100_vga_set_state, 640 .asic_reset = &rs600_asic_reset, 641 .mmio_hdp_flush = NULL, 642 .gui_idle = &r100_gui_idle, 643 .mc_wait_for_idle = &rs600_mc_wait_for_idle, 644 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 645 .gart = { 646 .tlb_flush = &rs600_gart_tlb_flush, 647 .get_page_entry = &rs600_gart_get_page_entry, 648 .set_page = &rs600_gart_set_page, 649 }, 650 .ring = { 651 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 652 }, 653 .irq = { 654 .set = &rs600_irq_set, 655 .process = &rs600_irq_process, 656 }, 657 .display = { 658 .bandwidth_update = &rs600_bandwidth_update, 659 .get_vblank_counter = &rs600_get_vblank_counter, 660 .wait_for_vblank = &avivo_wait_for_vblank, 661 .set_backlight_level = &atombios_set_backlight_level, 662 .get_backlight_level = &atombios_get_backlight_level, 663 }, 664 .copy = { 665 .blit = &r100_copy_blit, 666 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 667 .dma = &r200_copy_dma, 668 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 669 .copy = &r100_copy_blit, 670 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 671 }, 672 .surface = { 673 .set_reg = r100_set_surface_reg, 674 .clear_reg = r100_clear_surface_reg, 675 }, 676 .hpd = { 677 .init = &rs600_hpd_init, 678 .fini = &rs600_hpd_fini, 679 .sense = &rs600_hpd_sense, 680 .set_polarity = &rs600_hpd_set_polarity, 681 }, 682 .pm = { 683 .misc = &rs600_pm_misc, 684 .prepare = &rs600_pm_prepare, 685 .finish = &rs600_pm_finish, 686 .init_profile = &r420_pm_init_profile, 687 .get_dynpm_state = &r100_pm_get_dynpm_state, 688 .get_engine_clock = &radeon_atom_get_engine_clock, 689 .set_engine_clock = &radeon_atom_set_engine_clock, 690 .get_memory_clock = &radeon_atom_get_memory_clock, 691 .set_memory_clock = &radeon_atom_set_memory_clock, 692 .get_pcie_lanes = NULL, 693 .set_pcie_lanes = NULL, 694 .set_clock_gating = &radeon_atom_set_clock_gating, 695 }, 696 .pflip = { 697 .page_flip = &rs600_page_flip, 698 .page_flip_pending = &rs600_page_flip_pending, 699 }, 700 }; 701 702 static struct radeon_asic rs690_asic = { 703 .init = &rs690_init, 704 .fini = &rs690_fini, 705 .suspend = &rs690_suspend, 706 .resume = &rs690_resume, 707 .vga_set_state = &r100_vga_set_state, 708 .asic_reset = &rs600_asic_reset, 709 .mmio_hdp_flush = NULL, 710 .gui_idle = &r100_gui_idle, 711 .mc_wait_for_idle = &rs690_mc_wait_for_idle, 712 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 713 .gart = { 714 .tlb_flush = &rs400_gart_tlb_flush, 715 .get_page_entry = &rs400_gart_get_page_entry, 716 .set_page = &rs400_gart_set_page, 717 }, 718 .ring = { 719 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 720 }, 721 .irq = { 722 .set = &rs600_irq_set, 723 .process = &rs600_irq_process, 724 }, 725 .display = { 726 .get_vblank_counter = &rs600_get_vblank_counter, 727 .bandwidth_update = &rs690_bandwidth_update, 728 .wait_for_vblank = &avivo_wait_for_vblank, 729 .set_backlight_level = &atombios_set_backlight_level, 730 .get_backlight_level = &atombios_get_backlight_level, 731 }, 732 .copy = { 733 .blit = &r100_copy_blit, 734 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 735 .dma = &r200_copy_dma, 736 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 737 .copy = &r200_copy_dma, 738 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 739 }, 740 .surface = { 741 .set_reg = r100_set_surface_reg, 742 .clear_reg = r100_clear_surface_reg, 743 }, 744 .hpd = { 745 .init = &rs600_hpd_init, 746 .fini = &rs600_hpd_fini, 747 .sense = &rs600_hpd_sense, 748 .set_polarity = &rs600_hpd_set_polarity, 749 }, 750 .pm = { 751 .misc = &rs600_pm_misc, 752 .prepare = &rs600_pm_prepare, 753 .finish = &rs600_pm_finish, 754 .init_profile = &r420_pm_init_profile, 755 .get_dynpm_state = &r100_pm_get_dynpm_state, 756 .get_engine_clock = &radeon_atom_get_engine_clock, 757 .set_engine_clock = &radeon_atom_set_engine_clock, 758 .get_memory_clock = &radeon_atom_get_memory_clock, 759 .set_memory_clock = &radeon_atom_set_memory_clock, 760 .get_pcie_lanes = NULL, 761 .set_pcie_lanes = NULL, 762 .set_clock_gating = &radeon_atom_set_clock_gating, 763 }, 764 .pflip = { 765 .page_flip = &rs600_page_flip, 766 .page_flip_pending = &rs600_page_flip_pending, 767 }, 768 }; 769 770 static struct radeon_asic rv515_asic = { 771 .init = &rv515_init, 772 .fini = &rv515_fini, 773 .suspend = &rv515_suspend, 774 .resume = &rv515_resume, 775 .vga_set_state = &r100_vga_set_state, 776 .asic_reset = &rs600_asic_reset, 777 .mmio_hdp_flush = NULL, 778 .gui_idle = &r100_gui_idle, 779 .mc_wait_for_idle = &rv515_mc_wait_for_idle, 780 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 781 .gart = { 782 .tlb_flush = &rv370_pcie_gart_tlb_flush, 783 .get_page_entry = &rv370_pcie_gart_get_page_entry, 784 .set_page = &rv370_pcie_gart_set_page, 785 }, 786 .ring = { 787 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring 788 }, 789 .irq = { 790 .set = &rs600_irq_set, 791 .process = &rs600_irq_process, 792 }, 793 .display = { 794 .get_vblank_counter = &rs600_get_vblank_counter, 795 .bandwidth_update = &rv515_bandwidth_update, 796 .wait_for_vblank = &avivo_wait_for_vblank, 797 .set_backlight_level = &atombios_set_backlight_level, 798 .get_backlight_level = &atombios_get_backlight_level, 799 }, 800 .copy = { 801 .blit = &r100_copy_blit, 802 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 803 .dma = &r200_copy_dma, 804 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 805 .copy = &r100_copy_blit, 806 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 807 }, 808 .surface = { 809 .set_reg = r100_set_surface_reg, 810 .clear_reg = r100_clear_surface_reg, 811 }, 812 .hpd = { 813 .init = &rs600_hpd_init, 814 .fini = &rs600_hpd_fini, 815 .sense = &rs600_hpd_sense, 816 .set_polarity = &rs600_hpd_set_polarity, 817 }, 818 .pm = { 819 .misc = &rs600_pm_misc, 820 .prepare = &rs600_pm_prepare, 821 .finish = &rs600_pm_finish, 822 .init_profile = &r420_pm_init_profile, 823 .get_dynpm_state = &r100_pm_get_dynpm_state, 824 .get_engine_clock = &radeon_atom_get_engine_clock, 825 .set_engine_clock = &radeon_atom_set_engine_clock, 826 .get_memory_clock = &radeon_atom_get_memory_clock, 827 .set_memory_clock = &radeon_atom_set_memory_clock, 828 .get_pcie_lanes = &rv370_get_pcie_lanes, 829 .set_pcie_lanes = &rv370_set_pcie_lanes, 830 .set_clock_gating = &radeon_atom_set_clock_gating, 831 }, 832 .pflip = { 833 .page_flip = &rs600_page_flip, 834 .page_flip_pending = &rs600_page_flip_pending, 835 }, 836 }; 837 838 static struct radeon_asic r520_asic = { 839 .init = &r520_init, 840 .fini = &rv515_fini, 841 .suspend = &rv515_suspend, 842 .resume = &r520_resume, 843 .vga_set_state = &r100_vga_set_state, 844 .asic_reset = &rs600_asic_reset, 845 .mmio_hdp_flush = NULL, 846 .gui_idle = &r100_gui_idle, 847 .mc_wait_for_idle = &r520_mc_wait_for_idle, 848 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 849 .gart = { 850 .tlb_flush = &rv370_pcie_gart_tlb_flush, 851 .get_page_entry = &rv370_pcie_gart_get_page_entry, 852 .set_page = &rv370_pcie_gart_set_page, 853 }, 854 .ring = { 855 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring 856 }, 857 .irq = { 858 .set = &rs600_irq_set, 859 .process = &rs600_irq_process, 860 }, 861 .display = { 862 .bandwidth_update = &rv515_bandwidth_update, 863 .get_vblank_counter = &rs600_get_vblank_counter, 864 .wait_for_vblank = &avivo_wait_for_vblank, 865 .set_backlight_level = &atombios_set_backlight_level, 866 .get_backlight_level = &atombios_get_backlight_level, 867 }, 868 .copy = { 869 .blit = &r100_copy_blit, 870 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 871 .dma = &r200_copy_dma, 872 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 873 .copy = &r100_copy_blit, 874 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 875 }, 876 .surface = { 877 .set_reg = r100_set_surface_reg, 878 .clear_reg = r100_clear_surface_reg, 879 }, 880 .hpd = { 881 .init = &rs600_hpd_init, 882 .fini = &rs600_hpd_fini, 883 .sense = &rs600_hpd_sense, 884 .set_polarity = &rs600_hpd_set_polarity, 885 }, 886 .pm = { 887 .misc = &rs600_pm_misc, 888 .prepare = &rs600_pm_prepare, 889 .finish = &rs600_pm_finish, 890 .init_profile = &r420_pm_init_profile, 891 .get_dynpm_state = &r100_pm_get_dynpm_state, 892 .get_engine_clock = &radeon_atom_get_engine_clock, 893 .set_engine_clock = &radeon_atom_set_engine_clock, 894 .get_memory_clock = &radeon_atom_get_memory_clock, 895 .set_memory_clock = &radeon_atom_set_memory_clock, 896 .get_pcie_lanes = &rv370_get_pcie_lanes, 897 .set_pcie_lanes = &rv370_set_pcie_lanes, 898 .set_clock_gating = &radeon_atom_set_clock_gating, 899 }, 900 .pflip = { 901 .page_flip = &rs600_page_flip, 902 .page_flip_pending = &rs600_page_flip_pending, 903 }, 904 }; 905 906 static const struct radeon_asic_ring r600_gfx_ring = { 907 .ib_execute = &r600_ring_ib_execute, 908 .emit_fence = &r600_fence_ring_emit, 909 .emit_semaphore = &r600_semaphore_ring_emit, 910 .cs_parse = &r600_cs_parse, 911 .ring_test = &r600_ring_test, 912 .ib_test = &r600_ib_test, 913 .is_lockup = &r600_gfx_is_lockup, 914 .get_rptr = &r600_gfx_get_rptr, 915 .get_wptr = &r600_gfx_get_wptr, 916 .set_wptr = &r600_gfx_set_wptr, 917 }; 918 919 static const struct radeon_asic_ring r600_dma_ring = { 920 .ib_execute = &r600_dma_ring_ib_execute, 921 .emit_fence = &r600_dma_fence_ring_emit, 922 .emit_semaphore = &r600_dma_semaphore_ring_emit, 923 .cs_parse = &r600_dma_cs_parse, 924 .ring_test = &r600_dma_ring_test, 925 .ib_test = &r600_dma_ib_test, 926 .is_lockup = &r600_dma_is_lockup, 927 .get_rptr = &r600_dma_get_rptr, 928 .get_wptr = &r600_dma_get_wptr, 929 .set_wptr = &r600_dma_set_wptr, 930 }; 931 932 static struct radeon_asic r600_asic = { 933 .init = &r600_init, 934 .fini = &r600_fini, 935 .suspend = &r600_suspend, 936 .resume = &r600_resume, 937 .vga_set_state = &r600_vga_set_state, 938 .asic_reset = &r600_asic_reset, 939 .mmio_hdp_flush = r600_mmio_hdp_flush, 940 .gui_idle = &r600_gui_idle, 941 .mc_wait_for_idle = &r600_mc_wait_for_idle, 942 .get_xclk = &r600_get_xclk, 943 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 944 .get_allowed_info_register = r600_get_allowed_info_register, 945 .gart = { 946 .tlb_flush = &r600_pcie_gart_tlb_flush, 947 .get_page_entry = &rs600_gart_get_page_entry, 948 .set_page = &rs600_gart_set_page, 949 }, 950 .ring = { 951 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 952 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 953 }, 954 .irq = { 955 .set = &r600_irq_set, 956 .process = &r600_irq_process, 957 }, 958 .display = { 959 .bandwidth_update = &rv515_bandwidth_update, 960 .get_vblank_counter = &rs600_get_vblank_counter, 961 .wait_for_vblank = &avivo_wait_for_vblank, 962 .set_backlight_level = &atombios_set_backlight_level, 963 .get_backlight_level = &atombios_get_backlight_level, 964 }, 965 .copy = { 966 .blit = &r600_copy_cpdma, 967 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 968 .dma = &r600_copy_dma, 969 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 970 .copy = &r600_copy_cpdma, 971 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 972 }, 973 .surface = { 974 .set_reg = r600_set_surface_reg, 975 .clear_reg = r600_clear_surface_reg, 976 }, 977 .hpd = { 978 .init = &r600_hpd_init, 979 .fini = &r600_hpd_fini, 980 .sense = &r600_hpd_sense, 981 .set_polarity = &r600_hpd_set_polarity, 982 }, 983 .pm = { 984 .misc = &r600_pm_misc, 985 .prepare = &rs600_pm_prepare, 986 .finish = &rs600_pm_finish, 987 .init_profile = &r600_pm_init_profile, 988 .get_dynpm_state = &r600_pm_get_dynpm_state, 989 .get_engine_clock = &radeon_atom_get_engine_clock, 990 .set_engine_clock = &radeon_atom_set_engine_clock, 991 .get_memory_clock = &radeon_atom_get_memory_clock, 992 .set_memory_clock = &radeon_atom_set_memory_clock, 993 .get_pcie_lanes = &r600_get_pcie_lanes, 994 .set_pcie_lanes = &r600_set_pcie_lanes, 995 .set_clock_gating = NULL, 996 .get_temperature = &rv6xx_get_temp, 997 }, 998 .pflip = { 999 .page_flip = &rs600_page_flip, 1000 .page_flip_pending = &rs600_page_flip_pending, 1001 }, 1002 }; 1003 1004 static const struct radeon_asic_ring rv6xx_uvd_ring = { 1005 .ib_execute = &uvd_v1_0_ib_execute, 1006 .emit_fence = &uvd_v1_0_fence_emit, 1007 .emit_semaphore = &uvd_v1_0_semaphore_emit, 1008 .cs_parse = &radeon_uvd_cs_parse, 1009 .ring_test = &uvd_v1_0_ring_test, 1010 .ib_test = &uvd_v1_0_ib_test, 1011 .is_lockup = &radeon_ring_test_lockup, 1012 .get_rptr = &uvd_v1_0_get_rptr, 1013 .get_wptr = &uvd_v1_0_get_wptr, 1014 .set_wptr = &uvd_v1_0_set_wptr, 1015 }; 1016 1017 static struct radeon_asic rv6xx_asic = { 1018 .init = &r600_init, 1019 .fini = &r600_fini, 1020 .suspend = &r600_suspend, 1021 .resume = &r600_resume, 1022 .vga_set_state = &r600_vga_set_state, 1023 .asic_reset = &r600_asic_reset, 1024 .mmio_hdp_flush = r600_mmio_hdp_flush, 1025 .gui_idle = &r600_gui_idle, 1026 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1027 .get_xclk = &r600_get_xclk, 1028 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1029 .get_allowed_info_register = r600_get_allowed_info_register, 1030 .gart = { 1031 .tlb_flush = &r600_pcie_gart_tlb_flush, 1032 .get_page_entry = &rs600_gart_get_page_entry, 1033 .set_page = &rs600_gart_set_page, 1034 }, 1035 .ring = { 1036 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1037 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1038 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring, 1039 }, 1040 .irq = { 1041 .set = &r600_irq_set, 1042 .process = &r600_irq_process, 1043 }, 1044 .display = { 1045 .bandwidth_update = &rv515_bandwidth_update, 1046 .get_vblank_counter = &rs600_get_vblank_counter, 1047 .wait_for_vblank = &avivo_wait_for_vblank, 1048 .set_backlight_level = &atombios_set_backlight_level, 1049 .get_backlight_level = &atombios_get_backlight_level, 1050 }, 1051 .copy = { 1052 .blit = &r600_copy_cpdma, 1053 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1054 .dma = &r600_copy_dma, 1055 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1056 .copy = &r600_copy_cpdma, 1057 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1058 }, 1059 .surface = { 1060 .set_reg = r600_set_surface_reg, 1061 .clear_reg = r600_clear_surface_reg, 1062 }, 1063 .hpd = { 1064 .init = &r600_hpd_init, 1065 .fini = &r600_hpd_fini, 1066 .sense = &r600_hpd_sense, 1067 .set_polarity = &r600_hpd_set_polarity, 1068 }, 1069 .pm = { 1070 .misc = &r600_pm_misc, 1071 .prepare = &rs600_pm_prepare, 1072 .finish = &rs600_pm_finish, 1073 .init_profile = &r600_pm_init_profile, 1074 .get_dynpm_state = &r600_pm_get_dynpm_state, 1075 .get_engine_clock = &radeon_atom_get_engine_clock, 1076 .set_engine_clock = &radeon_atom_set_engine_clock, 1077 .get_memory_clock = &radeon_atom_get_memory_clock, 1078 .set_memory_clock = &radeon_atom_set_memory_clock, 1079 .get_pcie_lanes = &r600_get_pcie_lanes, 1080 .set_pcie_lanes = &r600_set_pcie_lanes, 1081 .set_clock_gating = NULL, 1082 .get_temperature = &rv6xx_get_temp, 1083 .set_uvd_clocks = &r600_set_uvd_clocks, 1084 }, 1085 .dpm = { 1086 .init = &rv6xx_dpm_init, 1087 .setup_asic = &rv6xx_setup_asic, 1088 .enable = &rv6xx_dpm_enable, 1089 .late_enable = &r600_dpm_late_enable, 1090 .disable = &rv6xx_dpm_disable, 1091 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1092 .set_power_state = &rv6xx_dpm_set_power_state, 1093 .post_set_power_state = &r600_dpm_post_set_power_state, 1094 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed, 1095 .fini = &rv6xx_dpm_fini, 1096 .get_sclk = &rv6xx_dpm_get_sclk, 1097 .get_mclk = &rv6xx_dpm_get_mclk, 1098 .print_power_state = &rv6xx_dpm_print_power_state, 1099 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level, 1100 .force_performance_level = &rv6xx_dpm_force_performance_level, 1101 .get_current_sclk = &rv6xx_dpm_get_current_sclk, 1102 .get_current_mclk = &rv6xx_dpm_get_current_mclk, 1103 }, 1104 .pflip = { 1105 .page_flip = &rs600_page_flip, 1106 .page_flip_pending = &rs600_page_flip_pending, 1107 }, 1108 }; 1109 1110 static struct radeon_asic rs780_asic = { 1111 .init = &r600_init, 1112 .fini = &r600_fini, 1113 .suspend = &r600_suspend, 1114 .resume = &r600_resume, 1115 .vga_set_state = &r600_vga_set_state, 1116 .asic_reset = &r600_asic_reset, 1117 .mmio_hdp_flush = r600_mmio_hdp_flush, 1118 .gui_idle = &r600_gui_idle, 1119 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1120 .get_xclk = &r600_get_xclk, 1121 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1122 .get_allowed_info_register = r600_get_allowed_info_register, 1123 .gart = { 1124 .tlb_flush = &r600_pcie_gart_tlb_flush, 1125 .get_page_entry = &rs600_gart_get_page_entry, 1126 .set_page = &rs600_gart_set_page, 1127 }, 1128 .ring = { 1129 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1130 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1131 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring, 1132 }, 1133 .irq = { 1134 .set = &r600_irq_set, 1135 .process = &r600_irq_process, 1136 }, 1137 .display = { 1138 .bandwidth_update = &rs690_bandwidth_update, 1139 .get_vblank_counter = &rs600_get_vblank_counter, 1140 .wait_for_vblank = &avivo_wait_for_vblank, 1141 .set_backlight_level = &atombios_set_backlight_level, 1142 .get_backlight_level = &atombios_get_backlight_level, 1143 }, 1144 .copy = { 1145 .blit = &r600_copy_cpdma, 1146 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1147 .dma = &r600_copy_dma, 1148 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1149 .copy = &r600_copy_cpdma, 1150 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1151 }, 1152 .surface = { 1153 .set_reg = r600_set_surface_reg, 1154 .clear_reg = r600_clear_surface_reg, 1155 }, 1156 .hpd = { 1157 .init = &r600_hpd_init, 1158 .fini = &r600_hpd_fini, 1159 .sense = &r600_hpd_sense, 1160 .set_polarity = &r600_hpd_set_polarity, 1161 }, 1162 .pm = { 1163 .misc = &r600_pm_misc, 1164 .prepare = &rs600_pm_prepare, 1165 .finish = &rs600_pm_finish, 1166 .init_profile = &rs780_pm_init_profile, 1167 .get_dynpm_state = &r600_pm_get_dynpm_state, 1168 .get_engine_clock = &radeon_atom_get_engine_clock, 1169 .set_engine_clock = &radeon_atom_set_engine_clock, 1170 .get_memory_clock = NULL, 1171 .set_memory_clock = NULL, 1172 .get_pcie_lanes = NULL, 1173 .set_pcie_lanes = NULL, 1174 .set_clock_gating = NULL, 1175 .get_temperature = &rv6xx_get_temp, 1176 .set_uvd_clocks = &r600_set_uvd_clocks, 1177 }, 1178 .dpm = { 1179 .init = &rs780_dpm_init, 1180 .setup_asic = &rs780_dpm_setup_asic, 1181 .enable = &rs780_dpm_enable, 1182 .late_enable = &r600_dpm_late_enable, 1183 .disable = &rs780_dpm_disable, 1184 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1185 .set_power_state = &rs780_dpm_set_power_state, 1186 .post_set_power_state = &r600_dpm_post_set_power_state, 1187 .display_configuration_changed = &rs780_dpm_display_configuration_changed, 1188 .fini = &rs780_dpm_fini, 1189 .get_sclk = &rs780_dpm_get_sclk, 1190 .get_mclk = &rs780_dpm_get_mclk, 1191 .print_power_state = &rs780_dpm_print_power_state, 1192 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level, 1193 .force_performance_level = &rs780_dpm_force_performance_level, 1194 .get_current_sclk = &rs780_dpm_get_current_sclk, 1195 .get_current_mclk = &rs780_dpm_get_current_mclk, 1196 }, 1197 .pflip = { 1198 .page_flip = &rs600_page_flip, 1199 .page_flip_pending = &rs600_page_flip_pending, 1200 }, 1201 }; 1202 1203 static const struct radeon_asic_ring rv770_uvd_ring = { 1204 .ib_execute = &uvd_v1_0_ib_execute, 1205 .emit_fence = &uvd_v2_2_fence_emit, 1206 .emit_semaphore = &uvd_v2_2_semaphore_emit, 1207 .cs_parse = &radeon_uvd_cs_parse, 1208 .ring_test = &uvd_v1_0_ring_test, 1209 .ib_test = &uvd_v1_0_ib_test, 1210 .is_lockup = &radeon_ring_test_lockup, 1211 .get_rptr = &uvd_v1_0_get_rptr, 1212 .get_wptr = &uvd_v1_0_get_wptr, 1213 .set_wptr = &uvd_v1_0_set_wptr, 1214 }; 1215 1216 static struct radeon_asic rv770_asic = { 1217 .init = &rv770_init, 1218 .fini = &rv770_fini, 1219 .suspend = &rv770_suspend, 1220 .resume = &rv770_resume, 1221 .asic_reset = &r600_asic_reset, 1222 .vga_set_state = &r600_vga_set_state, 1223 .mmio_hdp_flush = r600_mmio_hdp_flush, 1224 .gui_idle = &r600_gui_idle, 1225 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1226 .get_xclk = &rv770_get_xclk, 1227 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1228 .get_allowed_info_register = r600_get_allowed_info_register, 1229 .gart = { 1230 .tlb_flush = &r600_pcie_gart_tlb_flush, 1231 .get_page_entry = &rs600_gart_get_page_entry, 1232 .set_page = &rs600_gart_set_page, 1233 }, 1234 .ring = { 1235 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1236 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1237 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1238 }, 1239 .irq = { 1240 .set = &r600_irq_set, 1241 .process = &r600_irq_process, 1242 }, 1243 .display = { 1244 .bandwidth_update = &rv515_bandwidth_update, 1245 .get_vblank_counter = &rs600_get_vblank_counter, 1246 .wait_for_vblank = &avivo_wait_for_vblank, 1247 .set_backlight_level = &atombios_set_backlight_level, 1248 .get_backlight_level = &atombios_get_backlight_level, 1249 }, 1250 .copy = { 1251 .blit = &r600_copy_cpdma, 1252 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1253 .dma = &rv770_copy_dma, 1254 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1255 .copy = &rv770_copy_dma, 1256 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1257 }, 1258 .surface = { 1259 .set_reg = r600_set_surface_reg, 1260 .clear_reg = r600_clear_surface_reg, 1261 }, 1262 .hpd = { 1263 .init = &r600_hpd_init, 1264 .fini = &r600_hpd_fini, 1265 .sense = &r600_hpd_sense, 1266 .set_polarity = &r600_hpd_set_polarity, 1267 }, 1268 .pm = { 1269 .misc = &rv770_pm_misc, 1270 .prepare = &rs600_pm_prepare, 1271 .finish = &rs600_pm_finish, 1272 .init_profile = &r600_pm_init_profile, 1273 .get_dynpm_state = &r600_pm_get_dynpm_state, 1274 .get_engine_clock = &radeon_atom_get_engine_clock, 1275 .set_engine_clock = &radeon_atom_set_engine_clock, 1276 .get_memory_clock = &radeon_atom_get_memory_clock, 1277 .set_memory_clock = &radeon_atom_set_memory_clock, 1278 .get_pcie_lanes = &r600_get_pcie_lanes, 1279 .set_pcie_lanes = &r600_set_pcie_lanes, 1280 .set_clock_gating = &radeon_atom_set_clock_gating, 1281 .set_uvd_clocks = &rv770_set_uvd_clocks, 1282 .get_temperature = &rv770_get_temp, 1283 }, 1284 .dpm = { 1285 .init = &rv770_dpm_init, 1286 .setup_asic = &rv770_dpm_setup_asic, 1287 .enable = &rv770_dpm_enable, 1288 .late_enable = &rv770_dpm_late_enable, 1289 .disable = &rv770_dpm_disable, 1290 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1291 .set_power_state = &rv770_dpm_set_power_state, 1292 .post_set_power_state = &r600_dpm_post_set_power_state, 1293 .display_configuration_changed = &rv770_dpm_display_configuration_changed, 1294 .fini = &rv770_dpm_fini, 1295 .get_sclk = &rv770_dpm_get_sclk, 1296 .get_mclk = &rv770_dpm_get_mclk, 1297 .print_power_state = &rv770_dpm_print_power_state, 1298 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1299 .force_performance_level = &rv770_dpm_force_performance_level, 1300 .vblank_too_short = &rv770_dpm_vblank_too_short, 1301 .get_current_sclk = &rv770_dpm_get_current_sclk, 1302 .get_current_mclk = &rv770_dpm_get_current_mclk, 1303 }, 1304 .pflip = { 1305 .page_flip = &rv770_page_flip, 1306 .page_flip_pending = &rv770_page_flip_pending, 1307 }, 1308 }; 1309 1310 static const struct radeon_asic_ring evergreen_gfx_ring = { 1311 .ib_execute = &evergreen_ring_ib_execute, 1312 .emit_fence = &r600_fence_ring_emit, 1313 .emit_semaphore = &r600_semaphore_ring_emit, 1314 .cs_parse = &evergreen_cs_parse, 1315 .ring_test = &r600_ring_test, 1316 .ib_test = &r600_ib_test, 1317 .is_lockup = &evergreen_gfx_is_lockup, 1318 .get_rptr = &r600_gfx_get_rptr, 1319 .get_wptr = &r600_gfx_get_wptr, 1320 .set_wptr = &r600_gfx_set_wptr, 1321 }; 1322 1323 static const struct radeon_asic_ring evergreen_dma_ring = { 1324 .ib_execute = &evergreen_dma_ring_ib_execute, 1325 .emit_fence = &evergreen_dma_fence_ring_emit, 1326 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1327 .cs_parse = &evergreen_dma_cs_parse, 1328 .ring_test = &r600_dma_ring_test, 1329 .ib_test = &r600_dma_ib_test, 1330 .is_lockup = &evergreen_dma_is_lockup, 1331 .get_rptr = &r600_dma_get_rptr, 1332 .get_wptr = &r600_dma_get_wptr, 1333 .set_wptr = &r600_dma_set_wptr, 1334 }; 1335 1336 static struct radeon_asic evergreen_asic = { 1337 .init = &evergreen_init, 1338 .fini = &evergreen_fini, 1339 .suspend = &evergreen_suspend, 1340 .resume = &evergreen_resume, 1341 .asic_reset = &evergreen_asic_reset, 1342 .vga_set_state = &r600_vga_set_state, 1343 .mmio_hdp_flush = r600_mmio_hdp_flush, 1344 .gui_idle = &r600_gui_idle, 1345 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1346 .get_xclk = &rv770_get_xclk, 1347 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1348 .get_allowed_info_register = evergreen_get_allowed_info_register, 1349 .gart = { 1350 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1351 .get_page_entry = &rs600_gart_get_page_entry, 1352 .set_page = &rs600_gart_set_page, 1353 }, 1354 .ring = { 1355 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1356 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1357 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1358 }, 1359 .irq = { 1360 .set = &evergreen_irq_set, 1361 .process = &evergreen_irq_process, 1362 }, 1363 .display = { 1364 .bandwidth_update = &evergreen_bandwidth_update, 1365 .get_vblank_counter = &evergreen_get_vblank_counter, 1366 .wait_for_vblank = &dce4_wait_for_vblank, 1367 .set_backlight_level = &atombios_set_backlight_level, 1368 .get_backlight_level = &atombios_get_backlight_level, 1369 }, 1370 .copy = { 1371 .blit = &r600_copy_cpdma, 1372 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1373 .dma = &evergreen_copy_dma, 1374 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1375 .copy = &evergreen_copy_dma, 1376 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1377 }, 1378 .surface = { 1379 .set_reg = r600_set_surface_reg, 1380 .clear_reg = r600_clear_surface_reg, 1381 }, 1382 .hpd = { 1383 .init = &evergreen_hpd_init, 1384 .fini = &evergreen_hpd_fini, 1385 .sense = &evergreen_hpd_sense, 1386 .set_polarity = &evergreen_hpd_set_polarity, 1387 }, 1388 .pm = { 1389 .misc = &evergreen_pm_misc, 1390 .prepare = &evergreen_pm_prepare, 1391 .finish = &evergreen_pm_finish, 1392 .init_profile = &r600_pm_init_profile, 1393 .get_dynpm_state = &r600_pm_get_dynpm_state, 1394 .get_engine_clock = &radeon_atom_get_engine_clock, 1395 .set_engine_clock = &radeon_atom_set_engine_clock, 1396 .get_memory_clock = &radeon_atom_get_memory_clock, 1397 .set_memory_clock = &radeon_atom_set_memory_clock, 1398 .get_pcie_lanes = &r600_get_pcie_lanes, 1399 .set_pcie_lanes = &r600_set_pcie_lanes, 1400 .set_clock_gating = NULL, 1401 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1402 .get_temperature = &evergreen_get_temp, 1403 }, 1404 .dpm = { 1405 .init = &cypress_dpm_init, 1406 .setup_asic = &cypress_dpm_setup_asic, 1407 .enable = &cypress_dpm_enable, 1408 .late_enable = &rv770_dpm_late_enable, 1409 .disable = &cypress_dpm_disable, 1410 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1411 .set_power_state = &cypress_dpm_set_power_state, 1412 .post_set_power_state = &r600_dpm_post_set_power_state, 1413 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1414 .fini = &cypress_dpm_fini, 1415 .get_sclk = &rv770_dpm_get_sclk, 1416 .get_mclk = &rv770_dpm_get_mclk, 1417 .print_power_state = &rv770_dpm_print_power_state, 1418 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1419 .force_performance_level = &rv770_dpm_force_performance_level, 1420 .vblank_too_short = &cypress_dpm_vblank_too_short, 1421 .get_current_sclk = &rv770_dpm_get_current_sclk, 1422 .get_current_mclk = &rv770_dpm_get_current_mclk, 1423 }, 1424 .pflip = { 1425 .page_flip = &evergreen_page_flip, 1426 .page_flip_pending = &evergreen_page_flip_pending, 1427 }, 1428 }; 1429 1430 static struct radeon_asic sumo_asic = { 1431 .init = &evergreen_init, 1432 .fini = &evergreen_fini, 1433 .suspend = &evergreen_suspend, 1434 .resume = &evergreen_resume, 1435 .asic_reset = &evergreen_asic_reset, 1436 .vga_set_state = &r600_vga_set_state, 1437 .mmio_hdp_flush = r600_mmio_hdp_flush, 1438 .gui_idle = &r600_gui_idle, 1439 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1440 .get_xclk = &r600_get_xclk, 1441 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1442 .get_allowed_info_register = evergreen_get_allowed_info_register, 1443 .gart = { 1444 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1445 .get_page_entry = &rs600_gart_get_page_entry, 1446 .set_page = &rs600_gart_set_page, 1447 }, 1448 .ring = { 1449 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1450 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1451 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1452 }, 1453 .irq = { 1454 .set = &evergreen_irq_set, 1455 .process = &evergreen_irq_process, 1456 }, 1457 .display = { 1458 .bandwidth_update = &evergreen_bandwidth_update, 1459 .get_vblank_counter = &evergreen_get_vblank_counter, 1460 .wait_for_vblank = &dce4_wait_for_vblank, 1461 .set_backlight_level = &atombios_set_backlight_level, 1462 .get_backlight_level = &atombios_get_backlight_level, 1463 }, 1464 .copy = { 1465 .blit = &r600_copy_cpdma, 1466 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1467 .dma = &evergreen_copy_dma, 1468 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1469 .copy = &evergreen_copy_dma, 1470 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1471 }, 1472 .surface = { 1473 .set_reg = r600_set_surface_reg, 1474 .clear_reg = r600_clear_surface_reg, 1475 }, 1476 .hpd = { 1477 .init = &evergreen_hpd_init, 1478 .fini = &evergreen_hpd_fini, 1479 .sense = &evergreen_hpd_sense, 1480 .set_polarity = &evergreen_hpd_set_polarity, 1481 }, 1482 .pm = { 1483 .misc = &evergreen_pm_misc, 1484 .prepare = &evergreen_pm_prepare, 1485 .finish = &evergreen_pm_finish, 1486 .init_profile = &sumo_pm_init_profile, 1487 .get_dynpm_state = &r600_pm_get_dynpm_state, 1488 .get_engine_clock = &radeon_atom_get_engine_clock, 1489 .set_engine_clock = &radeon_atom_set_engine_clock, 1490 .get_memory_clock = NULL, 1491 .set_memory_clock = NULL, 1492 .get_pcie_lanes = NULL, 1493 .set_pcie_lanes = NULL, 1494 .set_clock_gating = NULL, 1495 .set_uvd_clocks = &sumo_set_uvd_clocks, 1496 .get_temperature = &sumo_get_temp, 1497 }, 1498 .dpm = { 1499 .init = &sumo_dpm_init, 1500 .setup_asic = &sumo_dpm_setup_asic, 1501 .enable = &sumo_dpm_enable, 1502 .late_enable = &sumo_dpm_late_enable, 1503 .disable = &sumo_dpm_disable, 1504 .pre_set_power_state = &sumo_dpm_pre_set_power_state, 1505 .set_power_state = &sumo_dpm_set_power_state, 1506 .post_set_power_state = &sumo_dpm_post_set_power_state, 1507 .display_configuration_changed = &sumo_dpm_display_configuration_changed, 1508 .fini = &sumo_dpm_fini, 1509 .get_sclk = &sumo_dpm_get_sclk, 1510 .get_mclk = &sumo_dpm_get_mclk, 1511 .print_power_state = &sumo_dpm_print_power_state, 1512 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level, 1513 .force_performance_level = &sumo_dpm_force_performance_level, 1514 .get_current_sclk = &sumo_dpm_get_current_sclk, 1515 .get_current_mclk = &sumo_dpm_get_current_mclk, 1516 }, 1517 .pflip = { 1518 .page_flip = &evergreen_page_flip, 1519 .page_flip_pending = &evergreen_page_flip_pending, 1520 }, 1521 }; 1522 1523 static struct radeon_asic btc_asic = { 1524 .init = &evergreen_init, 1525 .fini = &evergreen_fini, 1526 .suspend = &evergreen_suspend, 1527 .resume = &evergreen_resume, 1528 .asic_reset = &evergreen_asic_reset, 1529 .vga_set_state = &r600_vga_set_state, 1530 .mmio_hdp_flush = r600_mmio_hdp_flush, 1531 .gui_idle = &r600_gui_idle, 1532 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1533 .get_xclk = &rv770_get_xclk, 1534 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1535 .get_allowed_info_register = evergreen_get_allowed_info_register, 1536 .gart = { 1537 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1538 .get_page_entry = &rs600_gart_get_page_entry, 1539 .set_page = &rs600_gart_set_page, 1540 }, 1541 .ring = { 1542 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1543 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1544 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1545 }, 1546 .irq = { 1547 .set = &evergreen_irq_set, 1548 .process = &evergreen_irq_process, 1549 }, 1550 .display = { 1551 .bandwidth_update = &evergreen_bandwidth_update, 1552 .get_vblank_counter = &evergreen_get_vblank_counter, 1553 .wait_for_vblank = &dce4_wait_for_vblank, 1554 .set_backlight_level = &atombios_set_backlight_level, 1555 .get_backlight_level = &atombios_get_backlight_level, 1556 }, 1557 .copy = { 1558 .blit = &r600_copy_cpdma, 1559 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1560 .dma = &evergreen_copy_dma, 1561 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1562 .copy = &evergreen_copy_dma, 1563 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1564 }, 1565 .surface = { 1566 .set_reg = r600_set_surface_reg, 1567 .clear_reg = r600_clear_surface_reg, 1568 }, 1569 .hpd = { 1570 .init = &evergreen_hpd_init, 1571 .fini = &evergreen_hpd_fini, 1572 .sense = &evergreen_hpd_sense, 1573 .set_polarity = &evergreen_hpd_set_polarity, 1574 }, 1575 .pm = { 1576 .misc = &evergreen_pm_misc, 1577 .prepare = &evergreen_pm_prepare, 1578 .finish = &evergreen_pm_finish, 1579 .init_profile = &btc_pm_init_profile, 1580 .get_dynpm_state = &r600_pm_get_dynpm_state, 1581 .get_engine_clock = &radeon_atom_get_engine_clock, 1582 .set_engine_clock = &radeon_atom_set_engine_clock, 1583 .get_memory_clock = &radeon_atom_get_memory_clock, 1584 .set_memory_clock = &radeon_atom_set_memory_clock, 1585 .get_pcie_lanes = &r600_get_pcie_lanes, 1586 .set_pcie_lanes = &r600_set_pcie_lanes, 1587 .set_clock_gating = NULL, 1588 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1589 .get_temperature = &evergreen_get_temp, 1590 }, 1591 .dpm = { 1592 .init = &btc_dpm_init, 1593 .setup_asic = &btc_dpm_setup_asic, 1594 .enable = &btc_dpm_enable, 1595 .late_enable = &rv770_dpm_late_enable, 1596 .disable = &btc_dpm_disable, 1597 .pre_set_power_state = &btc_dpm_pre_set_power_state, 1598 .set_power_state = &btc_dpm_set_power_state, 1599 .post_set_power_state = &btc_dpm_post_set_power_state, 1600 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1601 .fini = &btc_dpm_fini, 1602 .get_sclk = &btc_dpm_get_sclk, 1603 .get_mclk = &btc_dpm_get_mclk, 1604 .print_power_state = &rv770_dpm_print_power_state, 1605 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level, 1606 .force_performance_level = &rv770_dpm_force_performance_level, 1607 .vblank_too_short = &btc_dpm_vblank_too_short, 1608 .get_current_sclk = &btc_dpm_get_current_sclk, 1609 .get_current_mclk = &btc_dpm_get_current_mclk, 1610 }, 1611 .pflip = { 1612 .page_flip = &evergreen_page_flip, 1613 .page_flip_pending = &evergreen_page_flip_pending, 1614 }, 1615 }; 1616 1617 static const struct radeon_asic_ring cayman_gfx_ring = { 1618 .ib_execute = &cayman_ring_ib_execute, 1619 .ib_parse = &evergreen_ib_parse, 1620 .emit_fence = &cayman_fence_ring_emit, 1621 .emit_semaphore = &r600_semaphore_ring_emit, 1622 .cs_parse = &evergreen_cs_parse, 1623 .ring_test = &r600_ring_test, 1624 .ib_test = &r600_ib_test, 1625 .is_lockup = &cayman_gfx_is_lockup, 1626 .vm_flush = &cayman_vm_flush, 1627 .get_rptr = &cayman_gfx_get_rptr, 1628 .get_wptr = &cayman_gfx_get_wptr, 1629 .set_wptr = &cayman_gfx_set_wptr, 1630 }; 1631 1632 static const struct radeon_asic_ring cayman_dma_ring = { 1633 .ib_execute = &cayman_dma_ring_ib_execute, 1634 .ib_parse = &evergreen_dma_ib_parse, 1635 .emit_fence = &evergreen_dma_fence_ring_emit, 1636 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1637 .cs_parse = &evergreen_dma_cs_parse, 1638 .ring_test = &r600_dma_ring_test, 1639 .ib_test = &r600_dma_ib_test, 1640 .is_lockup = &cayman_dma_is_lockup, 1641 .vm_flush = &cayman_dma_vm_flush, 1642 .get_rptr = &cayman_dma_get_rptr, 1643 .get_wptr = &cayman_dma_get_wptr, 1644 .set_wptr = &cayman_dma_set_wptr 1645 }; 1646 1647 static const struct radeon_asic_ring cayman_uvd_ring = { 1648 .ib_execute = &uvd_v1_0_ib_execute, 1649 .emit_fence = &uvd_v2_2_fence_emit, 1650 .emit_semaphore = &uvd_v3_1_semaphore_emit, 1651 .cs_parse = &radeon_uvd_cs_parse, 1652 .ring_test = &uvd_v1_0_ring_test, 1653 .ib_test = &uvd_v1_0_ib_test, 1654 .is_lockup = &radeon_ring_test_lockup, 1655 .get_rptr = &uvd_v1_0_get_rptr, 1656 .get_wptr = &uvd_v1_0_get_wptr, 1657 .set_wptr = &uvd_v1_0_set_wptr, 1658 }; 1659 1660 static struct radeon_asic cayman_asic = { 1661 .init = &cayman_init, 1662 .fini = &cayman_fini, 1663 .suspend = &cayman_suspend, 1664 .resume = &cayman_resume, 1665 .asic_reset = &cayman_asic_reset, 1666 .vga_set_state = &r600_vga_set_state, 1667 .mmio_hdp_flush = r600_mmio_hdp_flush, 1668 .gui_idle = &r600_gui_idle, 1669 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1670 .get_xclk = &rv770_get_xclk, 1671 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1672 .get_allowed_info_register = cayman_get_allowed_info_register, 1673 .gart = { 1674 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1675 .get_page_entry = &rs600_gart_get_page_entry, 1676 .set_page = &rs600_gart_set_page, 1677 }, 1678 .vm = { 1679 .init = &cayman_vm_init, 1680 .fini = &cayman_vm_fini, 1681 .copy_pages = &cayman_dma_vm_copy_pages, 1682 .write_pages = &cayman_dma_vm_write_pages, 1683 .set_pages = &cayman_dma_vm_set_pages, 1684 .pad_ib = &cayman_dma_vm_pad_ib, 1685 }, 1686 .ring = { 1687 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, 1688 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, 1689 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, 1690 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, 1691 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, 1692 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1693 }, 1694 .irq = { 1695 .set = &evergreen_irq_set, 1696 .process = &evergreen_irq_process, 1697 }, 1698 .display = { 1699 .bandwidth_update = &evergreen_bandwidth_update, 1700 .get_vblank_counter = &evergreen_get_vblank_counter, 1701 .wait_for_vblank = &dce4_wait_for_vblank, 1702 .set_backlight_level = &atombios_set_backlight_level, 1703 .get_backlight_level = &atombios_get_backlight_level, 1704 }, 1705 .copy = { 1706 .blit = &r600_copy_cpdma, 1707 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1708 .dma = &evergreen_copy_dma, 1709 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1710 .copy = &evergreen_copy_dma, 1711 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1712 }, 1713 .surface = { 1714 .set_reg = r600_set_surface_reg, 1715 .clear_reg = r600_clear_surface_reg, 1716 }, 1717 .hpd = { 1718 .init = &evergreen_hpd_init, 1719 .fini = &evergreen_hpd_fini, 1720 .sense = &evergreen_hpd_sense, 1721 .set_polarity = &evergreen_hpd_set_polarity, 1722 }, 1723 .pm = { 1724 .misc = &evergreen_pm_misc, 1725 .prepare = &evergreen_pm_prepare, 1726 .finish = &evergreen_pm_finish, 1727 .init_profile = &btc_pm_init_profile, 1728 .get_dynpm_state = &r600_pm_get_dynpm_state, 1729 .get_engine_clock = &radeon_atom_get_engine_clock, 1730 .set_engine_clock = &radeon_atom_set_engine_clock, 1731 .get_memory_clock = &radeon_atom_get_memory_clock, 1732 .set_memory_clock = &radeon_atom_set_memory_clock, 1733 .get_pcie_lanes = &r600_get_pcie_lanes, 1734 .set_pcie_lanes = &r600_set_pcie_lanes, 1735 .set_clock_gating = NULL, 1736 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1737 .get_temperature = &evergreen_get_temp, 1738 }, 1739 .dpm = { 1740 .init = &ni_dpm_init, 1741 .setup_asic = &ni_dpm_setup_asic, 1742 .enable = &ni_dpm_enable, 1743 .late_enable = &rv770_dpm_late_enable, 1744 .disable = &ni_dpm_disable, 1745 .pre_set_power_state = &ni_dpm_pre_set_power_state, 1746 .set_power_state = &ni_dpm_set_power_state, 1747 .post_set_power_state = &ni_dpm_post_set_power_state, 1748 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1749 .fini = &ni_dpm_fini, 1750 .get_sclk = &ni_dpm_get_sclk, 1751 .get_mclk = &ni_dpm_get_mclk, 1752 .print_power_state = &ni_dpm_print_power_state, 1753 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level, 1754 .force_performance_level = &ni_dpm_force_performance_level, 1755 .vblank_too_short = &ni_dpm_vblank_too_short, 1756 .get_current_sclk = &ni_dpm_get_current_sclk, 1757 .get_current_mclk = &ni_dpm_get_current_mclk, 1758 }, 1759 .pflip = { 1760 .page_flip = &evergreen_page_flip, 1761 .page_flip_pending = &evergreen_page_flip_pending, 1762 }, 1763 }; 1764 1765 static const struct radeon_asic_ring trinity_vce_ring = { 1766 .ib_execute = &radeon_vce_ib_execute, 1767 .emit_fence = &radeon_vce_fence_emit, 1768 .emit_semaphore = &radeon_vce_semaphore_emit, 1769 .cs_parse = &radeon_vce_cs_parse, 1770 .ring_test = &radeon_vce_ring_test, 1771 .ib_test = &radeon_vce_ib_test, 1772 .is_lockup = &radeon_ring_test_lockup, 1773 .get_rptr = &vce_v1_0_get_rptr, 1774 .get_wptr = &vce_v1_0_get_wptr, 1775 .set_wptr = &vce_v1_0_set_wptr, 1776 }; 1777 1778 static struct radeon_asic trinity_asic = { 1779 .init = &cayman_init, 1780 .fini = &cayman_fini, 1781 .suspend = &cayman_suspend, 1782 .resume = &cayman_resume, 1783 .asic_reset = &cayman_asic_reset, 1784 .vga_set_state = &r600_vga_set_state, 1785 .mmio_hdp_flush = r600_mmio_hdp_flush, 1786 .gui_idle = &r600_gui_idle, 1787 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1788 .get_xclk = &r600_get_xclk, 1789 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1790 .get_allowed_info_register = cayman_get_allowed_info_register, 1791 .gart = { 1792 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1793 .get_page_entry = &rs600_gart_get_page_entry, 1794 .set_page = &rs600_gart_set_page, 1795 }, 1796 .vm = { 1797 .init = &cayman_vm_init, 1798 .fini = &cayman_vm_fini, 1799 .copy_pages = &cayman_dma_vm_copy_pages, 1800 .write_pages = &cayman_dma_vm_write_pages, 1801 .set_pages = &cayman_dma_vm_set_pages, 1802 .pad_ib = &cayman_dma_vm_pad_ib, 1803 }, 1804 .ring = { 1805 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, 1806 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, 1807 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, 1808 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, 1809 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, 1810 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1811 [TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring, 1812 [TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring, 1813 }, 1814 .irq = { 1815 .set = &evergreen_irq_set, 1816 .process = &evergreen_irq_process, 1817 }, 1818 .display = { 1819 .bandwidth_update = &dce6_bandwidth_update, 1820 .get_vblank_counter = &evergreen_get_vblank_counter, 1821 .wait_for_vblank = &dce4_wait_for_vblank, 1822 .set_backlight_level = &atombios_set_backlight_level, 1823 .get_backlight_level = &atombios_get_backlight_level, 1824 }, 1825 .copy = { 1826 .blit = &r600_copy_cpdma, 1827 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1828 .dma = &evergreen_copy_dma, 1829 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1830 .copy = &evergreen_copy_dma, 1831 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1832 }, 1833 .surface = { 1834 .set_reg = r600_set_surface_reg, 1835 .clear_reg = r600_clear_surface_reg, 1836 }, 1837 .hpd = { 1838 .init = &evergreen_hpd_init, 1839 .fini = &evergreen_hpd_fini, 1840 .sense = &evergreen_hpd_sense, 1841 .set_polarity = &evergreen_hpd_set_polarity, 1842 }, 1843 .pm = { 1844 .misc = &evergreen_pm_misc, 1845 .prepare = &evergreen_pm_prepare, 1846 .finish = &evergreen_pm_finish, 1847 .init_profile = &sumo_pm_init_profile, 1848 .get_dynpm_state = &r600_pm_get_dynpm_state, 1849 .get_engine_clock = &radeon_atom_get_engine_clock, 1850 .set_engine_clock = &radeon_atom_set_engine_clock, 1851 .get_memory_clock = NULL, 1852 .set_memory_clock = NULL, 1853 .get_pcie_lanes = NULL, 1854 .set_pcie_lanes = NULL, 1855 .set_clock_gating = NULL, 1856 .set_uvd_clocks = &sumo_set_uvd_clocks, 1857 .set_vce_clocks = &tn_set_vce_clocks, 1858 .get_temperature = &tn_get_temp, 1859 }, 1860 .dpm = { 1861 .init = &trinity_dpm_init, 1862 .setup_asic = &trinity_dpm_setup_asic, 1863 .enable = &trinity_dpm_enable, 1864 .late_enable = &trinity_dpm_late_enable, 1865 .disable = &trinity_dpm_disable, 1866 .pre_set_power_state = &trinity_dpm_pre_set_power_state, 1867 .set_power_state = &trinity_dpm_set_power_state, 1868 .post_set_power_state = &trinity_dpm_post_set_power_state, 1869 .display_configuration_changed = &trinity_dpm_display_configuration_changed, 1870 .fini = &trinity_dpm_fini, 1871 .get_sclk = &trinity_dpm_get_sclk, 1872 .get_mclk = &trinity_dpm_get_mclk, 1873 .print_power_state = &trinity_dpm_print_power_state, 1874 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level, 1875 .force_performance_level = &trinity_dpm_force_performance_level, 1876 .enable_bapm = &trinity_dpm_enable_bapm, 1877 .get_current_sclk = &trinity_dpm_get_current_sclk, 1878 .get_current_mclk = &trinity_dpm_get_current_mclk, 1879 }, 1880 .pflip = { 1881 .page_flip = &evergreen_page_flip, 1882 .page_flip_pending = &evergreen_page_flip_pending, 1883 }, 1884 }; 1885 1886 static const struct radeon_asic_ring si_gfx_ring = { 1887 .ib_execute = &si_ring_ib_execute, 1888 .ib_parse = &si_ib_parse, 1889 .emit_fence = &si_fence_ring_emit, 1890 .emit_semaphore = &r600_semaphore_ring_emit, 1891 .cs_parse = NULL, 1892 .ring_test = &r600_ring_test, 1893 .ib_test = &r600_ib_test, 1894 .is_lockup = &si_gfx_is_lockup, 1895 .vm_flush = &si_vm_flush, 1896 .get_rptr = &cayman_gfx_get_rptr, 1897 .get_wptr = &cayman_gfx_get_wptr, 1898 .set_wptr = &cayman_gfx_set_wptr, 1899 }; 1900 1901 static const struct radeon_asic_ring si_dma_ring = { 1902 .ib_execute = &cayman_dma_ring_ib_execute, 1903 .ib_parse = &evergreen_dma_ib_parse, 1904 .emit_fence = &evergreen_dma_fence_ring_emit, 1905 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1906 .cs_parse = NULL, 1907 .ring_test = &r600_dma_ring_test, 1908 .ib_test = &r600_dma_ib_test, 1909 .is_lockup = &si_dma_is_lockup, 1910 .vm_flush = &si_dma_vm_flush, 1911 .get_rptr = &cayman_dma_get_rptr, 1912 .get_wptr = &cayman_dma_get_wptr, 1913 .set_wptr = &cayman_dma_set_wptr, 1914 }; 1915 1916 static struct radeon_asic si_asic = { 1917 .init = &si_init, 1918 .fini = &si_fini, 1919 .suspend = &si_suspend, 1920 .resume = &si_resume, 1921 .asic_reset = &si_asic_reset, 1922 .vga_set_state = &r600_vga_set_state, 1923 .mmio_hdp_flush = r600_mmio_hdp_flush, 1924 .gui_idle = &r600_gui_idle, 1925 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1926 .get_xclk = &si_get_xclk, 1927 .get_gpu_clock_counter = &si_get_gpu_clock_counter, 1928 .get_allowed_info_register = si_get_allowed_info_register, 1929 .gart = { 1930 .tlb_flush = &si_pcie_gart_tlb_flush, 1931 .get_page_entry = &rs600_gart_get_page_entry, 1932 .set_page = &rs600_gart_set_page, 1933 }, 1934 .vm = { 1935 .init = &si_vm_init, 1936 .fini = &si_vm_fini, 1937 .copy_pages = &si_dma_vm_copy_pages, 1938 .write_pages = &si_dma_vm_write_pages, 1939 .set_pages = &si_dma_vm_set_pages, 1940 .pad_ib = &cayman_dma_vm_pad_ib, 1941 }, 1942 .ring = { 1943 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring, 1944 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring, 1945 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring, 1946 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring, 1947 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring, 1948 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1949 [TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring, 1950 [TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring, 1951 }, 1952 .irq = { 1953 .set = &si_irq_set, 1954 .process = &si_irq_process, 1955 }, 1956 .display = { 1957 .bandwidth_update = &dce6_bandwidth_update, 1958 .get_vblank_counter = &evergreen_get_vblank_counter, 1959 .wait_for_vblank = &dce4_wait_for_vblank, 1960 .set_backlight_level = &atombios_set_backlight_level, 1961 .get_backlight_level = &atombios_get_backlight_level, 1962 }, 1963 .copy = { 1964 .blit = &r600_copy_cpdma, 1965 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1966 .dma = &si_copy_dma, 1967 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1968 .copy = &si_copy_dma, 1969 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1970 }, 1971 .surface = { 1972 .set_reg = r600_set_surface_reg, 1973 .clear_reg = r600_clear_surface_reg, 1974 }, 1975 .hpd = { 1976 .init = &evergreen_hpd_init, 1977 .fini = &evergreen_hpd_fini, 1978 .sense = &evergreen_hpd_sense, 1979 .set_polarity = &evergreen_hpd_set_polarity, 1980 }, 1981 .pm = { 1982 .misc = &evergreen_pm_misc, 1983 .prepare = &evergreen_pm_prepare, 1984 .finish = &evergreen_pm_finish, 1985 .init_profile = &sumo_pm_init_profile, 1986 .get_dynpm_state = &r600_pm_get_dynpm_state, 1987 .get_engine_clock = &radeon_atom_get_engine_clock, 1988 .set_engine_clock = &radeon_atom_set_engine_clock, 1989 .get_memory_clock = &radeon_atom_get_memory_clock, 1990 .set_memory_clock = &radeon_atom_set_memory_clock, 1991 .get_pcie_lanes = &r600_get_pcie_lanes, 1992 .set_pcie_lanes = &r600_set_pcie_lanes, 1993 .set_clock_gating = NULL, 1994 .set_uvd_clocks = &si_set_uvd_clocks, 1995 .set_vce_clocks = &si_set_vce_clocks, 1996 .get_temperature = &si_get_temp, 1997 }, 1998 .dpm = { 1999 .init = &si_dpm_init, 2000 .setup_asic = &si_dpm_setup_asic, 2001 .enable = &si_dpm_enable, 2002 .late_enable = &si_dpm_late_enable, 2003 .disable = &si_dpm_disable, 2004 .pre_set_power_state = &si_dpm_pre_set_power_state, 2005 .set_power_state = &si_dpm_set_power_state, 2006 .post_set_power_state = &si_dpm_post_set_power_state, 2007 .display_configuration_changed = &si_dpm_display_configuration_changed, 2008 .fini = &si_dpm_fini, 2009 .get_sclk = &ni_dpm_get_sclk, 2010 .get_mclk = &ni_dpm_get_mclk, 2011 .print_power_state = &ni_dpm_print_power_state, 2012 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, 2013 .force_performance_level = &si_dpm_force_performance_level, 2014 .vblank_too_short = &ni_dpm_vblank_too_short, 2015 .fan_ctrl_set_mode = &si_fan_ctrl_set_mode, 2016 .fan_ctrl_get_mode = &si_fan_ctrl_get_mode, 2017 .get_fan_speed_percent = &si_fan_ctrl_get_fan_speed_percent, 2018 .set_fan_speed_percent = &si_fan_ctrl_set_fan_speed_percent, 2019 .get_current_sclk = &si_dpm_get_current_sclk, 2020 .get_current_mclk = &si_dpm_get_current_mclk, 2021 }, 2022 .pflip = { 2023 .page_flip = &evergreen_page_flip, 2024 .page_flip_pending = &evergreen_page_flip_pending, 2025 }, 2026 }; 2027 2028 static const struct radeon_asic_ring ci_gfx_ring = { 2029 .ib_execute = &cik_ring_ib_execute, 2030 .ib_parse = &cik_ib_parse, 2031 .emit_fence = &cik_fence_gfx_ring_emit, 2032 .emit_semaphore = &cik_semaphore_ring_emit, 2033 .cs_parse = NULL, 2034 .ring_test = &cik_ring_test, 2035 .ib_test = &cik_ib_test, 2036 .is_lockup = &cik_gfx_is_lockup, 2037 .vm_flush = &cik_vm_flush, 2038 .get_rptr = &cik_gfx_get_rptr, 2039 .get_wptr = &cik_gfx_get_wptr, 2040 .set_wptr = &cik_gfx_set_wptr, 2041 }; 2042 2043 static const struct radeon_asic_ring ci_cp_ring = { 2044 .ib_execute = &cik_ring_ib_execute, 2045 .ib_parse = &cik_ib_parse, 2046 .emit_fence = &cik_fence_compute_ring_emit, 2047 .emit_semaphore = &cik_semaphore_ring_emit, 2048 .cs_parse = NULL, 2049 .ring_test = &cik_ring_test, 2050 .ib_test = &cik_ib_test, 2051 .is_lockup = &cik_gfx_is_lockup, 2052 .vm_flush = &cik_vm_flush, 2053 .get_rptr = &cik_compute_get_rptr, 2054 .get_wptr = &cik_compute_get_wptr, 2055 .set_wptr = &cik_compute_set_wptr, 2056 }; 2057 2058 static const struct radeon_asic_ring ci_dma_ring = { 2059 .ib_execute = &cik_sdma_ring_ib_execute, 2060 .ib_parse = &cik_ib_parse, 2061 .emit_fence = &cik_sdma_fence_ring_emit, 2062 .emit_semaphore = &cik_sdma_semaphore_ring_emit, 2063 .cs_parse = NULL, 2064 .ring_test = &cik_sdma_ring_test, 2065 .ib_test = &cik_sdma_ib_test, 2066 .is_lockup = &cik_sdma_is_lockup, 2067 .vm_flush = &cik_dma_vm_flush, 2068 .get_rptr = &cik_sdma_get_rptr, 2069 .get_wptr = &cik_sdma_get_wptr, 2070 .set_wptr = &cik_sdma_set_wptr, 2071 }; 2072 2073 static const struct radeon_asic_ring ci_vce_ring = { 2074 .ib_execute = &radeon_vce_ib_execute, 2075 .emit_fence = &radeon_vce_fence_emit, 2076 .emit_semaphore = &radeon_vce_semaphore_emit, 2077 .cs_parse = &radeon_vce_cs_parse, 2078 .ring_test = &radeon_vce_ring_test, 2079 .ib_test = &radeon_vce_ib_test, 2080 .is_lockup = &radeon_ring_test_lockup, 2081 .get_rptr = &vce_v1_0_get_rptr, 2082 .get_wptr = &vce_v1_0_get_wptr, 2083 .set_wptr = &vce_v1_0_set_wptr, 2084 }; 2085 2086 static struct radeon_asic ci_asic = { 2087 .init = &cik_init, 2088 .fini = &cik_fini, 2089 .suspend = &cik_suspend, 2090 .resume = &cik_resume, 2091 .asic_reset = &cik_asic_reset, 2092 .vga_set_state = &r600_vga_set_state, 2093 .mmio_hdp_flush = &r600_mmio_hdp_flush, 2094 .gui_idle = &r600_gui_idle, 2095 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2096 .get_xclk = &cik_get_xclk, 2097 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2098 .get_allowed_info_register = cik_get_allowed_info_register, 2099 .gart = { 2100 .tlb_flush = &cik_pcie_gart_tlb_flush, 2101 .get_page_entry = &rs600_gart_get_page_entry, 2102 .set_page = &rs600_gart_set_page, 2103 }, 2104 .vm = { 2105 .init = &cik_vm_init, 2106 .fini = &cik_vm_fini, 2107 .copy_pages = &cik_sdma_vm_copy_pages, 2108 .write_pages = &cik_sdma_vm_write_pages, 2109 .set_pages = &cik_sdma_vm_set_pages, 2110 .pad_ib = &cik_sdma_vm_pad_ib, 2111 }, 2112 .ring = { 2113 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, 2114 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, 2115 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, 2116 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, 2117 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, 2118 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 2119 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, 2120 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, 2121 }, 2122 .irq = { 2123 .set = &cik_irq_set, 2124 .process = &cik_irq_process, 2125 }, 2126 .display = { 2127 .bandwidth_update = &dce8_bandwidth_update, 2128 .get_vblank_counter = &evergreen_get_vblank_counter, 2129 .wait_for_vblank = &dce4_wait_for_vblank, 2130 .set_backlight_level = &atombios_set_backlight_level, 2131 .get_backlight_level = &atombios_get_backlight_level, 2132 }, 2133 .copy = { 2134 .blit = &cik_copy_cpdma, 2135 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2136 .dma = &cik_copy_dma, 2137 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2138 .copy = &cik_copy_dma, 2139 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2140 }, 2141 .surface = { 2142 .set_reg = r600_set_surface_reg, 2143 .clear_reg = r600_clear_surface_reg, 2144 }, 2145 .hpd = { 2146 .init = &evergreen_hpd_init, 2147 .fini = &evergreen_hpd_fini, 2148 .sense = &evergreen_hpd_sense, 2149 .set_polarity = &evergreen_hpd_set_polarity, 2150 }, 2151 .pm = { 2152 .misc = &evergreen_pm_misc, 2153 .prepare = &evergreen_pm_prepare, 2154 .finish = &evergreen_pm_finish, 2155 .init_profile = &sumo_pm_init_profile, 2156 .get_dynpm_state = &r600_pm_get_dynpm_state, 2157 .get_engine_clock = &radeon_atom_get_engine_clock, 2158 .set_engine_clock = &radeon_atom_set_engine_clock, 2159 .get_memory_clock = &radeon_atom_get_memory_clock, 2160 .set_memory_clock = &radeon_atom_set_memory_clock, 2161 .get_pcie_lanes = NULL, 2162 .set_pcie_lanes = NULL, 2163 .set_clock_gating = NULL, 2164 .set_uvd_clocks = &cik_set_uvd_clocks, 2165 .set_vce_clocks = &cik_set_vce_clocks, 2166 .get_temperature = &ci_get_temp, 2167 }, 2168 .dpm = { 2169 .init = &ci_dpm_init, 2170 .setup_asic = &ci_dpm_setup_asic, 2171 .enable = &ci_dpm_enable, 2172 .late_enable = &ci_dpm_late_enable, 2173 .disable = &ci_dpm_disable, 2174 .pre_set_power_state = &ci_dpm_pre_set_power_state, 2175 .set_power_state = &ci_dpm_set_power_state, 2176 .post_set_power_state = &ci_dpm_post_set_power_state, 2177 .display_configuration_changed = &ci_dpm_display_configuration_changed, 2178 .fini = &ci_dpm_fini, 2179 .get_sclk = &ci_dpm_get_sclk, 2180 .get_mclk = &ci_dpm_get_mclk, 2181 .print_power_state = &ci_dpm_print_power_state, 2182 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level, 2183 .force_performance_level = &ci_dpm_force_performance_level, 2184 .vblank_too_short = &ci_dpm_vblank_too_short, 2185 .powergate_uvd = &ci_dpm_powergate_uvd, 2186 .fan_ctrl_set_mode = &ci_fan_ctrl_set_mode, 2187 .fan_ctrl_get_mode = &ci_fan_ctrl_get_mode, 2188 .get_fan_speed_percent = &ci_fan_ctrl_get_fan_speed_percent, 2189 .set_fan_speed_percent = &ci_fan_ctrl_set_fan_speed_percent, 2190 .get_current_sclk = &ci_dpm_get_current_sclk, 2191 .get_current_mclk = &ci_dpm_get_current_mclk, 2192 }, 2193 .pflip = { 2194 .page_flip = &evergreen_page_flip, 2195 .page_flip_pending = &evergreen_page_flip_pending, 2196 }, 2197 }; 2198 2199 static struct radeon_asic kv_asic = { 2200 .init = &cik_init, 2201 .fini = &cik_fini, 2202 .suspend = &cik_suspend, 2203 .resume = &cik_resume, 2204 .asic_reset = &cik_asic_reset, 2205 .vga_set_state = &r600_vga_set_state, 2206 .mmio_hdp_flush = &r600_mmio_hdp_flush, 2207 .gui_idle = &r600_gui_idle, 2208 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2209 .get_xclk = &cik_get_xclk, 2210 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2211 .get_allowed_info_register = cik_get_allowed_info_register, 2212 .gart = { 2213 .tlb_flush = &cik_pcie_gart_tlb_flush, 2214 .get_page_entry = &rs600_gart_get_page_entry, 2215 .set_page = &rs600_gart_set_page, 2216 }, 2217 .vm = { 2218 .init = &cik_vm_init, 2219 .fini = &cik_vm_fini, 2220 .copy_pages = &cik_sdma_vm_copy_pages, 2221 .write_pages = &cik_sdma_vm_write_pages, 2222 .set_pages = &cik_sdma_vm_set_pages, 2223 .pad_ib = &cik_sdma_vm_pad_ib, 2224 }, 2225 .ring = { 2226 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, 2227 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, 2228 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, 2229 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, 2230 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, 2231 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 2232 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, 2233 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, 2234 }, 2235 .irq = { 2236 .set = &cik_irq_set, 2237 .process = &cik_irq_process, 2238 }, 2239 .display = { 2240 .bandwidth_update = &dce8_bandwidth_update, 2241 .get_vblank_counter = &evergreen_get_vblank_counter, 2242 .wait_for_vblank = &dce4_wait_for_vblank, 2243 .set_backlight_level = &atombios_set_backlight_level, 2244 .get_backlight_level = &atombios_get_backlight_level, 2245 }, 2246 .copy = { 2247 .blit = &cik_copy_cpdma, 2248 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2249 .dma = &cik_copy_dma, 2250 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2251 .copy = &cik_copy_dma, 2252 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2253 }, 2254 .surface = { 2255 .set_reg = r600_set_surface_reg, 2256 .clear_reg = r600_clear_surface_reg, 2257 }, 2258 .hpd = { 2259 .init = &evergreen_hpd_init, 2260 .fini = &evergreen_hpd_fini, 2261 .sense = &evergreen_hpd_sense, 2262 .set_polarity = &evergreen_hpd_set_polarity, 2263 }, 2264 .pm = { 2265 .misc = &evergreen_pm_misc, 2266 .prepare = &evergreen_pm_prepare, 2267 .finish = &evergreen_pm_finish, 2268 .init_profile = &sumo_pm_init_profile, 2269 .get_dynpm_state = &r600_pm_get_dynpm_state, 2270 .get_engine_clock = &radeon_atom_get_engine_clock, 2271 .set_engine_clock = &radeon_atom_set_engine_clock, 2272 .get_memory_clock = &radeon_atom_get_memory_clock, 2273 .set_memory_clock = &radeon_atom_set_memory_clock, 2274 .get_pcie_lanes = NULL, 2275 .set_pcie_lanes = NULL, 2276 .set_clock_gating = NULL, 2277 .set_uvd_clocks = &cik_set_uvd_clocks, 2278 .set_vce_clocks = &cik_set_vce_clocks, 2279 .get_temperature = &kv_get_temp, 2280 }, 2281 .dpm = { 2282 .init = &kv_dpm_init, 2283 .setup_asic = &kv_dpm_setup_asic, 2284 .enable = &kv_dpm_enable, 2285 .late_enable = &kv_dpm_late_enable, 2286 .disable = &kv_dpm_disable, 2287 .pre_set_power_state = &kv_dpm_pre_set_power_state, 2288 .set_power_state = &kv_dpm_set_power_state, 2289 .post_set_power_state = &kv_dpm_post_set_power_state, 2290 .display_configuration_changed = &kv_dpm_display_configuration_changed, 2291 .fini = &kv_dpm_fini, 2292 .get_sclk = &kv_dpm_get_sclk, 2293 .get_mclk = &kv_dpm_get_mclk, 2294 .print_power_state = &kv_dpm_print_power_state, 2295 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level, 2296 .force_performance_level = &kv_dpm_force_performance_level, 2297 .powergate_uvd = &kv_dpm_powergate_uvd, 2298 .enable_bapm = &kv_dpm_enable_bapm, 2299 .get_current_sclk = &kv_dpm_get_current_sclk, 2300 .get_current_mclk = &kv_dpm_get_current_mclk, 2301 }, 2302 .pflip = { 2303 .page_flip = &evergreen_page_flip, 2304 .page_flip_pending = &evergreen_page_flip_pending, 2305 }, 2306 }; 2307 2308 /** 2309 * radeon_asic_init - register asic specific callbacks 2310 * 2311 * @rdev: radeon device pointer 2312 * 2313 * Registers the appropriate asic specific callbacks for each 2314 * chip family. Also sets other asics specific info like the number 2315 * of crtcs and the register aperture accessors (all asics). 2316 * Returns 0 for success. 2317 */ 2318 int radeon_asic_init(struct radeon_device *rdev) 2319 { 2320 radeon_register_accessor_init(rdev); 2321 2322 /* set the number of crtcs */ 2323 if (rdev->flags & RADEON_SINGLE_CRTC) 2324 rdev->num_crtc = 1; 2325 else 2326 rdev->num_crtc = 2; 2327 2328 rdev->has_uvd = false; 2329 rdev->has_vce = false; 2330 2331 switch (rdev->family) { 2332 case CHIP_R100: 2333 case CHIP_RV100: 2334 case CHIP_RS100: 2335 case CHIP_RV200: 2336 case CHIP_RS200: 2337 rdev->asic = &r100_asic; 2338 break; 2339 case CHIP_R200: 2340 case CHIP_RV250: 2341 case CHIP_RS300: 2342 case CHIP_RV280: 2343 rdev->asic = &r200_asic; 2344 break; 2345 case CHIP_R300: 2346 case CHIP_R350: 2347 case CHIP_RV350: 2348 case CHIP_RV380: 2349 if (rdev->flags & RADEON_IS_PCIE) 2350 rdev->asic = &r300_asic_pcie; 2351 else 2352 rdev->asic = &r300_asic; 2353 break; 2354 case CHIP_R420: 2355 case CHIP_R423: 2356 case CHIP_RV410: 2357 rdev->asic = &r420_asic; 2358 /* handle macs */ 2359 if (rdev->bios == NULL) { 2360 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; 2361 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; 2362 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; 2363 rdev->asic->pm.set_memory_clock = NULL; 2364 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; 2365 } 2366 break; 2367 case CHIP_RS400: 2368 case CHIP_RS480: 2369 rdev->asic = &rs400_asic; 2370 break; 2371 case CHIP_RS600: 2372 rdev->asic = &rs600_asic; 2373 break; 2374 case CHIP_RS690: 2375 case CHIP_RS740: 2376 rdev->asic = &rs690_asic; 2377 break; 2378 case CHIP_RV515: 2379 rdev->asic = &rv515_asic; 2380 break; 2381 case CHIP_R520: 2382 case CHIP_RV530: 2383 case CHIP_RV560: 2384 case CHIP_RV570: 2385 case CHIP_R580: 2386 rdev->asic = &r520_asic; 2387 break; 2388 case CHIP_R600: 2389 rdev->asic = &r600_asic; 2390 break; 2391 case CHIP_RV610: 2392 case CHIP_RV630: 2393 case CHIP_RV620: 2394 case CHIP_RV635: 2395 case CHIP_RV670: 2396 rdev->asic = &rv6xx_asic; 2397 rdev->has_uvd = true; 2398 break; 2399 case CHIP_RS780: 2400 case CHIP_RS880: 2401 rdev->asic = &rs780_asic; 2402 /* 760G/780V/880V don't have UVD */ 2403 if ((rdev->pdev->device == 0x9616)|| 2404 (rdev->pdev->device == 0x9611)|| 2405 (rdev->pdev->device == 0x9613)|| 2406 (rdev->pdev->device == 0x9711)|| 2407 (rdev->pdev->device == 0x9713)) 2408 rdev->has_uvd = false; 2409 else 2410 rdev->has_uvd = true; 2411 break; 2412 case CHIP_RV770: 2413 case CHIP_RV730: 2414 case CHIP_RV710: 2415 case CHIP_RV740: 2416 rdev->asic = &rv770_asic; 2417 rdev->has_uvd = true; 2418 break; 2419 case CHIP_CEDAR: 2420 case CHIP_REDWOOD: 2421 case CHIP_JUNIPER: 2422 case CHIP_CYPRESS: 2423 case CHIP_HEMLOCK: 2424 /* set num crtcs */ 2425 if (rdev->family == CHIP_CEDAR) 2426 rdev->num_crtc = 4; 2427 else 2428 rdev->num_crtc = 6; 2429 rdev->asic = &evergreen_asic; 2430 rdev->has_uvd = true; 2431 break; 2432 case CHIP_PALM: 2433 case CHIP_SUMO: 2434 case CHIP_SUMO2: 2435 rdev->asic = &sumo_asic; 2436 rdev->has_uvd = true; 2437 break; 2438 case CHIP_BARTS: 2439 case CHIP_TURKS: 2440 case CHIP_CAICOS: 2441 /* set num crtcs */ 2442 if (rdev->family == CHIP_CAICOS) 2443 rdev->num_crtc = 4; 2444 else 2445 rdev->num_crtc = 6; 2446 rdev->asic = &btc_asic; 2447 rdev->has_uvd = true; 2448 break; 2449 case CHIP_CAYMAN: 2450 rdev->asic = &cayman_asic; 2451 /* set num crtcs */ 2452 rdev->num_crtc = 6; 2453 rdev->has_uvd = true; 2454 break; 2455 case CHIP_ARUBA: 2456 rdev->asic = &trinity_asic; 2457 /* set num crtcs */ 2458 rdev->num_crtc = 4; 2459 rdev->has_uvd = true; 2460 rdev->has_vce = true; 2461 rdev->cg_flags = 2462 RADEON_CG_SUPPORT_VCE_MGCG; 2463 break; 2464 case CHIP_TAHITI: 2465 case CHIP_PITCAIRN: 2466 case CHIP_VERDE: 2467 case CHIP_OLAND: 2468 case CHIP_HAINAN: 2469 rdev->asic = &si_asic; 2470 /* set num crtcs */ 2471 if (rdev->family == CHIP_HAINAN) 2472 rdev->num_crtc = 0; 2473 else if (rdev->family == CHIP_OLAND) 2474 rdev->num_crtc = 2; 2475 else 2476 rdev->num_crtc = 6; 2477 if (rdev->family == CHIP_HAINAN) { 2478 rdev->has_uvd = false; 2479 rdev->has_vce = false; 2480 } else { 2481 rdev->has_uvd = true; 2482 rdev->has_vce = true; 2483 } 2484 switch (rdev->family) { 2485 case CHIP_TAHITI: 2486 rdev->cg_flags = 2487 RADEON_CG_SUPPORT_GFX_MGCG | 2488 RADEON_CG_SUPPORT_GFX_MGLS | 2489 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2490 RADEON_CG_SUPPORT_GFX_CGLS | 2491 RADEON_CG_SUPPORT_GFX_CGTS | 2492 RADEON_CG_SUPPORT_GFX_CP_LS | 2493 RADEON_CG_SUPPORT_MC_MGCG | 2494 RADEON_CG_SUPPORT_SDMA_MGCG | 2495 RADEON_CG_SUPPORT_BIF_LS | 2496 RADEON_CG_SUPPORT_VCE_MGCG | 2497 RADEON_CG_SUPPORT_UVD_MGCG | 2498 RADEON_CG_SUPPORT_HDP_LS | 2499 RADEON_CG_SUPPORT_HDP_MGCG; 2500 rdev->pg_flags = 0; 2501 break; 2502 case CHIP_PITCAIRN: 2503 rdev->cg_flags = 2504 RADEON_CG_SUPPORT_GFX_MGCG | 2505 RADEON_CG_SUPPORT_GFX_MGLS | 2506 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2507 RADEON_CG_SUPPORT_GFX_CGLS | 2508 RADEON_CG_SUPPORT_GFX_CGTS | 2509 RADEON_CG_SUPPORT_GFX_CP_LS | 2510 RADEON_CG_SUPPORT_GFX_RLC_LS | 2511 RADEON_CG_SUPPORT_MC_LS | 2512 RADEON_CG_SUPPORT_MC_MGCG | 2513 RADEON_CG_SUPPORT_SDMA_MGCG | 2514 RADEON_CG_SUPPORT_BIF_LS | 2515 RADEON_CG_SUPPORT_VCE_MGCG | 2516 RADEON_CG_SUPPORT_UVD_MGCG | 2517 RADEON_CG_SUPPORT_HDP_LS | 2518 RADEON_CG_SUPPORT_HDP_MGCG; 2519 rdev->pg_flags = 0; 2520 break; 2521 case CHIP_VERDE: 2522 rdev->cg_flags = 2523 RADEON_CG_SUPPORT_GFX_MGCG | 2524 RADEON_CG_SUPPORT_GFX_MGLS | 2525 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2526 RADEON_CG_SUPPORT_GFX_CGLS | 2527 RADEON_CG_SUPPORT_GFX_CGTS | 2528 RADEON_CG_SUPPORT_GFX_CP_LS | 2529 RADEON_CG_SUPPORT_GFX_RLC_LS | 2530 RADEON_CG_SUPPORT_MC_LS | 2531 RADEON_CG_SUPPORT_MC_MGCG | 2532 RADEON_CG_SUPPORT_SDMA_MGCG | 2533 RADEON_CG_SUPPORT_BIF_LS | 2534 RADEON_CG_SUPPORT_VCE_MGCG | 2535 RADEON_CG_SUPPORT_UVD_MGCG | 2536 RADEON_CG_SUPPORT_HDP_LS | 2537 RADEON_CG_SUPPORT_HDP_MGCG; 2538 rdev->pg_flags = 0 | 2539 /*RADEON_PG_SUPPORT_GFX_PG | */ 2540 RADEON_PG_SUPPORT_SDMA; 2541 break; 2542 case CHIP_OLAND: 2543 rdev->cg_flags = 2544 RADEON_CG_SUPPORT_GFX_MGCG | 2545 RADEON_CG_SUPPORT_GFX_MGLS | 2546 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2547 RADEON_CG_SUPPORT_GFX_CGLS | 2548 RADEON_CG_SUPPORT_GFX_CGTS | 2549 RADEON_CG_SUPPORT_GFX_CP_LS | 2550 RADEON_CG_SUPPORT_GFX_RLC_LS | 2551 RADEON_CG_SUPPORT_MC_LS | 2552 RADEON_CG_SUPPORT_MC_MGCG | 2553 RADEON_CG_SUPPORT_SDMA_MGCG | 2554 RADEON_CG_SUPPORT_BIF_LS | 2555 RADEON_CG_SUPPORT_UVD_MGCG | 2556 RADEON_CG_SUPPORT_HDP_LS | 2557 RADEON_CG_SUPPORT_HDP_MGCG; 2558 rdev->pg_flags = 0; 2559 break; 2560 case CHIP_HAINAN: 2561 rdev->cg_flags = 2562 RADEON_CG_SUPPORT_GFX_MGCG | 2563 RADEON_CG_SUPPORT_GFX_MGLS | 2564 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2565 RADEON_CG_SUPPORT_GFX_CGLS | 2566 RADEON_CG_SUPPORT_GFX_CGTS | 2567 RADEON_CG_SUPPORT_GFX_CP_LS | 2568 RADEON_CG_SUPPORT_GFX_RLC_LS | 2569 RADEON_CG_SUPPORT_MC_LS | 2570 RADEON_CG_SUPPORT_MC_MGCG | 2571 RADEON_CG_SUPPORT_SDMA_MGCG | 2572 RADEON_CG_SUPPORT_BIF_LS | 2573 RADEON_CG_SUPPORT_HDP_LS | 2574 RADEON_CG_SUPPORT_HDP_MGCG; 2575 rdev->pg_flags = 0; 2576 break; 2577 default: 2578 rdev->cg_flags = 0; 2579 rdev->pg_flags = 0; 2580 break; 2581 } 2582 break; 2583 case CHIP_BONAIRE: 2584 case CHIP_HAWAII: 2585 rdev->asic = &ci_asic; 2586 rdev->num_crtc = 6; 2587 rdev->has_uvd = true; 2588 rdev->has_vce = true; 2589 if (rdev->family == CHIP_BONAIRE) { 2590 rdev->cg_flags = 2591 RADEON_CG_SUPPORT_GFX_MGCG | 2592 RADEON_CG_SUPPORT_GFX_MGLS | 2593 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2594 RADEON_CG_SUPPORT_GFX_CGLS | 2595 RADEON_CG_SUPPORT_GFX_CGTS | 2596 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2597 RADEON_CG_SUPPORT_GFX_CP_LS | 2598 RADEON_CG_SUPPORT_MC_LS | 2599 RADEON_CG_SUPPORT_MC_MGCG | 2600 RADEON_CG_SUPPORT_SDMA_MGCG | 2601 RADEON_CG_SUPPORT_SDMA_LS | 2602 RADEON_CG_SUPPORT_BIF_LS | 2603 RADEON_CG_SUPPORT_VCE_MGCG | 2604 RADEON_CG_SUPPORT_UVD_MGCG | 2605 RADEON_CG_SUPPORT_HDP_LS | 2606 RADEON_CG_SUPPORT_HDP_MGCG; 2607 rdev->pg_flags = 0; 2608 } else { 2609 rdev->cg_flags = 2610 RADEON_CG_SUPPORT_GFX_MGCG | 2611 RADEON_CG_SUPPORT_GFX_MGLS | 2612 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2613 RADEON_CG_SUPPORT_GFX_CGLS | 2614 RADEON_CG_SUPPORT_GFX_CGTS | 2615 RADEON_CG_SUPPORT_GFX_CP_LS | 2616 RADEON_CG_SUPPORT_MC_LS | 2617 RADEON_CG_SUPPORT_MC_MGCG | 2618 RADEON_CG_SUPPORT_SDMA_MGCG | 2619 RADEON_CG_SUPPORT_SDMA_LS | 2620 RADEON_CG_SUPPORT_BIF_LS | 2621 RADEON_CG_SUPPORT_VCE_MGCG | 2622 RADEON_CG_SUPPORT_UVD_MGCG | 2623 RADEON_CG_SUPPORT_HDP_LS | 2624 RADEON_CG_SUPPORT_HDP_MGCG; 2625 rdev->pg_flags = 0; 2626 } 2627 break; 2628 case CHIP_KAVERI: 2629 case CHIP_KABINI: 2630 case CHIP_MULLINS: 2631 rdev->asic = &kv_asic; 2632 /* set num crtcs */ 2633 if (rdev->family == CHIP_KAVERI) { 2634 rdev->num_crtc = 4; 2635 rdev->cg_flags = 2636 RADEON_CG_SUPPORT_GFX_MGCG | 2637 RADEON_CG_SUPPORT_GFX_MGLS | 2638 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2639 RADEON_CG_SUPPORT_GFX_CGLS | 2640 RADEON_CG_SUPPORT_GFX_CGTS | 2641 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2642 RADEON_CG_SUPPORT_GFX_CP_LS | 2643 RADEON_CG_SUPPORT_SDMA_MGCG | 2644 RADEON_CG_SUPPORT_SDMA_LS | 2645 RADEON_CG_SUPPORT_BIF_LS | 2646 RADEON_CG_SUPPORT_VCE_MGCG | 2647 RADEON_CG_SUPPORT_UVD_MGCG | 2648 RADEON_CG_SUPPORT_HDP_LS | 2649 RADEON_CG_SUPPORT_HDP_MGCG; 2650 rdev->pg_flags = 0; 2651 /*RADEON_PG_SUPPORT_GFX_PG | 2652 RADEON_PG_SUPPORT_GFX_SMG | 2653 RADEON_PG_SUPPORT_GFX_DMG | 2654 RADEON_PG_SUPPORT_UVD | 2655 RADEON_PG_SUPPORT_VCE | 2656 RADEON_PG_SUPPORT_CP | 2657 RADEON_PG_SUPPORT_GDS | 2658 RADEON_PG_SUPPORT_RLC_SMU_HS | 2659 RADEON_PG_SUPPORT_ACP | 2660 RADEON_PG_SUPPORT_SAMU;*/ 2661 } else { 2662 rdev->num_crtc = 2; 2663 rdev->cg_flags = 2664 RADEON_CG_SUPPORT_GFX_MGCG | 2665 RADEON_CG_SUPPORT_GFX_MGLS | 2666 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2667 RADEON_CG_SUPPORT_GFX_CGLS | 2668 RADEON_CG_SUPPORT_GFX_CGTS | 2669 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2670 RADEON_CG_SUPPORT_GFX_CP_LS | 2671 RADEON_CG_SUPPORT_SDMA_MGCG | 2672 RADEON_CG_SUPPORT_SDMA_LS | 2673 RADEON_CG_SUPPORT_BIF_LS | 2674 RADEON_CG_SUPPORT_VCE_MGCG | 2675 RADEON_CG_SUPPORT_UVD_MGCG | 2676 RADEON_CG_SUPPORT_HDP_LS | 2677 RADEON_CG_SUPPORT_HDP_MGCG; 2678 rdev->pg_flags = 0; 2679 /*RADEON_PG_SUPPORT_GFX_PG | 2680 RADEON_PG_SUPPORT_GFX_SMG | 2681 RADEON_PG_SUPPORT_UVD | 2682 RADEON_PG_SUPPORT_VCE | 2683 RADEON_PG_SUPPORT_CP | 2684 RADEON_PG_SUPPORT_GDS | 2685 RADEON_PG_SUPPORT_RLC_SMU_HS | 2686 RADEON_PG_SUPPORT_SAMU;*/ 2687 } 2688 rdev->has_uvd = true; 2689 rdev->has_vce = true; 2690 break; 2691 default: 2692 /* FIXME: not supported yet */ 2693 return -EINVAL; 2694 } 2695 2696 if (rdev->flags & RADEON_IS_IGP) { 2697 rdev->asic->pm.get_memory_clock = NULL; 2698 rdev->asic->pm.set_memory_clock = NULL; 2699 } 2700 2701 if (!radeon_uvd) 2702 rdev->has_uvd = false; 2703 if (!radeon_vce) 2704 rdev->has_vce = false; 2705 2706 return 0; 2707 } 2708 2709