1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 
29 #include <linux/console.h>
30 #include <drm/drmP.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include "radeon_reg.h"
36 #include "radeon.h"
37 #include "radeon_asic.h"
38 #include "atom.h"
39 
40 /*
41  * Registers accessors functions.
42  */
43 /**
44  * radeon_invalid_rreg - dummy reg read function
45  *
46  * @rdev: radeon device pointer
47  * @reg: offset of register
48  *
49  * Dummy register read function.  Used for register blocks
50  * that certain asics don't have (all asics).
51  * Returns the value in the register.
52  */
53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54 {
55 	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
56 	BUG_ON(1);
57 	return 0;
58 }
59 
60 /**
61  * radeon_invalid_wreg - dummy reg write function
62  *
63  * @rdev: radeon device pointer
64  * @reg: offset of register
65  * @v: value to write to the register
66  *
67  * Dummy register read function.  Used for register blocks
68  * that certain asics don't have (all asics).
69  */
70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
71 {
72 	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
73 		  reg, v);
74 	BUG_ON(1);
75 }
76 
77 /**
78  * radeon_register_accessor_init - sets up the register accessor callbacks
79  *
80  * @rdev: radeon device pointer
81  *
82  * Sets up the register accessor callbacks for various register
83  * apertures.  Not all asics have all apertures (all asics).
84  */
85 static void radeon_register_accessor_init(struct radeon_device *rdev)
86 {
87 	rdev->mc_rreg = &radeon_invalid_rreg;
88 	rdev->mc_wreg = &radeon_invalid_wreg;
89 	rdev->pll_rreg = &radeon_invalid_rreg;
90 	rdev->pll_wreg = &radeon_invalid_wreg;
91 	rdev->pciep_rreg = &radeon_invalid_rreg;
92 	rdev->pciep_wreg = &radeon_invalid_wreg;
93 
94 	/* Don't change order as we are overridding accessor. */
95 	if (rdev->family < CHIP_RV515) {
96 		rdev->pcie_reg_mask = 0xff;
97 	} else {
98 		rdev->pcie_reg_mask = 0x7ff;
99 	}
100 	/* FIXME: not sure here */
101 	if (rdev->family <= CHIP_R580) {
102 		rdev->pll_rreg = &r100_pll_rreg;
103 		rdev->pll_wreg = &r100_pll_wreg;
104 	}
105 	if (rdev->family >= CHIP_R420) {
106 		rdev->mc_rreg = &r420_mc_rreg;
107 		rdev->mc_wreg = &r420_mc_wreg;
108 	}
109 	if (rdev->family >= CHIP_RV515) {
110 		rdev->mc_rreg = &rv515_mc_rreg;
111 		rdev->mc_wreg = &rv515_mc_wreg;
112 	}
113 	if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
114 		rdev->mc_rreg = &rs400_mc_rreg;
115 		rdev->mc_wreg = &rs400_mc_wreg;
116 	}
117 	if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
118 		rdev->mc_rreg = &rs690_mc_rreg;
119 		rdev->mc_wreg = &rs690_mc_wreg;
120 	}
121 	if (rdev->family == CHIP_RS600) {
122 		rdev->mc_rreg = &rs600_mc_rreg;
123 		rdev->mc_wreg = &rs600_mc_wreg;
124 	}
125 	if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
126 		rdev->mc_rreg = &rs780_mc_rreg;
127 		rdev->mc_wreg = &rs780_mc_wreg;
128 	}
129 
130 	if (rdev->family >= CHIP_BONAIRE) {
131 		rdev->pciep_rreg = &cik_pciep_rreg;
132 		rdev->pciep_wreg = &cik_pciep_wreg;
133 	} else if (rdev->family >= CHIP_R600) {
134 		rdev->pciep_rreg = &r600_pciep_rreg;
135 		rdev->pciep_wreg = &r600_pciep_wreg;
136 	}
137 }
138 
139 
140 /* helper to disable agp */
141 /**
142  * radeon_agp_disable - AGP disable helper function
143  *
144  * @rdev: radeon device pointer
145  *
146  * Removes AGP flags and changes the gart callbacks on AGP
147  * cards when using the internal gart rather than AGP (all asics).
148  */
149 void radeon_agp_disable(struct radeon_device *rdev)
150 {
151 	rdev->flags &= ~RADEON_IS_AGP;
152 	if (rdev->family >= CHIP_R600) {
153 		DRM_INFO("Forcing AGP to PCIE mode\n");
154 		rdev->flags |= RADEON_IS_PCIE;
155 	} else if (rdev->family >= CHIP_RV515 ||
156 			rdev->family == CHIP_RV380 ||
157 			rdev->family == CHIP_RV410 ||
158 			rdev->family == CHIP_R423) {
159 		DRM_INFO("Forcing AGP to PCIE mode\n");
160 		rdev->flags |= RADEON_IS_PCIE;
161 		rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
162 		rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
163 	} else {
164 		DRM_INFO("Forcing AGP to PCI mode\n");
165 		rdev->flags |= RADEON_IS_PCI;
166 		rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
167 		rdev->asic->gart.set_page = &r100_pci_gart_set_page;
168 	}
169 	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
170 }
171 
172 /*
173  * ASIC
174  */
175 
176 static struct radeon_asic_ring r100_gfx_ring = {
177 	.ib_execute = &r100_ring_ib_execute,
178 	.emit_fence = &r100_fence_ring_emit,
179 	.emit_semaphore = &r100_semaphore_ring_emit,
180 	.cs_parse = &r100_cs_parse,
181 	.ring_start = &r100_ring_start,
182 	.ring_test = &r100_ring_test,
183 	.ib_test = &r100_ib_test,
184 	.is_lockup = &r100_gpu_is_lockup,
185 	.get_rptr = &radeon_ring_generic_get_rptr,
186 	.get_wptr = &radeon_ring_generic_get_wptr,
187 	.set_wptr = &radeon_ring_generic_set_wptr,
188 };
189 
190 static struct radeon_asic r100_asic = {
191 	.init = &r100_init,
192 	.fini = &r100_fini,
193 	.suspend = &r100_suspend,
194 	.resume = &r100_resume,
195 	.vga_set_state = &r100_vga_set_state,
196 	.asic_reset = &r100_asic_reset,
197 	.ioctl_wait_idle = NULL,
198 	.gui_idle = &r100_gui_idle,
199 	.mc_wait_for_idle = &r100_mc_wait_for_idle,
200 	.gart = {
201 		.tlb_flush = &r100_pci_gart_tlb_flush,
202 		.set_page = &r100_pci_gart_set_page,
203 	},
204 	.ring = {
205 		[RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
206 	},
207 	.irq = {
208 		.set = &r100_irq_set,
209 		.process = &r100_irq_process,
210 	},
211 	.display = {
212 		.bandwidth_update = &r100_bandwidth_update,
213 		.get_vblank_counter = &r100_get_vblank_counter,
214 		.wait_for_vblank = &r100_wait_for_vblank,
215 		.set_backlight_level = &radeon_legacy_set_backlight_level,
216 		.get_backlight_level = &radeon_legacy_get_backlight_level,
217 	},
218 	.copy = {
219 		.blit = &r100_copy_blit,
220 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
221 		.dma = NULL,
222 		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
223 		.copy = &r100_copy_blit,
224 		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
225 	},
226 	.surface = {
227 		.set_reg = r100_set_surface_reg,
228 		.clear_reg = r100_clear_surface_reg,
229 	},
230 	.hpd = {
231 		.init = &r100_hpd_init,
232 		.fini = &r100_hpd_fini,
233 		.sense = &r100_hpd_sense,
234 		.set_polarity = &r100_hpd_set_polarity,
235 	},
236 	.pm = {
237 		.misc = &r100_pm_misc,
238 		.prepare = &r100_pm_prepare,
239 		.finish = &r100_pm_finish,
240 		.init_profile = &r100_pm_init_profile,
241 		.get_dynpm_state = &r100_pm_get_dynpm_state,
242 		.get_engine_clock = &radeon_legacy_get_engine_clock,
243 		.set_engine_clock = &radeon_legacy_set_engine_clock,
244 		.get_memory_clock = &radeon_legacy_get_memory_clock,
245 		.set_memory_clock = NULL,
246 		.get_pcie_lanes = NULL,
247 		.set_pcie_lanes = NULL,
248 		.set_clock_gating = &radeon_legacy_set_clock_gating,
249 	},
250 	.pflip = {
251 		.pre_page_flip = &r100_pre_page_flip,
252 		.page_flip = &r100_page_flip,
253 		.post_page_flip = &r100_post_page_flip,
254 	},
255 };
256 
257 static struct radeon_asic r200_asic = {
258 	.init = &r100_init,
259 	.fini = &r100_fini,
260 	.suspend = &r100_suspend,
261 	.resume = &r100_resume,
262 	.vga_set_state = &r100_vga_set_state,
263 	.asic_reset = &r100_asic_reset,
264 	.ioctl_wait_idle = NULL,
265 	.gui_idle = &r100_gui_idle,
266 	.mc_wait_for_idle = &r100_mc_wait_for_idle,
267 	.gart = {
268 		.tlb_flush = &r100_pci_gart_tlb_flush,
269 		.set_page = &r100_pci_gart_set_page,
270 	},
271 	.ring = {
272 		[RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
273 	},
274 	.irq = {
275 		.set = &r100_irq_set,
276 		.process = &r100_irq_process,
277 	},
278 	.display = {
279 		.bandwidth_update = &r100_bandwidth_update,
280 		.get_vblank_counter = &r100_get_vblank_counter,
281 		.wait_for_vblank = &r100_wait_for_vblank,
282 		.set_backlight_level = &radeon_legacy_set_backlight_level,
283 		.get_backlight_level = &radeon_legacy_get_backlight_level,
284 	},
285 	.copy = {
286 		.blit = &r100_copy_blit,
287 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
288 		.dma = &r200_copy_dma,
289 		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
290 		.copy = &r100_copy_blit,
291 		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
292 	},
293 	.surface = {
294 		.set_reg = r100_set_surface_reg,
295 		.clear_reg = r100_clear_surface_reg,
296 	},
297 	.hpd = {
298 		.init = &r100_hpd_init,
299 		.fini = &r100_hpd_fini,
300 		.sense = &r100_hpd_sense,
301 		.set_polarity = &r100_hpd_set_polarity,
302 	},
303 	.pm = {
304 		.misc = &r100_pm_misc,
305 		.prepare = &r100_pm_prepare,
306 		.finish = &r100_pm_finish,
307 		.init_profile = &r100_pm_init_profile,
308 		.get_dynpm_state = &r100_pm_get_dynpm_state,
309 		.get_engine_clock = &radeon_legacy_get_engine_clock,
310 		.set_engine_clock = &radeon_legacy_set_engine_clock,
311 		.get_memory_clock = &radeon_legacy_get_memory_clock,
312 		.set_memory_clock = NULL,
313 		.get_pcie_lanes = NULL,
314 		.set_pcie_lanes = NULL,
315 		.set_clock_gating = &radeon_legacy_set_clock_gating,
316 	},
317 	.pflip = {
318 		.pre_page_flip = &r100_pre_page_flip,
319 		.page_flip = &r100_page_flip,
320 		.post_page_flip = &r100_post_page_flip,
321 	},
322 };
323 
324 static struct radeon_asic_ring r300_gfx_ring = {
325 	.ib_execute = &r100_ring_ib_execute,
326 	.emit_fence = &r300_fence_ring_emit,
327 	.emit_semaphore = &r100_semaphore_ring_emit,
328 	.cs_parse = &r300_cs_parse,
329 	.ring_start = &r300_ring_start,
330 	.ring_test = &r100_ring_test,
331 	.ib_test = &r100_ib_test,
332 	.is_lockup = &r100_gpu_is_lockup,
333 	.get_rptr = &radeon_ring_generic_get_rptr,
334 	.get_wptr = &radeon_ring_generic_get_wptr,
335 	.set_wptr = &radeon_ring_generic_set_wptr,
336 };
337 
338 static struct radeon_asic r300_asic = {
339 	.init = &r300_init,
340 	.fini = &r300_fini,
341 	.suspend = &r300_suspend,
342 	.resume = &r300_resume,
343 	.vga_set_state = &r100_vga_set_state,
344 	.asic_reset = &r300_asic_reset,
345 	.ioctl_wait_idle = NULL,
346 	.gui_idle = &r100_gui_idle,
347 	.mc_wait_for_idle = &r300_mc_wait_for_idle,
348 	.gart = {
349 		.tlb_flush = &r100_pci_gart_tlb_flush,
350 		.set_page = &r100_pci_gart_set_page,
351 	},
352 	.ring = {
353 		[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
354 	},
355 	.irq = {
356 		.set = &r100_irq_set,
357 		.process = &r100_irq_process,
358 	},
359 	.display = {
360 		.bandwidth_update = &r100_bandwidth_update,
361 		.get_vblank_counter = &r100_get_vblank_counter,
362 		.wait_for_vblank = &r100_wait_for_vblank,
363 		.set_backlight_level = &radeon_legacy_set_backlight_level,
364 		.get_backlight_level = &radeon_legacy_get_backlight_level,
365 	},
366 	.copy = {
367 		.blit = &r100_copy_blit,
368 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
369 		.dma = &r200_copy_dma,
370 		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
371 		.copy = &r100_copy_blit,
372 		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
373 	},
374 	.surface = {
375 		.set_reg = r100_set_surface_reg,
376 		.clear_reg = r100_clear_surface_reg,
377 	},
378 	.hpd = {
379 		.init = &r100_hpd_init,
380 		.fini = &r100_hpd_fini,
381 		.sense = &r100_hpd_sense,
382 		.set_polarity = &r100_hpd_set_polarity,
383 	},
384 	.pm = {
385 		.misc = &r100_pm_misc,
386 		.prepare = &r100_pm_prepare,
387 		.finish = &r100_pm_finish,
388 		.init_profile = &r100_pm_init_profile,
389 		.get_dynpm_state = &r100_pm_get_dynpm_state,
390 		.get_engine_clock = &radeon_legacy_get_engine_clock,
391 		.set_engine_clock = &radeon_legacy_set_engine_clock,
392 		.get_memory_clock = &radeon_legacy_get_memory_clock,
393 		.set_memory_clock = NULL,
394 		.get_pcie_lanes = &rv370_get_pcie_lanes,
395 		.set_pcie_lanes = &rv370_set_pcie_lanes,
396 		.set_clock_gating = &radeon_legacy_set_clock_gating,
397 	},
398 	.pflip = {
399 		.pre_page_flip = &r100_pre_page_flip,
400 		.page_flip = &r100_page_flip,
401 		.post_page_flip = &r100_post_page_flip,
402 	},
403 };
404 
405 static struct radeon_asic r300_asic_pcie = {
406 	.init = &r300_init,
407 	.fini = &r300_fini,
408 	.suspend = &r300_suspend,
409 	.resume = &r300_resume,
410 	.vga_set_state = &r100_vga_set_state,
411 	.asic_reset = &r300_asic_reset,
412 	.ioctl_wait_idle = NULL,
413 	.gui_idle = &r100_gui_idle,
414 	.mc_wait_for_idle = &r300_mc_wait_for_idle,
415 	.gart = {
416 		.tlb_flush = &rv370_pcie_gart_tlb_flush,
417 		.set_page = &rv370_pcie_gart_set_page,
418 	},
419 	.ring = {
420 		[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
421 	},
422 	.irq = {
423 		.set = &r100_irq_set,
424 		.process = &r100_irq_process,
425 	},
426 	.display = {
427 		.bandwidth_update = &r100_bandwidth_update,
428 		.get_vblank_counter = &r100_get_vblank_counter,
429 		.wait_for_vblank = &r100_wait_for_vblank,
430 		.set_backlight_level = &radeon_legacy_set_backlight_level,
431 		.get_backlight_level = &radeon_legacy_get_backlight_level,
432 	},
433 	.copy = {
434 		.blit = &r100_copy_blit,
435 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
436 		.dma = &r200_copy_dma,
437 		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
438 		.copy = &r100_copy_blit,
439 		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
440 	},
441 	.surface = {
442 		.set_reg = r100_set_surface_reg,
443 		.clear_reg = r100_clear_surface_reg,
444 	},
445 	.hpd = {
446 		.init = &r100_hpd_init,
447 		.fini = &r100_hpd_fini,
448 		.sense = &r100_hpd_sense,
449 		.set_polarity = &r100_hpd_set_polarity,
450 	},
451 	.pm = {
452 		.misc = &r100_pm_misc,
453 		.prepare = &r100_pm_prepare,
454 		.finish = &r100_pm_finish,
455 		.init_profile = &r100_pm_init_profile,
456 		.get_dynpm_state = &r100_pm_get_dynpm_state,
457 		.get_engine_clock = &radeon_legacy_get_engine_clock,
458 		.set_engine_clock = &radeon_legacy_set_engine_clock,
459 		.get_memory_clock = &radeon_legacy_get_memory_clock,
460 		.set_memory_clock = NULL,
461 		.get_pcie_lanes = &rv370_get_pcie_lanes,
462 		.set_pcie_lanes = &rv370_set_pcie_lanes,
463 		.set_clock_gating = &radeon_legacy_set_clock_gating,
464 	},
465 	.pflip = {
466 		.pre_page_flip = &r100_pre_page_flip,
467 		.page_flip = &r100_page_flip,
468 		.post_page_flip = &r100_post_page_flip,
469 	},
470 };
471 
472 static struct radeon_asic r420_asic = {
473 	.init = &r420_init,
474 	.fini = &r420_fini,
475 	.suspend = &r420_suspend,
476 	.resume = &r420_resume,
477 	.vga_set_state = &r100_vga_set_state,
478 	.asic_reset = &r300_asic_reset,
479 	.ioctl_wait_idle = NULL,
480 	.gui_idle = &r100_gui_idle,
481 	.mc_wait_for_idle = &r300_mc_wait_for_idle,
482 	.gart = {
483 		.tlb_flush = &rv370_pcie_gart_tlb_flush,
484 		.set_page = &rv370_pcie_gart_set_page,
485 	},
486 	.ring = {
487 		[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
488 	},
489 	.irq = {
490 		.set = &r100_irq_set,
491 		.process = &r100_irq_process,
492 	},
493 	.display = {
494 		.bandwidth_update = &r100_bandwidth_update,
495 		.get_vblank_counter = &r100_get_vblank_counter,
496 		.wait_for_vblank = &r100_wait_for_vblank,
497 		.set_backlight_level = &atombios_set_backlight_level,
498 		.get_backlight_level = &atombios_get_backlight_level,
499 	},
500 	.copy = {
501 		.blit = &r100_copy_blit,
502 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
503 		.dma = &r200_copy_dma,
504 		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
505 		.copy = &r100_copy_blit,
506 		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
507 	},
508 	.surface = {
509 		.set_reg = r100_set_surface_reg,
510 		.clear_reg = r100_clear_surface_reg,
511 	},
512 	.hpd = {
513 		.init = &r100_hpd_init,
514 		.fini = &r100_hpd_fini,
515 		.sense = &r100_hpd_sense,
516 		.set_polarity = &r100_hpd_set_polarity,
517 	},
518 	.pm = {
519 		.misc = &r100_pm_misc,
520 		.prepare = &r100_pm_prepare,
521 		.finish = &r100_pm_finish,
522 		.init_profile = &r420_pm_init_profile,
523 		.get_dynpm_state = &r100_pm_get_dynpm_state,
524 		.get_engine_clock = &radeon_atom_get_engine_clock,
525 		.set_engine_clock = &radeon_atom_set_engine_clock,
526 		.get_memory_clock = &radeon_atom_get_memory_clock,
527 		.set_memory_clock = &radeon_atom_set_memory_clock,
528 		.get_pcie_lanes = &rv370_get_pcie_lanes,
529 		.set_pcie_lanes = &rv370_set_pcie_lanes,
530 		.set_clock_gating = &radeon_atom_set_clock_gating,
531 	},
532 	.pflip = {
533 		.pre_page_flip = &r100_pre_page_flip,
534 		.page_flip = &r100_page_flip,
535 		.post_page_flip = &r100_post_page_flip,
536 	},
537 };
538 
539 static struct radeon_asic rs400_asic = {
540 	.init = &rs400_init,
541 	.fini = &rs400_fini,
542 	.suspend = &rs400_suspend,
543 	.resume = &rs400_resume,
544 	.vga_set_state = &r100_vga_set_state,
545 	.asic_reset = &r300_asic_reset,
546 	.ioctl_wait_idle = NULL,
547 	.gui_idle = &r100_gui_idle,
548 	.mc_wait_for_idle = &rs400_mc_wait_for_idle,
549 	.gart = {
550 		.tlb_flush = &rs400_gart_tlb_flush,
551 		.set_page = &rs400_gart_set_page,
552 	},
553 	.ring = {
554 		[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
555 	},
556 	.irq = {
557 		.set = &r100_irq_set,
558 		.process = &r100_irq_process,
559 	},
560 	.display = {
561 		.bandwidth_update = &r100_bandwidth_update,
562 		.get_vblank_counter = &r100_get_vblank_counter,
563 		.wait_for_vblank = &r100_wait_for_vblank,
564 		.set_backlight_level = &radeon_legacy_set_backlight_level,
565 		.get_backlight_level = &radeon_legacy_get_backlight_level,
566 	},
567 	.copy = {
568 		.blit = &r100_copy_blit,
569 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
570 		.dma = &r200_copy_dma,
571 		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
572 		.copy = &r100_copy_blit,
573 		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
574 	},
575 	.surface = {
576 		.set_reg = r100_set_surface_reg,
577 		.clear_reg = r100_clear_surface_reg,
578 	},
579 	.hpd = {
580 		.init = &r100_hpd_init,
581 		.fini = &r100_hpd_fini,
582 		.sense = &r100_hpd_sense,
583 		.set_polarity = &r100_hpd_set_polarity,
584 	},
585 	.pm = {
586 		.misc = &r100_pm_misc,
587 		.prepare = &r100_pm_prepare,
588 		.finish = &r100_pm_finish,
589 		.init_profile = &r100_pm_init_profile,
590 		.get_dynpm_state = &r100_pm_get_dynpm_state,
591 		.get_engine_clock = &radeon_legacy_get_engine_clock,
592 		.set_engine_clock = &radeon_legacy_set_engine_clock,
593 		.get_memory_clock = &radeon_legacy_get_memory_clock,
594 		.set_memory_clock = NULL,
595 		.get_pcie_lanes = NULL,
596 		.set_pcie_lanes = NULL,
597 		.set_clock_gating = &radeon_legacy_set_clock_gating,
598 	},
599 	.pflip = {
600 		.pre_page_flip = &r100_pre_page_flip,
601 		.page_flip = &r100_page_flip,
602 		.post_page_flip = &r100_post_page_flip,
603 	},
604 };
605 
606 static struct radeon_asic rs600_asic = {
607 	.init = &rs600_init,
608 	.fini = &rs600_fini,
609 	.suspend = &rs600_suspend,
610 	.resume = &rs600_resume,
611 	.vga_set_state = &r100_vga_set_state,
612 	.asic_reset = &rs600_asic_reset,
613 	.ioctl_wait_idle = NULL,
614 	.gui_idle = &r100_gui_idle,
615 	.mc_wait_for_idle = &rs600_mc_wait_for_idle,
616 	.gart = {
617 		.tlb_flush = &rs600_gart_tlb_flush,
618 		.set_page = &rs600_gart_set_page,
619 	},
620 	.ring = {
621 		[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
622 	},
623 	.irq = {
624 		.set = &rs600_irq_set,
625 		.process = &rs600_irq_process,
626 	},
627 	.display = {
628 		.bandwidth_update = &rs600_bandwidth_update,
629 		.get_vblank_counter = &rs600_get_vblank_counter,
630 		.wait_for_vblank = &avivo_wait_for_vblank,
631 		.set_backlight_level = &atombios_set_backlight_level,
632 		.get_backlight_level = &atombios_get_backlight_level,
633 		.hdmi_enable = &r600_hdmi_enable,
634 		.hdmi_setmode = &r600_hdmi_setmode,
635 	},
636 	.copy = {
637 		.blit = &r100_copy_blit,
638 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
639 		.dma = &r200_copy_dma,
640 		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
641 		.copy = &r100_copy_blit,
642 		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
643 	},
644 	.surface = {
645 		.set_reg = r100_set_surface_reg,
646 		.clear_reg = r100_clear_surface_reg,
647 	},
648 	.hpd = {
649 		.init = &rs600_hpd_init,
650 		.fini = &rs600_hpd_fini,
651 		.sense = &rs600_hpd_sense,
652 		.set_polarity = &rs600_hpd_set_polarity,
653 	},
654 	.pm = {
655 		.misc = &rs600_pm_misc,
656 		.prepare = &rs600_pm_prepare,
657 		.finish = &rs600_pm_finish,
658 		.init_profile = &r420_pm_init_profile,
659 		.get_dynpm_state = &r100_pm_get_dynpm_state,
660 		.get_engine_clock = &radeon_atom_get_engine_clock,
661 		.set_engine_clock = &radeon_atom_set_engine_clock,
662 		.get_memory_clock = &radeon_atom_get_memory_clock,
663 		.set_memory_clock = &radeon_atom_set_memory_clock,
664 		.get_pcie_lanes = NULL,
665 		.set_pcie_lanes = NULL,
666 		.set_clock_gating = &radeon_atom_set_clock_gating,
667 	},
668 	.pflip = {
669 		.pre_page_flip = &rs600_pre_page_flip,
670 		.page_flip = &rs600_page_flip,
671 		.post_page_flip = &rs600_post_page_flip,
672 	},
673 };
674 
675 static struct radeon_asic rs690_asic = {
676 	.init = &rs690_init,
677 	.fini = &rs690_fini,
678 	.suspend = &rs690_suspend,
679 	.resume = &rs690_resume,
680 	.vga_set_state = &r100_vga_set_state,
681 	.asic_reset = &rs600_asic_reset,
682 	.ioctl_wait_idle = NULL,
683 	.gui_idle = &r100_gui_idle,
684 	.mc_wait_for_idle = &rs690_mc_wait_for_idle,
685 	.gart = {
686 		.tlb_flush = &rs400_gart_tlb_flush,
687 		.set_page = &rs400_gart_set_page,
688 	},
689 	.ring = {
690 		[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
691 	},
692 	.irq = {
693 		.set = &rs600_irq_set,
694 		.process = &rs600_irq_process,
695 	},
696 	.display = {
697 		.get_vblank_counter = &rs600_get_vblank_counter,
698 		.bandwidth_update = &rs690_bandwidth_update,
699 		.wait_for_vblank = &avivo_wait_for_vblank,
700 		.set_backlight_level = &atombios_set_backlight_level,
701 		.get_backlight_level = &atombios_get_backlight_level,
702 		.hdmi_enable = &r600_hdmi_enable,
703 		.hdmi_setmode = &r600_hdmi_setmode,
704 	},
705 	.copy = {
706 		.blit = &r100_copy_blit,
707 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
708 		.dma = &r200_copy_dma,
709 		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
710 		.copy = &r200_copy_dma,
711 		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
712 	},
713 	.surface = {
714 		.set_reg = r100_set_surface_reg,
715 		.clear_reg = r100_clear_surface_reg,
716 	},
717 	.hpd = {
718 		.init = &rs600_hpd_init,
719 		.fini = &rs600_hpd_fini,
720 		.sense = &rs600_hpd_sense,
721 		.set_polarity = &rs600_hpd_set_polarity,
722 	},
723 	.pm = {
724 		.misc = &rs600_pm_misc,
725 		.prepare = &rs600_pm_prepare,
726 		.finish = &rs600_pm_finish,
727 		.init_profile = &r420_pm_init_profile,
728 		.get_dynpm_state = &r100_pm_get_dynpm_state,
729 		.get_engine_clock = &radeon_atom_get_engine_clock,
730 		.set_engine_clock = &radeon_atom_set_engine_clock,
731 		.get_memory_clock = &radeon_atom_get_memory_clock,
732 		.set_memory_clock = &radeon_atom_set_memory_clock,
733 		.get_pcie_lanes = NULL,
734 		.set_pcie_lanes = NULL,
735 		.set_clock_gating = &radeon_atom_set_clock_gating,
736 	},
737 	.pflip = {
738 		.pre_page_flip = &rs600_pre_page_flip,
739 		.page_flip = &rs600_page_flip,
740 		.post_page_flip = &rs600_post_page_flip,
741 	},
742 };
743 
744 static struct radeon_asic rv515_asic = {
745 	.init = &rv515_init,
746 	.fini = &rv515_fini,
747 	.suspend = &rv515_suspend,
748 	.resume = &rv515_resume,
749 	.vga_set_state = &r100_vga_set_state,
750 	.asic_reset = &rs600_asic_reset,
751 	.ioctl_wait_idle = NULL,
752 	.gui_idle = &r100_gui_idle,
753 	.mc_wait_for_idle = &rv515_mc_wait_for_idle,
754 	.gart = {
755 		.tlb_flush = &rv370_pcie_gart_tlb_flush,
756 		.set_page = &rv370_pcie_gart_set_page,
757 	},
758 	.ring = {
759 		[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
760 	},
761 	.irq = {
762 		.set = &rs600_irq_set,
763 		.process = &rs600_irq_process,
764 	},
765 	.display = {
766 		.get_vblank_counter = &rs600_get_vblank_counter,
767 		.bandwidth_update = &rv515_bandwidth_update,
768 		.wait_for_vblank = &avivo_wait_for_vblank,
769 		.set_backlight_level = &atombios_set_backlight_level,
770 		.get_backlight_level = &atombios_get_backlight_level,
771 	},
772 	.copy = {
773 		.blit = &r100_copy_blit,
774 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
775 		.dma = &r200_copy_dma,
776 		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
777 		.copy = &r100_copy_blit,
778 		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
779 	},
780 	.surface = {
781 		.set_reg = r100_set_surface_reg,
782 		.clear_reg = r100_clear_surface_reg,
783 	},
784 	.hpd = {
785 		.init = &rs600_hpd_init,
786 		.fini = &rs600_hpd_fini,
787 		.sense = &rs600_hpd_sense,
788 		.set_polarity = &rs600_hpd_set_polarity,
789 	},
790 	.pm = {
791 		.misc = &rs600_pm_misc,
792 		.prepare = &rs600_pm_prepare,
793 		.finish = &rs600_pm_finish,
794 		.init_profile = &r420_pm_init_profile,
795 		.get_dynpm_state = &r100_pm_get_dynpm_state,
796 		.get_engine_clock = &radeon_atom_get_engine_clock,
797 		.set_engine_clock = &radeon_atom_set_engine_clock,
798 		.get_memory_clock = &radeon_atom_get_memory_clock,
799 		.set_memory_clock = &radeon_atom_set_memory_clock,
800 		.get_pcie_lanes = &rv370_get_pcie_lanes,
801 		.set_pcie_lanes = &rv370_set_pcie_lanes,
802 		.set_clock_gating = &radeon_atom_set_clock_gating,
803 	},
804 	.pflip = {
805 		.pre_page_flip = &rs600_pre_page_flip,
806 		.page_flip = &rs600_page_flip,
807 		.post_page_flip = &rs600_post_page_flip,
808 	},
809 };
810 
811 static struct radeon_asic r520_asic = {
812 	.init = &r520_init,
813 	.fini = &rv515_fini,
814 	.suspend = &rv515_suspend,
815 	.resume = &r520_resume,
816 	.vga_set_state = &r100_vga_set_state,
817 	.asic_reset = &rs600_asic_reset,
818 	.ioctl_wait_idle = NULL,
819 	.gui_idle = &r100_gui_idle,
820 	.mc_wait_for_idle = &r520_mc_wait_for_idle,
821 	.gart = {
822 		.tlb_flush = &rv370_pcie_gart_tlb_flush,
823 		.set_page = &rv370_pcie_gart_set_page,
824 	},
825 	.ring = {
826 		[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
827 	},
828 	.irq = {
829 		.set = &rs600_irq_set,
830 		.process = &rs600_irq_process,
831 	},
832 	.display = {
833 		.bandwidth_update = &rv515_bandwidth_update,
834 		.get_vblank_counter = &rs600_get_vblank_counter,
835 		.wait_for_vblank = &avivo_wait_for_vblank,
836 		.set_backlight_level = &atombios_set_backlight_level,
837 		.get_backlight_level = &atombios_get_backlight_level,
838 	},
839 	.copy = {
840 		.blit = &r100_copy_blit,
841 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
842 		.dma = &r200_copy_dma,
843 		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
844 		.copy = &r100_copy_blit,
845 		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
846 	},
847 	.surface = {
848 		.set_reg = r100_set_surface_reg,
849 		.clear_reg = r100_clear_surface_reg,
850 	},
851 	.hpd = {
852 		.init = &rs600_hpd_init,
853 		.fini = &rs600_hpd_fini,
854 		.sense = &rs600_hpd_sense,
855 		.set_polarity = &rs600_hpd_set_polarity,
856 	},
857 	.pm = {
858 		.misc = &rs600_pm_misc,
859 		.prepare = &rs600_pm_prepare,
860 		.finish = &rs600_pm_finish,
861 		.init_profile = &r420_pm_init_profile,
862 		.get_dynpm_state = &r100_pm_get_dynpm_state,
863 		.get_engine_clock = &radeon_atom_get_engine_clock,
864 		.set_engine_clock = &radeon_atom_set_engine_clock,
865 		.get_memory_clock = &radeon_atom_get_memory_clock,
866 		.set_memory_clock = &radeon_atom_set_memory_clock,
867 		.get_pcie_lanes = &rv370_get_pcie_lanes,
868 		.set_pcie_lanes = &rv370_set_pcie_lanes,
869 		.set_clock_gating = &radeon_atom_set_clock_gating,
870 	},
871 	.pflip = {
872 		.pre_page_flip = &rs600_pre_page_flip,
873 		.page_flip = &rs600_page_flip,
874 		.post_page_flip = &rs600_post_page_flip,
875 	},
876 };
877 
878 static struct radeon_asic_ring r600_gfx_ring = {
879 	.ib_execute = &r600_ring_ib_execute,
880 	.emit_fence = &r600_fence_ring_emit,
881 	.emit_semaphore = &r600_semaphore_ring_emit,
882 	.cs_parse = &r600_cs_parse,
883 	.ring_test = &r600_ring_test,
884 	.ib_test = &r600_ib_test,
885 	.is_lockup = &r600_gfx_is_lockup,
886 	.get_rptr = &radeon_ring_generic_get_rptr,
887 	.get_wptr = &radeon_ring_generic_get_wptr,
888 	.set_wptr = &radeon_ring_generic_set_wptr,
889 };
890 
891 static struct radeon_asic_ring r600_dma_ring = {
892 	.ib_execute = &r600_dma_ring_ib_execute,
893 	.emit_fence = &r600_dma_fence_ring_emit,
894 	.emit_semaphore = &r600_dma_semaphore_ring_emit,
895 	.cs_parse = &r600_dma_cs_parse,
896 	.ring_test = &r600_dma_ring_test,
897 	.ib_test = &r600_dma_ib_test,
898 	.is_lockup = &r600_dma_is_lockup,
899 	.get_rptr = &r600_dma_get_rptr,
900 	.get_wptr = &r600_dma_get_wptr,
901 	.set_wptr = &r600_dma_set_wptr,
902 };
903 
904 static struct radeon_asic r600_asic = {
905 	.init = &r600_init,
906 	.fini = &r600_fini,
907 	.suspend = &r600_suspend,
908 	.resume = &r600_resume,
909 	.vga_set_state = &r600_vga_set_state,
910 	.asic_reset = &r600_asic_reset,
911 	.ioctl_wait_idle = r600_ioctl_wait_idle,
912 	.gui_idle = &r600_gui_idle,
913 	.mc_wait_for_idle = &r600_mc_wait_for_idle,
914 	.get_xclk = &r600_get_xclk,
915 	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
916 	.gart = {
917 		.tlb_flush = &r600_pcie_gart_tlb_flush,
918 		.set_page = &rs600_gart_set_page,
919 	},
920 	.ring = {
921 		[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
922 		[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
923 	},
924 	.irq = {
925 		.set = &r600_irq_set,
926 		.process = &r600_irq_process,
927 	},
928 	.display = {
929 		.bandwidth_update = &rv515_bandwidth_update,
930 		.get_vblank_counter = &rs600_get_vblank_counter,
931 		.wait_for_vblank = &avivo_wait_for_vblank,
932 		.set_backlight_level = &atombios_set_backlight_level,
933 		.get_backlight_level = &atombios_get_backlight_level,
934 		.hdmi_enable = &r600_hdmi_enable,
935 		.hdmi_setmode = &r600_hdmi_setmode,
936 	},
937 	.copy = {
938 		.blit = &r600_copy_cpdma,
939 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
940 		.dma = &r600_copy_dma,
941 		.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
942 		.copy = &r600_copy_cpdma,
943 		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
944 	},
945 	.surface = {
946 		.set_reg = r600_set_surface_reg,
947 		.clear_reg = r600_clear_surface_reg,
948 	},
949 	.hpd = {
950 		.init = &r600_hpd_init,
951 		.fini = &r600_hpd_fini,
952 		.sense = &r600_hpd_sense,
953 		.set_polarity = &r600_hpd_set_polarity,
954 	},
955 	.pm = {
956 		.misc = &r600_pm_misc,
957 		.prepare = &rs600_pm_prepare,
958 		.finish = &rs600_pm_finish,
959 		.init_profile = &r600_pm_init_profile,
960 		.get_dynpm_state = &r600_pm_get_dynpm_state,
961 		.get_engine_clock = &radeon_atom_get_engine_clock,
962 		.set_engine_clock = &radeon_atom_set_engine_clock,
963 		.get_memory_clock = &radeon_atom_get_memory_clock,
964 		.set_memory_clock = &radeon_atom_set_memory_clock,
965 		.get_pcie_lanes = &r600_get_pcie_lanes,
966 		.set_pcie_lanes = &r600_set_pcie_lanes,
967 		.set_clock_gating = NULL,
968 		.get_temperature = &rv6xx_get_temp,
969 	},
970 	.pflip = {
971 		.pre_page_flip = &rs600_pre_page_flip,
972 		.page_flip = &rs600_page_flip,
973 		.post_page_flip = &rs600_post_page_flip,
974 	},
975 };
976 
977 static struct radeon_asic rv6xx_asic = {
978 	.init = &r600_init,
979 	.fini = &r600_fini,
980 	.suspend = &r600_suspend,
981 	.resume = &r600_resume,
982 	.vga_set_state = &r600_vga_set_state,
983 	.asic_reset = &r600_asic_reset,
984 	.ioctl_wait_idle = r600_ioctl_wait_idle,
985 	.gui_idle = &r600_gui_idle,
986 	.mc_wait_for_idle = &r600_mc_wait_for_idle,
987 	.get_xclk = &r600_get_xclk,
988 	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
989 	.gart = {
990 		.tlb_flush = &r600_pcie_gart_tlb_flush,
991 		.set_page = &rs600_gart_set_page,
992 	},
993 	.ring = {
994 		[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
995 		[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
996 	},
997 	.irq = {
998 		.set = &r600_irq_set,
999 		.process = &r600_irq_process,
1000 	},
1001 	.display = {
1002 		.bandwidth_update = &rv515_bandwidth_update,
1003 		.get_vblank_counter = &rs600_get_vblank_counter,
1004 		.wait_for_vblank = &avivo_wait_for_vblank,
1005 		.set_backlight_level = &atombios_set_backlight_level,
1006 		.get_backlight_level = &atombios_get_backlight_level,
1007 		.hdmi_enable = &r600_hdmi_enable,
1008 		.hdmi_setmode = &r600_hdmi_setmode,
1009 	},
1010 	.copy = {
1011 		.blit = &r600_copy_cpdma,
1012 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1013 		.dma = &r600_copy_dma,
1014 		.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1015 		.copy = &r600_copy_cpdma,
1016 		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1017 	},
1018 	.surface = {
1019 		.set_reg = r600_set_surface_reg,
1020 		.clear_reg = r600_clear_surface_reg,
1021 	},
1022 	.hpd = {
1023 		.init = &r600_hpd_init,
1024 		.fini = &r600_hpd_fini,
1025 		.sense = &r600_hpd_sense,
1026 		.set_polarity = &r600_hpd_set_polarity,
1027 	},
1028 	.pm = {
1029 		.misc = &r600_pm_misc,
1030 		.prepare = &rs600_pm_prepare,
1031 		.finish = &rs600_pm_finish,
1032 		.init_profile = &r600_pm_init_profile,
1033 		.get_dynpm_state = &r600_pm_get_dynpm_state,
1034 		.get_engine_clock = &radeon_atom_get_engine_clock,
1035 		.set_engine_clock = &radeon_atom_set_engine_clock,
1036 		.get_memory_clock = &radeon_atom_get_memory_clock,
1037 		.set_memory_clock = &radeon_atom_set_memory_clock,
1038 		.get_pcie_lanes = &r600_get_pcie_lanes,
1039 		.set_pcie_lanes = &r600_set_pcie_lanes,
1040 		.set_clock_gating = NULL,
1041 		.get_temperature = &rv6xx_get_temp,
1042 		.set_uvd_clocks = &r600_set_uvd_clocks,
1043 	},
1044 	.dpm = {
1045 		.init = &rv6xx_dpm_init,
1046 		.setup_asic = &rv6xx_setup_asic,
1047 		.enable = &rv6xx_dpm_enable,
1048 		.disable = &rv6xx_dpm_disable,
1049 		.pre_set_power_state = &r600_dpm_pre_set_power_state,
1050 		.set_power_state = &rv6xx_dpm_set_power_state,
1051 		.post_set_power_state = &r600_dpm_post_set_power_state,
1052 		.display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1053 		.fini = &rv6xx_dpm_fini,
1054 		.get_sclk = &rv6xx_dpm_get_sclk,
1055 		.get_mclk = &rv6xx_dpm_get_mclk,
1056 		.print_power_state = &rv6xx_dpm_print_power_state,
1057 		.debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1058 		.force_performance_level = &rv6xx_dpm_force_performance_level,
1059 	},
1060 	.pflip = {
1061 		.pre_page_flip = &rs600_pre_page_flip,
1062 		.page_flip = &rs600_page_flip,
1063 		.post_page_flip = &rs600_post_page_flip,
1064 	},
1065 };
1066 
1067 static struct radeon_asic rs780_asic = {
1068 	.init = &r600_init,
1069 	.fini = &r600_fini,
1070 	.suspend = &r600_suspend,
1071 	.resume = &r600_resume,
1072 	.vga_set_state = &r600_vga_set_state,
1073 	.asic_reset = &r600_asic_reset,
1074 	.ioctl_wait_idle = r600_ioctl_wait_idle,
1075 	.gui_idle = &r600_gui_idle,
1076 	.mc_wait_for_idle = &r600_mc_wait_for_idle,
1077 	.get_xclk = &r600_get_xclk,
1078 	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1079 	.gart = {
1080 		.tlb_flush = &r600_pcie_gart_tlb_flush,
1081 		.set_page = &rs600_gart_set_page,
1082 	},
1083 	.ring = {
1084 		[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1085 		[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1086 	},
1087 	.irq = {
1088 		.set = &r600_irq_set,
1089 		.process = &r600_irq_process,
1090 	},
1091 	.display = {
1092 		.bandwidth_update = &rs690_bandwidth_update,
1093 		.get_vblank_counter = &rs600_get_vblank_counter,
1094 		.wait_for_vblank = &avivo_wait_for_vblank,
1095 		.set_backlight_level = &atombios_set_backlight_level,
1096 		.get_backlight_level = &atombios_get_backlight_level,
1097 		.hdmi_enable = &r600_hdmi_enable,
1098 		.hdmi_setmode = &r600_hdmi_setmode,
1099 	},
1100 	.copy = {
1101 		.blit = &r600_copy_cpdma,
1102 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1103 		.dma = &r600_copy_dma,
1104 		.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1105 		.copy = &r600_copy_cpdma,
1106 		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1107 	},
1108 	.surface = {
1109 		.set_reg = r600_set_surface_reg,
1110 		.clear_reg = r600_clear_surface_reg,
1111 	},
1112 	.hpd = {
1113 		.init = &r600_hpd_init,
1114 		.fini = &r600_hpd_fini,
1115 		.sense = &r600_hpd_sense,
1116 		.set_polarity = &r600_hpd_set_polarity,
1117 	},
1118 	.pm = {
1119 		.misc = &r600_pm_misc,
1120 		.prepare = &rs600_pm_prepare,
1121 		.finish = &rs600_pm_finish,
1122 		.init_profile = &rs780_pm_init_profile,
1123 		.get_dynpm_state = &r600_pm_get_dynpm_state,
1124 		.get_engine_clock = &radeon_atom_get_engine_clock,
1125 		.set_engine_clock = &radeon_atom_set_engine_clock,
1126 		.get_memory_clock = NULL,
1127 		.set_memory_clock = NULL,
1128 		.get_pcie_lanes = NULL,
1129 		.set_pcie_lanes = NULL,
1130 		.set_clock_gating = NULL,
1131 		.get_temperature = &rv6xx_get_temp,
1132 		.set_uvd_clocks = &r600_set_uvd_clocks,
1133 	},
1134 	.dpm = {
1135 		.init = &rs780_dpm_init,
1136 		.setup_asic = &rs780_dpm_setup_asic,
1137 		.enable = &rs780_dpm_enable,
1138 		.disable = &rs780_dpm_disable,
1139 		.pre_set_power_state = &r600_dpm_pre_set_power_state,
1140 		.set_power_state = &rs780_dpm_set_power_state,
1141 		.post_set_power_state = &r600_dpm_post_set_power_state,
1142 		.display_configuration_changed = &rs780_dpm_display_configuration_changed,
1143 		.fini = &rs780_dpm_fini,
1144 		.get_sclk = &rs780_dpm_get_sclk,
1145 		.get_mclk = &rs780_dpm_get_mclk,
1146 		.print_power_state = &rs780_dpm_print_power_state,
1147 		.debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
1148 		.force_performance_level = &rs780_dpm_force_performance_level,
1149 	},
1150 	.pflip = {
1151 		.pre_page_flip = &rs600_pre_page_flip,
1152 		.page_flip = &rs600_page_flip,
1153 		.post_page_flip = &rs600_post_page_flip,
1154 	},
1155 };
1156 
1157 static struct radeon_asic_ring rv770_uvd_ring = {
1158 	.ib_execute = &uvd_v1_0_ib_execute,
1159 	.emit_fence = &uvd_v2_2_fence_emit,
1160 	.emit_semaphore = &uvd_v1_0_semaphore_emit,
1161 	.cs_parse = &radeon_uvd_cs_parse,
1162 	.ring_test = &uvd_v1_0_ring_test,
1163 	.ib_test = &uvd_v1_0_ib_test,
1164 	.is_lockup = &radeon_ring_test_lockup,
1165 	.get_rptr = &uvd_v1_0_get_rptr,
1166 	.get_wptr = &uvd_v1_0_get_wptr,
1167 	.set_wptr = &uvd_v1_0_set_wptr,
1168 };
1169 
1170 static struct radeon_asic rv770_asic = {
1171 	.init = &rv770_init,
1172 	.fini = &rv770_fini,
1173 	.suspend = &rv770_suspend,
1174 	.resume = &rv770_resume,
1175 	.asic_reset = &r600_asic_reset,
1176 	.vga_set_state = &r600_vga_set_state,
1177 	.ioctl_wait_idle = r600_ioctl_wait_idle,
1178 	.gui_idle = &r600_gui_idle,
1179 	.mc_wait_for_idle = &r600_mc_wait_for_idle,
1180 	.get_xclk = &rv770_get_xclk,
1181 	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1182 	.gart = {
1183 		.tlb_flush = &r600_pcie_gart_tlb_flush,
1184 		.set_page = &rs600_gart_set_page,
1185 	},
1186 	.ring = {
1187 		[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1188 		[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1189 		[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1190 	},
1191 	.irq = {
1192 		.set = &r600_irq_set,
1193 		.process = &r600_irq_process,
1194 	},
1195 	.display = {
1196 		.bandwidth_update = &rv515_bandwidth_update,
1197 		.get_vblank_counter = &rs600_get_vblank_counter,
1198 		.wait_for_vblank = &avivo_wait_for_vblank,
1199 		.set_backlight_level = &atombios_set_backlight_level,
1200 		.get_backlight_level = &atombios_get_backlight_level,
1201 		.hdmi_enable = &r600_hdmi_enable,
1202 		.hdmi_setmode = &r600_hdmi_setmode,
1203 	},
1204 	.copy = {
1205 		.blit = &r600_copy_cpdma,
1206 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1207 		.dma = &rv770_copy_dma,
1208 		.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1209 		.copy = &rv770_copy_dma,
1210 		.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1211 	},
1212 	.surface = {
1213 		.set_reg = r600_set_surface_reg,
1214 		.clear_reg = r600_clear_surface_reg,
1215 	},
1216 	.hpd = {
1217 		.init = &r600_hpd_init,
1218 		.fini = &r600_hpd_fini,
1219 		.sense = &r600_hpd_sense,
1220 		.set_polarity = &r600_hpd_set_polarity,
1221 	},
1222 	.pm = {
1223 		.misc = &rv770_pm_misc,
1224 		.prepare = &rs600_pm_prepare,
1225 		.finish = &rs600_pm_finish,
1226 		.init_profile = &r600_pm_init_profile,
1227 		.get_dynpm_state = &r600_pm_get_dynpm_state,
1228 		.get_engine_clock = &radeon_atom_get_engine_clock,
1229 		.set_engine_clock = &radeon_atom_set_engine_clock,
1230 		.get_memory_clock = &radeon_atom_get_memory_clock,
1231 		.set_memory_clock = &radeon_atom_set_memory_clock,
1232 		.get_pcie_lanes = &r600_get_pcie_lanes,
1233 		.set_pcie_lanes = &r600_set_pcie_lanes,
1234 		.set_clock_gating = &radeon_atom_set_clock_gating,
1235 		.set_uvd_clocks = &rv770_set_uvd_clocks,
1236 		.get_temperature = &rv770_get_temp,
1237 	},
1238 	.dpm = {
1239 		.init = &rv770_dpm_init,
1240 		.setup_asic = &rv770_dpm_setup_asic,
1241 		.enable = &rv770_dpm_enable,
1242 		.disable = &rv770_dpm_disable,
1243 		.pre_set_power_state = &r600_dpm_pre_set_power_state,
1244 		.set_power_state = &rv770_dpm_set_power_state,
1245 		.post_set_power_state = &r600_dpm_post_set_power_state,
1246 		.display_configuration_changed = &rv770_dpm_display_configuration_changed,
1247 		.fini = &rv770_dpm_fini,
1248 		.get_sclk = &rv770_dpm_get_sclk,
1249 		.get_mclk = &rv770_dpm_get_mclk,
1250 		.print_power_state = &rv770_dpm_print_power_state,
1251 		.debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1252 		.force_performance_level = &rv770_dpm_force_performance_level,
1253 		.vblank_too_short = &rv770_dpm_vblank_too_short,
1254 	},
1255 	.pflip = {
1256 		.pre_page_flip = &rs600_pre_page_flip,
1257 		.page_flip = &rv770_page_flip,
1258 		.post_page_flip = &rs600_post_page_flip,
1259 	},
1260 };
1261 
1262 static struct radeon_asic_ring evergreen_gfx_ring = {
1263 	.ib_execute = &evergreen_ring_ib_execute,
1264 	.emit_fence = &r600_fence_ring_emit,
1265 	.emit_semaphore = &r600_semaphore_ring_emit,
1266 	.cs_parse = &evergreen_cs_parse,
1267 	.ring_test = &r600_ring_test,
1268 	.ib_test = &r600_ib_test,
1269 	.is_lockup = &evergreen_gfx_is_lockup,
1270 	.get_rptr = &radeon_ring_generic_get_rptr,
1271 	.get_wptr = &radeon_ring_generic_get_wptr,
1272 	.set_wptr = &radeon_ring_generic_set_wptr,
1273 };
1274 
1275 static struct radeon_asic_ring evergreen_dma_ring = {
1276 	.ib_execute = &evergreen_dma_ring_ib_execute,
1277 	.emit_fence = &evergreen_dma_fence_ring_emit,
1278 	.emit_semaphore = &r600_dma_semaphore_ring_emit,
1279 	.cs_parse = &evergreen_dma_cs_parse,
1280 	.ring_test = &r600_dma_ring_test,
1281 	.ib_test = &r600_dma_ib_test,
1282 	.is_lockup = &evergreen_dma_is_lockup,
1283 	.get_rptr = &r600_dma_get_rptr,
1284 	.get_wptr = &r600_dma_get_wptr,
1285 	.set_wptr = &r600_dma_set_wptr,
1286 };
1287 
1288 static struct radeon_asic evergreen_asic = {
1289 	.init = &evergreen_init,
1290 	.fini = &evergreen_fini,
1291 	.suspend = &evergreen_suspend,
1292 	.resume = &evergreen_resume,
1293 	.asic_reset = &evergreen_asic_reset,
1294 	.vga_set_state = &r600_vga_set_state,
1295 	.ioctl_wait_idle = r600_ioctl_wait_idle,
1296 	.gui_idle = &r600_gui_idle,
1297 	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1298 	.get_xclk = &rv770_get_xclk,
1299 	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1300 	.gart = {
1301 		.tlb_flush = &evergreen_pcie_gart_tlb_flush,
1302 		.set_page = &rs600_gart_set_page,
1303 	},
1304 	.ring = {
1305 		[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1306 		[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1307 		[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1308 	},
1309 	.irq = {
1310 		.set = &evergreen_irq_set,
1311 		.process = &evergreen_irq_process,
1312 	},
1313 	.display = {
1314 		.bandwidth_update = &evergreen_bandwidth_update,
1315 		.get_vblank_counter = &evergreen_get_vblank_counter,
1316 		.wait_for_vblank = &dce4_wait_for_vblank,
1317 		.set_backlight_level = &atombios_set_backlight_level,
1318 		.get_backlight_level = &atombios_get_backlight_level,
1319 		.hdmi_enable = &evergreen_hdmi_enable,
1320 		.hdmi_setmode = &evergreen_hdmi_setmode,
1321 	},
1322 	.copy = {
1323 		.blit = &r600_copy_cpdma,
1324 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1325 		.dma = &evergreen_copy_dma,
1326 		.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1327 		.copy = &evergreen_copy_dma,
1328 		.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1329 	},
1330 	.surface = {
1331 		.set_reg = r600_set_surface_reg,
1332 		.clear_reg = r600_clear_surface_reg,
1333 	},
1334 	.hpd = {
1335 		.init = &evergreen_hpd_init,
1336 		.fini = &evergreen_hpd_fini,
1337 		.sense = &evergreen_hpd_sense,
1338 		.set_polarity = &evergreen_hpd_set_polarity,
1339 	},
1340 	.pm = {
1341 		.misc = &evergreen_pm_misc,
1342 		.prepare = &evergreen_pm_prepare,
1343 		.finish = &evergreen_pm_finish,
1344 		.init_profile = &r600_pm_init_profile,
1345 		.get_dynpm_state = &r600_pm_get_dynpm_state,
1346 		.get_engine_clock = &radeon_atom_get_engine_clock,
1347 		.set_engine_clock = &radeon_atom_set_engine_clock,
1348 		.get_memory_clock = &radeon_atom_get_memory_clock,
1349 		.set_memory_clock = &radeon_atom_set_memory_clock,
1350 		.get_pcie_lanes = &r600_get_pcie_lanes,
1351 		.set_pcie_lanes = &r600_set_pcie_lanes,
1352 		.set_clock_gating = NULL,
1353 		.set_uvd_clocks = &evergreen_set_uvd_clocks,
1354 		.get_temperature = &evergreen_get_temp,
1355 	},
1356 	.dpm = {
1357 		.init = &cypress_dpm_init,
1358 		.setup_asic = &cypress_dpm_setup_asic,
1359 		.enable = &cypress_dpm_enable,
1360 		.disable = &cypress_dpm_disable,
1361 		.pre_set_power_state = &r600_dpm_pre_set_power_state,
1362 		.set_power_state = &cypress_dpm_set_power_state,
1363 		.post_set_power_state = &r600_dpm_post_set_power_state,
1364 		.display_configuration_changed = &cypress_dpm_display_configuration_changed,
1365 		.fini = &cypress_dpm_fini,
1366 		.get_sclk = &rv770_dpm_get_sclk,
1367 		.get_mclk = &rv770_dpm_get_mclk,
1368 		.print_power_state = &rv770_dpm_print_power_state,
1369 		.debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1370 		.force_performance_level = &rv770_dpm_force_performance_level,
1371 		.vblank_too_short = &cypress_dpm_vblank_too_short,
1372 	},
1373 	.pflip = {
1374 		.pre_page_flip = &evergreen_pre_page_flip,
1375 		.page_flip = &evergreen_page_flip,
1376 		.post_page_flip = &evergreen_post_page_flip,
1377 	},
1378 };
1379 
1380 static struct radeon_asic sumo_asic = {
1381 	.init = &evergreen_init,
1382 	.fini = &evergreen_fini,
1383 	.suspend = &evergreen_suspend,
1384 	.resume = &evergreen_resume,
1385 	.asic_reset = &evergreen_asic_reset,
1386 	.vga_set_state = &r600_vga_set_state,
1387 	.ioctl_wait_idle = r600_ioctl_wait_idle,
1388 	.gui_idle = &r600_gui_idle,
1389 	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1390 	.get_xclk = &r600_get_xclk,
1391 	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1392 	.gart = {
1393 		.tlb_flush = &evergreen_pcie_gart_tlb_flush,
1394 		.set_page = &rs600_gart_set_page,
1395 	},
1396 	.ring = {
1397 		[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1398 		[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1399 		[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1400 	},
1401 	.irq = {
1402 		.set = &evergreen_irq_set,
1403 		.process = &evergreen_irq_process,
1404 	},
1405 	.display = {
1406 		.bandwidth_update = &evergreen_bandwidth_update,
1407 		.get_vblank_counter = &evergreen_get_vblank_counter,
1408 		.wait_for_vblank = &dce4_wait_for_vblank,
1409 		.set_backlight_level = &atombios_set_backlight_level,
1410 		.get_backlight_level = &atombios_get_backlight_level,
1411 		.hdmi_enable = &evergreen_hdmi_enable,
1412 		.hdmi_setmode = &evergreen_hdmi_setmode,
1413 	},
1414 	.copy = {
1415 		.blit = &r600_copy_cpdma,
1416 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1417 		.dma = &evergreen_copy_dma,
1418 		.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1419 		.copy = &evergreen_copy_dma,
1420 		.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1421 	},
1422 	.surface = {
1423 		.set_reg = r600_set_surface_reg,
1424 		.clear_reg = r600_clear_surface_reg,
1425 	},
1426 	.hpd = {
1427 		.init = &evergreen_hpd_init,
1428 		.fini = &evergreen_hpd_fini,
1429 		.sense = &evergreen_hpd_sense,
1430 		.set_polarity = &evergreen_hpd_set_polarity,
1431 	},
1432 	.pm = {
1433 		.misc = &evergreen_pm_misc,
1434 		.prepare = &evergreen_pm_prepare,
1435 		.finish = &evergreen_pm_finish,
1436 		.init_profile = &sumo_pm_init_profile,
1437 		.get_dynpm_state = &r600_pm_get_dynpm_state,
1438 		.get_engine_clock = &radeon_atom_get_engine_clock,
1439 		.set_engine_clock = &radeon_atom_set_engine_clock,
1440 		.get_memory_clock = NULL,
1441 		.set_memory_clock = NULL,
1442 		.get_pcie_lanes = NULL,
1443 		.set_pcie_lanes = NULL,
1444 		.set_clock_gating = NULL,
1445 		.set_uvd_clocks = &sumo_set_uvd_clocks,
1446 		.get_temperature = &sumo_get_temp,
1447 	},
1448 	.dpm = {
1449 		.init = &sumo_dpm_init,
1450 		.setup_asic = &sumo_dpm_setup_asic,
1451 		.enable = &sumo_dpm_enable,
1452 		.disable = &sumo_dpm_disable,
1453 		.pre_set_power_state = &sumo_dpm_pre_set_power_state,
1454 		.set_power_state = &sumo_dpm_set_power_state,
1455 		.post_set_power_state = &sumo_dpm_post_set_power_state,
1456 		.display_configuration_changed = &sumo_dpm_display_configuration_changed,
1457 		.fini = &sumo_dpm_fini,
1458 		.get_sclk = &sumo_dpm_get_sclk,
1459 		.get_mclk = &sumo_dpm_get_mclk,
1460 		.print_power_state = &sumo_dpm_print_power_state,
1461 		.debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
1462 		.force_performance_level = &sumo_dpm_force_performance_level,
1463 	},
1464 	.pflip = {
1465 		.pre_page_flip = &evergreen_pre_page_flip,
1466 		.page_flip = &evergreen_page_flip,
1467 		.post_page_flip = &evergreen_post_page_flip,
1468 	},
1469 };
1470 
1471 static struct radeon_asic btc_asic = {
1472 	.init = &evergreen_init,
1473 	.fini = &evergreen_fini,
1474 	.suspend = &evergreen_suspend,
1475 	.resume = &evergreen_resume,
1476 	.asic_reset = &evergreen_asic_reset,
1477 	.vga_set_state = &r600_vga_set_state,
1478 	.ioctl_wait_idle = r600_ioctl_wait_idle,
1479 	.gui_idle = &r600_gui_idle,
1480 	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1481 	.get_xclk = &rv770_get_xclk,
1482 	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1483 	.gart = {
1484 		.tlb_flush = &evergreen_pcie_gart_tlb_flush,
1485 		.set_page = &rs600_gart_set_page,
1486 	},
1487 	.ring = {
1488 		[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1489 		[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1490 		[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1491 	},
1492 	.irq = {
1493 		.set = &evergreen_irq_set,
1494 		.process = &evergreen_irq_process,
1495 	},
1496 	.display = {
1497 		.bandwidth_update = &evergreen_bandwidth_update,
1498 		.get_vblank_counter = &evergreen_get_vblank_counter,
1499 		.wait_for_vblank = &dce4_wait_for_vblank,
1500 		.set_backlight_level = &atombios_set_backlight_level,
1501 		.get_backlight_level = &atombios_get_backlight_level,
1502 		.hdmi_enable = &evergreen_hdmi_enable,
1503 		.hdmi_setmode = &evergreen_hdmi_setmode,
1504 	},
1505 	.copy = {
1506 		.blit = &r600_copy_cpdma,
1507 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1508 		.dma = &evergreen_copy_dma,
1509 		.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1510 		.copy = &evergreen_copy_dma,
1511 		.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1512 	},
1513 	.surface = {
1514 		.set_reg = r600_set_surface_reg,
1515 		.clear_reg = r600_clear_surface_reg,
1516 	},
1517 	.hpd = {
1518 		.init = &evergreen_hpd_init,
1519 		.fini = &evergreen_hpd_fini,
1520 		.sense = &evergreen_hpd_sense,
1521 		.set_polarity = &evergreen_hpd_set_polarity,
1522 	},
1523 	.pm = {
1524 		.misc = &evergreen_pm_misc,
1525 		.prepare = &evergreen_pm_prepare,
1526 		.finish = &evergreen_pm_finish,
1527 		.init_profile = &btc_pm_init_profile,
1528 		.get_dynpm_state = &r600_pm_get_dynpm_state,
1529 		.get_engine_clock = &radeon_atom_get_engine_clock,
1530 		.set_engine_clock = &radeon_atom_set_engine_clock,
1531 		.get_memory_clock = &radeon_atom_get_memory_clock,
1532 		.set_memory_clock = &radeon_atom_set_memory_clock,
1533 		.get_pcie_lanes = &r600_get_pcie_lanes,
1534 		.set_pcie_lanes = &r600_set_pcie_lanes,
1535 		.set_clock_gating = NULL,
1536 		.set_uvd_clocks = &evergreen_set_uvd_clocks,
1537 		.get_temperature = &evergreen_get_temp,
1538 	},
1539 	.dpm = {
1540 		.init = &btc_dpm_init,
1541 		.setup_asic = &btc_dpm_setup_asic,
1542 		.enable = &btc_dpm_enable,
1543 		.disable = &btc_dpm_disable,
1544 		.pre_set_power_state = &btc_dpm_pre_set_power_state,
1545 		.set_power_state = &btc_dpm_set_power_state,
1546 		.post_set_power_state = &btc_dpm_post_set_power_state,
1547 		.display_configuration_changed = &cypress_dpm_display_configuration_changed,
1548 		.fini = &btc_dpm_fini,
1549 		.get_sclk = &btc_dpm_get_sclk,
1550 		.get_mclk = &btc_dpm_get_mclk,
1551 		.print_power_state = &rv770_dpm_print_power_state,
1552 		.debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1553 		.force_performance_level = &rv770_dpm_force_performance_level,
1554 		.vblank_too_short = &btc_dpm_vblank_too_short,
1555 	},
1556 	.pflip = {
1557 		.pre_page_flip = &evergreen_pre_page_flip,
1558 		.page_flip = &evergreen_page_flip,
1559 		.post_page_flip = &evergreen_post_page_flip,
1560 	},
1561 };
1562 
1563 static struct radeon_asic_ring cayman_gfx_ring = {
1564 	.ib_execute = &cayman_ring_ib_execute,
1565 	.ib_parse = &evergreen_ib_parse,
1566 	.emit_fence = &cayman_fence_ring_emit,
1567 	.emit_semaphore = &r600_semaphore_ring_emit,
1568 	.cs_parse = &evergreen_cs_parse,
1569 	.ring_test = &r600_ring_test,
1570 	.ib_test = &r600_ib_test,
1571 	.is_lockup = &cayman_gfx_is_lockup,
1572 	.vm_flush = &cayman_vm_flush,
1573 	.get_rptr = &radeon_ring_generic_get_rptr,
1574 	.get_wptr = &radeon_ring_generic_get_wptr,
1575 	.set_wptr = &radeon_ring_generic_set_wptr,
1576 };
1577 
1578 static struct radeon_asic_ring cayman_dma_ring = {
1579 	.ib_execute = &cayman_dma_ring_ib_execute,
1580 	.ib_parse = &evergreen_dma_ib_parse,
1581 	.emit_fence = &evergreen_dma_fence_ring_emit,
1582 	.emit_semaphore = &r600_dma_semaphore_ring_emit,
1583 	.cs_parse = &evergreen_dma_cs_parse,
1584 	.ring_test = &r600_dma_ring_test,
1585 	.ib_test = &r600_dma_ib_test,
1586 	.is_lockup = &cayman_dma_is_lockup,
1587 	.vm_flush = &cayman_dma_vm_flush,
1588 	.get_rptr = &r600_dma_get_rptr,
1589 	.get_wptr = &r600_dma_get_wptr,
1590 	.set_wptr = &r600_dma_set_wptr
1591 };
1592 
1593 static struct radeon_asic_ring cayman_uvd_ring = {
1594 	.ib_execute = &uvd_v1_0_ib_execute,
1595 	.emit_fence = &uvd_v2_2_fence_emit,
1596 	.emit_semaphore = &uvd_v3_1_semaphore_emit,
1597 	.cs_parse = &radeon_uvd_cs_parse,
1598 	.ring_test = &uvd_v1_0_ring_test,
1599 	.ib_test = &uvd_v1_0_ib_test,
1600 	.is_lockup = &radeon_ring_test_lockup,
1601 	.get_rptr = &uvd_v1_0_get_rptr,
1602 	.get_wptr = &uvd_v1_0_get_wptr,
1603 	.set_wptr = &uvd_v1_0_set_wptr,
1604 };
1605 
1606 static struct radeon_asic cayman_asic = {
1607 	.init = &cayman_init,
1608 	.fini = &cayman_fini,
1609 	.suspend = &cayman_suspend,
1610 	.resume = &cayman_resume,
1611 	.asic_reset = &cayman_asic_reset,
1612 	.vga_set_state = &r600_vga_set_state,
1613 	.ioctl_wait_idle = r600_ioctl_wait_idle,
1614 	.gui_idle = &r600_gui_idle,
1615 	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1616 	.get_xclk = &rv770_get_xclk,
1617 	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1618 	.gart = {
1619 		.tlb_flush = &cayman_pcie_gart_tlb_flush,
1620 		.set_page = &rs600_gart_set_page,
1621 	},
1622 	.vm = {
1623 		.init = &cayman_vm_init,
1624 		.fini = &cayman_vm_fini,
1625 		.set_page = &cayman_dma_vm_set_page,
1626 	},
1627 	.ring = {
1628 		[RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1629 		[CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1630 		[CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1631 		[R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1632 		[CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1633 		[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1634 	},
1635 	.irq = {
1636 		.set = &evergreen_irq_set,
1637 		.process = &evergreen_irq_process,
1638 	},
1639 	.display = {
1640 		.bandwidth_update = &evergreen_bandwidth_update,
1641 		.get_vblank_counter = &evergreen_get_vblank_counter,
1642 		.wait_for_vblank = &dce4_wait_for_vblank,
1643 		.set_backlight_level = &atombios_set_backlight_level,
1644 		.get_backlight_level = &atombios_get_backlight_level,
1645 		.hdmi_enable = &evergreen_hdmi_enable,
1646 		.hdmi_setmode = &evergreen_hdmi_setmode,
1647 	},
1648 	.copy = {
1649 		.blit = &r600_copy_cpdma,
1650 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1651 		.dma = &evergreen_copy_dma,
1652 		.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1653 		.copy = &evergreen_copy_dma,
1654 		.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1655 	},
1656 	.surface = {
1657 		.set_reg = r600_set_surface_reg,
1658 		.clear_reg = r600_clear_surface_reg,
1659 	},
1660 	.hpd = {
1661 		.init = &evergreen_hpd_init,
1662 		.fini = &evergreen_hpd_fini,
1663 		.sense = &evergreen_hpd_sense,
1664 		.set_polarity = &evergreen_hpd_set_polarity,
1665 	},
1666 	.pm = {
1667 		.misc = &evergreen_pm_misc,
1668 		.prepare = &evergreen_pm_prepare,
1669 		.finish = &evergreen_pm_finish,
1670 		.init_profile = &btc_pm_init_profile,
1671 		.get_dynpm_state = &r600_pm_get_dynpm_state,
1672 		.get_engine_clock = &radeon_atom_get_engine_clock,
1673 		.set_engine_clock = &radeon_atom_set_engine_clock,
1674 		.get_memory_clock = &radeon_atom_get_memory_clock,
1675 		.set_memory_clock = &radeon_atom_set_memory_clock,
1676 		.get_pcie_lanes = &r600_get_pcie_lanes,
1677 		.set_pcie_lanes = &r600_set_pcie_lanes,
1678 		.set_clock_gating = NULL,
1679 		.set_uvd_clocks = &evergreen_set_uvd_clocks,
1680 		.get_temperature = &evergreen_get_temp,
1681 	},
1682 	.dpm = {
1683 		.init = &ni_dpm_init,
1684 		.setup_asic = &ni_dpm_setup_asic,
1685 		.enable = &ni_dpm_enable,
1686 		.disable = &ni_dpm_disable,
1687 		.pre_set_power_state = &ni_dpm_pre_set_power_state,
1688 		.set_power_state = &ni_dpm_set_power_state,
1689 		.post_set_power_state = &ni_dpm_post_set_power_state,
1690 		.display_configuration_changed = &cypress_dpm_display_configuration_changed,
1691 		.fini = &ni_dpm_fini,
1692 		.get_sclk = &ni_dpm_get_sclk,
1693 		.get_mclk = &ni_dpm_get_mclk,
1694 		.print_power_state = &ni_dpm_print_power_state,
1695 		.debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
1696 		.force_performance_level = &ni_dpm_force_performance_level,
1697 		.vblank_too_short = &ni_dpm_vblank_too_short,
1698 	},
1699 	.pflip = {
1700 		.pre_page_flip = &evergreen_pre_page_flip,
1701 		.page_flip = &evergreen_page_flip,
1702 		.post_page_flip = &evergreen_post_page_flip,
1703 	},
1704 };
1705 
1706 static struct radeon_asic trinity_asic = {
1707 	.init = &cayman_init,
1708 	.fini = &cayman_fini,
1709 	.suspend = &cayman_suspend,
1710 	.resume = &cayman_resume,
1711 	.asic_reset = &cayman_asic_reset,
1712 	.vga_set_state = &r600_vga_set_state,
1713 	.ioctl_wait_idle = r600_ioctl_wait_idle,
1714 	.gui_idle = &r600_gui_idle,
1715 	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1716 	.get_xclk = &r600_get_xclk,
1717 	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1718 	.gart = {
1719 		.tlb_flush = &cayman_pcie_gart_tlb_flush,
1720 		.set_page = &rs600_gart_set_page,
1721 	},
1722 	.vm = {
1723 		.init = &cayman_vm_init,
1724 		.fini = &cayman_vm_fini,
1725 		.set_page = &cayman_dma_vm_set_page,
1726 	},
1727 	.ring = {
1728 		[RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1729 		[CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1730 		[CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1731 		[R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1732 		[CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1733 		[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1734 	},
1735 	.irq = {
1736 		.set = &evergreen_irq_set,
1737 		.process = &evergreen_irq_process,
1738 	},
1739 	.display = {
1740 		.bandwidth_update = &dce6_bandwidth_update,
1741 		.get_vblank_counter = &evergreen_get_vblank_counter,
1742 		.wait_for_vblank = &dce4_wait_for_vblank,
1743 		.set_backlight_level = &atombios_set_backlight_level,
1744 		.get_backlight_level = &atombios_get_backlight_level,
1745 		.hdmi_enable = &evergreen_hdmi_enable,
1746 		.hdmi_setmode = &evergreen_hdmi_setmode,
1747 	},
1748 	.copy = {
1749 		.blit = &r600_copy_cpdma,
1750 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1751 		.dma = &evergreen_copy_dma,
1752 		.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1753 		.copy = &evergreen_copy_dma,
1754 		.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1755 	},
1756 	.surface = {
1757 		.set_reg = r600_set_surface_reg,
1758 		.clear_reg = r600_clear_surface_reg,
1759 	},
1760 	.hpd = {
1761 		.init = &evergreen_hpd_init,
1762 		.fini = &evergreen_hpd_fini,
1763 		.sense = &evergreen_hpd_sense,
1764 		.set_polarity = &evergreen_hpd_set_polarity,
1765 	},
1766 	.pm = {
1767 		.misc = &evergreen_pm_misc,
1768 		.prepare = &evergreen_pm_prepare,
1769 		.finish = &evergreen_pm_finish,
1770 		.init_profile = &sumo_pm_init_profile,
1771 		.get_dynpm_state = &r600_pm_get_dynpm_state,
1772 		.get_engine_clock = &radeon_atom_get_engine_clock,
1773 		.set_engine_clock = &radeon_atom_set_engine_clock,
1774 		.get_memory_clock = NULL,
1775 		.set_memory_clock = NULL,
1776 		.get_pcie_lanes = NULL,
1777 		.set_pcie_lanes = NULL,
1778 		.set_clock_gating = NULL,
1779 		.set_uvd_clocks = &sumo_set_uvd_clocks,
1780 		.get_temperature = &tn_get_temp,
1781 	},
1782 	.dpm = {
1783 		.init = &trinity_dpm_init,
1784 		.setup_asic = &trinity_dpm_setup_asic,
1785 		.enable = &trinity_dpm_enable,
1786 		.disable = &trinity_dpm_disable,
1787 		.pre_set_power_state = &trinity_dpm_pre_set_power_state,
1788 		.set_power_state = &trinity_dpm_set_power_state,
1789 		.post_set_power_state = &trinity_dpm_post_set_power_state,
1790 		.display_configuration_changed = &trinity_dpm_display_configuration_changed,
1791 		.fini = &trinity_dpm_fini,
1792 		.get_sclk = &trinity_dpm_get_sclk,
1793 		.get_mclk = &trinity_dpm_get_mclk,
1794 		.print_power_state = &trinity_dpm_print_power_state,
1795 		.debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
1796 		.force_performance_level = &trinity_dpm_force_performance_level,
1797 		.enable_bapm = &trinity_dpm_enable_bapm,
1798 	},
1799 	.pflip = {
1800 		.pre_page_flip = &evergreen_pre_page_flip,
1801 		.page_flip = &evergreen_page_flip,
1802 		.post_page_flip = &evergreen_post_page_flip,
1803 	},
1804 };
1805 
1806 static struct radeon_asic_ring si_gfx_ring = {
1807 	.ib_execute = &si_ring_ib_execute,
1808 	.ib_parse = &si_ib_parse,
1809 	.emit_fence = &si_fence_ring_emit,
1810 	.emit_semaphore = &r600_semaphore_ring_emit,
1811 	.cs_parse = NULL,
1812 	.ring_test = &r600_ring_test,
1813 	.ib_test = &r600_ib_test,
1814 	.is_lockup = &si_gfx_is_lockup,
1815 	.vm_flush = &si_vm_flush,
1816 	.get_rptr = &radeon_ring_generic_get_rptr,
1817 	.get_wptr = &radeon_ring_generic_get_wptr,
1818 	.set_wptr = &radeon_ring_generic_set_wptr,
1819 };
1820 
1821 static struct radeon_asic_ring si_dma_ring = {
1822 	.ib_execute = &cayman_dma_ring_ib_execute,
1823 	.ib_parse = &evergreen_dma_ib_parse,
1824 	.emit_fence = &evergreen_dma_fence_ring_emit,
1825 	.emit_semaphore = &r600_dma_semaphore_ring_emit,
1826 	.cs_parse = NULL,
1827 	.ring_test = &r600_dma_ring_test,
1828 	.ib_test = &r600_dma_ib_test,
1829 	.is_lockup = &si_dma_is_lockup,
1830 	.vm_flush = &si_dma_vm_flush,
1831 	.get_rptr = &r600_dma_get_rptr,
1832 	.get_wptr = &r600_dma_get_wptr,
1833 	.set_wptr = &r600_dma_set_wptr,
1834 };
1835 
1836 static struct radeon_asic si_asic = {
1837 	.init = &si_init,
1838 	.fini = &si_fini,
1839 	.suspend = &si_suspend,
1840 	.resume = &si_resume,
1841 	.asic_reset = &si_asic_reset,
1842 	.vga_set_state = &r600_vga_set_state,
1843 	.ioctl_wait_idle = r600_ioctl_wait_idle,
1844 	.gui_idle = &r600_gui_idle,
1845 	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1846 	.get_xclk = &si_get_xclk,
1847 	.get_gpu_clock_counter = &si_get_gpu_clock_counter,
1848 	.gart = {
1849 		.tlb_flush = &si_pcie_gart_tlb_flush,
1850 		.set_page = &rs600_gart_set_page,
1851 	},
1852 	.vm = {
1853 		.init = &si_vm_init,
1854 		.fini = &si_vm_fini,
1855 		.set_page = &si_dma_vm_set_page,
1856 	},
1857 	.ring = {
1858 		[RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1859 		[CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1860 		[CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1861 		[R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1862 		[CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1863 		[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1864 	},
1865 	.irq = {
1866 		.set = &si_irq_set,
1867 		.process = &si_irq_process,
1868 	},
1869 	.display = {
1870 		.bandwidth_update = &dce6_bandwidth_update,
1871 		.get_vblank_counter = &evergreen_get_vblank_counter,
1872 		.wait_for_vblank = &dce4_wait_for_vblank,
1873 		.set_backlight_level = &atombios_set_backlight_level,
1874 		.get_backlight_level = &atombios_get_backlight_level,
1875 		.hdmi_enable = &evergreen_hdmi_enable,
1876 		.hdmi_setmode = &evergreen_hdmi_setmode,
1877 	},
1878 	.copy = {
1879 		.blit = &r600_copy_cpdma,
1880 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1881 		.dma = &si_copy_dma,
1882 		.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1883 		.copy = &si_copy_dma,
1884 		.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1885 	},
1886 	.surface = {
1887 		.set_reg = r600_set_surface_reg,
1888 		.clear_reg = r600_clear_surface_reg,
1889 	},
1890 	.hpd = {
1891 		.init = &evergreen_hpd_init,
1892 		.fini = &evergreen_hpd_fini,
1893 		.sense = &evergreen_hpd_sense,
1894 		.set_polarity = &evergreen_hpd_set_polarity,
1895 	},
1896 	.pm = {
1897 		.misc = &evergreen_pm_misc,
1898 		.prepare = &evergreen_pm_prepare,
1899 		.finish = &evergreen_pm_finish,
1900 		.init_profile = &sumo_pm_init_profile,
1901 		.get_dynpm_state = &r600_pm_get_dynpm_state,
1902 		.get_engine_clock = &radeon_atom_get_engine_clock,
1903 		.set_engine_clock = &radeon_atom_set_engine_clock,
1904 		.get_memory_clock = &radeon_atom_get_memory_clock,
1905 		.set_memory_clock = &radeon_atom_set_memory_clock,
1906 		.get_pcie_lanes = &r600_get_pcie_lanes,
1907 		.set_pcie_lanes = &r600_set_pcie_lanes,
1908 		.set_clock_gating = NULL,
1909 		.set_uvd_clocks = &si_set_uvd_clocks,
1910 		.get_temperature = &si_get_temp,
1911 	},
1912 	.dpm = {
1913 		.init = &si_dpm_init,
1914 		.setup_asic = &si_dpm_setup_asic,
1915 		.enable = &si_dpm_enable,
1916 		.disable = &si_dpm_disable,
1917 		.pre_set_power_state = &si_dpm_pre_set_power_state,
1918 		.set_power_state = &si_dpm_set_power_state,
1919 		.post_set_power_state = &si_dpm_post_set_power_state,
1920 		.display_configuration_changed = &si_dpm_display_configuration_changed,
1921 		.fini = &si_dpm_fini,
1922 		.get_sclk = &ni_dpm_get_sclk,
1923 		.get_mclk = &ni_dpm_get_mclk,
1924 		.print_power_state = &ni_dpm_print_power_state,
1925 		.debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
1926 		.force_performance_level = &si_dpm_force_performance_level,
1927 		.vblank_too_short = &ni_dpm_vblank_too_short,
1928 	},
1929 	.pflip = {
1930 		.pre_page_flip = &evergreen_pre_page_flip,
1931 		.page_flip = &evergreen_page_flip,
1932 		.post_page_flip = &evergreen_post_page_flip,
1933 	},
1934 };
1935 
1936 static struct radeon_asic_ring ci_gfx_ring = {
1937 	.ib_execute = &cik_ring_ib_execute,
1938 	.ib_parse = &cik_ib_parse,
1939 	.emit_fence = &cik_fence_gfx_ring_emit,
1940 	.emit_semaphore = &cik_semaphore_ring_emit,
1941 	.cs_parse = NULL,
1942 	.ring_test = &cik_ring_test,
1943 	.ib_test = &cik_ib_test,
1944 	.is_lockup = &cik_gfx_is_lockup,
1945 	.vm_flush = &cik_vm_flush,
1946 	.get_rptr = &radeon_ring_generic_get_rptr,
1947 	.get_wptr = &radeon_ring_generic_get_wptr,
1948 	.set_wptr = &radeon_ring_generic_set_wptr,
1949 };
1950 
1951 static struct radeon_asic_ring ci_cp_ring = {
1952 	.ib_execute = &cik_ring_ib_execute,
1953 	.ib_parse = &cik_ib_parse,
1954 	.emit_fence = &cik_fence_compute_ring_emit,
1955 	.emit_semaphore = &cik_semaphore_ring_emit,
1956 	.cs_parse = NULL,
1957 	.ring_test = &cik_ring_test,
1958 	.ib_test = &cik_ib_test,
1959 	.is_lockup = &cik_gfx_is_lockup,
1960 	.vm_flush = &cik_vm_flush,
1961 	.get_rptr = &cik_compute_ring_get_rptr,
1962 	.get_wptr = &cik_compute_ring_get_wptr,
1963 	.set_wptr = &cik_compute_ring_set_wptr,
1964 };
1965 
1966 static struct radeon_asic_ring ci_dma_ring = {
1967 	.ib_execute = &cik_sdma_ring_ib_execute,
1968 	.ib_parse = &cik_ib_parse,
1969 	.emit_fence = &cik_sdma_fence_ring_emit,
1970 	.emit_semaphore = &cik_sdma_semaphore_ring_emit,
1971 	.cs_parse = NULL,
1972 	.ring_test = &cik_sdma_ring_test,
1973 	.ib_test = &cik_sdma_ib_test,
1974 	.is_lockup = &cik_sdma_is_lockup,
1975 	.vm_flush = &cik_dma_vm_flush,
1976 	.get_rptr = &r600_dma_get_rptr,
1977 	.get_wptr = &r600_dma_get_wptr,
1978 	.set_wptr = &r600_dma_set_wptr,
1979 };
1980 
1981 static struct radeon_asic ci_asic = {
1982 	.init = &cik_init,
1983 	.fini = &cik_fini,
1984 	.suspend = &cik_suspend,
1985 	.resume = &cik_resume,
1986 	.asic_reset = &cik_asic_reset,
1987 	.vga_set_state = &r600_vga_set_state,
1988 	.ioctl_wait_idle = NULL,
1989 	.gui_idle = &r600_gui_idle,
1990 	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1991 	.get_xclk = &cik_get_xclk,
1992 	.get_gpu_clock_counter = &cik_get_gpu_clock_counter,
1993 	.gart = {
1994 		.tlb_flush = &cik_pcie_gart_tlb_flush,
1995 		.set_page = &rs600_gart_set_page,
1996 	},
1997 	.vm = {
1998 		.init = &cik_vm_init,
1999 		.fini = &cik_vm_fini,
2000 		.set_page = &cik_sdma_vm_set_page,
2001 	},
2002 	.ring = {
2003 		[RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2004 		[CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2005 		[CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2006 		[R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2007 		[CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2008 		[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2009 	},
2010 	.irq = {
2011 		.set = &cik_irq_set,
2012 		.process = &cik_irq_process,
2013 	},
2014 	.display = {
2015 		.bandwidth_update = &dce8_bandwidth_update,
2016 		.get_vblank_counter = &evergreen_get_vblank_counter,
2017 		.wait_for_vblank = &dce4_wait_for_vblank,
2018 		.set_backlight_level = &atombios_set_backlight_level,
2019 		.get_backlight_level = &atombios_get_backlight_level,
2020 		.hdmi_enable = &evergreen_hdmi_enable,
2021 		.hdmi_setmode = &evergreen_hdmi_setmode,
2022 	},
2023 	.copy = {
2024 		.blit = &cik_copy_cpdma,
2025 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2026 		.dma = &cik_copy_dma,
2027 		.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2028 		.copy = &cik_copy_dma,
2029 		.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2030 	},
2031 	.surface = {
2032 		.set_reg = r600_set_surface_reg,
2033 		.clear_reg = r600_clear_surface_reg,
2034 	},
2035 	.hpd = {
2036 		.init = &evergreen_hpd_init,
2037 		.fini = &evergreen_hpd_fini,
2038 		.sense = &evergreen_hpd_sense,
2039 		.set_polarity = &evergreen_hpd_set_polarity,
2040 	},
2041 	.pm = {
2042 		.misc = &evergreen_pm_misc,
2043 		.prepare = &evergreen_pm_prepare,
2044 		.finish = &evergreen_pm_finish,
2045 		.init_profile = &sumo_pm_init_profile,
2046 		.get_dynpm_state = &r600_pm_get_dynpm_state,
2047 		.get_engine_clock = &radeon_atom_get_engine_clock,
2048 		.set_engine_clock = &radeon_atom_set_engine_clock,
2049 		.get_memory_clock = &radeon_atom_get_memory_clock,
2050 		.set_memory_clock = &radeon_atom_set_memory_clock,
2051 		.get_pcie_lanes = NULL,
2052 		.set_pcie_lanes = NULL,
2053 		.set_clock_gating = NULL,
2054 		.set_uvd_clocks = &cik_set_uvd_clocks,
2055 		.get_temperature = &ci_get_temp,
2056 	},
2057 	.dpm = {
2058 		.init = &ci_dpm_init,
2059 		.setup_asic = &ci_dpm_setup_asic,
2060 		.enable = &ci_dpm_enable,
2061 		.disable = &ci_dpm_disable,
2062 		.pre_set_power_state = &ci_dpm_pre_set_power_state,
2063 		.set_power_state = &ci_dpm_set_power_state,
2064 		.post_set_power_state = &ci_dpm_post_set_power_state,
2065 		.display_configuration_changed = &ci_dpm_display_configuration_changed,
2066 		.fini = &ci_dpm_fini,
2067 		.get_sclk = &ci_dpm_get_sclk,
2068 		.get_mclk = &ci_dpm_get_mclk,
2069 		.print_power_state = &ci_dpm_print_power_state,
2070 		.debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
2071 		.force_performance_level = &ci_dpm_force_performance_level,
2072 		.vblank_too_short = &ci_dpm_vblank_too_short,
2073 		.powergate_uvd = &ci_dpm_powergate_uvd,
2074 	},
2075 	.pflip = {
2076 		.pre_page_flip = &evergreen_pre_page_flip,
2077 		.page_flip = &evergreen_page_flip,
2078 		.post_page_flip = &evergreen_post_page_flip,
2079 	},
2080 };
2081 
2082 static struct radeon_asic kv_asic = {
2083 	.init = &cik_init,
2084 	.fini = &cik_fini,
2085 	.suspend = &cik_suspend,
2086 	.resume = &cik_resume,
2087 	.asic_reset = &cik_asic_reset,
2088 	.vga_set_state = &r600_vga_set_state,
2089 	.ioctl_wait_idle = NULL,
2090 	.gui_idle = &r600_gui_idle,
2091 	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2092 	.get_xclk = &cik_get_xclk,
2093 	.get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2094 	.gart = {
2095 		.tlb_flush = &cik_pcie_gart_tlb_flush,
2096 		.set_page = &rs600_gart_set_page,
2097 	},
2098 	.vm = {
2099 		.init = &cik_vm_init,
2100 		.fini = &cik_vm_fini,
2101 		.set_page = &cik_sdma_vm_set_page,
2102 	},
2103 	.ring = {
2104 		[RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2105 		[CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2106 		[CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2107 		[R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2108 		[CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2109 		[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2110 	},
2111 	.irq = {
2112 		.set = &cik_irq_set,
2113 		.process = &cik_irq_process,
2114 	},
2115 	.display = {
2116 		.bandwidth_update = &dce8_bandwidth_update,
2117 		.get_vblank_counter = &evergreen_get_vblank_counter,
2118 		.wait_for_vblank = &dce4_wait_for_vblank,
2119 		.set_backlight_level = &atombios_set_backlight_level,
2120 		.get_backlight_level = &atombios_get_backlight_level,
2121 		.hdmi_enable = &evergreen_hdmi_enable,
2122 		.hdmi_setmode = &evergreen_hdmi_setmode,
2123 	},
2124 	.copy = {
2125 		.blit = &cik_copy_cpdma,
2126 		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2127 		.dma = &cik_copy_dma,
2128 		.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2129 		.copy = &cik_copy_dma,
2130 		.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2131 	},
2132 	.surface = {
2133 		.set_reg = r600_set_surface_reg,
2134 		.clear_reg = r600_clear_surface_reg,
2135 	},
2136 	.hpd = {
2137 		.init = &evergreen_hpd_init,
2138 		.fini = &evergreen_hpd_fini,
2139 		.sense = &evergreen_hpd_sense,
2140 		.set_polarity = &evergreen_hpd_set_polarity,
2141 	},
2142 	.pm = {
2143 		.misc = &evergreen_pm_misc,
2144 		.prepare = &evergreen_pm_prepare,
2145 		.finish = &evergreen_pm_finish,
2146 		.init_profile = &sumo_pm_init_profile,
2147 		.get_dynpm_state = &r600_pm_get_dynpm_state,
2148 		.get_engine_clock = &radeon_atom_get_engine_clock,
2149 		.set_engine_clock = &radeon_atom_set_engine_clock,
2150 		.get_memory_clock = &radeon_atom_get_memory_clock,
2151 		.set_memory_clock = &radeon_atom_set_memory_clock,
2152 		.get_pcie_lanes = NULL,
2153 		.set_pcie_lanes = NULL,
2154 		.set_clock_gating = NULL,
2155 		.set_uvd_clocks = &cik_set_uvd_clocks,
2156 		.get_temperature = &kv_get_temp,
2157 	},
2158 	.dpm = {
2159 		.init = &kv_dpm_init,
2160 		.setup_asic = &kv_dpm_setup_asic,
2161 		.enable = &kv_dpm_enable,
2162 		.disable = &kv_dpm_disable,
2163 		.pre_set_power_state = &kv_dpm_pre_set_power_state,
2164 		.set_power_state = &kv_dpm_set_power_state,
2165 		.post_set_power_state = &kv_dpm_post_set_power_state,
2166 		.display_configuration_changed = &kv_dpm_display_configuration_changed,
2167 		.fini = &kv_dpm_fini,
2168 		.get_sclk = &kv_dpm_get_sclk,
2169 		.get_mclk = &kv_dpm_get_mclk,
2170 		.print_power_state = &kv_dpm_print_power_state,
2171 		.debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2172 		.force_performance_level = &kv_dpm_force_performance_level,
2173 		.powergate_uvd = &kv_dpm_powergate_uvd,
2174 		.enable_bapm = &kv_dpm_enable_bapm,
2175 	},
2176 	.pflip = {
2177 		.pre_page_flip = &evergreen_pre_page_flip,
2178 		.page_flip = &evergreen_page_flip,
2179 		.post_page_flip = &evergreen_post_page_flip,
2180 	},
2181 };
2182 
2183 /**
2184  * radeon_asic_init - register asic specific callbacks
2185  *
2186  * @rdev: radeon device pointer
2187  *
2188  * Registers the appropriate asic specific callbacks for each
2189  * chip family.  Also sets other asics specific info like the number
2190  * of crtcs and the register aperture accessors (all asics).
2191  * Returns 0 for success.
2192  */
2193 int radeon_asic_init(struct radeon_device *rdev)
2194 {
2195 	radeon_register_accessor_init(rdev);
2196 
2197 	/* set the number of crtcs */
2198 	if (rdev->flags & RADEON_SINGLE_CRTC)
2199 		rdev->num_crtc = 1;
2200 	else
2201 		rdev->num_crtc = 2;
2202 
2203 	rdev->has_uvd = false;
2204 
2205 	switch (rdev->family) {
2206 	case CHIP_R100:
2207 	case CHIP_RV100:
2208 	case CHIP_RS100:
2209 	case CHIP_RV200:
2210 	case CHIP_RS200:
2211 		rdev->asic = &r100_asic;
2212 		break;
2213 	case CHIP_R200:
2214 	case CHIP_RV250:
2215 	case CHIP_RS300:
2216 	case CHIP_RV280:
2217 		rdev->asic = &r200_asic;
2218 		break;
2219 	case CHIP_R300:
2220 	case CHIP_R350:
2221 	case CHIP_RV350:
2222 	case CHIP_RV380:
2223 		if (rdev->flags & RADEON_IS_PCIE)
2224 			rdev->asic = &r300_asic_pcie;
2225 		else
2226 			rdev->asic = &r300_asic;
2227 		break;
2228 	case CHIP_R420:
2229 	case CHIP_R423:
2230 	case CHIP_RV410:
2231 		rdev->asic = &r420_asic;
2232 		/* handle macs */
2233 		if (rdev->bios == NULL) {
2234 			rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2235 			rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2236 			rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2237 			rdev->asic->pm.set_memory_clock = NULL;
2238 			rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2239 		}
2240 		break;
2241 	case CHIP_RS400:
2242 	case CHIP_RS480:
2243 		rdev->asic = &rs400_asic;
2244 		break;
2245 	case CHIP_RS600:
2246 		rdev->asic = &rs600_asic;
2247 		break;
2248 	case CHIP_RS690:
2249 	case CHIP_RS740:
2250 		rdev->asic = &rs690_asic;
2251 		break;
2252 	case CHIP_RV515:
2253 		rdev->asic = &rv515_asic;
2254 		break;
2255 	case CHIP_R520:
2256 	case CHIP_RV530:
2257 	case CHIP_RV560:
2258 	case CHIP_RV570:
2259 	case CHIP_R580:
2260 		rdev->asic = &r520_asic;
2261 		break;
2262 	case CHIP_R600:
2263 		rdev->asic = &r600_asic;
2264 		break;
2265 	case CHIP_RV610:
2266 	case CHIP_RV630:
2267 	case CHIP_RV620:
2268 	case CHIP_RV635:
2269 	case CHIP_RV670:
2270 		rdev->asic = &rv6xx_asic;
2271 		rdev->has_uvd = true;
2272 		break;
2273 	case CHIP_RS780:
2274 	case CHIP_RS880:
2275 		rdev->asic = &rs780_asic;
2276 		rdev->has_uvd = true;
2277 		break;
2278 	case CHIP_RV770:
2279 	case CHIP_RV730:
2280 	case CHIP_RV710:
2281 	case CHIP_RV740:
2282 		rdev->asic = &rv770_asic;
2283 		rdev->has_uvd = true;
2284 		break;
2285 	case CHIP_CEDAR:
2286 	case CHIP_REDWOOD:
2287 	case CHIP_JUNIPER:
2288 	case CHIP_CYPRESS:
2289 	case CHIP_HEMLOCK:
2290 		/* set num crtcs */
2291 		if (rdev->family == CHIP_CEDAR)
2292 			rdev->num_crtc = 4;
2293 		else
2294 			rdev->num_crtc = 6;
2295 		rdev->asic = &evergreen_asic;
2296 		rdev->has_uvd = true;
2297 		break;
2298 	case CHIP_PALM:
2299 	case CHIP_SUMO:
2300 	case CHIP_SUMO2:
2301 		rdev->asic = &sumo_asic;
2302 		rdev->has_uvd = true;
2303 		break;
2304 	case CHIP_BARTS:
2305 	case CHIP_TURKS:
2306 	case CHIP_CAICOS:
2307 		/* set num crtcs */
2308 		if (rdev->family == CHIP_CAICOS)
2309 			rdev->num_crtc = 4;
2310 		else
2311 			rdev->num_crtc = 6;
2312 		rdev->asic = &btc_asic;
2313 		rdev->has_uvd = true;
2314 		break;
2315 	case CHIP_CAYMAN:
2316 		rdev->asic = &cayman_asic;
2317 		/* set num crtcs */
2318 		rdev->num_crtc = 6;
2319 		rdev->has_uvd = true;
2320 		break;
2321 	case CHIP_ARUBA:
2322 		rdev->asic = &trinity_asic;
2323 		/* set num crtcs */
2324 		rdev->num_crtc = 4;
2325 		rdev->has_uvd = true;
2326 		break;
2327 	case CHIP_TAHITI:
2328 	case CHIP_PITCAIRN:
2329 	case CHIP_VERDE:
2330 	case CHIP_OLAND:
2331 	case CHIP_HAINAN:
2332 		rdev->asic = &si_asic;
2333 		/* set num crtcs */
2334 		if (rdev->family == CHIP_HAINAN)
2335 			rdev->num_crtc = 0;
2336 		else if (rdev->family == CHIP_OLAND)
2337 			rdev->num_crtc = 2;
2338 		else
2339 			rdev->num_crtc = 6;
2340 		if (rdev->family == CHIP_HAINAN)
2341 			rdev->has_uvd = false;
2342 		else
2343 			rdev->has_uvd = true;
2344 		switch (rdev->family) {
2345 		case CHIP_TAHITI:
2346 			rdev->cg_flags =
2347 				RADEON_CG_SUPPORT_GFX_MGCG |
2348 				RADEON_CG_SUPPORT_GFX_MGLS |
2349 				/*RADEON_CG_SUPPORT_GFX_CGCG |*/
2350 				RADEON_CG_SUPPORT_GFX_CGLS |
2351 				RADEON_CG_SUPPORT_GFX_CGTS |
2352 				RADEON_CG_SUPPORT_GFX_CP_LS |
2353 				RADEON_CG_SUPPORT_MC_MGCG |
2354 				RADEON_CG_SUPPORT_SDMA_MGCG |
2355 				RADEON_CG_SUPPORT_BIF_LS |
2356 				RADEON_CG_SUPPORT_VCE_MGCG |
2357 				RADEON_CG_SUPPORT_UVD_MGCG |
2358 				RADEON_CG_SUPPORT_HDP_LS |
2359 				RADEON_CG_SUPPORT_HDP_MGCG;
2360 			rdev->pg_flags = 0;
2361 			break;
2362 		case CHIP_PITCAIRN:
2363 			rdev->cg_flags =
2364 				RADEON_CG_SUPPORT_GFX_MGCG |
2365 				RADEON_CG_SUPPORT_GFX_MGLS |
2366 				/*RADEON_CG_SUPPORT_GFX_CGCG |*/
2367 				RADEON_CG_SUPPORT_GFX_CGLS |
2368 				RADEON_CG_SUPPORT_GFX_CGTS |
2369 				RADEON_CG_SUPPORT_GFX_CP_LS |
2370 				RADEON_CG_SUPPORT_GFX_RLC_LS |
2371 				RADEON_CG_SUPPORT_MC_LS |
2372 				RADEON_CG_SUPPORT_MC_MGCG |
2373 				RADEON_CG_SUPPORT_SDMA_MGCG |
2374 				RADEON_CG_SUPPORT_BIF_LS |
2375 				RADEON_CG_SUPPORT_VCE_MGCG |
2376 				RADEON_CG_SUPPORT_UVD_MGCG |
2377 				RADEON_CG_SUPPORT_HDP_LS |
2378 				RADEON_CG_SUPPORT_HDP_MGCG;
2379 			rdev->pg_flags = 0;
2380 			break;
2381 		case CHIP_VERDE:
2382 			rdev->cg_flags =
2383 				RADEON_CG_SUPPORT_GFX_MGCG |
2384 				RADEON_CG_SUPPORT_GFX_MGLS |
2385 				/*RADEON_CG_SUPPORT_GFX_CGCG |*/
2386 				RADEON_CG_SUPPORT_GFX_CGLS |
2387 				RADEON_CG_SUPPORT_GFX_CGTS |
2388 				RADEON_CG_SUPPORT_GFX_CP_LS |
2389 				RADEON_CG_SUPPORT_GFX_RLC_LS |
2390 				RADEON_CG_SUPPORT_MC_LS |
2391 				RADEON_CG_SUPPORT_MC_MGCG |
2392 				RADEON_CG_SUPPORT_SDMA_MGCG |
2393 				RADEON_CG_SUPPORT_BIF_LS |
2394 				RADEON_CG_SUPPORT_VCE_MGCG |
2395 				RADEON_CG_SUPPORT_UVD_MGCG |
2396 				RADEON_CG_SUPPORT_HDP_LS |
2397 				RADEON_CG_SUPPORT_HDP_MGCG;
2398 			rdev->pg_flags = 0 |
2399 				/*RADEON_PG_SUPPORT_GFX_PG | */
2400 				RADEON_PG_SUPPORT_SDMA;
2401 			break;
2402 		case CHIP_OLAND:
2403 			rdev->cg_flags =
2404 				RADEON_CG_SUPPORT_GFX_MGCG |
2405 				RADEON_CG_SUPPORT_GFX_MGLS |
2406 				/*RADEON_CG_SUPPORT_GFX_CGCG |*/
2407 				RADEON_CG_SUPPORT_GFX_CGLS |
2408 				RADEON_CG_SUPPORT_GFX_CGTS |
2409 				RADEON_CG_SUPPORT_GFX_CP_LS |
2410 				RADEON_CG_SUPPORT_GFX_RLC_LS |
2411 				RADEON_CG_SUPPORT_MC_LS |
2412 				RADEON_CG_SUPPORT_MC_MGCG |
2413 				RADEON_CG_SUPPORT_SDMA_MGCG |
2414 				RADEON_CG_SUPPORT_BIF_LS |
2415 				RADEON_CG_SUPPORT_UVD_MGCG |
2416 				RADEON_CG_SUPPORT_HDP_LS |
2417 				RADEON_CG_SUPPORT_HDP_MGCG;
2418 			rdev->pg_flags = 0;
2419 			break;
2420 		case CHIP_HAINAN:
2421 			rdev->cg_flags =
2422 				RADEON_CG_SUPPORT_GFX_MGCG |
2423 				RADEON_CG_SUPPORT_GFX_MGLS |
2424 				/*RADEON_CG_SUPPORT_GFX_CGCG |*/
2425 				RADEON_CG_SUPPORT_GFX_CGLS |
2426 				RADEON_CG_SUPPORT_GFX_CGTS |
2427 				RADEON_CG_SUPPORT_GFX_CP_LS |
2428 				RADEON_CG_SUPPORT_GFX_RLC_LS |
2429 				RADEON_CG_SUPPORT_MC_LS |
2430 				RADEON_CG_SUPPORT_MC_MGCG |
2431 				RADEON_CG_SUPPORT_SDMA_MGCG |
2432 				RADEON_CG_SUPPORT_BIF_LS |
2433 				RADEON_CG_SUPPORT_HDP_LS |
2434 				RADEON_CG_SUPPORT_HDP_MGCG;
2435 			rdev->pg_flags = 0;
2436 			break;
2437 		default:
2438 			rdev->cg_flags = 0;
2439 			rdev->pg_flags = 0;
2440 			break;
2441 		}
2442 		break;
2443 	case CHIP_BONAIRE:
2444 	case CHIP_HAWAII:
2445 		rdev->asic = &ci_asic;
2446 		rdev->num_crtc = 6;
2447 		rdev->has_uvd = true;
2448 		if (rdev->family == CHIP_BONAIRE) {
2449 			rdev->cg_flags =
2450 				RADEON_CG_SUPPORT_GFX_MGCG |
2451 				RADEON_CG_SUPPORT_GFX_MGLS |
2452 				/*RADEON_CG_SUPPORT_GFX_CGCG |*/
2453 				RADEON_CG_SUPPORT_GFX_CGLS |
2454 				RADEON_CG_SUPPORT_GFX_CGTS |
2455 				RADEON_CG_SUPPORT_GFX_CGTS_LS |
2456 				RADEON_CG_SUPPORT_GFX_CP_LS |
2457 				RADEON_CG_SUPPORT_MC_LS |
2458 				RADEON_CG_SUPPORT_MC_MGCG |
2459 				RADEON_CG_SUPPORT_SDMA_MGCG |
2460 				RADEON_CG_SUPPORT_SDMA_LS |
2461 				RADEON_CG_SUPPORT_BIF_LS |
2462 				RADEON_CG_SUPPORT_VCE_MGCG |
2463 				RADEON_CG_SUPPORT_UVD_MGCG |
2464 				RADEON_CG_SUPPORT_HDP_LS |
2465 				RADEON_CG_SUPPORT_HDP_MGCG;
2466 			rdev->pg_flags = 0;
2467 		} else {
2468 			rdev->cg_flags =
2469 				RADEON_CG_SUPPORT_GFX_MGCG |
2470 				RADEON_CG_SUPPORT_GFX_MGLS |
2471 				/*RADEON_CG_SUPPORT_GFX_CGCG |*/
2472 				RADEON_CG_SUPPORT_GFX_CGLS |
2473 				RADEON_CG_SUPPORT_GFX_CGTS |
2474 				RADEON_CG_SUPPORT_GFX_CP_LS |
2475 				RADEON_CG_SUPPORT_MC_LS |
2476 				RADEON_CG_SUPPORT_MC_MGCG |
2477 				RADEON_CG_SUPPORT_SDMA_MGCG |
2478 				RADEON_CG_SUPPORT_SDMA_LS |
2479 				RADEON_CG_SUPPORT_BIF_LS |
2480 				RADEON_CG_SUPPORT_VCE_MGCG |
2481 				RADEON_CG_SUPPORT_UVD_MGCG |
2482 				RADEON_CG_SUPPORT_HDP_LS |
2483 				RADEON_CG_SUPPORT_HDP_MGCG;
2484 			rdev->pg_flags = 0;
2485 		}
2486 		break;
2487 	case CHIP_KAVERI:
2488 	case CHIP_KABINI:
2489 		rdev->asic = &kv_asic;
2490 		/* set num crtcs */
2491 		if (rdev->family == CHIP_KAVERI) {
2492 			rdev->num_crtc = 4;
2493 			rdev->cg_flags =
2494 				RADEON_CG_SUPPORT_GFX_MGCG |
2495 				RADEON_CG_SUPPORT_GFX_MGLS |
2496 				/*RADEON_CG_SUPPORT_GFX_CGCG |*/
2497 				RADEON_CG_SUPPORT_GFX_CGLS |
2498 				RADEON_CG_SUPPORT_GFX_CGTS |
2499 				RADEON_CG_SUPPORT_GFX_CGTS_LS |
2500 				RADEON_CG_SUPPORT_GFX_CP_LS |
2501 				RADEON_CG_SUPPORT_SDMA_MGCG |
2502 				RADEON_CG_SUPPORT_SDMA_LS |
2503 				RADEON_CG_SUPPORT_BIF_LS |
2504 				RADEON_CG_SUPPORT_VCE_MGCG |
2505 				RADEON_CG_SUPPORT_UVD_MGCG |
2506 				RADEON_CG_SUPPORT_HDP_LS |
2507 				RADEON_CG_SUPPORT_HDP_MGCG;
2508 			rdev->pg_flags = 0;
2509 				/*RADEON_PG_SUPPORT_GFX_PG |
2510 				RADEON_PG_SUPPORT_GFX_SMG |
2511 				RADEON_PG_SUPPORT_GFX_DMG |
2512 				RADEON_PG_SUPPORT_UVD |
2513 				RADEON_PG_SUPPORT_VCE |
2514 				RADEON_PG_SUPPORT_CP |
2515 				RADEON_PG_SUPPORT_GDS |
2516 				RADEON_PG_SUPPORT_RLC_SMU_HS |
2517 				RADEON_PG_SUPPORT_ACP |
2518 				RADEON_PG_SUPPORT_SAMU;*/
2519 		} else {
2520 			rdev->num_crtc = 2;
2521 			rdev->cg_flags =
2522 				RADEON_CG_SUPPORT_GFX_MGCG |
2523 				RADEON_CG_SUPPORT_GFX_MGLS |
2524 				/*RADEON_CG_SUPPORT_GFX_CGCG |*/
2525 				RADEON_CG_SUPPORT_GFX_CGLS |
2526 				RADEON_CG_SUPPORT_GFX_CGTS |
2527 				RADEON_CG_SUPPORT_GFX_CGTS_LS |
2528 				RADEON_CG_SUPPORT_GFX_CP_LS |
2529 				RADEON_CG_SUPPORT_SDMA_MGCG |
2530 				RADEON_CG_SUPPORT_SDMA_LS |
2531 				RADEON_CG_SUPPORT_BIF_LS |
2532 				RADEON_CG_SUPPORT_VCE_MGCG |
2533 				RADEON_CG_SUPPORT_UVD_MGCG |
2534 				RADEON_CG_SUPPORT_HDP_LS |
2535 				RADEON_CG_SUPPORT_HDP_MGCG;
2536 			rdev->pg_flags = 0;
2537 				/*RADEON_PG_SUPPORT_GFX_PG |
2538 				RADEON_PG_SUPPORT_GFX_SMG |
2539 				RADEON_PG_SUPPORT_UVD |
2540 				RADEON_PG_SUPPORT_VCE |
2541 				RADEON_PG_SUPPORT_CP |
2542 				RADEON_PG_SUPPORT_GDS |
2543 				RADEON_PG_SUPPORT_RLC_SMU_HS |
2544 				RADEON_PG_SUPPORT_SAMU;*/
2545 		}
2546 		rdev->has_uvd = true;
2547 		break;
2548 	default:
2549 		/* FIXME: not supported yet */
2550 		return -EINVAL;
2551 	}
2552 
2553 	if (rdev->flags & RADEON_IS_IGP) {
2554 		rdev->asic->pm.get_memory_clock = NULL;
2555 		rdev->asic->pm.set_memory_clock = NULL;
2556 	}
2557 
2558 	return 0;
2559 }
2560 
2561