1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/console.h> 30 #include <drm/drmP.h> 31 #include <drm/drm_crtc_helper.h> 32 #include <drm/radeon_drm.h> 33 #include <linux/vgaarb.h> 34 #include <linux/vga_switcheroo.h> 35 #include "radeon_reg.h" 36 #include "radeon.h" 37 #include "radeon_asic.h" 38 #include "atom.h" 39 40 /* 41 * Registers accessors functions. 42 */ 43 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) 44 { 45 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); 46 BUG_ON(1); 47 return 0; 48 } 49 50 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 51 { 52 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", 53 reg, v); 54 BUG_ON(1); 55 } 56 57 static void radeon_register_accessor_init(struct radeon_device *rdev) 58 { 59 rdev->mc_rreg = &radeon_invalid_rreg; 60 rdev->mc_wreg = &radeon_invalid_wreg; 61 rdev->pll_rreg = &radeon_invalid_rreg; 62 rdev->pll_wreg = &radeon_invalid_wreg; 63 rdev->pciep_rreg = &radeon_invalid_rreg; 64 rdev->pciep_wreg = &radeon_invalid_wreg; 65 66 /* Don't change order as we are overridding accessor. */ 67 if (rdev->family < CHIP_RV515) { 68 rdev->pcie_reg_mask = 0xff; 69 } else { 70 rdev->pcie_reg_mask = 0x7ff; 71 } 72 /* FIXME: not sure here */ 73 if (rdev->family <= CHIP_R580) { 74 rdev->pll_rreg = &r100_pll_rreg; 75 rdev->pll_wreg = &r100_pll_wreg; 76 } 77 if (rdev->family >= CHIP_R420) { 78 rdev->mc_rreg = &r420_mc_rreg; 79 rdev->mc_wreg = &r420_mc_wreg; 80 } 81 if (rdev->family >= CHIP_RV515) { 82 rdev->mc_rreg = &rv515_mc_rreg; 83 rdev->mc_wreg = &rv515_mc_wreg; 84 } 85 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { 86 rdev->mc_rreg = &rs400_mc_rreg; 87 rdev->mc_wreg = &rs400_mc_wreg; 88 } 89 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 90 rdev->mc_rreg = &rs690_mc_rreg; 91 rdev->mc_wreg = &rs690_mc_wreg; 92 } 93 if (rdev->family == CHIP_RS600) { 94 rdev->mc_rreg = &rs600_mc_rreg; 95 rdev->mc_wreg = &rs600_mc_wreg; 96 } 97 if (rdev->family >= CHIP_R600) { 98 rdev->pciep_rreg = &r600_pciep_rreg; 99 rdev->pciep_wreg = &r600_pciep_wreg; 100 } 101 } 102 103 104 /* helper to disable agp */ 105 void radeon_agp_disable(struct radeon_device *rdev) 106 { 107 rdev->flags &= ~RADEON_IS_AGP; 108 if (rdev->family >= CHIP_R600) { 109 DRM_INFO("Forcing AGP to PCIE mode\n"); 110 rdev->flags |= RADEON_IS_PCIE; 111 } else if (rdev->family >= CHIP_RV515 || 112 rdev->family == CHIP_RV380 || 113 rdev->family == CHIP_RV410 || 114 rdev->family == CHIP_R423) { 115 DRM_INFO("Forcing AGP to PCIE mode\n"); 116 rdev->flags |= RADEON_IS_PCIE; 117 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; 118 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; 119 } else { 120 DRM_INFO("Forcing AGP to PCI mode\n"); 121 rdev->flags |= RADEON_IS_PCI; 122 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; 123 rdev->asic->gart_set_page = &r100_pci_gart_set_page; 124 } 125 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 126 } 127 128 /* 129 * ASIC 130 */ 131 static struct radeon_asic r100_asic = { 132 .init = &r100_init, 133 .fini = &r100_fini, 134 .suspend = &r100_suspend, 135 .resume = &r100_resume, 136 .vga_set_state = &r100_vga_set_state, 137 .gpu_is_lockup = &r100_gpu_is_lockup, 138 .asic_reset = &r100_asic_reset, 139 .gart_tlb_flush = &r100_pci_gart_tlb_flush, 140 .gart_set_page = &r100_pci_gart_set_page, 141 .cp_commit = &r100_cp_commit, 142 .ring_start = &r100_ring_start, 143 .ring_test = &r100_ring_test, 144 .ring_ib_execute = &r100_ring_ib_execute, 145 .irq_set = &r100_irq_set, 146 .irq_process = &r100_irq_process, 147 .get_vblank_counter = &r100_get_vblank_counter, 148 .fence_ring_emit = &r100_fence_ring_emit, 149 .cs_parse = &r100_cs_parse, 150 .copy_blit = &r100_copy_blit, 151 .copy_dma = NULL, 152 .copy = &r100_copy_blit, 153 .get_engine_clock = &radeon_legacy_get_engine_clock, 154 .set_engine_clock = &radeon_legacy_set_engine_clock, 155 .get_memory_clock = &radeon_legacy_get_memory_clock, 156 .set_memory_clock = NULL, 157 .get_pcie_lanes = NULL, 158 .set_pcie_lanes = NULL, 159 .set_clock_gating = &radeon_legacy_set_clock_gating, 160 .set_surface_reg = r100_set_surface_reg, 161 .clear_surface_reg = r100_clear_surface_reg, 162 .bandwidth_update = &r100_bandwidth_update, 163 .hpd_init = &r100_hpd_init, 164 .hpd_fini = &r100_hpd_fini, 165 .hpd_sense = &r100_hpd_sense, 166 .hpd_set_polarity = &r100_hpd_set_polarity, 167 .ioctl_wait_idle = NULL, 168 .gui_idle = &r100_gui_idle, 169 .pm_misc = &r100_pm_misc, 170 .pm_prepare = &r100_pm_prepare, 171 .pm_finish = &r100_pm_finish, 172 .pm_init_profile = &r100_pm_init_profile, 173 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 174 .pre_page_flip = &r100_pre_page_flip, 175 .page_flip = &r100_page_flip, 176 .post_page_flip = &r100_post_page_flip, 177 }; 178 179 static struct radeon_asic r200_asic = { 180 .init = &r100_init, 181 .fini = &r100_fini, 182 .suspend = &r100_suspend, 183 .resume = &r100_resume, 184 .vga_set_state = &r100_vga_set_state, 185 .gpu_is_lockup = &r100_gpu_is_lockup, 186 .asic_reset = &r100_asic_reset, 187 .gart_tlb_flush = &r100_pci_gart_tlb_flush, 188 .gart_set_page = &r100_pci_gart_set_page, 189 .cp_commit = &r100_cp_commit, 190 .ring_start = &r100_ring_start, 191 .ring_test = &r100_ring_test, 192 .ring_ib_execute = &r100_ring_ib_execute, 193 .irq_set = &r100_irq_set, 194 .irq_process = &r100_irq_process, 195 .get_vblank_counter = &r100_get_vblank_counter, 196 .fence_ring_emit = &r100_fence_ring_emit, 197 .cs_parse = &r100_cs_parse, 198 .copy_blit = &r100_copy_blit, 199 .copy_dma = &r200_copy_dma, 200 .copy = &r100_copy_blit, 201 .get_engine_clock = &radeon_legacy_get_engine_clock, 202 .set_engine_clock = &radeon_legacy_set_engine_clock, 203 .get_memory_clock = &radeon_legacy_get_memory_clock, 204 .set_memory_clock = NULL, 205 .set_pcie_lanes = NULL, 206 .set_clock_gating = &radeon_legacy_set_clock_gating, 207 .set_surface_reg = r100_set_surface_reg, 208 .clear_surface_reg = r100_clear_surface_reg, 209 .bandwidth_update = &r100_bandwidth_update, 210 .hpd_init = &r100_hpd_init, 211 .hpd_fini = &r100_hpd_fini, 212 .hpd_sense = &r100_hpd_sense, 213 .hpd_set_polarity = &r100_hpd_set_polarity, 214 .ioctl_wait_idle = NULL, 215 .gui_idle = &r100_gui_idle, 216 .pm_misc = &r100_pm_misc, 217 .pm_prepare = &r100_pm_prepare, 218 .pm_finish = &r100_pm_finish, 219 .pm_init_profile = &r100_pm_init_profile, 220 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 221 .pre_page_flip = &r100_pre_page_flip, 222 .page_flip = &r100_page_flip, 223 .post_page_flip = &r100_post_page_flip, 224 }; 225 226 static struct radeon_asic r300_asic = { 227 .init = &r300_init, 228 .fini = &r300_fini, 229 .suspend = &r300_suspend, 230 .resume = &r300_resume, 231 .vga_set_state = &r100_vga_set_state, 232 .gpu_is_lockup = &r300_gpu_is_lockup, 233 .asic_reset = &r300_asic_reset, 234 .gart_tlb_flush = &r100_pci_gart_tlb_flush, 235 .gart_set_page = &r100_pci_gart_set_page, 236 .cp_commit = &r100_cp_commit, 237 .ring_start = &r300_ring_start, 238 .ring_test = &r100_ring_test, 239 .ring_ib_execute = &r100_ring_ib_execute, 240 .irq_set = &r100_irq_set, 241 .irq_process = &r100_irq_process, 242 .get_vblank_counter = &r100_get_vblank_counter, 243 .fence_ring_emit = &r300_fence_ring_emit, 244 .cs_parse = &r300_cs_parse, 245 .copy_blit = &r100_copy_blit, 246 .copy_dma = &r200_copy_dma, 247 .copy = &r100_copy_blit, 248 .get_engine_clock = &radeon_legacy_get_engine_clock, 249 .set_engine_clock = &radeon_legacy_set_engine_clock, 250 .get_memory_clock = &radeon_legacy_get_memory_clock, 251 .set_memory_clock = NULL, 252 .get_pcie_lanes = &rv370_get_pcie_lanes, 253 .set_pcie_lanes = &rv370_set_pcie_lanes, 254 .set_clock_gating = &radeon_legacy_set_clock_gating, 255 .set_surface_reg = r100_set_surface_reg, 256 .clear_surface_reg = r100_clear_surface_reg, 257 .bandwidth_update = &r100_bandwidth_update, 258 .hpd_init = &r100_hpd_init, 259 .hpd_fini = &r100_hpd_fini, 260 .hpd_sense = &r100_hpd_sense, 261 .hpd_set_polarity = &r100_hpd_set_polarity, 262 .ioctl_wait_idle = NULL, 263 .gui_idle = &r100_gui_idle, 264 .pm_misc = &r100_pm_misc, 265 .pm_prepare = &r100_pm_prepare, 266 .pm_finish = &r100_pm_finish, 267 .pm_init_profile = &r100_pm_init_profile, 268 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 269 .pre_page_flip = &r100_pre_page_flip, 270 .page_flip = &r100_page_flip, 271 .post_page_flip = &r100_post_page_flip, 272 }; 273 274 static struct radeon_asic r300_asic_pcie = { 275 .init = &r300_init, 276 .fini = &r300_fini, 277 .suspend = &r300_suspend, 278 .resume = &r300_resume, 279 .vga_set_state = &r100_vga_set_state, 280 .gpu_is_lockup = &r300_gpu_is_lockup, 281 .asic_reset = &r300_asic_reset, 282 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 283 .gart_set_page = &rv370_pcie_gart_set_page, 284 .cp_commit = &r100_cp_commit, 285 .ring_start = &r300_ring_start, 286 .ring_test = &r100_ring_test, 287 .ring_ib_execute = &r100_ring_ib_execute, 288 .irq_set = &r100_irq_set, 289 .irq_process = &r100_irq_process, 290 .get_vblank_counter = &r100_get_vblank_counter, 291 .fence_ring_emit = &r300_fence_ring_emit, 292 .cs_parse = &r300_cs_parse, 293 .copy_blit = &r100_copy_blit, 294 .copy_dma = &r200_copy_dma, 295 .copy = &r100_copy_blit, 296 .get_engine_clock = &radeon_legacy_get_engine_clock, 297 .set_engine_clock = &radeon_legacy_set_engine_clock, 298 .get_memory_clock = &radeon_legacy_get_memory_clock, 299 .set_memory_clock = NULL, 300 .set_pcie_lanes = &rv370_set_pcie_lanes, 301 .set_clock_gating = &radeon_legacy_set_clock_gating, 302 .set_surface_reg = r100_set_surface_reg, 303 .clear_surface_reg = r100_clear_surface_reg, 304 .bandwidth_update = &r100_bandwidth_update, 305 .hpd_init = &r100_hpd_init, 306 .hpd_fini = &r100_hpd_fini, 307 .hpd_sense = &r100_hpd_sense, 308 .hpd_set_polarity = &r100_hpd_set_polarity, 309 .ioctl_wait_idle = NULL, 310 .gui_idle = &r100_gui_idle, 311 .pm_misc = &r100_pm_misc, 312 .pm_prepare = &r100_pm_prepare, 313 .pm_finish = &r100_pm_finish, 314 .pm_init_profile = &r100_pm_init_profile, 315 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 316 .pre_page_flip = &r100_pre_page_flip, 317 .page_flip = &r100_page_flip, 318 .post_page_flip = &r100_post_page_flip, 319 }; 320 321 static struct radeon_asic r420_asic = { 322 .init = &r420_init, 323 .fini = &r420_fini, 324 .suspend = &r420_suspend, 325 .resume = &r420_resume, 326 .vga_set_state = &r100_vga_set_state, 327 .gpu_is_lockup = &r300_gpu_is_lockup, 328 .asic_reset = &r300_asic_reset, 329 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 330 .gart_set_page = &rv370_pcie_gart_set_page, 331 .cp_commit = &r100_cp_commit, 332 .ring_start = &r300_ring_start, 333 .ring_test = &r100_ring_test, 334 .ring_ib_execute = &r100_ring_ib_execute, 335 .irq_set = &r100_irq_set, 336 .irq_process = &r100_irq_process, 337 .get_vblank_counter = &r100_get_vblank_counter, 338 .fence_ring_emit = &r300_fence_ring_emit, 339 .cs_parse = &r300_cs_parse, 340 .copy_blit = &r100_copy_blit, 341 .copy_dma = &r200_copy_dma, 342 .copy = &r100_copy_blit, 343 .get_engine_clock = &radeon_atom_get_engine_clock, 344 .set_engine_clock = &radeon_atom_set_engine_clock, 345 .get_memory_clock = &radeon_atom_get_memory_clock, 346 .set_memory_clock = &radeon_atom_set_memory_clock, 347 .get_pcie_lanes = &rv370_get_pcie_lanes, 348 .set_pcie_lanes = &rv370_set_pcie_lanes, 349 .set_clock_gating = &radeon_atom_set_clock_gating, 350 .set_surface_reg = r100_set_surface_reg, 351 .clear_surface_reg = r100_clear_surface_reg, 352 .bandwidth_update = &r100_bandwidth_update, 353 .hpd_init = &r100_hpd_init, 354 .hpd_fini = &r100_hpd_fini, 355 .hpd_sense = &r100_hpd_sense, 356 .hpd_set_polarity = &r100_hpd_set_polarity, 357 .ioctl_wait_idle = NULL, 358 .gui_idle = &r100_gui_idle, 359 .pm_misc = &r100_pm_misc, 360 .pm_prepare = &r100_pm_prepare, 361 .pm_finish = &r100_pm_finish, 362 .pm_init_profile = &r420_pm_init_profile, 363 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 364 .pre_page_flip = &r100_pre_page_flip, 365 .page_flip = &r100_page_flip, 366 .post_page_flip = &r100_post_page_flip, 367 }; 368 369 static struct radeon_asic rs400_asic = { 370 .init = &rs400_init, 371 .fini = &rs400_fini, 372 .suspend = &rs400_suspend, 373 .resume = &rs400_resume, 374 .vga_set_state = &r100_vga_set_state, 375 .gpu_is_lockup = &r300_gpu_is_lockup, 376 .asic_reset = &r300_asic_reset, 377 .gart_tlb_flush = &rs400_gart_tlb_flush, 378 .gart_set_page = &rs400_gart_set_page, 379 .cp_commit = &r100_cp_commit, 380 .ring_start = &r300_ring_start, 381 .ring_test = &r100_ring_test, 382 .ring_ib_execute = &r100_ring_ib_execute, 383 .irq_set = &r100_irq_set, 384 .irq_process = &r100_irq_process, 385 .get_vblank_counter = &r100_get_vblank_counter, 386 .fence_ring_emit = &r300_fence_ring_emit, 387 .cs_parse = &r300_cs_parse, 388 .copy_blit = &r100_copy_blit, 389 .copy_dma = &r200_copy_dma, 390 .copy = &r100_copy_blit, 391 .get_engine_clock = &radeon_legacy_get_engine_clock, 392 .set_engine_clock = &radeon_legacy_set_engine_clock, 393 .get_memory_clock = &radeon_legacy_get_memory_clock, 394 .set_memory_clock = NULL, 395 .get_pcie_lanes = NULL, 396 .set_pcie_lanes = NULL, 397 .set_clock_gating = &radeon_legacy_set_clock_gating, 398 .set_surface_reg = r100_set_surface_reg, 399 .clear_surface_reg = r100_clear_surface_reg, 400 .bandwidth_update = &r100_bandwidth_update, 401 .hpd_init = &r100_hpd_init, 402 .hpd_fini = &r100_hpd_fini, 403 .hpd_sense = &r100_hpd_sense, 404 .hpd_set_polarity = &r100_hpd_set_polarity, 405 .ioctl_wait_idle = NULL, 406 .gui_idle = &r100_gui_idle, 407 .pm_misc = &r100_pm_misc, 408 .pm_prepare = &r100_pm_prepare, 409 .pm_finish = &r100_pm_finish, 410 .pm_init_profile = &r100_pm_init_profile, 411 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 412 .pre_page_flip = &r100_pre_page_flip, 413 .page_flip = &r100_page_flip, 414 .post_page_flip = &r100_post_page_flip, 415 }; 416 417 static struct radeon_asic rs600_asic = { 418 .init = &rs600_init, 419 .fini = &rs600_fini, 420 .suspend = &rs600_suspend, 421 .resume = &rs600_resume, 422 .vga_set_state = &r100_vga_set_state, 423 .gpu_is_lockup = &r300_gpu_is_lockup, 424 .asic_reset = &rs600_asic_reset, 425 .gart_tlb_flush = &rs600_gart_tlb_flush, 426 .gart_set_page = &rs600_gart_set_page, 427 .cp_commit = &r100_cp_commit, 428 .ring_start = &r300_ring_start, 429 .ring_test = &r100_ring_test, 430 .ring_ib_execute = &r100_ring_ib_execute, 431 .irq_set = &rs600_irq_set, 432 .irq_process = &rs600_irq_process, 433 .get_vblank_counter = &rs600_get_vblank_counter, 434 .fence_ring_emit = &r300_fence_ring_emit, 435 .cs_parse = &r300_cs_parse, 436 .copy_blit = &r100_copy_blit, 437 .copy_dma = &r200_copy_dma, 438 .copy = &r100_copy_blit, 439 .get_engine_clock = &radeon_atom_get_engine_clock, 440 .set_engine_clock = &radeon_atom_set_engine_clock, 441 .get_memory_clock = &radeon_atom_get_memory_clock, 442 .set_memory_clock = &radeon_atom_set_memory_clock, 443 .get_pcie_lanes = NULL, 444 .set_pcie_lanes = NULL, 445 .set_clock_gating = &radeon_atom_set_clock_gating, 446 .set_surface_reg = r100_set_surface_reg, 447 .clear_surface_reg = r100_clear_surface_reg, 448 .bandwidth_update = &rs600_bandwidth_update, 449 .hpd_init = &rs600_hpd_init, 450 .hpd_fini = &rs600_hpd_fini, 451 .hpd_sense = &rs600_hpd_sense, 452 .hpd_set_polarity = &rs600_hpd_set_polarity, 453 .ioctl_wait_idle = NULL, 454 .gui_idle = &r100_gui_idle, 455 .pm_misc = &rs600_pm_misc, 456 .pm_prepare = &rs600_pm_prepare, 457 .pm_finish = &rs600_pm_finish, 458 .pm_init_profile = &r420_pm_init_profile, 459 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 460 .pre_page_flip = &rs600_pre_page_flip, 461 .page_flip = &rs600_page_flip, 462 .post_page_flip = &rs600_post_page_flip, 463 }; 464 465 static struct radeon_asic rs690_asic = { 466 .init = &rs690_init, 467 .fini = &rs690_fini, 468 .suspend = &rs690_suspend, 469 .resume = &rs690_resume, 470 .vga_set_state = &r100_vga_set_state, 471 .gpu_is_lockup = &r300_gpu_is_lockup, 472 .asic_reset = &rs600_asic_reset, 473 .gart_tlb_flush = &rs400_gart_tlb_flush, 474 .gart_set_page = &rs400_gart_set_page, 475 .cp_commit = &r100_cp_commit, 476 .ring_start = &r300_ring_start, 477 .ring_test = &r100_ring_test, 478 .ring_ib_execute = &r100_ring_ib_execute, 479 .irq_set = &rs600_irq_set, 480 .irq_process = &rs600_irq_process, 481 .get_vblank_counter = &rs600_get_vblank_counter, 482 .fence_ring_emit = &r300_fence_ring_emit, 483 .cs_parse = &r300_cs_parse, 484 .copy_blit = &r100_copy_blit, 485 .copy_dma = &r200_copy_dma, 486 .copy = &r200_copy_dma, 487 .get_engine_clock = &radeon_atom_get_engine_clock, 488 .set_engine_clock = &radeon_atom_set_engine_clock, 489 .get_memory_clock = &radeon_atom_get_memory_clock, 490 .set_memory_clock = &radeon_atom_set_memory_clock, 491 .get_pcie_lanes = NULL, 492 .set_pcie_lanes = NULL, 493 .set_clock_gating = &radeon_atom_set_clock_gating, 494 .set_surface_reg = r100_set_surface_reg, 495 .clear_surface_reg = r100_clear_surface_reg, 496 .bandwidth_update = &rs690_bandwidth_update, 497 .hpd_init = &rs600_hpd_init, 498 .hpd_fini = &rs600_hpd_fini, 499 .hpd_sense = &rs600_hpd_sense, 500 .hpd_set_polarity = &rs600_hpd_set_polarity, 501 .ioctl_wait_idle = NULL, 502 .gui_idle = &r100_gui_idle, 503 .pm_misc = &rs600_pm_misc, 504 .pm_prepare = &rs600_pm_prepare, 505 .pm_finish = &rs600_pm_finish, 506 .pm_init_profile = &r420_pm_init_profile, 507 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 508 .pre_page_flip = &rs600_pre_page_flip, 509 .page_flip = &rs600_page_flip, 510 .post_page_flip = &rs600_post_page_flip, 511 }; 512 513 static struct radeon_asic rv515_asic = { 514 .init = &rv515_init, 515 .fini = &rv515_fini, 516 .suspend = &rv515_suspend, 517 .resume = &rv515_resume, 518 .vga_set_state = &r100_vga_set_state, 519 .gpu_is_lockup = &r300_gpu_is_lockup, 520 .asic_reset = &rs600_asic_reset, 521 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 522 .gart_set_page = &rv370_pcie_gart_set_page, 523 .cp_commit = &r100_cp_commit, 524 .ring_start = &rv515_ring_start, 525 .ring_test = &r100_ring_test, 526 .ring_ib_execute = &r100_ring_ib_execute, 527 .irq_set = &rs600_irq_set, 528 .irq_process = &rs600_irq_process, 529 .get_vblank_counter = &rs600_get_vblank_counter, 530 .fence_ring_emit = &r300_fence_ring_emit, 531 .cs_parse = &r300_cs_parse, 532 .copy_blit = &r100_copy_blit, 533 .copy_dma = &r200_copy_dma, 534 .copy = &r100_copy_blit, 535 .get_engine_clock = &radeon_atom_get_engine_clock, 536 .set_engine_clock = &radeon_atom_set_engine_clock, 537 .get_memory_clock = &radeon_atom_get_memory_clock, 538 .set_memory_clock = &radeon_atom_set_memory_clock, 539 .get_pcie_lanes = &rv370_get_pcie_lanes, 540 .set_pcie_lanes = &rv370_set_pcie_lanes, 541 .set_clock_gating = &radeon_atom_set_clock_gating, 542 .set_surface_reg = r100_set_surface_reg, 543 .clear_surface_reg = r100_clear_surface_reg, 544 .bandwidth_update = &rv515_bandwidth_update, 545 .hpd_init = &rs600_hpd_init, 546 .hpd_fini = &rs600_hpd_fini, 547 .hpd_sense = &rs600_hpd_sense, 548 .hpd_set_polarity = &rs600_hpd_set_polarity, 549 .ioctl_wait_idle = NULL, 550 .gui_idle = &r100_gui_idle, 551 .pm_misc = &rs600_pm_misc, 552 .pm_prepare = &rs600_pm_prepare, 553 .pm_finish = &rs600_pm_finish, 554 .pm_init_profile = &r420_pm_init_profile, 555 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 556 .pre_page_flip = &rs600_pre_page_flip, 557 .page_flip = &rs600_page_flip, 558 .post_page_flip = &rs600_post_page_flip, 559 }; 560 561 static struct radeon_asic r520_asic = { 562 .init = &r520_init, 563 .fini = &rv515_fini, 564 .suspend = &rv515_suspend, 565 .resume = &r520_resume, 566 .vga_set_state = &r100_vga_set_state, 567 .gpu_is_lockup = &r300_gpu_is_lockup, 568 .asic_reset = &rs600_asic_reset, 569 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 570 .gart_set_page = &rv370_pcie_gart_set_page, 571 .cp_commit = &r100_cp_commit, 572 .ring_start = &rv515_ring_start, 573 .ring_test = &r100_ring_test, 574 .ring_ib_execute = &r100_ring_ib_execute, 575 .irq_set = &rs600_irq_set, 576 .irq_process = &rs600_irq_process, 577 .get_vblank_counter = &rs600_get_vblank_counter, 578 .fence_ring_emit = &r300_fence_ring_emit, 579 .cs_parse = &r300_cs_parse, 580 .copy_blit = &r100_copy_blit, 581 .copy_dma = &r200_copy_dma, 582 .copy = &r100_copy_blit, 583 .get_engine_clock = &radeon_atom_get_engine_clock, 584 .set_engine_clock = &radeon_atom_set_engine_clock, 585 .get_memory_clock = &radeon_atom_get_memory_clock, 586 .set_memory_clock = &radeon_atom_set_memory_clock, 587 .get_pcie_lanes = &rv370_get_pcie_lanes, 588 .set_pcie_lanes = &rv370_set_pcie_lanes, 589 .set_clock_gating = &radeon_atom_set_clock_gating, 590 .set_surface_reg = r100_set_surface_reg, 591 .clear_surface_reg = r100_clear_surface_reg, 592 .bandwidth_update = &rv515_bandwidth_update, 593 .hpd_init = &rs600_hpd_init, 594 .hpd_fini = &rs600_hpd_fini, 595 .hpd_sense = &rs600_hpd_sense, 596 .hpd_set_polarity = &rs600_hpd_set_polarity, 597 .ioctl_wait_idle = NULL, 598 .gui_idle = &r100_gui_idle, 599 .pm_misc = &rs600_pm_misc, 600 .pm_prepare = &rs600_pm_prepare, 601 .pm_finish = &rs600_pm_finish, 602 .pm_init_profile = &r420_pm_init_profile, 603 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 604 .pre_page_flip = &rs600_pre_page_flip, 605 .page_flip = &rs600_page_flip, 606 .post_page_flip = &rs600_post_page_flip, 607 }; 608 609 static struct radeon_asic r600_asic = { 610 .init = &r600_init, 611 .fini = &r600_fini, 612 .suspend = &r600_suspend, 613 .resume = &r600_resume, 614 .cp_commit = &r600_cp_commit, 615 .vga_set_state = &r600_vga_set_state, 616 .gpu_is_lockup = &r600_gpu_is_lockup, 617 .asic_reset = &r600_asic_reset, 618 .gart_tlb_flush = &r600_pcie_gart_tlb_flush, 619 .gart_set_page = &rs600_gart_set_page, 620 .ring_test = &r600_ring_test, 621 .ring_ib_execute = &r600_ring_ib_execute, 622 .irq_set = &r600_irq_set, 623 .irq_process = &r600_irq_process, 624 .get_vblank_counter = &rs600_get_vblank_counter, 625 .fence_ring_emit = &r600_fence_ring_emit, 626 .cs_parse = &r600_cs_parse, 627 .copy_blit = &r600_copy_blit, 628 .copy_dma = NULL, 629 .copy = &r600_copy_blit, 630 .get_engine_clock = &radeon_atom_get_engine_clock, 631 .set_engine_clock = &radeon_atom_set_engine_clock, 632 .get_memory_clock = &radeon_atom_get_memory_clock, 633 .set_memory_clock = &radeon_atom_set_memory_clock, 634 .get_pcie_lanes = &r600_get_pcie_lanes, 635 .set_pcie_lanes = &r600_set_pcie_lanes, 636 .set_clock_gating = NULL, 637 .set_surface_reg = r600_set_surface_reg, 638 .clear_surface_reg = r600_clear_surface_reg, 639 .bandwidth_update = &rv515_bandwidth_update, 640 .hpd_init = &r600_hpd_init, 641 .hpd_fini = &r600_hpd_fini, 642 .hpd_sense = &r600_hpd_sense, 643 .hpd_set_polarity = &r600_hpd_set_polarity, 644 .ioctl_wait_idle = r600_ioctl_wait_idle, 645 .gui_idle = &r600_gui_idle, 646 .pm_misc = &r600_pm_misc, 647 .pm_prepare = &rs600_pm_prepare, 648 .pm_finish = &rs600_pm_finish, 649 .pm_init_profile = &r600_pm_init_profile, 650 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 651 .pre_page_flip = &rs600_pre_page_flip, 652 .page_flip = &rs600_page_flip, 653 .post_page_flip = &rs600_post_page_flip, 654 }; 655 656 static struct radeon_asic rs780_asic = { 657 .init = &r600_init, 658 .fini = &r600_fini, 659 .suspend = &r600_suspend, 660 .resume = &r600_resume, 661 .cp_commit = &r600_cp_commit, 662 .gpu_is_lockup = &r600_gpu_is_lockup, 663 .vga_set_state = &r600_vga_set_state, 664 .asic_reset = &r600_asic_reset, 665 .gart_tlb_flush = &r600_pcie_gart_tlb_flush, 666 .gart_set_page = &rs600_gart_set_page, 667 .ring_test = &r600_ring_test, 668 .ring_ib_execute = &r600_ring_ib_execute, 669 .irq_set = &r600_irq_set, 670 .irq_process = &r600_irq_process, 671 .get_vblank_counter = &rs600_get_vblank_counter, 672 .fence_ring_emit = &r600_fence_ring_emit, 673 .cs_parse = &r600_cs_parse, 674 .copy_blit = &r600_copy_blit, 675 .copy_dma = NULL, 676 .copy = &r600_copy_blit, 677 .get_engine_clock = &radeon_atom_get_engine_clock, 678 .set_engine_clock = &radeon_atom_set_engine_clock, 679 .get_memory_clock = NULL, 680 .set_memory_clock = NULL, 681 .get_pcie_lanes = NULL, 682 .set_pcie_lanes = NULL, 683 .set_clock_gating = NULL, 684 .set_surface_reg = r600_set_surface_reg, 685 .clear_surface_reg = r600_clear_surface_reg, 686 .bandwidth_update = &rs690_bandwidth_update, 687 .hpd_init = &r600_hpd_init, 688 .hpd_fini = &r600_hpd_fini, 689 .hpd_sense = &r600_hpd_sense, 690 .hpd_set_polarity = &r600_hpd_set_polarity, 691 .ioctl_wait_idle = r600_ioctl_wait_idle, 692 .gui_idle = &r600_gui_idle, 693 .pm_misc = &r600_pm_misc, 694 .pm_prepare = &rs600_pm_prepare, 695 .pm_finish = &rs600_pm_finish, 696 .pm_init_profile = &rs780_pm_init_profile, 697 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 698 .pre_page_flip = &rs600_pre_page_flip, 699 .page_flip = &rs600_page_flip, 700 .post_page_flip = &rs600_post_page_flip, 701 }; 702 703 static struct radeon_asic rv770_asic = { 704 .init = &rv770_init, 705 .fini = &rv770_fini, 706 .suspend = &rv770_suspend, 707 .resume = &rv770_resume, 708 .cp_commit = &r600_cp_commit, 709 .asic_reset = &r600_asic_reset, 710 .gpu_is_lockup = &r600_gpu_is_lockup, 711 .vga_set_state = &r600_vga_set_state, 712 .gart_tlb_flush = &r600_pcie_gart_tlb_flush, 713 .gart_set_page = &rs600_gart_set_page, 714 .ring_test = &r600_ring_test, 715 .ring_ib_execute = &r600_ring_ib_execute, 716 .irq_set = &r600_irq_set, 717 .irq_process = &r600_irq_process, 718 .get_vblank_counter = &rs600_get_vblank_counter, 719 .fence_ring_emit = &r600_fence_ring_emit, 720 .cs_parse = &r600_cs_parse, 721 .copy_blit = &r600_copy_blit, 722 .copy_dma = NULL, 723 .copy = &r600_copy_blit, 724 .get_engine_clock = &radeon_atom_get_engine_clock, 725 .set_engine_clock = &radeon_atom_set_engine_clock, 726 .get_memory_clock = &radeon_atom_get_memory_clock, 727 .set_memory_clock = &radeon_atom_set_memory_clock, 728 .get_pcie_lanes = &r600_get_pcie_lanes, 729 .set_pcie_lanes = &r600_set_pcie_lanes, 730 .set_clock_gating = &radeon_atom_set_clock_gating, 731 .set_surface_reg = r600_set_surface_reg, 732 .clear_surface_reg = r600_clear_surface_reg, 733 .bandwidth_update = &rv515_bandwidth_update, 734 .hpd_init = &r600_hpd_init, 735 .hpd_fini = &r600_hpd_fini, 736 .hpd_sense = &r600_hpd_sense, 737 .hpd_set_polarity = &r600_hpd_set_polarity, 738 .ioctl_wait_idle = r600_ioctl_wait_idle, 739 .gui_idle = &r600_gui_idle, 740 .pm_misc = &rv770_pm_misc, 741 .pm_prepare = &rs600_pm_prepare, 742 .pm_finish = &rs600_pm_finish, 743 .pm_init_profile = &r600_pm_init_profile, 744 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 745 .pre_page_flip = &rs600_pre_page_flip, 746 .page_flip = &rv770_page_flip, 747 .post_page_flip = &rs600_post_page_flip, 748 }; 749 750 static struct radeon_asic evergreen_asic = { 751 .init = &evergreen_init, 752 .fini = &evergreen_fini, 753 .suspend = &evergreen_suspend, 754 .resume = &evergreen_resume, 755 .cp_commit = &r600_cp_commit, 756 .gpu_is_lockup = &evergreen_gpu_is_lockup, 757 .asic_reset = &evergreen_asic_reset, 758 .vga_set_state = &r600_vga_set_state, 759 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, 760 .gart_set_page = &rs600_gart_set_page, 761 .ring_test = &r600_ring_test, 762 .ring_ib_execute = &evergreen_ring_ib_execute, 763 .irq_set = &evergreen_irq_set, 764 .irq_process = &evergreen_irq_process, 765 .get_vblank_counter = &evergreen_get_vblank_counter, 766 .fence_ring_emit = &r600_fence_ring_emit, 767 .cs_parse = &evergreen_cs_parse, 768 .copy_blit = &evergreen_copy_blit, 769 .copy_dma = NULL, 770 .copy = &evergreen_copy_blit, 771 .get_engine_clock = &radeon_atom_get_engine_clock, 772 .set_engine_clock = &radeon_atom_set_engine_clock, 773 .get_memory_clock = &radeon_atom_get_memory_clock, 774 .set_memory_clock = &radeon_atom_set_memory_clock, 775 .get_pcie_lanes = &r600_get_pcie_lanes, 776 .set_pcie_lanes = &r600_set_pcie_lanes, 777 .set_clock_gating = NULL, 778 .set_surface_reg = r600_set_surface_reg, 779 .clear_surface_reg = r600_clear_surface_reg, 780 .bandwidth_update = &evergreen_bandwidth_update, 781 .hpd_init = &evergreen_hpd_init, 782 .hpd_fini = &evergreen_hpd_fini, 783 .hpd_sense = &evergreen_hpd_sense, 784 .hpd_set_polarity = &evergreen_hpd_set_polarity, 785 .ioctl_wait_idle = r600_ioctl_wait_idle, 786 .gui_idle = &r600_gui_idle, 787 .pm_misc = &evergreen_pm_misc, 788 .pm_prepare = &evergreen_pm_prepare, 789 .pm_finish = &evergreen_pm_finish, 790 .pm_init_profile = &r600_pm_init_profile, 791 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 792 .pre_page_flip = &evergreen_pre_page_flip, 793 .page_flip = &evergreen_page_flip, 794 .post_page_flip = &evergreen_post_page_flip, 795 }; 796 797 static struct radeon_asic sumo_asic = { 798 .init = &evergreen_init, 799 .fini = &evergreen_fini, 800 .suspend = &evergreen_suspend, 801 .resume = &evergreen_resume, 802 .cp_commit = &r600_cp_commit, 803 .gpu_is_lockup = &evergreen_gpu_is_lockup, 804 .asic_reset = &evergreen_asic_reset, 805 .vga_set_state = &r600_vga_set_state, 806 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, 807 .gart_set_page = &rs600_gart_set_page, 808 .ring_test = &r600_ring_test, 809 .ring_ib_execute = &evergreen_ring_ib_execute, 810 .irq_set = &evergreen_irq_set, 811 .irq_process = &evergreen_irq_process, 812 .get_vblank_counter = &evergreen_get_vblank_counter, 813 .fence_ring_emit = &r600_fence_ring_emit, 814 .cs_parse = &evergreen_cs_parse, 815 .copy_blit = &evergreen_copy_blit, 816 .copy_dma = NULL, 817 .copy = &evergreen_copy_blit, 818 .get_engine_clock = &radeon_atom_get_engine_clock, 819 .set_engine_clock = &radeon_atom_set_engine_clock, 820 .get_memory_clock = NULL, 821 .set_memory_clock = NULL, 822 .get_pcie_lanes = NULL, 823 .set_pcie_lanes = NULL, 824 .set_clock_gating = NULL, 825 .set_surface_reg = r600_set_surface_reg, 826 .clear_surface_reg = r600_clear_surface_reg, 827 .bandwidth_update = &evergreen_bandwidth_update, 828 .hpd_init = &evergreen_hpd_init, 829 .hpd_fini = &evergreen_hpd_fini, 830 .hpd_sense = &evergreen_hpd_sense, 831 .hpd_set_polarity = &evergreen_hpd_set_polarity, 832 .ioctl_wait_idle = r600_ioctl_wait_idle, 833 .gui_idle = &r600_gui_idle, 834 .pm_misc = &evergreen_pm_misc, 835 .pm_prepare = &evergreen_pm_prepare, 836 .pm_finish = &evergreen_pm_finish, 837 .pm_init_profile = &rs780_pm_init_profile, 838 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 839 .pre_page_flip = &evergreen_pre_page_flip, 840 .page_flip = &evergreen_page_flip, 841 .post_page_flip = &evergreen_post_page_flip, 842 }; 843 844 static struct radeon_asic btc_asic = { 845 .init = &evergreen_init, 846 .fini = &evergreen_fini, 847 .suspend = &evergreen_suspend, 848 .resume = &evergreen_resume, 849 .cp_commit = &r600_cp_commit, 850 .gpu_is_lockup = &evergreen_gpu_is_lockup, 851 .asic_reset = &evergreen_asic_reset, 852 .vga_set_state = &r600_vga_set_state, 853 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, 854 .gart_set_page = &rs600_gart_set_page, 855 .ring_test = &r600_ring_test, 856 .ring_ib_execute = &evergreen_ring_ib_execute, 857 .irq_set = &evergreen_irq_set, 858 .irq_process = &evergreen_irq_process, 859 .get_vblank_counter = &evergreen_get_vblank_counter, 860 .fence_ring_emit = &r600_fence_ring_emit, 861 .cs_parse = &evergreen_cs_parse, 862 .copy_blit = &evergreen_copy_blit, 863 .copy_dma = NULL, 864 .copy = &evergreen_copy_blit, 865 .get_engine_clock = &radeon_atom_get_engine_clock, 866 .set_engine_clock = &radeon_atom_set_engine_clock, 867 .get_memory_clock = &radeon_atom_get_memory_clock, 868 .set_memory_clock = &radeon_atom_set_memory_clock, 869 .get_pcie_lanes = NULL, 870 .set_pcie_lanes = NULL, 871 .set_clock_gating = NULL, 872 .set_surface_reg = r600_set_surface_reg, 873 .clear_surface_reg = r600_clear_surface_reg, 874 .bandwidth_update = &evergreen_bandwidth_update, 875 .hpd_init = &evergreen_hpd_init, 876 .hpd_fini = &evergreen_hpd_fini, 877 .hpd_sense = &evergreen_hpd_sense, 878 .hpd_set_polarity = &evergreen_hpd_set_polarity, 879 .ioctl_wait_idle = r600_ioctl_wait_idle, 880 .gui_idle = &r600_gui_idle, 881 .pm_misc = &evergreen_pm_misc, 882 .pm_prepare = &evergreen_pm_prepare, 883 .pm_finish = &evergreen_pm_finish, 884 .pm_init_profile = &r600_pm_init_profile, 885 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 886 .pre_page_flip = &evergreen_pre_page_flip, 887 .page_flip = &evergreen_page_flip, 888 .post_page_flip = &evergreen_post_page_flip, 889 }; 890 891 static struct radeon_asic cayman_asic = { 892 .init = &cayman_init, 893 .fini = &cayman_fini, 894 .suspend = &cayman_suspend, 895 .resume = &cayman_resume, 896 .cp_commit = &r600_cp_commit, 897 .gpu_is_lockup = &cayman_gpu_is_lockup, 898 .asic_reset = &cayman_asic_reset, 899 .vga_set_state = &r600_vga_set_state, 900 .gart_tlb_flush = &cayman_pcie_gart_tlb_flush, 901 .gart_set_page = &rs600_gart_set_page, 902 .ring_test = &r600_ring_test, 903 .ring_ib_execute = &evergreen_ring_ib_execute, 904 .irq_set = &evergreen_irq_set, 905 .irq_process = &evergreen_irq_process, 906 .get_vblank_counter = &evergreen_get_vblank_counter, 907 .fence_ring_emit = &r600_fence_ring_emit, 908 .cs_parse = &evergreen_cs_parse, 909 .copy_blit = &evergreen_copy_blit, 910 .copy_dma = NULL, 911 .copy = &evergreen_copy_blit, 912 .get_engine_clock = &radeon_atom_get_engine_clock, 913 .set_engine_clock = &radeon_atom_set_engine_clock, 914 .get_memory_clock = &radeon_atom_get_memory_clock, 915 .set_memory_clock = &radeon_atom_set_memory_clock, 916 .get_pcie_lanes = NULL, 917 .set_pcie_lanes = NULL, 918 .set_clock_gating = NULL, 919 .set_surface_reg = r600_set_surface_reg, 920 .clear_surface_reg = r600_clear_surface_reg, 921 .bandwidth_update = &evergreen_bandwidth_update, 922 .hpd_init = &evergreen_hpd_init, 923 .hpd_fini = &evergreen_hpd_fini, 924 .hpd_sense = &evergreen_hpd_sense, 925 .hpd_set_polarity = &evergreen_hpd_set_polarity, 926 .ioctl_wait_idle = r600_ioctl_wait_idle, 927 .gui_idle = &r600_gui_idle, 928 .pm_misc = &evergreen_pm_misc, 929 .pm_prepare = &evergreen_pm_prepare, 930 .pm_finish = &evergreen_pm_finish, 931 .pm_init_profile = &r600_pm_init_profile, 932 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 933 .pre_page_flip = &evergreen_pre_page_flip, 934 .page_flip = &evergreen_page_flip, 935 .post_page_flip = &evergreen_post_page_flip, 936 }; 937 938 int radeon_asic_init(struct radeon_device *rdev) 939 { 940 radeon_register_accessor_init(rdev); 941 942 /* set the number of crtcs */ 943 if (rdev->flags & RADEON_SINGLE_CRTC) 944 rdev->num_crtc = 1; 945 else 946 rdev->num_crtc = 2; 947 948 switch (rdev->family) { 949 case CHIP_R100: 950 case CHIP_RV100: 951 case CHIP_RS100: 952 case CHIP_RV200: 953 case CHIP_RS200: 954 rdev->asic = &r100_asic; 955 break; 956 case CHIP_R200: 957 case CHIP_RV250: 958 case CHIP_RS300: 959 case CHIP_RV280: 960 rdev->asic = &r200_asic; 961 break; 962 case CHIP_R300: 963 case CHIP_R350: 964 case CHIP_RV350: 965 case CHIP_RV380: 966 if (rdev->flags & RADEON_IS_PCIE) 967 rdev->asic = &r300_asic_pcie; 968 else 969 rdev->asic = &r300_asic; 970 break; 971 case CHIP_R420: 972 case CHIP_R423: 973 case CHIP_RV410: 974 rdev->asic = &r420_asic; 975 /* handle macs */ 976 if (rdev->bios == NULL) { 977 rdev->asic->get_engine_clock = &radeon_legacy_get_engine_clock; 978 rdev->asic->set_engine_clock = &radeon_legacy_set_engine_clock; 979 rdev->asic->get_memory_clock = &radeon_legacy_get_memory_clock; 980 rdev->asic->set_memory_clock = NULL; 981 } 982 break; 983 case CHIP_RS400: 984 case CHIP_RS480: 985 rdev->asic = &rs400_asic; 986 break; 987 case CHIP_RS600: 988 rdev->asic = &rs600_asic; 989 break; 990 case CHIP_RS690: 991 case CHIP_RS740: 992 rdev->asic = &rs690_asic; 993 break; 994 case CHIP_RV515: 995 rdev->asic = &rv515_asic; 996 break; 997 case CHIP_R520: 998 case CHIP_RV530: 999 case CHIP_RV560: 1000 case CHIP_RV570: 1001 case CHIP_R580: 1002 rdev->asic = &r520_asic; 1003 break; 1004 case CHIP_R600: 1005 case CHIP_RV610: 1006 case CHIP_RV630: 1007 case CHIP_RV620: 1008 case CHIP_RV635: 1009 case CHIP_RV670: 1010 rdev->asic = &r600_asic; 1011 break; 1012 case CHIP_RS780: 1013 case CHIP_RS880: 1014 rdev->asic = &rs780_asic; 1015 break; 1016 case CHIP_RV770: 1017 case CHIP_RV730: 1018 case CHIP_RV710: 1019 case CHIP_RV740: 1020 rdev->asic = &rv770_asic; 1021 break; 1022 case CHIP_CEDAR: 1023 case CHIP_REDWOOD: 1024 case CHIP_JUNIPER: 1025 case CHIP_CYPRESS: 1026 case CHIP_HEMLOCK: 1027 /* set num crtcs */ 1028 if (rdev->family == CHIP_CEDAR) 1029 rdev->num_crtc = 4; 1030 else 1031 rdev->num_crtc = 6; 1032 rdev->asic = &evergreen_asic; 1033 break; 1034 case CHIP_PALM: 1035 case CHIP_SUMO: 1036 case CHIP_SUMO2: 1037 rdev->asic = &sumo_asic; 1038 break; 1039 case CHIP_BARTS: 1040 case CHIP_TURKS: 1041 case CHIP_CAICOS: 1042 /* set num crtcs */ 1043 if (rdev->family == CHIP_CAICOS) 1044 rdev->num_crtc = 4; 1045 else 1046 rdev->num_crtc = 6; 1047 rdev->asic = &btc_asic; 1048 break; 1049 case CHIP_CAYMAN: 1050 rdev->asic = &cayman_asic; 1051 /* set num crtcs */ 1052 rdev->num_crtc = 6; 1053 break; 1054 default: 1055 /* FIXME: not supported yet */ 1056 return -EINVAL; 1057 } 1058 1059 if (rdev->flags & RADEON_IS_IGP) { 1060 rdev->asic->get_memory_clock = NULL; 1061 rdev->asic->set_memory_clock = NULL; 1062 } 1063 1064 return 0; 1065 } 1066 1067