1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/console.h> 30 #include <drm/drmP.h> 31 #include <drm/drm_crtc_helper.h> 32 #include <drm/radeon_drm.h> 33 #include <linux/vgaarb.h> 34 #include <linux/vga_switcheroo.h> 35 #include "radeon_reg.h" 36 #include "radeon.h" 37 #include "radeon_asic.h" 38 #include "atom.h" 39 40 /* 41 * Registers accessors functions. 42 */ 43 /** 44 * radeon_invalid_rreg - dummy reg read function 45 * 46 * @rdev: radeon device pointer 47 * @reg: offset of register 48 * 49 * Dummy register read function. Used for register blocks 50 * that certain asics don't have (all asics). 51 * Returns the value in the register. 52 */ 53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) 54 { 55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); 56 BUG_ON(1); 57 return 0; 58 } 59 60 /** 61 * radeon_invalid_wreg - dummy reg write function 62 * 63 * @rdev: radeon device pointer 64 * @reg: offset of register 65 * @v: value to write to the register 66 * 67 * Dummy register read function. Used for register blocks 68 * that certain asics don't have (all asics). 69 */ 70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 71 { 72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", 73 reg, v); 74 BUG_ON(1); 75 } 76 77 /** 78 * radeon_register_accessor_init - sets up the register accessor callbacks 79 * 80 * @rdev: radeon device pointer 81 * 82 * Sets up the register accessor callbacks for various register 83 * apertures. Not all asics have all apertures (all asics). 84 */ 85 static void radeon_register_accessor_init(struct radeon_device *rdev) 86 { 87 rdev->mc_rreg = &radeon_invalid_rreg; 88 rdev->mc_wreg = &radeon_invalid_wreg; 89 rdev->pll_rreg = &radeon_invalid_rreg; 90 rdev->pll_wreg = &radeon_invalid_wreg; 91 rdev->pciep_rreg = &radeon_invalid_rreg; 92 rdev->pciep_wreg = &radeon_invalid_wreg; 93 94 /* Don't change order as we are overridding accessor. */ 95 if (rdev->family < CHIP_RV515) { 96 rdev->pcie_reg_mask = 0xff; 97 } else { 98 rdev->pcie_reg_mask = 0x7ff; 99 } 100 /* FIXME: not sure here */ 101 if (rdev->family <= CHIP_R580) { 102 rdev->pll_rreg = &r100_pll_rreg; 103 rdev->pll_wreg = &r100_pll_wreg; 104 } 105 if (rdev->family >= CHIP_R420) { 106 rdev->mc_rreg = &r420_mc_rreg; 107 rdev->mc_wreg = &r420_mc_wreg; 108 } 109 if (rdev->family >= CHIP_RV515) { 110 rdev->mc_rreg = &rv515_mc_rreg; 111 rdev->mc_wreg = &rv515_mc_wreg; 112 } 113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { 114 rdev->mc_rreg = &rs400_mc_rreg; 115 rdev->mc_wreg = &rs400_mc_wreg; 116 } 117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 118 rdev->mc_rreg = &rs690_mc_rreg; 119 rdev->mc_wreg = &rs690_mc_wreg; 120 } 121 if (rdev->family == CHIP_RS600) { 122 rdev->mc_rreg = &rs600_mc_rreg; 123 rdev->mc_wreg = &rs600_mc_wreg; 124 } 125 if (rdev->family >= CHIP_R600) { 126 rdev->pciep_rreg = &r600_pciep_rreg; 127 rdev->pciep_wreg = &r600_pciep_wreg; 128 } 129 } 130 131 132 /* helper to disable agp */ 133 /** 134 * radeon_agp_disable - AGP disable helper function 135 * 136 * @rdev: radeon device pointer 137 * 138 * Removes AGP flags and changes the gart callbacks on AGP 139 * cards when using the internal gart rather than AGP (all asics). 140 */ 141 void radeon_agp_disable(struct radeon_device *rdev) 142 { 143 rdev->flags &= ~RADEON_IS_AGP; 144 if (rdev->family >= CHIP_R600) { 145 DRM_INFO("Forcing AGP to PCIE mode\n"); 146 rdev->flags |= RADEON_IS_PCIE; 147 } else if (rdev->family >= CHIP_RV515 || 148 rdev->family == CHIP_RV380 || 149 rdev->family == CHIP_RV410 || 150 rdev->family == CHIP_R423) { 151 DRM_INFO("Forcing AGP to PCIE mode\n"); 152 rdev->flags |= RADEON_IS_PCIE; 153 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 154 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 155 } else { 156 DRM_INFO("Forcing AGP to PCI mode\n"); 157 rdev->flags |= RADEON_IS_PCI; 158 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 159 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 160 } 161 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 162 } 163 164 /* 165 * ASIC 166 */ 167 static struct radeon_asic r100_asic = { 168 .init = &r100_init, 169 .fini = &r100_fini, 170 .suspend = &r100_suspend, 171 .resume = &r100_resume, 172 .vga_set_state = &r100_vga_set_state, 173 .asic_reset = &r100_asic_reset, 174 .ioctl_wait_idle = NULL, 175 .gui_idle = &r100_gui_idle, 176 .mc_wait_for_idle = &r100_mc_wait_for_idle, 177 .gart = { 178 .tlb_flush = &r100_pci_gart_tlb_flush, 179 .set_page = &r100_pci_gart_set_page, 180 }, 181 .ring = { 182 [RADEON_RING_TYPE_GFX_INDEX] = { 183 .ib_execute = &r100_ring_ib_execute, 184 .emit_fence = &r100_fence_ring_emit, 185 .emit_semaphore = &r100_semaphore_ring_emit, 186 .cs_parse = &r100_cs_parse, 187 .ring_start = &r100_ring_start, 188 .ring_test = &r100_ring_test, 189 .ib_test = &r100_ib_test, 190 .is_lockup = &r100_gpu_is_lockup, 191 } 192 }, 193 .irq = { 194 .set = &r100_irq_set, 195 .process = &r100_irq_process, 196 }, 197 .display = { 198 .bandwidth_update = &r100_bandwidth_update, 199 .get_vblank_counter = &r100_get_vblank_counter, 200 .wait_for_vblank = &r100_wait_for_vblank, 201 .set_backlight_level = &radeon_legacy_set_backlight_level, 202 .get_backlight_level = &radeon_legacy_get_backlight_level, 203 }, 204 .copy = { 205 .blit = &r100_copy_blit, 206 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 207 .dma = NULL, 208 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 209 .copy = &r100_copy_blit, 210 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 211 }, 212 .surface = { 213 .set_reg = r100_set_surface_reg, 214 .clear_reg = r100_clear_surface_reg, 215 }, 216 .hpd = { 217 .init = &r100_hpd_init, 218 .fini = &r100_hpd_fini, 219 .sense = &r100_hpd_sense, 220 .set_polarity = &r100_hpd_set_polarity, 221 }, 222 .pm = { 223 .misc = &r100_pm_misc, 224 .prepare = &r100_pm_prepare, 225 .finish = &r100_pm_finish, 226 .init_profile = &r100_pm_init_profile, 227 .get_dynpm_state = &r100_pm_get_dynpm_state, 228 .get_engine_clock = &radeon_legacy_get_engine_clock, 229 .set_engine_clock = &radeon_legacy_set_engine_clock, 230 .get_memory_clock = &radeon_legacy_get_memory_clock, 231 .set_memory_clock = NULL, 232 .get_pcie_lanes = NULL, 233 .set_pcie_lanes = NULL, 234 .set_clock_gating = &radeon_legacy_set_clock_gating, 235 }, 236 .pflip = { 237 .pre_page_flip = &r100_pre_page_flip, 238 .page_flip = &r100_page_flip, 239 .post_page_flip = &r100_post_page_flip, 240 }, 241 }; 242 243 static struct radeon_asic r200_asic = { 244 .init = &r100_init, 245 .fini = &r100_fini, 246 .suspend = &r100_suspend, 247 .resume = &r100_resume, 248 .vga_set_state = &r100_vga_set_state, 249 .asic_reset = &r100_asic_reset, 250 .ioctl_wait_idle = NULL, 251 .gui_idle = &r100_gui_idle, 252 .mc_wait_for_idle = &r100_mc_wait_for_idle, 253 .gart = { 254 .tlb_flush = &r100_pci_gart_tlb_flush, 255 .set_page = &r100_pci_gart_set_page, 256 }, 257 .ring = { 258 [RADEON_RING_TYPE_GFX_INDEX] = { 259 .ib_execute = &r100_ring_ib_execute, 260 .emit_fence = &r100_fence_ring_emit, 261 .emit_semaphore = &r100_semaphore_ring_emit, 262 .cs_parse = &r100_cs_parse, 263 .ring_start = &r100_ring_start, 264 .ring_test = &r100_ring_test, 265 .ib_test = &r100_ib_test, 266 .is_lockup = &r100_gpu_is_lockup, 267 } 268 }, 269 .irq = { 270 .set = &r100_irq_set, 271 .process = &r100_irq_process, 272 }, 273 .display = { 274 .bandwidth_update = &r100_bandwidth_update, 275 .get_vblank_counter = &r100_get_vblank_counter, 276 .wait_for_vblank = &r100_wait_for_vblank, 277 .set_backlight_level = &radeon_legacy_set_backlight_level, 278 .get_backlight_level = &radeon_legacy_get_backlight_level, 279 }, 280 .copy = { 281 .blit = &r100_copy_blit, 282 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 283 .dma = &r200_copy_dma, 284 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 285 .copy = &r100_copy_blit, 286 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 287 }, 288 .surface = { 289 .set_reg = r100_set_surface_reg, 290 .clear_reg = r100_clear_surface_reg, 291 }, 292 .hpd = { 293 .init = &r100_hpd_init, 294 .fini = &r100_hpd_fini, 295 .sense = &r100_hpd_sense, 296 .set_polarity = &r100_hpd_set_polarity, 297 }, 298 .pm = { 299 .misc = &r100_pm_misc, 300 .prepare = &r100_pm_prepare, 301 .finish = &r100_pm_finish, 302 .init_profile = &r100_pm_init_profile, 303 .get_dynpm_state = &r100_pm_get_dynpm_state, 304 .get_engine_clock = &radeon_legacy_get_engine_clock, 305 .set_engine_clock = &radeon_legacy_set_engine_clock, 306 .get_memory_clock = &radeon_legacy_get_memory_clock, 307 .set_memory_clock = NULL, 308 .get_pcie_lanes = NULL, 309 .set_pcie_lanes = NULL, 310 .set_clock_gating = &radeon_legacy_set_clock_gating, 311 }, 312 .pflip = { 313 .pre_page_flip = &r100_pre_page_flip, 314 .page_flip = &r100_page_flip, 315 .post_page_flip = &r100_post_page_flip, 316 }, 317 }; 318 319 static struct radeon_asic r300_asic = { 320 .init = &r300_init, 321 .fini = &r300_fini, 322 .suspend = &r300_suspend, 323 .resume = &r300_resume, 324 .vga_set_state = &r100_vga_set_state, 325 .asic_reset = &r300_asic_reset, 326 .ioctl_wait_idle = NULL, 327 .gui_idle = &r100_gui_idle, 328 .mc_wait_for_idle = &r300_mc_wait_for_idle, 329 .gart = { 330 .tlb_flush = &r100_pci_gart_tlb_flush, 331 .set_page = &r100_pci_gart_set_page, 332 }, 333 .ring = { 334 [RADEON_RING_TYPE_GFX_INDEX] = { 335 .ib_execute = &r100_ring_ib_execute, 336 .emit_fence = &r300_fence_ring_emit, 337 .emit_semaphore = &r100_semaphore_ring_emit, 338 .cs_parse = &r300_cs_parse, 339 .ring_start = &r300_ring_start, 340 .ring_test = &r100_ring_test, 341 .ib_test = &r100_ib_test, 342 .is_lockup = &r100_gpu_is_lockup, 343 } 344 }, 345 .irq = { 346 .set = &r100_irq_set, 347 .process = &r100_irq_process, 348 }, 349 .display = { 350 .bandwidth_update = &r100_bandwidth_update, 351 .get_vblank_counter = &r100_get_vblank_counter, 352 .wait_for_vblank = &r100_wait_for_vblank, 353 .set_backlight_level = &radeon_legacy_set_backlight_level, 354 .get_backlight_level = &radeon_legacy_get_backlight_level, 355 }, 356 .copy = { 357 .blit = &r100_copy_blit, 358 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 359 .dma = &r200_copy_dma, 360 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 361 .copy = &r100_copy_blit, 362 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 363 }, 364 .surface = { 365 .set_reg = r100_set_surface_reg, 366 .clear_reg = r100_clear_surface_reg, 367 }, 368 .hpd = { 369 .init = &r100_hpd_init, 370 .fini = &r100_hpd_fini, 371 .sense = &r100_hpd_sense, 372 .set_polarity = &r100_hpd_set_polarity, 373 }, 374 .pm = { 375 .misc = &r100_pm_misc, 376 .prepare = &r100_pm_prepare, 377 .finish = &r100_pm_finish, 378 .init_profile = &r100_pm_init_profile, 379 .get_dynpm_state = &r100_pm_get_dynpm_state, 380 .get_engine_clock = &radeon_legacy_get_engine_clock, 381 .set_engine_clock = &radeon_legacy_set_engine_clock, 382 .get_memory_clock = &radeon_legacy_get_memory_clock, 383 .set_memory_clock = NULL, 384 .get_pcie_lanes = &rv370_get_pcie_lanes, 385 .set_pcie_lanes = &rv370_set_pcie_lanes, 386 .set_clock_gating = &radeon_legacy_set_clock_gating, 387 }, 388 .pflip = { 389 .pre_page_flip = &r100_pre_page_flip, 390 .page_flip = &r100_page_flip, 391 .post_page_flip = &r100_post_page_flip, 392 }, 393 }; 394 395 static struct radeon_asic r300_asic_pcie = { 396 .init = &r300_init, 397 .fini = &r300_fini, 398 .suspend = &r300_suspend, 399 .resume = &r300_resume, 400 .vga_set_state = &r100_vga_set_state, 401 .asic_reset = &r300_asic_reset, 402 .ioctl_wait_idle = NULL, 403 .gui_idle = &r100_gui_idle, 404 .mc_wait_for_idle = &r300_mc_wait_for_idle, 405 .gart = { 406 .tlb_flush = &rv370_pcie_gart_tlb_flush, 407 .set_page = &rv370_pcie_gart_set_page, 408 }, 409 .ring = { 410 [RADEON_RING_TYPE_GFX_INDEX] = { 411 .ib_execute = &r100_ring_ib_execute, 412 .emit_fence = &r300_fence_ring_emit, 413 .emit_semaphore = &r100_semaphore_ring_emit, 414 .cs_parse = &r300_cs_parse, 415 .ring_start = &r300_ring_start, 416 .ring_test = &r100_ring_test, 417 .ib_test = &r100_ib_test, 418 .is_lockup = &r100_gpu_is_lockup, 419 } 420 }, 421 .irq = { 422 .set = &r100_irq_set, 423 .process = &r100_irq_process, 424 }, 425 .display = { 426 .bandwidth_update = &r100_bandwidth_update, 427 .get_vblank_counter = &r100_get_vblank_counter, 428 .wait_for_vblank = &r100_wait_for_vblank, 429 .set_backlight_level = &radeon_legacy_set_backlight_level, 430 .get_backlight_level = &radeon_legacy_get_backlight_level, 431 }, 432 .copy = { 433 .blit = &r100_copy_blit, 434 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 435 .dma = &r200_copy_dma, 436 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 437 .copy = &r100_copy_blit, 438 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 439 }, 440 .surface = { 441 .set_reg = r100_set_surface_reg, 442 .clear_reg = r100_clear_surface_reg, 443 }, 444 .hpd = { 445 .init = &r100_hpd_init, 446 .fini = &r100_hpd_fini, 447 .sense = &r100_hpd_sense, 448 .set_polarity = &r100_hpd_set_polarity, 449 }, 450 .pm = { 451 .misc = &r100_pm_misc, 452 .prepare = &r100_pm_prepare, 453 .finish = &r100_pm_finish, 454 .init_profile = &r100_pm_init_profile, 455 .get_dynpm_state = &r100_pm_get_dynpm_state, 456 .get_engine_clock = &radeon_legacy_get_engine_clock, 457 .set_engine_clock = &radeon_legacy_set_engine_clock, 458 .get_memory_clock = &radeon_legacy_get_memory_clock, 459 .set_memory_clock = NULL, 460 .get_pcie_lanes = &rv370_get_pcie_lanes, 461 .set_pcie_lanes = &rv370_set_pcie_lanes, 462 .set_clock_gating = &radeon_legacy_set_clock_gating, 463 }, 464 .pflip = { 465 .pre_page_flip = &r100_pre_page_flip, 466 .page_flip = &r100_page_flip, 467 .post_page_flip = &r100_post_page_flip, 468 }, 469 }; 470 471 static struct radeon_asic r420_asic = { 472 .init = &r420_init, 473 .fini = &r420_fini, 474 .suspend = &r420_suspend, 475 .resume = &r420_resume, 476 .vga_set_state = &r100_vga_set_state, 477 .asic_reset = &r300_asic_reset, 478 .ioctl_wait_idle = NULL, 479 .gui_idle = &r100_gui_idle, 480 .mc_wait_for_idle = &r300_mc_wait_for_idle, 481 .gart = { 482 .tlb_flush = &rv370_pcie_gart_tlb_flush, 483 .set_page = &rv370_pcie_gart_set_page, 484 }, 485 .ring = { 486 [RADEON_RING_TYPE_GFX_INDEX] = { 487 .ib_execute = &r100_ring_ib_execute, 488 .emit_fence = &r300_fence_ring_emit, 489 .emit_semaphore = &r100_semaphore_ring_emit, 490 .cs_parse = &r300_cs_parse, 491 .ring_start = &r300_ring_start, 492 .ring_test = &r100_ring_test, 493 .ib_test = &r100_ib_test, 494 .is_lockup = &r100_gpu_is_lockup, 495 } 496 }, 497 .irq = { 498 .set = &r100_irq_set, 499 .process = &r100_irq_process, 500 }, 501 .display = { 502 .bandwidth_update = &r100_bandwidth_update, 503 .get_vblank_counter = &r100_get_vblank_counter, 504 .wait_for_vblank = &r100_wait_for_vblank, 505 .set_backlight_level = &atombios_set_backlight_level, 506 .get_backlight_level = &atombios_get_backlight_level, 507 }, 508 .copy = { 509 .blit = &r100_copy_blit, 510 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 511 .dma = &r200_copy_dma, 512 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 513 .copy = &r100_copy_blit, 514 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 515 }, 516 .surface = { 517 .set_reg = r100_set_surface_reg, 518 .clear_reg = r100_clear_surface_reg, 519 }, 520 .hpd = { 521 .init = &r100_hpd_init, 522 .fini = &r100_hpd_fini, 523 .sense = &r100_hpd_sense, 524 .set_polarity = &r100_hpd_set_polarity, 525 }, 526 .pm = { 527 .misc = &r100_pm_misc, 528 .prepare = &r100_pm_prepare, 529 .finish = &r100_pm_finish, 530 .init_profile = &r420_pm_init_profile, 531 .get_dynpm_state = &r100_pm_get_dynpm_state, 532 .get_engine_clock = &radeon_atom_get_engine_clock, 533 .set_engine_clock = &radeon_atom_set_engine_clock, 534 .get_memory_clock = &radeon_atom_get_memory_clock, 535 .set_memory_clock = &radeon_atom_set_memory_clock, 536 .get_pcie_lanes = &rv370_get_pcie_lanes, 537 .set_pcie_lanes = &rv370_set_pcie_lanes, 538 .set_clock_gating = &radeon_atom_set_clock_gating, 539 }, 540 .pflip = { 541 .pre_page_flip = &r100_pre_page_flip, 542 .page_flip = &r100_page_flip, 543 .post_page_flip = &r100_post_page_flip, 544 }, 545 }; 546 547 static struct radeon_asic rs400_asic = { 548 .init = &rs400_init, 549 .fini = &rs400_fini, 550 .suspend = &rs400_suspend, 551 .resume = &rs400_resume, 552 .vga_set_state = &r100_vga_set_state, 553 .asic_reset = &r300_asic_reset, 554 .ioctl_wait_idle = NULL, 555 .gui_idle = &r100_gui_idle, 556 .mc_wait_for_idle = &rs400_mc_wait_for_idle, 557 .gart = { 558 .tlb_flush = &rs400_gart_tlb_flush, 559 .set_page = &rs400_gart_set_page, 560 }, 561 .ring = { 562 [RADEON_RING_TYPE_GFX_INDEX] = { 563 .ib_execute = &r100_ring_ib_execute, 564 .emit_fence = &r300_fence_ring_emit, 565 .emit_semaphore = &r100_semaphore_ring_emit, 566 .cs_parse = &r300_cs_parse, 567 .ring_start = &r300_ring_start, 568 .ring_test = &r100_ring_test, 569 .ib_test = &r100_ib_test, 570 .is_lockup = &r100_gpu_is_lockup, 571 } 572 }, 573 .irq = { 574 .set = &r100_irq_set, 575 .process = &r100_irq_process, 576 }, 577 .display = { 578 .bandwidth_update = &r100_bandwidth_update, 579 .get_vblank_counter = &r100_get_vblank_counter, 580 .wait_for_vblank = &r100_wait_for_vblank, 581 .set_backlight_level = &radeon_legacy_set_backlight_level, 582 .get_backlight_level = &radeon_legacy_get_backlight_level, 583 }, 584 .copy = { 585 .blit = &r100_copy_blit, 586 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 587 .dma = &r200_copy_dma, 588 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 589 .copy = &r100_copy_blit, 590 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 591 }, 592 .surface = { 593 .set_reg = r100_set_surface_reg, 594 .clear_reg = r100_clear_surface_reg, 595 }, 596 .hpd = { 597 .init = &r100_hpd_init, 598 .fini = &r100_hpd_fini, 599 .sense = &r100_hpd_sense, 600 .set_polarity = &r100_hpd_set_polarity, 601 }, 602 .pm = { 603 .misc = &r100_pm_misc, 604 .prepare = &r100_pm_prepare, 605 .finish = &r100_pm_finish, 606 .init_profile = &r100_pm_init_profile, 607 .get_dynpm_state = &r100_pm_get_dynpm_state, 608 .get_engine_clock = &radeon_legacy_get_engine_clock, 609 .set_engine_clock = &radeon_legacy_set_engine_clock, 610 .get_memory_clock = &radeon_legacy_get_memory_clock, 611 .set_memory_clock = NULL, 612 .get_pcie_lanes = NULL, 613 .set_pcie_lanes = NULL, 614 .set_clock_gating = &radeon_legacy_set_clock_gating, 615 }, 616 .pflip = { 617 .pre_page_flip = &r100_pre_page_flip, 618 .page_flip = &r100_page_flip, 619 .post_page_flip = &r100_post_page_flip, 620 }, 621 }; 622 623 static struct radeon_asic rs600_asic = { 624 .init = &rs600_init, 625 .fini = &rs600_fini, 626 .suspend = &rs600_suspend, 627 .resume = &rs600_resume, 628 .vga_set_state = &r100_vga_set_state, 629 .asic_reset = &rs600_asic_reset, 630 .ioctl_wait_idle = NULL, 631 .gui_idle = &r100_gui_idle, 632 .mc_wait_for_idle = &rs600_mc_wait_for_idle, 633 .gart = { 634 .tlb_flush = &rs600_gart_tlb_flush, 635 .set_page = &rs600_gart_set_page, 636 }, 637 .ring = { 638 [RADEON_RING_TYPE_GFX_INDEX] = { 639 .ib_execute = &r100_ring_ib_execute, 640 .emit_fence = &r300_fence_ring_emit, 641 .emit_semaphore = &r100_semaphore_ring_emit, 642 .cs_parse = &r300_cs_parse, 643 .ring_start = &r300_ring_start, 644 .ring_test = &r100_ring_test, 645 .ib_test = &r100_ib_test, 646 .is_lockup = &r100_gpu_is_lockup, 647 } 648 }, 649 .irq = { 650 .set = &rs600_irq_set, 651 .process = &rs600_irq_process, 652 }, 653 .display = { 654 .bandwidth_update = &rs600_bandwidth_update, 655 .get_vblank_counter = &rs600_get_vblank_counter, 656 .wait_for_vblank = &avivo_wait_for_vblank, 657 .set_backlight_level = &atombios_set_backlight_level, 658 .get_backlight_level = &atombios_get_backlight_level, 659 }, 660 .copy = { 661 .blit = &r100_copy_blit, 662 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 663 .dma = &r200_copy_dma, 664 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 665 .copy = &r100_copy_blit, 666 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 667 }, 668 .surface = { 669 .set_reg = r100_set_surface_reg, 670 .clear_reg = r100_clear_surface_reg, 671 }, 672 .hpd = { 673 .init = &rs600_hpd_init, 674 .fini = &rs600_hpd_fini, 675 .sense = &rs600_hpd_sense, 676 .set_polarity = &rs600_hpd_set_polarity, 677 }, 678 .pm = { 679 .misc = &rs600_pm_misc, 680 .prepare = &rs600_pm_prepare, 681 .finish = &rs600_pm_finish, 682 .init_profile = &r420_pm_init_profile, 683 .get_dynpm_state = &r100_pm_get_dynpm_state, 684 .get_engine_clock = &radeon_atom_get_engine_clock, 685 .set_engine_clock = &radeon_atom_set_engine_clock, 686 .get_memory_clock = &radeon_atom_get_memory_clock, 687 .set_memory_clock = &radeon_atom_set_memory_clock, 688 .get_pcie_lanes = NULL, 689 .set_pcie_lanes = NULL, 690 .set_clock_gating = &radeon_atom_set_clock_gating, 691 }, 692 .pflip = { 693 .pre_page_flip = &rs600_pre_page_flip, 694 .page_flip = &rs600_page_flip, 695 .post_page_flip = &rs600_post_page_flip, 696 }, 697 }; 698 699 static struct radeon_asic rs690_asic = { 700 .init = &rs690_init, 701 .fini = &rs690_fini, 702 .suspend = &rs690_suspend, 703 .resume = &rs690_resume, 704 .vga_set_state = &r100_vga_set_state, 705 .asic_reset = &rs600_asic_reset, 706 .ioctl_wait_idle = NULL, 707 .gui_idle = &r100_gui_idle, 708 .mc_wait_for_idle = &rs690_mc_wait_for_idle, 709 .gart = { 710 .tlb_flush = &rs400_gart_tlb_flush, 711 .set_page = &rs400_gart_set_page, 712 }, 713 .ring = { 714 [RADEON_RING_TYPE_GFX_INDEX] = { 715 .ib_execute = &r100_ring_ib_execute, 716 .emit_fence = &r300_fence_ring_emit, 717 .emit_semaphore = &r100_semaphore_ring_emit, 718 .cs_parse = &r300_cs_parse, 719 .ring_start = &r300_ring_start, 720 .ring_test = &r100_ring_test, 721 .ib_test = &r100_ib_test, 722 .is_lockup = &r100_gpu_is_lockup, 723 } 724 }, 725 .irq = { 726 .set = &rs600_irq_set, 727 .process = &rs600_irq_process, 728 }, 729 .display = { 730 .get_vblank_counter = &rs600_get_vblank_counter, 731 .bandwidth_update = &rs690_bandwidth_update, 732 .wait_for_vblank = &avivo_wait_for_vblank, 733 .set_backlight_level = &atombios_set_backlight_level, 734 .get_backlight_level = &atombios_get_backlight_level, 735 }, 736 .copy = { 737 .blit = &r100_copy_blit, 738 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 739 .dma = &r200_copy_dma, 740 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 741 .copy = &r200_copy_dma, 742 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 743 }, 744 .surface = { 745 .set_reg = r100_set_surface_reg, 746 .clear_reg = r100_clear_surface_reg, 747 }, 748 .hpd = { 749 .init = &rs600_hpd_init, 750 .fini = &rs600_hpd_fini, 751 .sense = &rs600_hpd_sense, 752 .set_polarity = &rs600_hpd_set_polarity, 753 }, 754 .pm = { 755 .misc = &rs600_pm_misc, 756 .prepare = &rs600_pm_prepare, 757 .finish = &rs600_pm_finish, 758 .init_profile = &r420_pm_init_profile, 759 .get_dynpm_state = &r100_pm_get_dynpm_state, 760 .get_engine_clock = &radeon_atom_get_engine_clock, 761 .set_engine_clock = &radeon_atom_set_engine_clock, 762 .get_memory_clock = &radeon_atom_get_memory_clock, 763 .set_memory_clock = &radeon_atom_set_memory_clock, 764 .get_pcie_lanes = NULL, 765 .set_pcie_lanes = NULL, 766 .set_clock_gating = &radeon_atom_set_clock_gating, 767 }, 768 .pflip = { 769 .pre_page_flip = &rs600_pre_page_flip, 770 .page_flip = &rs600_page_flip, 771 .post_page_flip = &rs600_post_page_flip, 772 }, 773 }; 774 775 static struct radeon_asic rv515_asic = { 776 .init = &rv515_init, 777 .fini = &rv515_fini, 778 .suspend = &rv515_suspend, 779 .resume = &rv515_resume, 780 .vga_set_state = &r100_vga_set_state, 781 .asic_reset = &rs600_asic_reset, 782 .ioctl_wait_idle = NULL, 783 .gui_idle = &r100_gui_idle, 784 .mc_wait_for_idle = &rv515_mc_wait_for_idle, 785 .gart = { 786 .tlb_flush = &rv370_pcie_gart_tlb_flush, 787 .set_page = &rv370_pcie_gart_set_page, 788 }, 789 .ring = { 790 [RADEON_RING_TYPE_GFX_INDEX] = { 791 .ib_execute = &r100_ring_ib_execute, 792 .emit_fence = &r300_fence_ring_emit, 793 .emit_semaphore = &r100_semaphore_ring_emit, 794 .cs_parse = &r300_cs_parse, 795 .ring_start = &rv515_ring_start, 796 .ring_test = &r100_ring_test, 797 .ib_test = &r100_ib_test, 798 .is_lockup = &r100_gpu_is_lockup, 799 } 800 }, 801 .irq = { 802 .set = &rs600_irq_set, 803 .process = &rs600_irq_process, 804 }, 805 .display = { 806 .get_vblank_counter = &rs600_get_vblank_counter, 807 .bandwidth_update = &rv515_bandwidth_update, 808 .wait_for_vblank = &avivo_wait_for_vblank, 809 .set_backlight_level = &atombios_set_backlight_level, 810 .get_backlight_level = &atombios_get_backlight_level, 811 }, 812 .copy = { 813 .blit = &r100_copy_blit, 814 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 815 .dma = &r200_copy_dma, 816 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 817 .copy = &r100_copy_blit, 818 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 819 }, 820 .surface = { 821 .set_reg = r100_set_surface_reg, 822 .clear_reg = r100_clear_surface_reg, 823 }, 824 .hpd = { 825 .init = &rs600_hpd_init, 826 .fini = &rs600_hpd_fini, 827 .sense = &rs600_hpd_sense, 828 .set_polarity = &rs600_hpd_set_polarity, 829 }, 830 .pm = { 831 .misc = &rs600_pm_misc, 832 .prepare = &rs600_pm_prepare, 833 .finish = &rs600_pm_finish, 834 .init_profile = &r420_pm_init_profile, 835 .get_dynpm_state = &r100_pm_get_dynpm_state, 836 .get_engine_clock = &radeon_atom_get_engine_clock, 837 .set_engine_clock = &radeon_atom_set_engine_clock, 838 .get_memory_clock = &radeon_atom_get_memory_clock, 839 .set_memory_clock = &radeon_atom_set_memory_clock, 840 .get_pcie_lanes = &rv370_get_pcie_lanes, 841 .set_pcie_lanes = &rv370_set_pcie_lanes, 842 .set_clock_gating = &radeon_atom_set_clock_gating, 843 }, 844 .pflip = { 845 .pre_page_flip = &rs600_pre_page_flip, 846 .page_flip = &rs600_page_flip, 847 .post_page_flip = &rs600_post_page_flip, 848 }, 849 }; 850 851 static struct radeon_asic r520_asic = { 852 .init = &r520_init, 853 .fini = &rv515_fini, 854 .suspend = &rv515_suspend, 855 .resume = &r520_resume, 856 .vga_set_state = &r100_vga_set_state, 857 .asic_reset = &rs600_asic_reset, 858 .ioctl_wait_idle = NULL, 859 .gui_idle = &r100_gui_idle, 860 .mc_wait_for_idle = &r520_mc_wait_for_idle, 861 .gart = { 862 .tlb_flush = &rv370_pcie_gart_tlb_flush, 863 .set_page = &rv370_pcie_gart_set_page, 864 }, 865 .ring = { 866 [RADEON_RING_TYPE_GFX_INDEX] = { 867 .ib_execute = &r100_ring_ib_execute, 868 .emit_fence = &r300_fence_ring_emit, 869 .emit_semaphore = &r100_semaphore_ring_emit, 870 .cs_parse = &r300_cs_parse, 871 .ring_start = &rv515_ring_start, 872 .ring_test = &r100_ring_test, 873 .ib_test = &r100_ib_test, 874 .is_lockup = &r100_gpu_is_lockup, 875 } 876 }, 877 .irq = { 878 .set = &rs600_irq_set, 879 .process = &rs600_irq_process, 880 }, 881 .display = { 882 .bandwidth_update = &rv515_bandwidth_update, 883 .get_vblank_counter = &rs600_get_vblank_counter, 884 .wait_for_vblank = &avivo_wait_for_vblank, 885 .set_backlight_level = &atombios_set_backlight_level, 886 .get_backlight_level = &atombios_get_backlight_level, 887 }, 888 .copy = { 889 .blit = &r100_copy_blit, 890 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 891 .dma = &r200_copy_dma, 892 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 893 .copy = &r100_copy_blit, 894 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 895 }, 896 .surface = { 897 .set_reg = r100_set_surface_reg, 898 .clear_reg = r100_clear_surface_reg, 899 }, 900 .hpd = { 901 .init = &rs600_hpd_init, 902 .fini = &rs600_hpd_fini, 903 .sense = &rs600_hpd_sense, 904 .set_polarity = &rs600_hpd_set_polarity, 905 }, 906 .pm = { 907 .misc = &rs600_pm_misc, 908 .prepare = &rs600_pm_prepare, 909 .finish = &rs600_pm_finish, 910 .init_profile = &r420_pm_init_profile, 911 .get_dynpm_state = &r100_pm_get_dynpm_state, 912 .get_engine_clock = &radeon_atom_get_engine_clock, 913 .set_engine_clock = &radeon_atom_set_engine_clock, 914 .get_memory_clock = &radeon_atom_get_memory_clock, 915 .set_memory_clock = &radeon_atom_set_memory_clock, 916 .get_pcie_lanes = &rv370_get_pcie_lanes, 917 .set_pcie_lanes = &rv370_set_pcie_lanes, 918 .set_clock_gating = &radeon_atom_set_clock_gating, 919 }, 920 .pflip = { 921 .pre_page_flip = &rs600_pre_page_flip, 922 .page_flip = &rs600_page_flip, 923 .post_page_flip = &rs600_post_page_flip, 924 }, 925 }; 926 927 static struct radeon_asic r600_asic = { 928 .init = &r600_init, 929 .fini = &r600_fini, 930 .suspend = &r600_suspend, 931 .resume = &r600_resume, 932 .vga_set_state = &r600_vga_set_state, 933 .asic_reset = &r600_asic_reset, 934 .ioctl_wait_idle = r600_ioctl_wait_idle, 935 .gui_idle = &r600_gui_idle, 936 .mc_wait_for_idle = &r600_mc_wait_for_idle, 937 .get_xclk = &r600_get_xclk, 938 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 939 .gart = { 940 .tlb_flush = &r600_pcie_gart_tlb_flush, 941 .set_page = &rs600_gart_set_page, 942 }, 943 .ring = { 944 [RADEON_RING_TYPE_GFX_INDEX] = { 945 .ib_execute = &r600_ring_ib_execute, 946 .emit_fence = &r600_fence_ring_emit, 947 .emit_semaphore = &r600_semaphore_ring_emit, 948 .cs_parse = &r600_cs_parse, 949 .ring_test = &r600_ring_test, 950 .ib_test = &r600_ib_test, 951 .is_lockup = &r600_gfx_is_lockup, 952 }, 953 [R600_RING_TYPE_DMA_INDEX] = { 954 .ib_execute = &r600_dma_ring_ib_execute, 955 .emit_fence = &r600_dma_fence_ring_emit, 956 .emit_semaphore = &r600_dma_semaphore_ring_emit, 957 .cs_parse = &r600_dma_cs_parse, 958 .ring_test = &r600_dma_ring_test, 959 .ib_test = &r600_dma_ib_test, 960 .is_lockup = &r600_dma_is_lockup, 961 } 962 }, 963 .irq = { 964 .set = &r600_irq_set, 965 .process = &r600_irq_process, 966 }, 967 .display = { 968 .bandwidth_update = &rv515_bandwidth_update, 969 .get_vblank_counter = &rs600_get_vblank_counter, 970 .wait_for_vblank = &avivo_wait_for_vblank, 971 .set_backlight_level = &atombios_set_backlight_level, 972 .get_backlight_level = &atombios_get_backlight_level, 973 }, 974 .copy = { 975 .blit = &r600_copy_blit, 976 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 977 .dma = &r600_copy_dma, 978 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 979 .copy = &r600_copy_dma, 980 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 981 }, 982 .surface = { 983 .set_reg = r600_set_surface_reg, 984 .clear_reg = r600_clear_surface_reg, 985 }, 986 .hpd = { 987 .init = &r600_hpd_init, 988 .fini = &r600_hpd_fini, 989 .sense = &r600_hpd_sense, 990 .set_polarity = &r600_hpd_set_polarity, 991 }, 992 .pm = { 993 .misc = &r600_pm_misc, 994 .prepare = &rs600_pm_prepare, 995 .finish = &rs600_pm_finish, 996 .init_profile = &r600_pm_init_profile, 997 .get_dynpm_state = &r600_pm_get_dynpm_state, 998 .get_engine_clock = &radeon_atom_get_engine_clock, 999 .set_engine_clock = &radeon_atom_set_engine_clock, 1000 .get_memory_clock = &radeon_atom_get_memory_clock, 1001 .set_memory_clock = &radeon_atom_set_memory_clock, 1002 .get_pcie_lanes = &r600_get_pcie_lanes, 1003 .set_pcie_lanes = &r600_set_pcie_lanes, 1004 .set_clock_gating = NULL, 1005 }, 1006 .pflip = { 1007 .pre_page_flip = &rs600_pre_page_flip, 1008 .page_flip = &rs600_page_flip, 1009 .post_page_flip = &rs600_post_page_flip, 1010 }, 1011 }; 1012 1013 static struct radeon_asic rs780_asic = { 1014 .init = &r600_init, 1015 .fini = &r600_fini, 1016 .suspend = &r600_suspend, 1017 .resume = &r600_resume, 1018 .vga_set_state = &r600_vga_set_state, 1019 .asic_reset = &r600_asic_reset, 1020 .ioctl_wait_idle = r600_ioctl_wait_idle, 1021 .gui_idle = &r600_gui_idle, 1022 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1023 .get_xclk = &r600_get_xclk, 1024 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1025 .gart = { 1026 .tlb_flush = &r600_pcie_gart_tlb_flush, 1027 .set_page = &rs600_gart_set_page, 1028 }, 1029 .ring = { 1030 [RADEON_RING_TYPE_GFX_INDEX] = { 1031 .ib_execute = &r600_ring_ib_execute, 1032 .emit_fence = &r600_fence_ring_emit, 1033 .emit_semaphore = &r600_semaphore_ring_emit, 1034 .cs_parse = &r600_cs_parse, 1035 .ring_test = &r600_ring_test, 1036 .ib_test = &r600_ib_test, 1037 .is_lockup = &r600_gfx_is_lockup, 1038 }, 1039 [R600_RING_TYPE_DMA_INDEX] = { 1040 .ib_execute = &r600_dma_ring_ib_execute, 1041 .emit_fence = &r600_dma_fence_ring_emit, 1042 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1043 .cs_parse = &r600_dma_cs_parse, 1044 .ring_test = &r600_dma_ring_test, 1045 .ib_test = &r600_dma_ib_test, 1046 .is_lockup = &r600_dma_is_lockup, 1047 } 1048 }, 1049 .irq = { 1050 .set = &r600_irq_set, 1051 .process = &r600_irq_process, 1052 }, 1053 .display = { 1054 .bandwidth_update = &rs690_bandwidth_update, 1055 .get_vblank_counter = &rs600_get_vblank_counter, 1056 .wait_for_vblank = &avivo_wait_for_vblank, 1057 .set_backlight_level = &atombios_set_backlight_level, 1058 .get_backlight_level = &atombios_get_backlight_level, 1059 }, 1060 .copy = { 1061 .blit = &r600_copy_blit, 1062 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1063 .dma = &r600_copy_dma, 1064 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1065 .copy = &r600_copy_dma, 1066 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1067 }, 1068 .surface = { 1069 .set_reg = r600_set_surface_reg, 1070 .clear_reg = r600_clear_surface_reg, 1071 }, 1072 .hpd = { 1073 .init = &r600_hpd_init, 1074 .fini = &r600_hpd_fini, 1075 .sense = &r600_hpd_sense, 1076 .set_polarity = &r600_hpd_set_polarity, 1077 }, 1078 .pm = { 1079 .misc = &r600_pm_misc, 1080 .prepare = &rs600_pm_prepare, 1081 .finish = &rs600_pm_finish, 1082 .init_profile = &rs780_pm_init_profile, 1083 .get_dynpm_state = &r600_pm_get_dynpm_state, 1084 .get_engine_clock = &radeon_atom_get_engine_clock, 1085 .set_engine_clock = &radeon_atom_set_engine_clock, 1086 .get_memory_clock = NULL, 1087 .set_memory_clock = NULL, 1088 .get_pcie_lanes = NULL, 1089 .set_pcie_lanes = NULL, 1090 .set_clock_gating = NULL, 1091 }, 1092 .pflip = { 1093 .pre_page_flip = &rs600_pre_page_flip, 1094 .page_flip = &rs600_page_flip, 1095 .post_page_flip = &rs600_post_page_flip, 1096 }, 1097 }; 1098 1099 static struct radeon_asic rv770_asic = { 1100 .init = &rv770_init, 1101 .fini = &rv770_fini, 1102 .suspend = &rv770_suspend, 1103 .resume = &rv770_resume, 1104 .asic_reset = &r600_asic_reset, 1105 .vga_set_state = &r600_vga_set_state, 1106 .ioctl_wait_idle = r600_ioctl_wait_idle, 1107 .gui_idle = &r600_gui_idle, 1108 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1109 .get_xclk = &rv770_get_xclk, 1110 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1111 .gart = { 1112 .tlb_flush = &r600_pcie_gart_tlb_flush, 1113 .set_page = &rs600_gart_set_page, 1114 }, 1115 .ring = { 1116 [RADEON_RING_TYPE_GFX_INDEX] = { 1117 .ib_execute = &r600_ring_ib_execute, 1118 .emit_fence = &r600_fence_ring_emit, 1119 .emit_semaphore = &r600_semaphore_ring_emit, 1120 .cs_parse = &r600_cs_parse, 1121 .ring_test = &r600_ring_test, 1122 .ib_test = &r600_ib_test, 1123 .is_lockup = &r600_gfx_is_lockup, 1124 }, 1125 [R600_RING_TYPE_DMA_INDEX] = { 1126 .ib_execute = &r600_dma_ring_ib_execute, 1127 .emit_fence = &r600_dma_fence_ring_emit, 1128 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1129 .cs_parse = &r600_dma_cs_parse, 1130 .ring_test = &r600_dma_ring_test, 1131 .ib_test = &r600_dma_ib_test, 1132 .is_lockup = &r600_dma_is_lockup, 1133 } 1134 }, 1135 .irq = { 1136 .set = &r600_irq_set, 1137 .process = &r600_irq_process, 1138 }, 1139 .display = { 1140 .bandwidth_update = &rv515_bandwidth_update, 1141 .get_vblank_counter = &rs600_get_vblank_counter, 1142 .wait_for_vblank = &avivo_wait_for_vblank, 1143 .set_backlight_level = &atombios_set_backlight_level, 1144 .get_backlight_level = &atombios_get_backlight_level, 1145 }, 1146 .copy = { 1147 .blit = &r600_copy_blit, 1148 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1149 .dma = &rv770_copy_dma, 1150 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1151 .copy = &rv770_copy_dma, 1152 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1153 }, 1154 .surface = { 1155 .set_reg = r600_set_surface_reg, 1156 .clear_reg = r600_clear_surface_reg, 1157 }, 1158 .hpd = { 1159 .init = &r600_hpd_init, 1160 .fini = &r600_hpd_fini, 1161 .sense = &r600_hpd_sense, 1162 .set_polarity = &r600_hpd_set_polarity, 1163 }, 1164 .pm = { 1165 .misc = &rv770_pm_misc, 1166 .prepare = &rs600_pm_prepare, 1167 .finish = &rs600_pm_finish, 1168 .init_profile = &r600_pm_init_profile, 1169 .get_dynpm_state = &r600_pm_get_dynpm_state, 1170 .get_engine_clock = &radeon_atom_get_engine_clock, 1171 .set_engine_clock = &radeon_atom_set_engine_clock, 1172 .get_memory_clock = &radeon_atom_get_memory_clock, 1173 .set_memory_clock = &radeon_atom_set_memory_clock, 1174 .get_pcie_lanes = &r600_get_pcie_lanes, 1175 .set_pcie_lanes = &r600_set_pcie_lanes, 1176 .set_clock_gating = &radeon_atom_set_clock_gating, 1177 }, 1178 .pflip = { 1179 .pre_page_flip = &rs600_pre_page_flip, 1180 .page_flip = &rv770_page_flip, 1181 .post_page_flip = &rs600_post_page_flip, 1182 }, 1183 }; 1184 1185 static struct radeon_asic evergreen_asic = { 1186 .init = &evergreen_init, 1187 .fini = &evergreen_fini, 1188 .suspend = &evergreen_suspend, 1189 .resume = &evergreen_resume, 1190 .asic_reset = &evergreen_asic_reset, 1191 .vga_set_state = &r600_vga_set_state, 1192 .ioctl_wait_idle = r600_ioctl_wait_idle, 1193 .gui_idle = &r600_gui_idle, 1194 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1195 .get_xclk = &rv770_get_xclk, 1196 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1197 .gart = { 1198 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1199 .set_page = &rs600_gart_set_page, 1200 }, 1201 .ring = { 1202 [RADEON_RING_TYPE_GFX_INDEX] = { 1203 .ib_execute = &evergreen_ring_ib_execute, 1204 .emit_fence = &r600_fence_ring_emit, 1205 .emit_semaphore = &r600_semaphore_ring_emit, 1206 .cs_parse = &evergreen_cs_parse, 1207 .ring_test = &r600_ring_test, 1208 .ib_test = &r600_ib_test, 1209 .is_lockup = &evergreen_gfx_is_lockup, 1210 }, 1211 [R600_RING_TYPE_DMA_INDEX] = { 1212 .ib_execute = &evergreen_dma_ring_ib_execute, 1213 .emit_fence = &evergreen_dma_fence_ring_emit, 1214 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1215 .cs_parse = &evergreen_dma_cs_parse, 1216 .ring_test = &r600_dma_ring_test, 1217 .ib_test = &r600_dma_ib_test, 1218 .is_lockup = &evergreen_dma_is_lockup, 1219 } 1220 }, 1221 .irq = { 1222 .set = &evergreen_irq_set, 1223 .process = &evergreen_irq_process, 1224 }, 1225 .display = { 1226 .bandwidth_update = &evergreen_bandwidth_update, 1227 .get_vblank_counter = &evergreen_get_vblank_counter, 1228 .wait_for_vblank = &dce4_wait_for_vblank, 1229 .set_backlight_level = &atombios_set_backlight_level, 1230 .get_backlight_level = &atombios_get_backlight_level, 1231 }, 1232 .copy = { 1233 .blit = &r600_copy_blit, 1234 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1235 .dma = &evergreen_copy_dma, 1236 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1237 .copy = &evergreen_copy_dma, 1238 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1239 }, 1240 .surface = { 1241 .set_reg = r600_set_surface_reg, 1242 .clear_reg = r600_clear_surface_reg, 1243 }, 1244 .hpd = { 1245 .init = &evergreen_hpd_init, 1246 .fini = &evergreen_hpd_fini, 1247 .sense = &evergreen_hpd_sense, 1248 .set_polarity = &evergreen_hpd_set_polarity, 1249 }, 1250 .pm = { 1251 .misc = &evergreen_pm_misc, 1252 .prepare = &evergreen_pm_prepare, 1253 .finish = &evergreen_pm_finish, 1254 .init_profile = &r600_pm_init_profile, 1255 .get_dynpm_state = &r600_pm_get_dynpm_state, 1256 .get_engine_clock = &radeon_atom_get_engine_clock, 1257 .set_engine_clock = &radeon_atom_set_engine_clock, 1258 .get_memory_clock = &radeon_atom_get_memory_clock, 1259 .set_memory_clock = &radeon_atom_set_memory_clock, 1260 .get_pcie_lanes = &r600_get_pcie_lanes, 1261 .set_pcie_lanes = &r600_set_pcie_lanes, 1262 .set_clock_gating = NULL, 1263 }, 1264 .pflip = { 1265 .pre_page_flip = &evergreen_pre_page_flip, 1266 .page_flip = &evergreen_page_flip, 1267 .post_page_flip = &evergreen_post_page_flip, 1268 }, 1269 }; 1270 1271 static struct radeon_asic sumo_asic = { 1272 .init = &evergreen_init, 1273 .fini = &evergreen_fini, 1274 .suspend = &evergreen_suspend, 1275 .resume = &evergreen_resume, 1276 .asic_reset = &evergreen_asic_reset, 1277 .vga_set_state = &r600_vga_set_state, 1278 .ioctl_wait_idle = r600_ioctl_wait_idle, 1279 .gui_idle = &r600_gui_idle, 1280 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1281 .get_xclk = &r600_get_xclk, 1282 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1283 .gart = { 1284 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1285 .set_page = &rs600_gart_set_page, 1286 }, 1287 .ring = { 1288 [RADEON_RING_TYPE_GFX_INDEX] = { 1289 .ib_execute = &evergreen_ring_ib_execute, 1290 .emit_fence = &r600_fence_ring_emit, 1291 .emit_semaphore = &r600_semaphore_ring_emit, 1292 .cs_parse = &evergreen_cs_parse, 1293 .ring_test = &r600_ring_test, 1294 .ib_test = &r600_ib_test, 1295 .is_lockup = &evergreen_gfx_is_lockup, 1296 }, 1297 [R600_RING_TYPE_DMA_INDEX] = { 1298 .ib_execute = &evergreen_dma_ring_ib_execute, 1299 .emit_fence = &evergreen_dma_fence_ring_emit, 1300 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1301 .cs_parse = &evergreen_dma_cs_parse, 1302 .ring_test = &r600_dma_ring_test, 1303 .ib_test = &r600_dma_ib_test, 1304 .is_lockup = &evergreen_dma_is_lockup, 1305 } 1306 }, 1307 .irq = { 1308 .set = &evergreen_irq_set, 1309 .process = &evergreen_irq_process, 1310 }, 1311 .display = { 1312 .bandwidth_update = &evergreen_bandwidth_update, 1313 .get_vblank_counter = &evergreen_get_vblank_counter, 1314 .wait_for_vblank = &dce4_wait_for_vblank, 1315 .set_backlight_level = &atombios_set_backlight_level, 1316 .get_backlight_level = &atombios_get_backlight_level, 1317 }, 1318 .copy = { 1319 .blit = &r600_copy_blit, 1320 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1321 .dma = &evergreen_copy_dma, 1322 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1323 .copy = &evergreen_copy_dma, 1324 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1325 }, 1326 .surface = { 1327 .set_reg = r600_set_surface_reg, 1328 .clear_reg = r600_clear_surface_reg, 1329 }, 1330 .hpd = { 1331 .init = &evergreen_hpd_init, 1332 .fini = &evergreen_hpd_fini, 1333 .sense = &evergreen_hpd_sense, 1334 .set_polarity = &evergreen_hpd_set_polarity, 1335 }, 1336 .pm = { 1337 .misc = &evergreen_pm_misc, 1338 .prepare = &evergreen_pm_prepare, 1339 .finish = &evergreen_pm_finish, 1340 .init_profile = &sumo_pm_init_profile, 1341 .get_dynpm_state = &r600_pm_get_dynpm_state, 1342 .get_engine_clock = &radeon_atom_get_engine_clock, 1343 .set_engine_clock = &radeon_atom_set_engine_clock, 1344 .get_memory_clock = NULL, 1345 .set_memory_clock = NULL, 1346 .get_pcie_lanes = NULL, 1347 .set_pcie_lanes = NULL, 1348 .set_clock_gating = NULL, 1349 }, 1350 .pflip = { 1351 .pre_page_flip = &evergreen_pre_page_flip, 1352 .page_flip = &evergreen_page_flip, 1353 .post_page_flip = &evergreen_post_page_flip, 1354 }, 1355 }; 1356 1357 static struct radeon_asic btc_asic = { 1358 .init = &evergreen_init, 1359 .fini = &evergreen_fini, 1360 .suspend = &evergreen_suspend, 1361 .resume = &evergreen_resume, 1362 .asic_reset = &evergreen_asic_reset, 1363 .vga_set_state = &r600_vga_set_state, 1364 .ioctl_wait_idle = r600_ioctl_wait_idle, 1365 .gui_idle = &r600_gui_idle, 1366 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1367 .get_xclk = &rv770_get_xclk, 1368 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1369 .gart = { 1370 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1371 .set_page = &rs600_gart_set_page, 1372 }, 1373 .ring = { 1374 [RADEON_RING_TYPE_GFX_INDEX] = { 1375 .ib_execute = &evergreen_ring_ib_execute, 1376 .emit_fence = &r600_fence_ring_emit, 1377 .emit_semaphore = &r600_semaphore_ring_emit, 1378 .cs_parse = &evergreen_cs_parse, 1379 .ring_test = &r600_ring_test, 1380 .ib_test = &r600_ib_test, 1381 .is_lockup = &evergreen_gfx_is_lockup, 1382 }, 1383 [R600_RING_TYPE_DMA_INDEX] = { 1384 .ib_execute = &evergreen_dma_ring_ib_execute, 1385 .emit_fence = &evergreen_dma_fence_ring_emit, 1386 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1387 .cs_parse = &evergreen_dma_cs_parse, 1388 .ring_test = &r600_dma_ring_test, 1389 .ib_test = &r600_dma_ib_test, 1390 .is_lockup = &evergreen_dma_is_lockup, 1391 } 1392 }, 1393 .irq = { 1394 .set = &evergreen_irq_set, 1395 .process = &evergreen_irq_process, 1396 }, 1397 .display = { 1398 .bandwidth_update = &evergreen_bandwidth_update, 1399 .get_vblank_counter = &evergreen_get_vblank_counter, 1400 .wait_for_vblank = &dce4_wait_for_vblank, 1401 .set_backlight_level = &atombios_set_backlight_level, 1402 .get_backlight_level = &atombios_get_backlight_level, 1403 }, 1404 .copy = { 1405 .blit = &r600_copy_blit, 1406 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1407 .dma = &evergreen_copy_dma, 1408 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1409 .copy = &evergreen_copy_dma, 1410 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1411 }, 1412 .surface = { 1413 .set_reg = r600_set_surface_reg, 1414 .clear_reg = r600_clear_surface_reg, 1415 }, 1416 .hpd = { 1417 .init = &evergreen_hpd_init, 1418 .fini = &evergreen_hpd_fini, 1419 .sense = &evergreen_hpd_sense, 1420 .set_polarity = &evergreen_hpd_set_polarity, 1421 }, 1422 .pm = { 1423 .misc = &evergreen_pm_misc, 1424 .prepare = &evergreen_pm_prepare, 1425 .finish = &evergreen_pm_finish, 1426 .init_profile = &btc_pm_init_profile, 1427 .get_dynpm_state = &r600_pm_get_dynpm_state, 1428 .get_engine_clock = &radeon_atom_get_engine_clock, 1429 .set_engine_clock = &radeon_atom_set_engine_clock, 1430 .get_memory_clock = &radeon_atom_get_memory_clock, 1431 .set_memory_clock = &radeon_atom_set_memory_clock, 1432 .get_pcie_lanes = NULL, 1433 .set_pcie_lanes = NULL, 1434 .set_clock_gating = NULL, 1435 }, 1436 .pflip = { 1437 .pre_page_flip = &evergreen_pre_page_flip, 1438 .page_flip = &evergreen_page_flip, 1439 .post_page_flip = &evergreen_post_page_flip, 1440 }, 1441 }; 1442 1443 static struct radeon_asic cayman_asic = { 1444 .init = &cayman_init, 1445 .fini = &cayman_fini, 1446 .suspend = &cayman_suspend, 1447 .resume = &cayman_resume, 1448 .asic_reset = &cayman_asic_reset, 1449 .vga_set_state = &r600_vga_set_state, 1450 .ioctl_wait_idle = r600_ioctl_wait_idle, 1451 .gui_idle = &r600_gui_idle, 1452 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1453 .get_xclk = &rv770_get_xclk, 1454 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1455 .gart = { 1456 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1457 .set_page = &rs600_gart_set_page, 1458 }, 1459 .vm = { 1460 .init = &cayman_vm_init, 1461 .fini = &cayman_vm_fini, 1462 .pt_ring_index = R600_RING_TYPE_DMA_INDEX, 1463 .set_page = &cayman_vm_set_page, 1464 }, 1465 .ring = { 1466 [RADEON_RING_TYPE_GFX_INDEX] = { 1467 .ib_execute = &cayman_ring_ib_execute, 1468 .ib_parse = &evergreen_ib_parse, 1469 .emit_fence = &cayman_fence_ring_emit, 1470 .emit_semaphore = &r600_semaphore_ring_emit, 1471 .cs_parse = &evergreen_cs_parse, 1472 .ring_test = &r600_ring_test, 1473 .ib_test = &r600_ib_test, 1474 .is_lockup = &cayman_gfx_is_lockup, 1475 .vm_flush = &cayman_vm_flush, 1476 }, 1477 [CAYMAN_RING_TYPE_CP1_INDEX] = { 1478 .ib_execute = &cayman_ring_ib_execute, 1479 .ib_parse = &evergreen_ib_parse, 1480 .emit_fence = &cayman_fence_ring_emit, 1481 .emit_semaphore = &r600_semaphore_ring_emit, 1482 .cs_parse = &evergreen_cs_parse, 1483 .ring_test = &r600_ring_test, 1484 .ib_test = &r600_ib_test, 1485 .is_lockup = &cayman_gfx_is_lockup, 1486 .vm_flush = &cayman_vm_flush, 1487 }, 1488 [CAYMAN_RING_TYPE_CP2_INDEX] = { 1489 .ib_execute = &cayman_ring_ib_execute, 1490 .ib_parse = &evergreen_ib_parse, 1491 .emit_fence = &cayman_fence_ring_emit, 1492 .emit_semaphore = &r600_semaphore_ring_emit, 1493 .cs_parse = &evergreen_cs_parse, 1494 .ring_test = &r600_ring_test, 1495 .ib_test = &r600_ib_test, 1496 .is_lockup = &cayman_gfx_is_lockup, 1497 .vm_flush = &cayman_vm_flush, 1498 }, 1499 [R600_RING_TYPE_DMA_INDEX] = { 1500 .ib_execute = &cayman_dma_ring_ib_execute, 1501 .ib_parse = &evergreen_dma_ib_parse, 1502 .emit_fence = &evergreen_dma_fence_ring_emit, 1503 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1504 .cs_parse = &evergreen_dma_cs_parse, 1505 .ring_test = &r600_dma_ring_test, 1506 .ib_test = &r600_dma_ib_test, 1507 .is_lockup = &cayman_dma_is_lockup, 1508 .vm_flush = &cayman_dma_vm_flush, 1509 }, 1510 [CAYMAN_RING_TYPE_DMA1_INDEX] = { 1511 .ib_execute = &cayman_dma_ring_ib_execute, 1512 .ib_parse = &evergreen_dma_ib_parse, 1513 .emit_fence = &evergreen_dma_fence_ring_emit, 1514 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1515 .cs_parse = &evergreen_dma_cs_parse, 1516 .ring_test = &r600_dma_ring_test, 1517 .ib_test = &r600_dma_ib_test, 1518 .is_lockup = &cayman_dma_is_lockup, 1519 .vm_flush = &cayman_dma_vm_flush, 1520 } 1521 }, 1522 .irq = { 1523 .set = &evergreen_irq_set, 1524 .process = &evergreen_irq_process, 1525 }, 1526 .display = { 1527 .bandwidth_update = &evergreen_bandwidth_update, 1528 .get_vblank_counter = &evergreen_get_vblank_counter, 1529 .wait_for_vblank = &dce4_wait_for_vblank, 1530 .set_backlight_level = &atombios_set_backlight_level, 1531 .get_backlight_level = &atombios_get_backlight_level, 1532 }, 1533 .copy = { 1534 .blit = &r600_copy_blit, 1535 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1536 .dma = &evergreen_copy_dma, 1537 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1538 .copy = &evergreen_copy_dma, 1539 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1540 }, 1541 .surface = { 1542 .set_reg = r600_set_surface_reg, 1543 .clear_reg = r600_clear_surface_reg, 1544 }, 1545 .hpd = { 1546 .init = &evergreen_hpd_init, 1547 .fini = &evergreen_hpd_fini, 1548 .sense = &evergreen_hpd_sense, 1549 .set_polarity = &evergreen_hpd_set_polarity, 1550 }, 1551 .pm = { 1552 .misc = &evergreen_pm_misc, 1553 .prepare = &evergreen_pm_prepare, 1554 .finish = &evergreen_pm_finish, 1555 .init_profile = &btc_pm_init_profile, 1556 .get_dynpm_state = &r600_pm_get_dynpm_state, 1557 .get_engine_clock = &radeon_atom_get_engine_clock, 1558 .set_engine_clock = &radeon_atom_set_engine_clock, 1559 .get_memory_clock = &radeon_atom_get_memory_clock, 1560 .set_memory_clock = &radeon_atom_set_memory_clock, 1561 .get_pcie_lanes = NULL, 1562 .set_pcie_lanes = NULL, 1563 .set_clock_gating = NULL, 1564 }, 1565 .pflip = { 1566 .pre_page_flip = &evergreen_pre_page_flip, 1567 .page_flip = &evergreen_page_flip, 1568 .post_page_flip = &evergreen_post_page_flip, 1569 }, 1570 }; 1571 1572 static struct radeon_asic trinity_asic = { 1573 .init = &cayman_init, 1574 .fini = &cayman_fini, 1575 .suspend = &cayman_suspend, 1576 .resume = &cayman_resume, 1577 .asic_reset = &cayman_asic_reset, 1578 .vga_set_state = &r600_vga_set_state, 1579 .ioctl_wait_idle = r600_ioctl_wait_idle, 1580 .gui_idle = &r600_gui_idle, 1581 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1582 .get_xclk = &r600_get_xclk, 1583 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1584 .gart = { 1585 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1586 .set_page = &rs600_gart_set_page, 1587 }, 1588 .vm = { 1589 .init = &cayman_vm_init, 1590 .fini = &cayman_vm_fini, 1591 .pt_ring_index = R600_RING_TYPE_DMA_INDEX, 1592 .set_page = &cayman_vm_set_page, 1593 }, 1594 .ring = { 1595 [RADEON_RING_TYPE_GFX_INDEX] = { 1596 .ib_execute = &cayman_ring_ib_execute, 1597 .ib_parse = &evergreen_ib_parse, 1598 .emit_fence = &cayman_fence_ring_emit, 1599 .emit_semaphore = &r600_semaphore_ring_emit, 1600 .cs_parse = &evergreen_cs_parse, 1601 .ring_test = &r600_ring_test, 1602 .ib_test = &r600_ib_test, 1603 .is_lockup = &cayman_gfx_is_lockup, 1604 .vm_flush = &cayman_vm_flush, 1605 }, 1606 [CAYMAN_RING_TYPE_CP1_INDEX] = { 1607 .ib_execute = &cayman_ring_ib_execute, 1608 .ib_parse = &evergreen_ib_parse, 1609 .emit_fence = &cayman_fence_ring_emit, 1610 .emit_semaphore = &r600_semaphore_ring_emit, 1611 .cs_parse = &evergreen_cs_parse, 1612 .ring_test = &r600_ring_test, 1613 .ib_test = &r600_ib_test, 1614 .is_lockup = &cayman_gfx_is_lockup, 1615 .vm_flush = &cayman_vm_flush, 1616 }, 1617 [CAYMAN_RING_TYPE_CP2_INDEX] = { 1618 .ib_execute = &cayman_ring_ib_execute, 1619 .ib_parse = &evergreen_ib_parse, 1620 .emit_fence = &cayman_fence_ring_emit, 1621 .emit_semaphore = &r600_semaphore_ring_emit, 1622 .cs_parse = &evergreen_cs_parse, 1623 .ring_test = &r600_ring_test, 1624 .ib_test = &r600_ib_test, 1625 .is_lockup = &cayman_gfx_is_lockup, 1626 .vm_flush = &cayman_vm_flush, 1627 }, 1628 [R600_RING_TYPE_DMA_INDEX] = { 1629 .ib_execute = &cayman_dma_ring_ib_execute, 1630 .ib_parse = &evergreen_dma_ib_parse, 1631 .emit_fence = &evergreen_dma_fence_ring_emit, 1632 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1633 .cs_parse = &evergreen_dma_cs_parse, 1634 .ring_test = &r600_dma_ring_test, 1635 .ib_test = &r600_dma_ib_test, 1636 .is_lockup = &cayman_dma_is_lockup, 1637 .vm_flush = &cayman_dma_vm_flush, 1638 }, 1639 [CAYMAN_RING_TYPE_DMA1_INDEX] = { 1640 .ib_execute = &cayman_dma_ring_ib_execute, 1641 .ib_parse = &evergreen_dma_ib_parse, 1642 .emit_fence = &evergreen_dma_fence_ring_emit, 1643 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1644 .cs_parse = &evergreen_dma_cs_parse, 1645 .ring_test = &r600_dma_ring_test, 1646 .ib_test = &r600_dma_ib_test, 1647 .is_lockup = &cayman_dma_is_lockup, 1648 .vm_flush = &cayman_dma_vm_flush, 1649 } 1650 }, 1651 .irq = { 1652 .set = &evergreen_irq_set, 1653 .process = &evergreen_irq_process, 1654 }, 1655 .display = { 1656 .bandwidth_update = &dce6_bandwidth_update, 1657 .get_vblank_counter = &evergreen_get_vblank_counter, 1658 .wait_for_vblank = &dce4_wait_for_vblank, 1659 .set_backlight_level = &atombios_set_backlight_level, 1660 .get_backlight_level = &atombios_get_backlight_level, 1661 }, 1662 .copy = { 1663 .blit = &r600_copy_blit, 1664 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1665 .dma = &evergreen_copy_dma, 1666 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1667 .copy = &evergreen_copy_dma, 1668 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1669 }, 1670 .surface = { 1671 .set_reg = r600_set_surface_reg, 1672 .clear_reg = r600_clear_surface_reg, 1673 }, 1674 .hpd = { 1675 .init = &evergreen_hpd_init, 1676 .fini = &evergreen_hpd_fini, 1677 .sense = &evergreen_hpd_sense, 1678 .set_polarity = &evergreen_hpd_set_polarity, 1679 }, 1680 .pm = { 1681 .misc = &evergreen_pm_misc, 1682 .prepare = &evergreen_pm_prepare, 1683 .finish = &evergreen_pm_finish, 1684 .init_profile = &sumo_pm_init_profile, 1685 .get_dynpm_state = &r600_pm_get_dynpm_state, 1686 .get_engine_clock = &radeon_atom_get_engine_clock, 1687 .set_engine_clock = &radeon_atom_set_engine_clock, 1688 .get_memory_clock = NULL, 1689 .set_memory_clock = NULL, 1690 .get_pcie_lanes = NULL, 1691 .set_pcie_lanes = NULL, 1692 .set_clock_gating = NULL, 1693 }, 1694 .pflip = { 1695 .pre_page_flip = &evergreen_pre_page_flip, 1696 .page_flip = &evergreen_page_flip, 1697 .post_page_flip = &evergreen_post_page_flip, 1698 }, 1699 }; 1700 1701 static struct radeon_asic si_asic = { 1702 .init = &si_init, 1703 .fini = &si_fini, 1704 .suspend = &si_suspend, 1705 .resume = &si_resume, 1706 .asic_reset = &si_asic_reset, 1707 .vga_set_state = &r600_vga_set_state, 1708 .ioctl_wait_idle = r600_ioctl_wait_idle, 1709 .gui_idle = &r600_gui_idle, 1710 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1711 .get_xclk = &si_get_xclk, 1712 .get_gpu_clock_counter = &si_get_gpu_clock_counter, 1713 .gart = { 1714 .tlb_flush = &si_pcie_gart_tlb_flush, 1715 .set_page = &rs600_gart_set_page, 1716 }, 1717 .vm = { 1718 .init = &si_vm_init, 1719 .fini = &si_vm_fini, 1720 .pt_ring_index = R600_RING_TYPE_DMA_INDEX, 1721 .set_page = &si_vm_set_page, 1722 }, 1723 .ring = { 1724 [RADEON_RING_TYPE_GFX_INDEX] = { 1725 .ib_execute = &si_ring_ib_execute, 1726 .ib_parse = &si_ib_parse, 1727 .emit_fence = &si_fence_ring_emit, 1728 .emit_semaphore = &r600_semaphore_ring_emit, 1729 .cs_parse = NULL, 1730 .ring_test = &r600_ring_test, 1731 .ib_test = &r600_ib_test, 1732 .is_lockup = &si_gfx_is_lockup, 1733 .vm_flush = &si_vm_flush, 1734 }, 1735 [CAYMAN_RING_TYPE_CP1_INDEX] = { 1736 .ib_execute = &si_ring_ib_execute, 1737 .ib_parse = &si_ib_parse, 1738 .emit_fence = &si_fence_ring_emit, 1739 .emit_semaphore = &r600_semaphore_ring_emit, 1740 .cs_parse = NULL, 1741 .ring_test = &r600_ring_test, 1742 .ib_test = &r600_ib_test, 1743 .is_lockup = &si_gfx_is_lockup, 1744 .vm_flush = &si_vm_flush, 1745 }, 1746 [CAYMAN_RING_TYPE_CP2_INDEX] = { 1747 .ib_execute = &si_ring_ib_execute, 1748 .ib_parse = &si_ib_parse, 1749 .emit_fence = &si_fence_ring_emit, 1750 .emit_semaphore = &r600_semaphore_ring_emit, 1751 .cs_parse = NULL, 1752 .ring_test = &r600_ring_test, 1753 .ib_test = &r600_ib_test, 1754 .is_lockup = &si_gfx_is_lockup, 1755 .vm_flush = &si_vm_flush, 1756 }, 1757 [R600_RING_TYPE_DMA_INDEX] = { 1758 .ib_execute = &cayman_dma_ring_ib_execute, 1759 .ib_parse = &evergreen_dma_ib_parse, 1760 .emit_fence = &evergreen_dma_fence_ring_emit, 1761 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1762 .cs_parse = NULL, 1763 .ring_test = &r600_dma_ring_test, 1764 .ib_test = &r600_dma_ib_test, 1765 .is_lockup = &si_dma_is_lockup, 1766 .vm_flush = &si_dma_vm_flush, 1767 }, 1768 [CAYMAN_RING_TYPE_DMA1_INDEX] = { 1769 .ib_execute = &cayman_dma_ring_ib_execute, 1770 .ib_parse = &evergreen_dma_ib_parse, 1771 .emit_fence = &evergreen_dma_fence_ring_emit, 1772 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1773 .cs_parse = NULL, 1774 .ring_test = &r600_dma_ring_test, 1775 .ib_test = &r600_dma_ib_test, 1776 .is_lockup = &si_dma_is_lockup, 1777 .vm_flush = &si_dma_vm_flush, 1778 } 1779 }, 1780 .irq = { 1781 .set = &si_irq_set, 1782 .process = &si_irq_process, 1783 }, 1784 .display = { 1785 .bandwidth_update = &dce6_bandwidth_update, 1786 .get_vblank_counter = &evergreen_get_vblank_counter, 1787 .wait_for_vblank = &dce4_wait_for_vblank, 1788 .set_backlight_level = &atombios_set_backlight_level, 1789 .get_backlight_level = &atombios_get_backlight_level, 1790 }, 1791 .copy = { 1792 .blit = NULL, 1793 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1794 .dma = &si_copy_dma, 1795 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1796 .copy = &si_copy_dma, 1797 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1798 }, 1799 .surface = { 1800 .set_reg = r600_set_surface_reg, 1801 .clear_reg = r600_clear_surface_reg, 1802 }, 1803 .hpd = { 1804 .init = &evergreen_hpd_init, 1805 .fini = &evergreen_hpd_fini, 1806 .sense = &evergreen_hpd_sense, 1807 .set_polarity = &evergreen_hpd_set_polarity, 1808 }, 1809 .pm = { 1810 .misc = &evergreen_pm_misc, 1811 .prepare = &evergreen_pm_prepare, 1812 .finish = &evergreen_pm_finish, 1813 .init_profile = &sumo_pm_init_profile, 1814 .get_dynpm_state = &r600_pm_get_dynpm_state, 1815 .get_engine_clock = &radeon_atom_get_engine_clock, 1816 .set_engine_clock = &radeon_atom_set_engine_clock, 1817 .get_memory_clock = &radeon_atom_get_memory_clock, 1818 .set_memory_clock = &radeon_atom_set_memory_clock, 1819 .get_pcie_lanes = NULL, 1820 .set_pcie_lanes = NULL, 1821 .set_clock_gating = NULL, 1822 }, 1823 .pflip = { 1824 .pre_page_flip = &evergreen_pre_page_flip, 1825 .page_flip = &evergreen_page_flip, 1826 .post_page_flip = &evergreen_post_page_flip, 1827 }, 1828 }; 1829 1830 /** 1831 * radeon_asic_init - register asic specific callbacks 1832 * 1833 * @rdev: radeon device pointer 1834 * 1835 * Registers the appropriate asic specific callbacks for each 1836 * chip family. Also sets other asics specific info like the number 1837 * of crtcs and the register aperture accessors (all asics). 1838 * Returns 0 for success. 1839 */ 1840 int radeon_asic_init(struct radeon_device *rdev) 1841 { 1842 radeon_register_accessor_init(rdev); 1843 1844 /* set the number of crtcs */ 1845 if (rdev->flags & RADEON_SINGLE_CRTC) 1846 rdev->num_crtc = 1; 1847 else 1848 rdev->num_crtc = 2; 1849 1850 switch (rdev->family) { 1851 case CHIP_R100: 1852 case CHIP_RV100: 1853 case CHIP_RS100: 1854 case CHIP_RV200: 1855 case CHIP_RS200: 1856 rdev->asic = &r100_asic; 1857 break; 1858 case CHIP_R200: 1859 case CHIP_RV250: 1860 case CHIP_RS300: 1861 case CHIP_RV280: 1862 rdev->asic = &r200_asic; 1863 break; 1864 case CHIP_R300: 1865 case CHIP_R350: 1866 case CHIP_RV350: 1867 case CHIP_RV380: 1868 if (rdev->flags & RADEON_IS_PCIE) 1869 rdev->asic = &r300_asic_pcie; 1870 else 1871 rdev->asic = &r300_asic; 1872 break; 1873 case CHIP_R420: 1874 case CHIP_R423: 1875 case CHIP_RV410: 1876 rdev->asic = &r420_asic; 1877 /* handle macs */ 1878 if (rdev->bios == NULL) { 1879 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; 1880 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; 1881 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; 1882 rdev->asic->pm.set_memory_clock = NULL; 1883 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; 1884 } 1885 break; 1886 case CHIP_RS400: 1887 case CHIP_RS480: 1888 rdev->asic = &rs400_asic; 1889 break; 1890 case CHIP_RS600: 1891 rdev->asic = &rs600_asic; 1892 break; 1893 case CHIP_RS690: 1894 case CHIP_RS740: 1895 rdev->asic = &rs690_asic; 1896 break; 1897 case CHIP_RV515: 1898 rdev->asic = &rv515_asic; 1899 break; 1900 case CHIP_R520: 1901 case CHIP_RV530: 1902 case CHIP_RV560: 1903 case CHIP_RV570: 1904 case CHIP_R580: 1905 rdev->asic = &r520_asic; 1906 break; 1907 case CHIP_R600: 1908 case CHIP_RV610: 1909 case CHIP_RV630: 1910 case CHIP_RV620: 1911 case CHIP_RV635: 1912 case CHIP_RV670: 1913 rdev->asic = &r600_asic; 1914 break; 1915 case CHIP_RS780: 1916 case CHIP_RS880: 1917 rdev->asic = &rs780_asic; 1918 break; 1919 case CHIP_RV770: 1920 case CHIP_RV730: 1921 case CHIP_RV710: 1922 case CHIP_RV740: 1923 rdev->asic = &rv770_asic; 1924 break; 1925 case CHIP_CEDAR: 1926 case CHIP_REDWOOD: 1927 case CHIP_JUNIPER: 1928 case CHIP_CYPRESS: 1929 case CHIP_HEMLOCK: 1930 /* set num crtcs */ 1931 if (rdev->family == CHIP_CEDAR) 1932 rdev->num_crtc = 4; 1933 else 1934 rdev->num_crtc = 6; 1935 rdev->asic = &evergreen_asic; 1936 break; 1937 case CHIP_PALM: 1938 case CHIP_SUMO: 1939 case CHIP_SUMO2: 1940 rdev->asic = &sumo_asic; 1941 break; 1942 case CHIP_BARTS: 1943 case CHIP_TURKS: 1944 case CHIP_CAICOS: 1945 /* set num crtcs */ 1946 if (rdev->family == CHIP_CAICOS) 1947 rdev->num_crtc = 4; 1948 else 1949 rdev->num_crtc = 6; 1950 rdev->asic = &btc_asic; 1951 break; 1952 case CHIP_CAYMAN: 1953 rdev->asic = &cayman_asic; 1954 /* set num crtcs */ 1955 rdev->num_crtc = 6; 1956 break; 1957 case CHIP_ARUBA: 1958 rdev->asic = &trinity_asic; 1959 /* set num crtcs */ 1960 rdev->num_crtc = 4; 1961 break; 1962 case CHIP_TAHITI: 1963 case CHIP_PITCAIRN: 1964 case CHIP_VERDE: 1965 case CHIP_OLAND: 1966 rdev->asic = &si_asic; 1967 /* set num crtcs */ 1968 if (rdev->family == CHIP_OLAND) 1969 rdev->num_crtc = 2; 1970 else 1971 rdev->num_crtc = 6; 1972 break; 1973 default: 1974 /* FIXME: not supported yet */ 1975 return -EINVAL; 1976 } 1977 1978 if (rdev->flags & RADEON_IS_IGP) { 1979 rdev->asic->pm.get_memory_clock = NULL; 1980 rdev->asic->pm.set_memory_clock = NULL; 1981 } 1982 1983 return 0; 1984 } 1985 1986