1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 /* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45 /* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63 #include <linux/atomic.h> 64 #include <linux/wait.h> 65 #include <linux/list.h> 66 #include <linux/kref.h> 67 68 #include <ttm/ttm_bo_api.h> 69 #include <ttm/ttm_bo_driver.h> 70 #include <ttm/ttm_placement.h> 71 #include <ttm/ttm_module.h> 72 #include <ttm/ttm_execbuf_util.h> 73 74 #include "radeon_family.h" 75 #include "radeon_mode.h" 76 #include "radeon_reg.h" 77 78 /* 79 * Modules parameters. 80 */ 81 extern int radeon_no_wb; 82 extern int radeon_modeset; 83 extern int radeon_dynclks; 84 extern int radeon_r4xx_atom; 85 extern int radeon_agpmode; 86 extern int radeon_vram_limit; 87 extern int radeon_gart_size; 88 extern int radeon_benchmarking; 89 extern int radeon_testing; 90 extern int radeon_connector_table; 91 extern int radeon_tv; 92 extern int radeon_audio; 93 extern int radeon_disp_priority; 94 extern int radeon_hw_i2c; 95 extern int radeon_pcie_gen2; 96 extern int radeon_msi; 97 extern int radeon_lockup_timeout; 98 extern int radeon_fastfb; 99 extern int radeon_dpm; 100 extern int radeon_aspm; 101 102 /* 103 * Copy from radeon_drv.h so we don't have to include both and have conflicting 104 * symbol; 105 */ 106 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 107 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 108 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 109 #define RADEON_IB_POOL_SIZE 16 110 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 111 #define RADEONFB_CONN_LIMIT 4 112 #define RADEON_BIOS_NUM_SCRATCH 8 113 114 /* max number of rings */ 115 #define RADEON_NUM_RINGS 6 116 117 /* fence seq are set to this number when signaled */ 118 #define RADEON_FENCE_SIGNALED_SEQ 0LL 119 120 /* internal ring indices */ 121 /* r1xx+ has gfx CP ring */ 122 #define RADEON_RING_TYPE_GFX_INDEX 0 123 124 /* cayman has 2 compute CP rings */ 125 #define CAYMAN_RING_TYPE_CP1_INDEX 1 126 #define CAYMAN_RING_TYPE_CP2_INDEX 2 127 128 /* R600+ has an async dma ring */ 129 #define R600_RING_TYPE_DMA_INDEX 3 130 /* cayman add a second async dma ring */ 131 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 132 133 /* R600+ */ 134 #define R600_RING_TYPE_UVD_INDEX 5 135 136 /* hardcode those limit for now */ 137 #define RADEON_VA_IB_OFFSET (1 << 20) 138 #define RADEON_VA_RESERVED_SIZE (8 << 20) 139 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 140 141 /* reset flags */ 142 #define RADEON_RESET_GFX (1 << 0) 143 #define RADEON_RESET_COMPUTE (1 << 1) 144 #define RADEON_RESET_DMA (1 << 2) 145 #define RADEON_RESET_CP (1 << 3) 146 #define RADEON_RESET_GRBM (1 << 4) 147 #define RADEON_RESET_DMA1 (1 << 5) 148 #define RADEON_RESET_RLC (1 << 6) 149 #define RADEON_RESET_SEM (1 << 7) 150 #define RADEON_RESET_IH (1 << 8) 151 #define RADEON_RESET_VMC (1 << 9) 152 #define RADEON_RESET_MC (1 << 10) 153 #define RADEON_RESET_DISPLAY (1 << 11) 154 155 /* max cursor sizes (in pixels) */ 156 #define CURSOR_WIDTH 64 157 #define CURSOR_HEIGHT 64 158 159 #define CIK_CURSOR_WIDTH 128 160 #define CIK_CURSOR_HEIGHT 128 161 162 /* 163 * Errata workarounds. 164 */ 165 enum radeon_pll_errata { 166 CHIP_ERRATA_R300_CG = 0x00000001, 167 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 168 CHIP_ERRATA_PLL_DELAY = 0x00000004 169 }; 170 171 172 struct radeon_device; 173 174 175 /* 176 * BIOS. 177 */ 178 bool radeon_get_bios(struct radeon_device *rdev); 179 180 /* 181 * Dummy page 182 */ 183 struct radeon_dummy_page { 184 struct page *page; 185 dma_addr_t addr; 186 }; 187 int radeon_dummy_page_init(struct radeon_device *rdev); 188 void radeon_dummy_page_fini(struct radeon_device *rdev); 189 190 191 /* 192 * Clocks 193 */ 194 struct radeon_clock { 195 struct radeon_pll p1pll; 196 struct radeon_pll p2pll; 197 struct radeon_pll dcpll; 198 struct radeon_pll spll; 199 struct radeon_pll mpll; 200 /* 10 Khz units */ 201 uint32_t default_mclk; 202 uint32_t default_sclk; 203 uint32_t default_dispclk; 204 uint32_t current_dispclk; 205 uint32_t dp_extclk; 206 uint32_t max_pixel_clock; 207 }; 208 209 /* 210 * Power management 211 */ 212 int radeon_pm_init(struct radeon_device *rdev); 213 void radeon_pm_fini(struct radeon_device *rdev); 214 void radeon_pm_compute_clocks(struct radeon_device *rdev); 215 void radeon_pm_suspend(struct radeon_device *rdev); 216 void radeon_pm_resume(struct radeon_device *rdev); 217 void radeon_combios_get_power_modes(struct radeon_device *rdev); 218 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 219 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 220 u8 clock_type, 221 u32 clock, 222 bool strobe_mode, 223 struct atom_clock_dividers *dividers); 224 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 225 u32 clock, 226 bool strobe_mode, 227 struct atom_mpll_param *mpll_param); 228 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 229 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 230 u16 voltage_level, u8 voltage_type, 231 u32 *gpio_value, u32 *gpio_mask); 232 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 233 u32 eng_clock, u32 mem_clock); 234 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 235 u8 voltage_type, u16 *voltage_step); 236 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 237 u16 voltage_id, u16 *voltage); 238 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 239 u16 *voltage, 240 u16 leakage_idx); 241 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 242 u8 voltage_type, 243 u16 nominal_voltage, 244 u16 *true_voltage); 245 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 246 u8 voltage_type, u16 *min_voltage); 247 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 248 u8 voltage_type, u16 *max_voltage); 249 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 250 u8 voltage_type, u8 voltage_mode, 251 struct atom_voltage_table *voltage_table); 252 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 253 u8 voltage_type, u8 voltage_mode); 254 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 255 u32 mem_clock); 256 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 257 u32 mem_clock); 258 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 259 u8 module_index, 260 struct atom_mc_reg_table *reg_table); 261 int radeon_atom_get_memory_info(struct radeon_device *rdev, 262 u8 module_index, struct atom_memory_info *mem_info); 263 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 264 bool gddr5, u8 module_index, 265 struct atom_memory_clock_range_table *mclk_range_table); 266 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 267 u16 voltage_id, u16 *voltage); 268 void rs690_pm_info(struct radeon_device *rdev); 269 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 270 unsigned *bankh, unsigned *mtaspect, 271 unsigned *tile_split); 272 273 /* 274 * Fences. 275 */ 276 struct radeon_fence_driver { 277 uint32_t scratch_reg; 278 uint64_t gpu_addr; 279 volatile uint32_t *cpu_addr; 280 /* sync_seq is protected by ring emission lock */ 281 uint64_t sync_seq[RADEON_NUM_RINGS]; 282 atomic64_t last_seq; 283 unsigned long last_activity; 284 bool initialized; 285 }; 286 287 struct radeon_fence { 288 struct radeon_device *rdev; 289 struct kref kref; 290 /* protected by radeon_fence.lock */ 291 uint64_t seq; 292 /* RB, DMA, etc. */ 293 unsigned ring; 294 }; 295 296 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 297 int radeon_fence_driver_init(struct radeon_device *rdev); 298 void radeon_fence_driver_fini(struct radeon_device *rdev); 299 void radeon_fence_driver_force_completion(struct radeon_device *rdev); 300 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 301 void radeon_fence_process(struct radeon_device *rdev, int ring); 302 bool radeon_fence_signaled(struct radeon_fence *fence); 303 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 304 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring); 305 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring); 306 int radeon_fence_wait_any(struct radeon_device *rdev, 307 struct radeon_fence **fences, 308 bool intr); 309 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 310 void radeon_fence_unref(struct radeon_fence **fence); 311 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 312 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 313 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 314 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 315 struct radeon_fence *b) 316 { 317 if (!a) { 318 return b; 319 } 320 321 if (!b) { 322 return a; 323 } 324 325 BUG_ON(a->ring != b->ring); 326 327 if (a->seq > b->seq) { 328 return a; 329 } else { 330 return b; 331 } 332 } 333 334 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 335 struct radeon_fence *b) 336 { 337 if (!a) { 338 return false; 339 } 340 341 if (!b) { 342 return true; 343 } 344 345 BUG_ON(a->ring != b->ring); 346 347 return a->seq < b->seq; 348 } 349 350 /* 351 * Tiling registers 352 */ 353 struct radeon_surface_reg { 354 struct radeon_bo *bo; 355 }; 356 357 #define RADEON_GEM_MAX_SURFACES 8 358 359 /* 360 * TTM. 361 */ 362 struct radeon_mman { 363 struct ttm_bo_global_ref bo_global_ref; 364 struct drm_global_reference mem_global_ref; 365 struct ttm_bo_device bdev; 366 bool mem_global_referenced; 367 bool initialized; 368 }; 369 370 /* bo virtual address in a specific vm */ 371 struct radeon_bo_va { 372 /* protected by bo being reserved */ 373 struct list_head bo_list; 374 uint64_t soffset; 375 uint64_t eoffset; 376 uint32_t flags; 377 bool valid; 378 unsigned ref_count; 379 380 /* protected by vm mutex */ 381 struct list_head vm_list; 382 383 /* constant after initialization */ 384 struct radeon_vm *vm; 385 struct radeon_bo *bo; 386 }; 387 388 struct radeon_bo { 389 /* Protected by gem.mutex */ 390 struct list_head list; 391 /* Protected by tbo.reserved */ 392 u32 placements[3]; 393 struct ttm_placement placement; 394 struct ttm_buffer_object tbo; 395 struct ttm_bo_kmap_obj kmap; 396 unsigned pin_count; 397 void *kptr; 398 u32 tiling_flags; 399 u32 pitch; 400 int surface_reg; 401 /* list of all virtual address to which this bo 402 * is associated to 403 */ 404 struct list_head va; 405 /* Constant after initialization */ 406 struct radeon_device *rdev; 407 struct drm_gem_object gem_base; 408 409 struct ttm_bo_kmap_obj dma_buf_vmap; 410 pid_t pid; 411 }; 412 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 413 414 struct radeon_bo_list { 415 struct ttm_validate_buffer tv; 416 struct radeon_bo *bo; 417 uint64_t gpu_offset; 418 bool written; 419 unsigned domain; 420 unsigned alt_domain; 421 u32 tiling_flags; 422 }; 423 424 int radeon_gem_debugfs_init(struct radeon_device *rdev); 425 426 /* sub-allocation manager, it has to be protected by another lock. 427 * By conception this is an helper for other part of the driver 428 * like the indirect buffer or semaphore, which both have their 429 * locking. 430 * 431 * Principe is simple, we keep a list of sub allocation in offset 432 * order (first entry has offset == 0, last entry has the highest 433 * offset). 434 * 435 * When allocating new object we first check if there is room at 436 * the end total_size - (last_object_offset + last_object_size) >= 437 * alloc_size. If so we allocate new object there. 438 * 439 * When there is not enough room at the end, we start waiting for 440 * each sub object until we reach object_offset+object_size >= 441 * alloc_size, this object then become the sub object we return. 442 * 443 * Alignment can't be bigger than page size. 444 * 445 * Hole are not considered for allocation to keep things simple. 446 * Assumption is that there won't be hole (all object on same 447 * alignment). 448 */ 449 struct radeon_sa_manager { 450 wait_queue_head_t wq; 451 struct radeon_bo *bo; 452 struct list_head *hole; 453 struct list_head flist[RADEON_NUM_RINGS]; 454 struct list_head olist; 455 unsigned size; 456 uint64_t gpu_addr; 457 void *cpu_ptr; 458 uint32_t domain; 459 uint32_t align; 460 }; 461 462 struct radeon_sa_bo; 463 464 /* sub-allocation buffer */ 465 struct radeon_sa_bo { 466 struct list_head olist; 467 struct list_head flist; 468 struct radeon_sa_manager *manager; 469 unsigned soffset; 470 unsigned eoffset; 471 struct radeon_fence *fence; 472 }; 473 474 /* 475 * GEM objects. 476 */ 477 struct radeon_gem { 478 struct mutex mutex; 479 struct list_head objects; 480 }; 481 482 int radeon_gem_init(struct radeon_device *rdev); 483 void radeon_gem_fini(struct radeon_device *rdev); 484 int radeon_gem_object_create(struct radeon_device *rdev, int size, 485 int alignment, int initial_domain, 486 bool discardable, bool kernel, 487 struct drm_gem_object **obj); 488 489 int radeon_mode_dumb_create(struct drm_file *file_priv, 490 struct drm_device *dev, 491 struct drm_mode_create_dumb *args); 492 int radeon_mode_dumb_mmap(struct drm_file *filp, 493 struct drm_device *dev, 494 uint32_t handle, uint64_t *offset_p); 495 int radeon_mode_dumb_destroy(struct drm_file *file_priv, 496 struct drm_device *dev, 497 uint32_t handle); 498 499 /* 500 * Semaphores. 501 */ 502 /* everything here is constant */ 503 struct radeon_semaphore { 504 struct radeon_sa_bo *sa_bo; 505 signed waiters; 506 uint64_t gpu_addr; 507 }; 508 509 int radeon_semaphore_create(struct radeon_device *rdev, 510 struct radeon_semaphore **semaphore); 511 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 512 struct radeon_semaphore *semaphore); 513 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 514 struct radeon_semaphore *semaphore); 515 int radeon_semaphore_sync_rings(struct radeon_device *rdev, 516 struct radeon_semaphore *semaphore, 517 int signaler, int waiter); 518 void radeon_semaphore_free(struct radeon_device *rdev, 519 struct radeon_semaphore **semaphore, 520 struct radeon_fence *fence); 521 522 /* 523 * GART structures, functions & helpers 524 */ 525 struct radeon_mc; 526 527 #define RADEON_GPU_PAGE_SIZE 4096 528 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 529 #define RADEON_GPU_PAGE_SHIFT 12 530 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 531 532 struct radeon_gart { 533 dma_addr_t table_addr; 534 struct radeon_bo *robj; 535 void *ptr; 536 unsigned num_gpu_pages; 537 unsigned num_cpu_pages; 538 unsigned table_size; 539 struct page **pages; 540 dma_addr_t *pages_addr; 541 bool ready; 542 }; 543 544 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 545 void radeon_gart_table_ram_free(struct radeon_device *rdev); 546 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 547 void radeon_gart_table_vram_free(struct radeon_device *rdev); 548 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 549 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 550 int radeon_gart_init(struct radeon_device *rdev); 551 void radeon_gart_fini(struct radeon_device *rdev); 552 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 553 int pages); 554 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 555 int pages, struct page **pagelist, 556 dma_addr_t *dma_addr); 557 void radeon_gart_restore(struct radeon_device *rdev); 558 559 560 /* 561 * GPU MC structures, functions & helpers 562 */ 563 struct radeon_mc { 564 resource_size_t aper_size; 565 resource_size_t aper_base; 566 resource_size_t agp_base; 567 /* for some chips with <= 32MB we need to lie 568 * about vram size near mc fb location */ 569 u64 mc_vram_size; 570 u64 visible_vram_size; 571 u64 gtt_size; 572 u64 gtt_start; 573 u64 gtt_end; 574 u64 vram_start; 575 u64 vram_end; 576 unsigned vram_width; 577 u64 real_vram_size; 578 int vram_mtrr; 579 bool vram_is_ddr; 580 bool igp_sideport_enabled; 581 u64 gtt_base_align; 582 u64 mc_mask; 583 }; 584 585 bool radeon_combios_sideport_present(struct radeon_device *rdev); 586 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 587 588 /* 589 * GPU scratch registers structures, functions & helpers 590 */ 591 struct radeon_scratch { 592 unsigned num_reg; 593 uint32_t reg_base; 594 bool free[32]; 595 uint32_t reg[32]; 596 }; 597 598 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 599 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 600 601 /* 602 * GPU doorbell structures, functions & helpers 603 */ 604 struct radeon_doorbell { 605 u32 num_pages; 606 bool free[1024]; 607 /* doorbell mmio */ 608 resource_size_t base; 609 resource_size_t size; 610 void __iomem *ptr; 611 }; 612 613 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 614 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 615 616 /* 617 * IRQS. 618 */ 619 620 struct radeon_unpin_work { 621 struct work_struct work; 622 struct radeon_device *rdev; 623 int crtc_id; 624 struct radeon_fence *fence; 625 struct drm_pending_vblank_event *event; 626 struct radeon_bo *old_rbo; 627 u64 new_crtc_base; 628 }; 629 630 struct r500_irq_stat_regs { 631 u32 disp_int; 632 u32 hdmi0_status; 633 }; 634 635 struct r600_irq_stat_regs { 636 u32 disp_int; 637 u32 disp_int_cont; 638 u32 disp_int_cont2; 639 u32 d1grph_int; 640 u32 d2grph_int; 641 u32 hdmi0_status; 642 u32 hdmi1_status; 643 }; 644 645 struct evergreen_irq_stat_regs { 646 u32 disp_int; 647 u32 disp_int_cont; 648 u32 disp_int_cont2; 649 u32 disp_int_cont3; 650 u32 disp_int_cont4; 651 u32 disp_int_cont5; 652 u32 d1grph_int; 653 u32 d2grph_int; 654 u32 d3grph_int; 655 u32 d4grph_int; 656 u32 d5grph_int; 657 u32 d6grph_int; 658 u32 afmt_status1; 659 u32 afmt_status2; 660 u32 afmt_status3; 661 u32 afmt_status4; 662 u32 afmt_status5; 663 u32 afmt_status6; 664 }; 665 666 struct cik_irq_stat_regs { 667 u32 disp_int; 668 u32 disp_int_cont; 669 u32 disp_int_cont2; 670 u32 disp_int_cont3; 671 u32 disp_int_cont4; 672 u32 disp_int_cont5; 673 u32 disp_int_cont6; 674 }; 675 676 union radeon_irq_stat_regs { 677 struct r500_irq_stat_regs r500; 678 struct r600_irq_stat_regs r600; 679 struct evergreen_irq_stat_regs evergreen; 680 struct cik_irq_stat_regs cik; 681 }; 682 683 #define RADEON_MAX_HPD_PINS 6 684 #define RADEON_MAX_CRTCS 6 685 #define RADEON_MAX_AFMT_BLOCKS 6 686 687 struct radeon_irq { 688 bool installed; 689 spinlock_t lock; 690 atomic_t ring_int[RADEON_NUM_RINGS]; 691 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 692 atomic_t pflip[RADEON_MAX_CRTCS]; 693 wait_queue_head_t vblank_queue; 694 bool hpd[RADEON_MAX_HPD_PINS]; 695 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 696 union radeon_irq_stat_regs stat_regs; 697 bool dpm_thermal; 698 }; 699 700 int radeon_irq_kms_init(struct radeon_device *rdev); 701 void radeon_irq_kms_fini(struct radeon_device *rdev); 702 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 703 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 704 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 705 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 706 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 707 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 708 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 709 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 710 711 /* 712 * CP & rings. 713 */ 714 715 struct radeon_ib { 716 struct radeon_sa_bo *sa_bo; 717 uint32_t length_dw; 718 uint64_t gpu_addr; 719 uint32_t *ptr; 720 int ring; 721 struct radeon_fence *fence; 722 struct radeon_vm *vm; 723 bool is_const_ib; 724 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 725 struct radeon_semaphore *semaphore; 726 }; 727 728 struct radeon_ring { 729 struct radeon_bo *ring_obj; 730 volatile uint32_t *ring; 731 unsigned rptr; 732 unsigned rptr_offs; 733 unsigned rptr_reg; 734 unsigned rptr_save_reg; 735 u64 next_rptr_gpu_addr; 736 volatile u32 *next_rptr_cpu_addr; 737 unsigned wptr; 738 unsigned wptr_old; 739 unsigned wptr_reg; 740 unsigned ring_size; 741 unsigned ring_free_dw; 742 int count_dw; 743 unsigned long last_activity; 744 unsigned last_rptr; 745 uint64_t gpu_addr; 746 uint32_t align_mask; 747 uint32_t ptr_mask; 748 bool ready; 749 u32 ptr_reg_shift; 750 u32 ptr_reg_mask; 751 u32 nop; 752 u32 idx; 753 u64 last_semaphore_signal_addr; 754 u64 last_semaphore_wait_addr; 755 /* for CIK queues */ 756 u32 me; 757 u32 pipe; 758 u32 queue; 759 struct radeon_bo *mqd_obj; 760 u32 doorbell_page_num; 761 u32 doorbell_offset; 762 unsigned wptr_offs; 763 }; 764 765 struct radeon_mec { 766 struct radeon_bo *hpd_eop_obj; 767 u64 hpd_eop_gpu_addr; 768 u32 num_pipe; 769 u32 num_mec; 770 u32 num_queue; 771 }; 772 773 /* 774 * VM 775 */ 776 777 /* maximum number of VMIDs */ 778 #define RADEON_NUM_VM 16 779 780 /* defines number of bits in page table versus page directory, 781 * a page is 4KB so we have 12 bits offset, 9 bits in the page 782 * table and the remaining 19 bits are in the page directory */ 783 #define RADEON_VM_BLOCK_SIZE 9 784 785 /* number of entries in page table */ 786 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) 787 788 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 789 #define RADEON_VM_PTB_ALIGN_SIZE 32768 790 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 791 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 792 793 struct radeon_vm { 794 struct list_head list; 795 struct list_head va; 796 unsigned id; 797 798 /* contains the page directory */ 799 struct radeon_sa_bo *page_directory; 800 uint64_t pd_gpu_addr; 801 802 /* array of page tables, one for each page directory entry */ 803 struct radeon_sa_bo **page_tables; 804 805 struct mutex mutex; 806 /* last fence for cs using this vm */ 807 struct radeon_fence *fence; 808 /* last flush or NULL if we still need to flush */ 809 struct radeon_fence *last_flush; 810 }; 811 812 struct radeon_vm_manager { 813 struct mutex lock; 814 struct list_head lru_vm; 815 struct radeon_fence *active[RADEON_NUM_VM]; 816 struct radeon_sa_manager sa_manager; 817 uint32_t max_pfn; 818 /* number of VMIDs */ 819 unsigned nvm; 820 /* vram base address for page table entry */ 821 u64 vram_base_offset; 822 /* is vm enabled? */ 823 bool enabled; 824 }; 825 826 /* 827 * file private structure 828 */ 829 struct radeon_fpriv { 830 struct radeon_vm vm; 831 }; 832 833 /* 834 * R6xx+ IH ring 835 */ 836 struct r600_ih { 837 struct radeon_bo *ring_obj; 838 volatile uint32_t *ring; 839 unsigned rptr; 840 unsigned ring_size; 841 uint64_t gpu_addr; 842 uint32_t ptr_mask; 843 atomic_t lock; 844 bool enabled; 845 }; 846 847 struct r600_blit_cp_primitives { 848 void (*set_render_target)(struct radeon_device *rdev, int format, 849 int w, int h, u64 gpu_addr); 850 void (*cp_set_surface_sync)(struct radeon_device *rdev, 851 u32 sync_type, u32 size, 852 u64 mc_addr); 853 void (*set_shaders)(struct radeon_device *rdev); 854 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr); 855 void (*set_tex_resource)(struct radeon_device *rdev, 856 int format, int w, int h, int pitch, 857 u64 gpu_addr, u32 size); 858 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1, 859 int x2, int y2); 860 void (*draw_auto)(struct radeon_device *rdev); 861 void (*set_default_state)(struct radeon_device *rdev); 862 }; 863 864 struct r600_blit { 865 struct radeon_bo *shader_obj; 866 struct r600_blit_cp_primitives primitives; 867 int max_dim; 868 int ring_size_common; 869 int ring_size_per_loop; 870 u64 shader_gpu_addr; 871 u32 vs_offset, ps_offset; 872 u32 state_offset; 873 u32 state_len; 874 }; 875 876 /* 877 * RLC stuff 878 */ 879 #include "clearstate_defs.h" 880 881 struct radeon_rlc { 882 /* for power gating */ 883 struct radeon_bo *save_restore_obj; 884 uint64_t save_restore_gpu_addr; 885 volatile uint32_t *sr_ptr; 886 u32 *reg_list; 887 u32 reg_list_size; 888 /* for clear state */ 889 struct radeon_bo *clear_state_obj; 890 uint64_t clear_state_gpu_addr; 891 volatile uint32_t *cs_ptr; 892 struct cs_section_def *cs_data; 893 }; 894 895 int radeon_ib_get(struct radeon_device *rdev, int ring, 896 struct radeon_ib *ib, struct radeon_vm *vm, 897 unsigned size); 898 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 899 void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence); 900 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 901 struct radeon_ib *const_ib); 902 int radeon_ib_pool_init(struct radeon_device *rdev); 903 void radeon_ib_pool_fini(struct radeon_device *rdev); 904 int radeon_ib_ring_tests(struct radeon_device *rdev); 905 /* Ring access between begin & end cannot sleep */ 906 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 907 struct radeon_ring *ring); 908 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 909 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 910 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 911 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); 912 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); 913 void radeon_ring_undo(struct radeon_ring *ring); 914 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 915 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 916 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring); 917 void radeon_ring_lockup_update(struct radeon_ring *ring); 918 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 919 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 920 uint32_t **data); 921 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 922 unsigned size, uint32_t *data); 923 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 924 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, 925 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop); 926 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 927 928 929 /* r600 async dma */ 930 void r600_dma_stop(struct radeon_device *rdev); 931 int r600_dma_resume(struct radeon_device *rdev); 932 void r600_dma_fini(struct radeon_device *rdev); 933 934 void cayman_dma_stop(struct radeon_device *rdev); 935 int cayman_dma_resume(struct radeon_device *rdev); 936 void cayman_dma_fini(struct radeon_device *rdev); 937 938 /* 939 * CS. 940 */ 941 struct radeon_cs_reloc { 942 struct drm_gem_object *gobj; 943 struct radeon_bo *robj; 944 struct radeon_bo_list lobj; 945 uint32_t handle; 946 uint32_t flags; 947 }; 948 949 struct radeon_cs_chunk { 950 uint32_t chunk_id; 951 uint32_t length_dw; 952 int kpage_idx[2]; 953 uint32_t *kpage[2]; 954 uint32_t *kdata; 955 void __user *user_ptr; 956 int last_copied_page; 957 int last_page_index; 958 }; 959 960 struct radeon_cs_parser { 961 struct device *dev; 962 struct radeon_device *rdev; 963 struct drm_file *filp; 964 /* chunks */ 965 unsigned nchunks; 966 struct radeon_cs_chunk *chunks; 967 uint64_t *chunks_array; 968 /* IB */ 969 unsigned idx; 970 /* relocations */ 971 unsigned nrelocs; 972 struct radeon_cs_reloc *relocs; 973 struct radeon_cs_reloc **relocs_ptr; 974 struct list_head validated; 975 unsigned dma_reloc_idx; 976 /* indices of various chunks */ 977 int chunk_ib_idx; 978 int chunk_relocs_idx; 979 int chunk_flags_idx; 980 int chunk_const_ib_idx; 981 struct radeon_ib ib; 982 struct radeon_ib const_ib; 983 void *track; 984 unsigned family; 985 int parser_error; 986 u32 cs_flags; 987 u32 ring; 988 s32 priority; 989 struct ww_acquire_ctx ticket; 990 }; 991 992 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); 993 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); 994 995 struct radeon_cs_packet { 996 unsigned idx; 997 unsigned type; 998 unsigned reg; 999 unsigned opcode; 1000 int count; 1001 unsigned one_reg_wr; 1002 }; 1003 1004 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1005 struct radeon_cs_packet *pkt, 1006 unsigned idx, unsigned reg); 1007 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1008 struct radeon_cs_packet *pkt); 1009 1010 1011 /* 1012 * AGP 1013 */ 1014 int radeon_agp_init(struct radeon_device *rdev); 1015 void radeon_agp_resume(struct radeon_device *rdev); 1016 void radeon_agp_suspend(struct radeon_device *rdev); 1017 void radeon_agp_fini(struct radeon_device *rdev); 1018 1019 1020 /* 1021 * Writeback 1022 */ 1023 struct radeon_wb { 1024 struct radeon_bo *wb_obj; 1025 volatile uint32_t *wb; 1026 uint64_t gpu_addr; 1027 bool enabled; 1028 bool use_event; 1029 }; 1030 1031 #define RADEON_WB_SCRATCH_OFFSET 0 1032 #define RADEON_WB_RING0_NEXT_RPTR 256 1033 #define RADEON_WB_CP_RPTR_OFFSET 1024 1034 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1035 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1036 #define R600_WB_DMA_RPTR_OFFSET 1792 1037 #define R600_WB_IH_WPTR_OFFSET 2048 1038 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1039 #define R600_WB_UVD_RPTR_OFFSET 2560 1040 #define R600_WB_EVENT_OFFSET 3072 1041 #define CIK_WB_CP1_WPTR_OFFSET 3328 1042 #define CIK_WB_CP2_WPTR_OFFSET 3584 1043 1044 /** 1045 * struct radeon_pm - power management datas 1046 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1047 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1048 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1049 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1050 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1051 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1052 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1053 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1054 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1055 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1056 * @needed_bandwidth: current bandwidth needs 1057 * 1058 * It keeps track of various data needed to take powermanagement decision. 1059 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1060 * Equation between gpu/memory clock and available bandwidth is hw dependent 1061 * (type of memory, bus size, efficiency, ...) 1062 */ 1063 1064 enum radeon_pm_method { 1065 PM_METHOD_PROFILE, 1066 PM_METHOD_DYNPM, 1067 PM_METHOD_DPM, 1068 }; 1069 1070 enum radeon_dynpm_state { 1071 DYNPM_STATE_DISABLED, 1072 DYNPM_STATE_MINIMUM, 1073 DYNPM_STATE_PAUSED, 1074 DYNPM_STATE_ACTIVE, 1075 DYNPM_STATE_SUSPENDED, 1076 }; 1077 enum radeon_dynpm_action { 1078 DYNPM_ACTION_NONE, 1079 DYNPM_ACTION_MINIMUM, 1080 DYNPM_ACTION_DOWNCLOCK, 1081 DYNPM_ACTION_UPCLOCK, 1082 DYNPM_ACTION_DEFAULT 1083 }; 1084 1085 enum radeon_voltage_type { 1086 VOLTAGE_NONE = 0, 1087 VOLTAGE_GPIO, 1088 VOLTAGE_VDDC, 1089 VOLTAGE_SW 1090 }; 1091 1092 enum radeon_pm_state_type { 1093 /* not used for dpm */ 1094 POWER_STATE_TYPE_DEFAULT, 1095 POWER_STATE_TYPE_POWERSAVE, 1096 /* user selectable states */ 1097 POWER_STATE_TYPE_BATTERY, 1098 POWER_STATE_TYPE_BALANCED, 1099 POWER_STATE_TYPE_PERFORMANCE, 1100 /* internal states */ 1101 POWER_STATE_TYPE_INTERNAL_UVD, 1102 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1103 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1104 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1105 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1106 POWER_STATE_TYPE_INTERNAL_BOOT, 1107 POWER_STATE_TYPE_INTERNAL_THERMAL, 1108 POWER_STATE_TYPE_INTERNAL_ACPI, 1109 POWER_STATE_TYPE_INTERNAL_ULV, 1110 POWER_STATE_TYPE_INTERNAL_3DPERF, 1111 }; 1112 1113 enum radeon_pm_profile_type { 1114 PM_PROFILE_DEFAULT, 1115 PM_PROFILE_AUTO, 1116 PM_PROFILE_LOW, 1117 PM_PROFILE_MID, 1118 PM_PROFILE_HIGH, 1119 }; 1120 1121 #define PM_PROFILE_DEFAULT_IDX 0 1122 #define PM_PROFILE_LOW_SH_IDX 1 1123 #define PM_PROFILE_MID_SH_IDX 2 1124 #define PM_PROFILE_HIGH_SH_IDX 3 1125 #define PM_PROFILE_LOW_MH_IDX 4 1126 #define PM_PROFILE_MID_MH_IDX 5 1127 #define PM_PROFILE_HIGH_MH_IDX 6 1128 #define PM_PROFILE_MAX 7 1129 1130 struct radeon_pm_profile { 1131 int dpms_off_ps_idx; 1132 int dpms_on_ps_idx; 1133 int dpms_off_cm_idx; 1134 int dpms_on_cm_idx; 1135 }; 1136 1137 enum radeon_int_thermal_type { 1138 THERMAL_TYPE_NONE, 1139 THERMAL_TYPE_EXTERNAL, 1140 THERMAL_TYPE_EXTERNAL_GPIO, 1141 THERMAL_TYPE_RV6XX, 1142 THERMAL_TYPE_RV770, 1143 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1144 THERMAL_TYPE_EVERGREEN, 1145 THERMAL_TYPE_SUMO, 1146 THERMAL_TYPE_NI, 1147 THERMAL_TYPE_SI, 1148 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1149 THERMAL_TYPE_CI, 1150 }; 1151 1152 struct radeon_voltage { 1153 enum radeon_voltage_type type; 1154 /* gpio voltage */ 1155 struct radeon_gpio_rec gpio; 1156 u32 delay; /* delay in usec from voltage drop to sclk change */ 1157 bool active_high; /* voltage drop is active when bit is high */ 1158 /* VDDC voltage */ 1159 u8 vddc_id; /* index into vddc voltage table */ 1160 u8 vddci_id; /* index into vddci voltage table */ 1161 bool vddci_enabled; 1162 /* r6xx+ sw */ 1163 u16 voltage; 1164 /* evergreen+ vddci */ 1165 u16 vddci; 1166 }; 1167 1168 /* clock mode flags */ 1169 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1170 1171 struct radeon_pm_clock_info { 1172 /* memory clock */ 1173 u32 mclk; 1174 /* engine clock */ 1175 u32 sclk; 1176 /* voltage info */ 1177 struct radeon_voltage voltage; 1178 /* standardized clock flags */ 1179 u32 flags; 1180 }; 1181 1182 /* state flags */ 1183 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1184 1185 struct radeon_power_state { 1186 enum radeon_pm_state_type type; 1187 struct radeon_pm_clock_info *clock_info; 1188 /* number of valid clock modes in this power state */ 1189 int num_clock_modes; 1190 struct radeon_pm_clock_info *default_clock_mode; 1191 /* standardized state flags */ 1192 u32 flags; 1193 u32 misc; /* vbios specific flags */ 1194 u32 misc2; /* vbios specific flags */ 1195 int pcie_lanes; /* pcie lanes */ 1196 }; 1197 1198 /* 1199 * Some modes are overclocked by very low value, accept them 1200 */ 1201 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1202 1203 enum radeon_dpm_auto_throttle_src { 1204 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1205 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1206 }; 1207 1208 enum radeon_dpm_event_src { 1209 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1210 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1211 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1212 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1213 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1214 }; 1215 1216 struct radeon_ps { 1217 u32 caps; /* vbios flags */ 1218 u32 class; /* vbios flags */ 1219 u32 class2; /* vbios flags */ 1220 /* UVD clocks */ 1221 u32 vclk; 1222 u32 dclk; 1223 /* asic priv */ 1224 void *ps_priv; 1225 }; 1226 1227 struct radeon_dpm_thermal { 1228 /* thermal interrupt work */ 1229 struct work_struct work; 1230 /* low temperature threshold */ 1231 int min_temp; 1232 /* high temperature threshold */ 1233 int max_temp; 1234 /* was interrupt low to high or high to low */ 1235 bool high_to_low; 1236 }; 1237 1238 enum radeon_clk_action 1239 { 1240 RADEON_SCLK_UP = 1, 1241 RADEON_SCLK_DOWN 1242 }; 1243 1244 struct radeon_blacklist_clocks 1245 { 1246 u32 sclk; 1247 u32 mclk; 1248 enum radeon_clk_action action; 1249 }; 1250 1251 struct radeon_clock_and_voltage_limits { 1252 u32 sclk; 1253 u32 mclk; 1254 u32 vddc; 1255 u32 vddci; 1256 }; 1257 1258 struct radeon_clock_array { 1259 u32 count; 1260 u32 *values; 1261 }; 1262 1263 struct radeon_clock_voltage_dependency_entry { 1264 u32 clk; 1265 u16 v; 1266 }; 1267 1268 struct radeon_clock_voltage_dependency_table { 1269 u32 count; 1270 struct radeon_clock_voltage_dependency_entry *entries; 1271 }; 1272 1273 struct radeon_cac_leakage_entry { 1274 u16 vddc; 1275 u32 leakage; 1276 }; 1277 1278 struct radeon_cac_leakage_table { 1279 u32 count; 1280 struct radeon_cac_leakage_entry *entries; 1281 }; 1282 1283 struct radeon_phase_shedding_limits_entry { 1284 u16 voltage; 1285 u32 sclk; 1286 u32 mclk; 1287 }; 1288 1289 struct radeon_phase_shedding_limits_table { 1290 u32 count; 1291 struct radeon_phase_shedding_limits_entry *entries; 1292 }; 1293 1294 struct radeon_ppm_table { 1295 u8 ppm_design; 1296 u16 cpu_core_number; 1297 u32 platform_tdp; 1298 u32 small_ac_platform_tdp; 1299 u32 platform_tdc; 1300 u32 small_ac_platform_tdc; 1301 u32 apu_tdp; 1302 u32 dgpu_tdp; 1303 u32 dgpu_ulv_power; 1304 u32 tj_max; 1305 }; 1306 1307 struct radeon_dpm_dynamic_state { 1308 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1309 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1310 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1311 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1312 struct radeon_clock_array valid_sclk_values; 1313 struct radeon_clock_array valid_mclk_values; 1314 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1315 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1316 u32 mclk_sclk_ratio; 1317 u32 sclk_mclk_delta; 1318 u16 vddc_vddci_delta; 1319 u16 min_vddc_for_pcie_gen2; 1320 struct radeon_cac_leakage_table cac_leakage_table; 1321 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1322 struct radeon_ppm_table *ppm_table; 1323 }; 1324 1325 struct radeon_dpm_fan { 1326 u16 t_min; 1327 u16 t_med; 1328 u16 t_high; 1329 u16 pwm_min; 1330 u16 pwm_med; 1331 u16 pwm_high; 1332 u8 t_hyst; 1333 u32 cycle_delay; 1334 u16 t_max; 1335 bool ucode_fan_control; 1336 }; 1337 1338 enum radeon_pcie_gen { 1339 RADEON_PCIE_GEN1 = 0, 1340 RADEON_PCIE_GEN2 = 1, 1341 RADEON_PCIE_GEN3 = 2, 1342 RADEON_PCIE_GEN_INVALID = 0xffff 1343 }; 1344 1345 enum radeon_dpm_forced_level { 1346 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1347 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1348 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1349 }; 1350 1351 struct radeon_dpm { 1352 struct radeon_ps *ps; 1353 /* number of valid power states */ 1354 int num_ps; 1355 /* current power state that is active */ 1356 struct radeon_ps *current_ps; 1357 /* requested power state */ 1358 struct radeon_ps *requested_ps; 1359 /* boot up power state */ 1360 struct radeon_ps *boot_ps; 1361 /* default uvd power state */ 1362 struct radeon_ps *uvd_ps; 1363 enum radeon_pm_state_type state; 1364 enum radeon_pm_state_type user_state; 1365 u32 platform_caps; 1366 u32 voltage_response_time; 1367 u32 backbias_response_time; 1368 void *priv; 1369 u32 new_active_crtcs; 1370 int new_active_crtc_count; 1371 u32 current_active_crtcs; 1372 int current_active_crtc_count; 1373 struct radeon_dpm_dynamic_state dyn_state; 1374 struct radeon_dpm_fan fan; 1375 u32 tdp_limit; 1376 u32 near_tdp_limit; 1377 u32 near_tdp_limit_adjusted; 1378 u32 sq_ramping_threshold; 1379 u32 cac_leakage; 1380 u16 tdp_od_limit; 1381 u32 tdp_adjustment; 1382 u16 load_line_slope; 1383 bool power_control; 1384 bool ac_power; 1385 /* special states active */ 1386 bool thermal_active; 1387 bool uvd_active; 1388 /* thermal handling */ 1389 struct radeon_dpm_thermal thermal; 1390 /* forced levels */ 1391 enum radeon_dpm_forced_level forced_level; 1392 }; 1393 1394 void radeon_dpm_enable_power_state(struct radeon_device *rdev, 1395 enum radeon_pm_state_type dpm_state); 1396 1397 1398 struct radeon_pm { 1399 struct mutex mutex; 1400 /* write locked while reprogramming mclk */ 1401 struct rw_semaphore mclk_lock; 1402 u32 active_crtcs; 1403 int active_crtc_count; 1404 int req_vblank; 1405 bool vblank_sync; 1406 fixed20_12 max_bandwidth; 1407 fixed20_12 igp_sideport_mclk; 1408 fixed20_12 igp_system_mclk; 1409 fixed20_12 igp_ht_link_clk; 1410 fixed20_12 igp_ht_link_width; 1411 fixed20_12 k8_bandwidth; 1412 fixed20_12 sideport_bandwidth; 1413 fixed20_12 ht_bandwidth; 1414 fixed20_12 core_bandwidth; 1415 fixed20_12 sclk; 1416 fixed20_12 mclk; 1417 fixed20_12 needed_bandwidth; 1418 struct radeon_power_state *power_state; 1419 /* number of valid power states */ 1420 int num_power_states; 1421 int current_power_state_index; 1422 int current_clock_mode_index; 1423 int requested_power_state_index; 1424 int requested_clock_mode_index; 1425 int default_power_state_index; 1426 u32 current_sclk; 1427 u32 current_mclk; 1428 u16 current_vddc; 1429 u16 current_vddci; 1430 u32 default_sclk; 1431 u32 default_mclk; 1432 u16 default_vddc; 1433 u16 default_vddci; 1434 struct radeon_i2c_chan *i2c_bus; 1435 /* selected pm method */ 1436 enum radeon_pm_method pm_method; 1437 /* dynpm power management */ 1438 struct delayed_work dynpm_idle_work; 1439 enum radeon_dynpm_state dynpm_state; 1440 enum radeon_dynpm_action dynpm_planned_action; 1441 unsigned long dynpm_action_timeout; 1442 bool dynpm_can_upclock; 1443 bool dynpm_can_downclock; 1444 /* profile-based power management */ 1445 enum radeon_pm_profile_type profile; 1446 int profile_index; 1447 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1448 /* internal thermal controller on rv6xx+ */ 1449 enum radeon_int_thermal_type int_thermal_type; 1450 struct device *int_hwmon_dev; 1451 /* dpm */ 1452 bool dpm_enabled; 1453 struct radeon_dpm dpm; 1454 }; 1455 1456 int radeon_pm_get_type_index(struct radeon_device *rdev, 1457 enum radeon_pm_state_type ps_type, 1458 int instance); 1459 /* 1460 * UVD 1461 */ 1462 #define RADEON_MAX_UVD_HANDLES 10 1463 #define RADEON_UVD_STACK_SIZE (1024*1024) 1464 #define RADEON_UVD_HEAP_SIZE (1024*1024) 1465 1466 struct radeon_uvd { 1467 struct radeon_bo *vcpu_bo; 1468 void *cpu_addr; 1469 uint64_t gpu_addr; 1470 void *saved_bo; 1471 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1472 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1473 struct delayed_work idle_work; 1474 }; 1475 1476 int radeon_uvd_init(struct radeon_device *rdev); 1477 void radeon_uvd_fini(struct radeon_device *rdev); 1478 int radeon_uvd_suspend(struct radeon_device *rdev); 1479 int radeon_uvd_resume(struct radeon_device *rdev); 1480 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1481 uint32_t handle, struct radeon_fence **fence); 1482 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1483 uint32_t handle, struct radeon_fence **fence); 1484 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo); 1485 void radeon_uvd_free_handles(struct radeon_device *rdev, 1486 struct drm_file *filp); 1487 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1488 void radeon_uvd_note_usage(struct radeon_device *rdev); 1489 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1490 unsigned vclk, unsigned dclk, 1491 unsigned vco_min, unsigned vco_max, 1492 unsigned fb_factor, unsigned fb_mask, 1493 unsigned pd_min, unsigned pd_max, 1494 unsigned pd_even, 1495 unsigned *optimal_fb_div, 1496 unsigned *optimal_vclk_div, 1497 unsigned *optimal_dclk_div); 1498 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1499 unsigned cg_upll_func_cntl); 1500 1501 struct r600_audio { 1502 int channels; 1503 int rate; 1504 int bits_per_sample; 1505 u8 status_bits; 1506 u8 category_code; 1507 }; 1508 1509 /* 1510 * Benchmarking 1511 */ 1512 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1513 1514 1515 /* 1516 * Testing 1517 */ 1518 void radeon_test_moves(struct radeon_device *rdev); 1519 void radeon_test_ring_sync(struct radeon_device *rdev, 1520 struct radeon_ring *cpA, 1521 struct radeon_ring *cpB); 1522 void radeon_test_syncing(struct radeon_device *rdev); 1523 1524 1525 /* 1526 * Debugfs 1527 */ 1528 struct radeon_debugfs { 1529 struct drm_info_list *files; 1530 unsigned num_files; 1531 }; 1532 1533 int radeon_debugfs_add_files(struct radeon_device *rdev, 1534 struct drm_info_list *files, 1535 unsigned nfiles); 1536 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1537 1538 1539 /* 1540 * ASIC specific functions. 1541 */ 1542 struct radeon_asic { 1543 int (*init)(struct radeon_device *rdev); 1544 void (*fini)(struct radeon_device *rdev); 1545 int (*resume)(struct radeon_device *rdev); 1546 int (*suspend)(struct radeon_device *rdev); 1547 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1548 int (*asic_reset)(struct radeon_device *rdev); 1549 /* ioctl hw specific callback. Some hw might want to perform special 1550 * operation on specific ioctl. For instance on wait idle some hw 1551 * might want to perform and HDP flush through MMIO as it seems that 1552 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed 1553 * through ring. 1554 */ 1555 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); 1556 /* check if 3D engine is idle */ 1557 bool (*gui_idle)(struct radeon_device *rdev); 1558 /* wait for mc_idle */ 1559 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1560 /* get the reference clock */ 1561 u32 (*get_xclk)(struct radeon_device *rdev); 1562 /* get the gpu clock counter */ 1563 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1564 /* gart */ 1565 struct { 1566 void (*tlb_flush)(struct radeon_device *rdev); 1567 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); 1568 } gart; 1569 struct { 1570 int (*init)(struct radeon_device *rdev); 1571 void (*fini)(struct radeon_device *rdev); 1572 1573 u32 pt_ring_index; 1574 void (*set_page)(struct radeon_device *rdev, 1575 struct radeon_ib *ib, 1576 uint64_t pe, 1577 uint64_t addr, unsigned count, 1578 uint32_t incr, uint32_t flags); 1579 } vm; 1580 /* ring specific callbacks */ 1581 struct { 1582 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1583 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1584 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1585 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1586 struct radeon_semaphore *semaphore, bool emit_wait); 1587 int (*cs_parse)(struct radeon_cs_parser *p); 1588 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1589 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1590 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1591 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1592 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 1593 1594 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1595 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1596 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1597 } ring[RADEON_NUM_RINGS]; 1598 /* irqs */ 1599 struct { 1600 int (*set)(struct radeon_device *rdev); 1601 int (*process)(struct radeon_device *rdev); 1602 } irq; 1603 /* displays */ 1604 struct { 1605 /* display watermarks */ 1606 void (*bandwidth_update)(struct radeon_device *rdev); 1607 /* get frame count */ 1608 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1609 /* wait for vblank */ 1610 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1611 /* set backlight level */ 1612 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1613 /* get backlight level */ 1614 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1615 /* audio callbacks */ 1616 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1617 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1618 } display; 1619 /* copy functions for bo handling */ 1620 struct { 1621 int (*blit)(struct radeon_device *rdev, 1622 uint64_t src_offset, 1623 uint64_t dst_offset, 1624 unsigned num_gpu_pages, 1625 struct radeon_fence **fence); 1626 u32 blit_ring_index; 1627 int (*dma)(struct radeon_device *rdev, 1628 uint64_t src_offset, 1629 uint64_t dst_offset, 1630 unsigned num_gpu_pages, 1631 struct radeon_fence **fence); 1632 u32 dma_ring_index; 1633 /* method used for bo copy */ 1634 int (*copy)(struct radeon_device *rdev, 1635 uint64_t src_offset, 1636 uint64_t dst_offset, 1637 unsigned num_gpu_pages, 1638 struct radeon_fence **fence); 1639 /* ring used for bo copies */ 1640 u32 copy_ring_index; 1641 } copy; 1642 /* surfaces */ 1643 struct { 1644 int (*set_reg)(struct radeon_device *rdev, int reg, 1645 uint32_t tiling_flags, uint32_t pitch, 1646 uint32_t offset, uint32_t obj_size); 1647 void (*clear_reg)(struct radeon_device *rdev, int reg); 1648 } surface; 1649 /* hotplug detect */ 1650 struct { 1651 void (*init)(struct radeon_device *rdev); 1652 void (*fini)(struct radeon_device *rdev); 1653 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1654 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1655 } hpd; 1656 /* static power management */ 1657 struct { 1658 void (*misc)(struct radeon_device *rdev); 1659 void (*prepare)(struct radeon_device *rdev); 1660 void (*finish)(struct radeon_device *rdev); 1661 void (*init_profile)(struct radeon_device *rdev); 1662 void (*get_dynpm_state)(struct radeon_device *rdev); 1663 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1664 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1665 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1666 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1667 int (*get_pcie_lanes)(struct radeon_device *rdev); 1668 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1669 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1670 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1671 int (*get_temperature)(struct radeon_device *rdev); 1672 } pm; 1673 /* dynamic power management */ 1674 struct { 1675 int (*init)(struct radeon_device *rdev); 1676 void (*setup_asic)(struct radeon_device *rdev); 1677 int (*enable)(struct radeon_device *rdev); 1678 void (*disable)(struct radeon_device *rdev); 1679 int (*pre_set_power_state)(struct radeon_device *rdev); 1680 int (*set_power_state)(struct radeon_device *rdev); 1681 void (*post_set_power_state)(struct radeon_device *rdev); 1682 void (*display_configuration_changed)(struct radeon_device *rdev); 1683 void (*fini)(struct radeon_device *rdev); 1684 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1685 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1686 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1687 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1688 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 1689 bool (*vblank_too_short)(struct radeon_device *rdev); 1690 } dpm; 1691 /* pageflipping */ 1692 struct { 1693 void (*pre_page_flip)(struct radeon_device *rdev, int crtc); 1694 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1695 void (*post_page_flip)(struct radeon_device *rdev, int crtc); 1696 } pflip; 1697 }; 1698 1699 /* 1700 * Asic structures 1701 */ 1702 struct r100_asic { 1703 const unsigned *reg_safe_bm; 1704 unsigned reg_safe_bm_size; 1705 u32 hdp_cntl; 1706 }; 1707 1708 struct r300_asic { 1709 const unsigned *reg_safe_bm; 1710 unsigned reg_safe_bm_size; 1711 u32 resync_scratch; 1712 u32 hdp_cntl; 1713 }; 1714 1715 struct r600_asic { 1716 unsigned max_pipes; 1717 unsigned max_tile_pipes; 1718 unsigned max_simds; 1719 unsigned max_backends; 1720 unsigned max_gprs; 1721 unsigned max_threads; 1722 unsigned max_stack_entries; 1723 unsigned max_hw_contexts; 1724 unsigned max_gs_threads; 1725 unsigned sx_max_export_size; 1726 unsigned sx_max_export_pos_size; 1727 unsigned sx_max_export_smx_size; 1728 unsigned sq_num_cf_insts; 1729 unsigned tiling_nbanks; 1730 unsigned tiling_npipes; 1731 unsigned tiling_group_size; 1732 unsigned tile_config; 1733 unsigned backend_map; 1734 }; 1735 1736 struct rv770_asic { 1737 unsigned max_pipes; 1738 unsigned max_tile_pipes; 1739 unsigned max_simds; 1740 unsigned max_backends; 1741 unsigned max_gprs; 1742 unsigned max_threads; 1743 unsigned max_stack_entries; 1744 unsigned max_hw_contexts; 1745 unsigned max_gs_threads; 1746 unsigned sx_max_export_size; 1747 unsigned sx_max_export_pos_size; 1748 unsigned sx_max_export_smx_size; 1749 unsigned sq_num_cf_insts; 1750 unsigned sx_num_of_sets; 1751 unsigned sc_prim_fifo_size; 1752 unsigned sc_hiz_tile_fifo_size; 1753 unsigned sc_earlyz_tile_fifo_fize; 1754 unsigned tiling_nbanks; 1755 unsigned tiling_npipes; 1756 unsigned tiling_group_size; 1757 unsigned tile_config; 1758 unsigned backend_map; 1759 }; 1760 1761 struct evergreen_asic { 1762 unsigned num_ses; 1763 unsigned max_pipes; 1764 unsigned max_tile_pipes; 1765 unsigned max_simds; 1766 unsigned max_backends; 1767 unsigned max_gprs; 1768 unsigned max_threads; 1769 unsigned max_stack_entries; 1770 unsigned max_hw_contexts; 1771 unsigned max_gs_threads; 1772 unsigned sx_max_export_size; 1773 unsigned sx_max_export_pos_size; 1774 unsigned sx_max_export_smx_size; 1775 unsigned sq_num_cf_insts; 1776 unsigned sx_num_of_sets; 1777 unsigned sc_prim_fifo_size; 1778 unsigned sc_hiz_tile_fifo_size; 1779 unsigned sc_earlyz_tile_fifo_size; 1780 unsigned tiling_nbanks; 1781 unsigned tiling_npipes; 1782 unsigned tiling_group_size; 1783 unsigned tile_config; 1784 unsigned backend_map; 1785 }; 1786 1787 struct cayman_asic { 1788 unsigned max_shader_engines; 1789 unsigned max_pipes_per_simd; 1790 unsigned max_tile_pipes; 1791 unsigned max_simds_per_se; 1792 unsigned max_backends_per_se; 1793 unsigned max_texture_channel_caches; 1794 unsigned max_gprs; 1795 unsigned max_threads; 1796 unsigned max_gs_threads; 1797 unsigned max_stack_entries; 1798 unsigned sx_num_of_sets; 1799 unsigned sx_max_export_size; 1800 unsigned sx_max_export_pos_size; 1801 unsigned sx_max_export_smx_size; 1802 unsigned max_hw_contexts; 1803 unsigned sq_num_cf_insts; 1804 unsigned sc_prim_fifo_size; 1805 unsigned sc_hiz_tile_fifo_size; 1806 unsigned sc_earlyz_tile_fifo_size; 1807 1808 unsigned num_shader_engines; 1809 unsigned num_shader_pipes_per_simd; 1810 unsigned num_tile_pipes; 1811 unsigned num_simds_per_se; 1812 unsigned num_backends_per_se; 1813 unsigned backend_disable_mask_per_asic; 1814 unsigned backend_map; 1815 unsigned num_texture_channel_caches; 1816 unsigned mem_max_burst_length_bytes; 1817 unsigned mem_row_size_in_kb; 1818 unsigned shader_engine_tile_size; 1819 unsigned num_gpus; 1820 unsigned multi_gpu_tile_size; 1821 1822 unsigned tile_config; 1823 }; 1824 1825 struct si_asic { 1826 unsigned max_shader_engines; 1827 unsigned max_tile_pipes; 1828 unsigned max_cu_per_sh; 1829 unsigned max_sh_per_se; 1830 unsigned max_backends_per_se; 1831 unsigned max_texture_channel_caches; 1832 unsigned max_gprs; 1833 unsigned max_gs_threads; 1834 unsigned max_hw_contexts; 1835 unsigned sc_prim_fifo_size_frontend; 1836 unsigned sc_prim_fifo_size_backend; 1837 unsigned sc_hiz_tile_fifo_size; 1838 unsigned sc_earlyz_tile_fifo_size; 1839 1840 unsigned num_tile_pipes; 1841 unsigned num_backends_per_se; 1842 unsigned backend_disable_mask_per_asic; 1843 unsigned backend_map; 1844 unsigned num_texture_channel_caches; 1845 unsigned mem_max_burst_length_bytes; 1846 unsigned mem_row_size_in_kb; 1847 unsigned shader_engine_tile_size; 1848 unsigned num_gpus; 1849 unsigned multi_gpu_tile_size; 1850 1851 unsigned tile_config; 1852 uint32_t tile_mode_array[32]; 1853 }; 1854 1855 struct cik_asic { 1856 unsigned max_shader_engines; 1857 unsigned max_tile_pipes; 1858 unsigned max_cu_per_sh; 1859 unsigned max_sh_per_se; 1860 unsigned max_backends_per_se; 1861 unsigned max_texture_channel_caches; 1862 unsigned max_gprs; 1863 unsigned max_gs_threads; 1864 unsigned max_hw_contexts; 1865 unsigned sc_prim_fifo_size_frontend; 1866 unsigned sc_prim_fifo_size_backend; 1867 unsigned sc_hiz_tile_fifo_size; 1868 unsigned sc_earlyz_tile_fifo_size; 1869 1870 unsigned num_tile_pipes; 1871 unsigned num_backends_per_se; 1872 unsigned backend_disable_mask_per_asic; 1873 unsigned backend_map; 1874 unsigned num_texture_channel_caches; 1875 unsigned mem_max_burst_length_bytes; 1876 unsigned mem_row_size_in_kb; 1877 unsigned shader_engine_tile_size; 1878 unsigned num_gpus; 1879 unsigned multi_gpu_tile_size; 1880 1881 unsigned tile_config; 1882 uint32_t tile_mode_array[32]; 1883 }; 1884 1885 union radeon_asic_config { 1886 struct r300_asic r300; 1887 struct r100_asic r100; 1888 struct r600_asic r600; 1889 struct rv770_asic rv770; 1890 struct evergreen_asic evergreen; 1891 struct cayman_asic cayman; 1892 struct si_asic si; 1893 struct cik_asic cik; 1894 }; 1895 1896 /* 1897 * asic initizalization from radeon_asic.c 1898 */ 1899 void radeon_agp_disable(struct radeon_device *rdev); 1900 int radeon_asic_init(struct radeon_device *rdev); 1901 1902 1903 /* 1904 * IOCTL. 1905 */ 1906 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 1907 struct drm_file *filp); 1908 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 1909 struct drm_file *filp); 1910 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 1911 struct drm_file *file_priv); 1912 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 1913 struct drm_file *file_priv); 1914 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1915 struct drm_file *file_priv); 1916 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 1917 struct drm_file *file_priv); 1918 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1919 struct drm_file *filp); 1920 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 1921 struct drm_file *filp); 1922 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 1923 struct drm_file *filp); 1924 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1925 struct drm_file *filp); 1926 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 1927 struct drm_file *filp); 1928 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1929 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 1930 struct drm_file *filp); 1931 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 1932 struct drm_file *filp); 1933 1934 /* VRAM scratch page for HDP bug, default vram page */ 1935 struct r600_vram_scratch { 1936 struct radeon_bo *robj; 1937 volatile uint32_t *ptr; 1938 u64 gpu_addr; 1939 }; 1940 1941 /* 1942 * ACPI 1943 */ 1944 struct radeon_atif_notification_cfg { 1945 bool enabled; 1946 int command_code; 1947 }; 1948 1949 struct radeon_atif_notifications { 1950 bool display_switch; 1951 bool expansion_mode_change; 1952 bool thermal_state; 1953 bool forced_power_state; 1954 bool system_power_state; 1955 bool display_conf_change; 1956 bool px_gfx_switch; 1957 bool brightness_change; 1958 bool dgpu_display_event; 1959 }; 1960 1961 struct radeon_atif_functions { 1962 bool system_params; 1963 bool sbios_requests; 1964 bool select_active_disp; 1965 bool lid_state; 1966 bool get_tv_standard; 1967 bool set_tv_standard; 1968 bool get_panel_expansion_mode; 1969 bool set_panel_expansion_mode; 1970 bool temperature_change; 1971 bool graphics_device_types; 1972 }; 1973 1974 struct radeon_atif { 1975 struct radeon_atif_notifications notifications; 1976 struct radeon_atif_functions functions; 1977 struct radeon_atif_notification_cfg notification_cfg; 1978 struct radeon_encoder *encoder_for_bl; 1979 }; 1980 1981 struct radeon_atcs_functions { 1982 bool get_ext_state; 1983 bool pcie_perf_req; 1984 bool pcie_dev_rdy; 1985 bool pcie_bus_width; 1986 }; 1987 1988 struct radeon_atcs { 1989 struct radeon_atcs_functions functions; 1990 }; 1991 1992 /* 1993 * Core structure, functions and helpers. 1994 */ 1995 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 1996 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 1997 1998 struct radeon_device { 1999 struct device *dev; 2000 struct drm_device *ddev; 2001 struct pci_dev *pdev; 2002 struct rw_semaphore exclusive_lock; 2003 /* ASIC */ 2004 union radeon_asic_config config; 2005 enum radeon_family family; 2006 unsigned long flags; 2007 int usec_timeout; 2008 enum radeon_pll_errata pll_errata; 2009 int num_gb_pipes; 2010 int num_z_pipes; 2011 int disp_priority; 2012 /* BIOS */ 2013 uint8_t *bios; 2014 bool is_atom_bios; 2015 uint16_t bios_header_start; 2016 struct radeon_bo *stollen_vga_memory; 2017 /* Register mmio */ 2018 resource_size_t rmmio_base; 2019 resource_size_t rmmio_size; 2020 /* protects concurrent MM_INDEX/DATA based register access */ 2021 spinlock_t mmio_idx_lock; 2022 void __iomem *rmmio; 2023 radeon_rreg_t mc_rreg; 2024 radeon_wreg_t mc_wreg; 2025 radeon_rreg_t pll_rreg; 2026 radeon_wreg_t pll_wreg; 2027 uint32_t pcie_reg_mask; 2028 radeon_rreg_t pciep_rreg; 2029 radeon_wreg_t pciep_wreg; 2030 /* io port */ 2031 void __iomem *rio_mem; 2032 resource_size_t rio_mem_size; 2033 struct radeon_clock clock; 2034 struct radeon_mc mc; 2035 struct radeon_gart gart; 2036 struct radeon_mode_info mode_info; 2037 struct radeon_scratch scratch; 2038 struct radeon_doorbell doorbell; 2039 struct radeon_mman mman; 2040 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2041 wait_queue_head_t fence_queue; 2042 struct mutex ring_lock; 2043 struct radeon_ring ring[RADEON_NUM_RINGS]; 2044 bool ib_pool_ready; 2045 struct radeon_sa_manager ring_tmp_bo; 2046 struct radeon_irq irq; 2047 struct radeon_asic *asic; 2048 struct radeon_gem gem; 2049 struct radeon_pm pm; 2050 struct radeon_uvd uvd; 2051 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2052 struct radeon_wb wb; 2053 struct radeon_dummy_page dummy_page; 2054 bool shutdown; 2055 bool suspend; 2056 bool need_dma32; 2057 bool accel_working; 2058 bool fastfb_working; /* IGP feature*/ 2059 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2060 const struct firmware *me_fw; /* all family ME firmware */ 2061 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2062 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2063 const struct firmware *mc_fw; /* NI MC firmware */ 2064 const struct firmware *ce_fw; /* SI CE firmware */ 2065 const struct firmware *mec_fw; /* CIK MEC firmware */ 2066 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2067 const struct firmware *smc_fw; /* SMC firmware */ 2068 const struct firmware *uvd_fw; /* UVD firmware */ 2069 struct r600_blit r600_blit; 2070 struct r600_vram_scratch vram_scratch; 2071 int msi_enabled; /* msi enabled */ 2072 struct r600_ih ih; /* r6/700 interrupt ring */ 2073 struct radeon_rlc rlc; 2074 struct radeon_mec mec; 2075 struct work_struct hotplug_work; 2076 struct work_struct audio_work; 2077 struct work_struct reset_work; 2078 int num_crtc; /* number of crtcs */ 2079 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2080 bool audio_enabled; 2081 bool has_uvd; 2082 struct r600_audio audio_status; /* audio stuff */ 2083 struct notifier_block acpi_nb; 2084 /* only one userspace can use Hyperz features or CMASK at a time */ 2085 struct drm_file *hyperz_filp; 2086 struct drm_file *cmask_filp; 2087 /* i2c buses */ 2088 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2089 /* debugfs */ 2090 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2091 unsigned debugfs_count; 2092 /* virtual memory */ 2093 struct radeon_vm_manager vm_manager; 2094 struct mutex gpu_clock_mutex; 2095 /* ACPI interface */ 2096 struct radeon_atif atif; 2097 struct radeon_atcs atcs; 2098 /* srbm instance registers */ 2099 struct mutex srbm_mutex; 2100 }; 2101 2102 int radeon_device_init(struct radeon_device *rdev, 2103 struct drm_device *ddev, 2104 struct pci_dev *pdev, 2105 uint32_t flags); 2106 void radeon_device_fini(struct radeon_device *rdev); 2107 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2108 2109 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2110 bool always_indirect); 2111 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2112 bool always_indirect); 2113 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2114 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2115 2116 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset); 2117 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v); 2118 2119 /* 2120 * Cast helper 2121 */ 2122 #define to_radeon_fence(p) ((struct radeon_fence *)(p)) 2123 2124 /* 2125 * Registers read & write functions. 2126 */ 2127 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 2128 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 2129 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 2130 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 2131 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2132 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2133 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) 2134 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2135 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2136 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2137 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2138 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2139 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2140 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2141 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2142 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2143 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2144 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2145 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2146 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2147 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2148 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2149 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2150 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2151 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2152 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2153 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2154 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2155 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2156 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2157 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2158 #define WREG32_P(reg, val, mask) \ 2159 do { \ 2160 uint32_t tmp_ = RREG32(reg); \ 2161 tmp_ &= (mask); \ 2162 tmp_ |= ((val) & ~(mask)); \ 2163 WREG32(reg, tmp_); \ 2164 } while (0) 2165 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2166 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2167 #define WREG32_PLL_P(reg, val, mask) \ 2168 do { \ 2169 uint32_t tmp_ = RREG32_PLL(reg); \ 2170 tmp_ &= (mask); \ 2171 tmp_ |= ((val) & ~(mask)); \ 2172 WREG32_PLL(reg, tmp_); \ 2173 } while (0) 2174 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2175 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2176 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2177 2178 #define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset)) 2179 #define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v)) 2180 2181 /* 2182 * Indirect registers accessor 2183 */ 2184 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 2185 { 2186 uint32_t r; 2187 2188 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2189 r = RREG32(RADEON_PCIE_DATA); 2190 return r; 2191 } 2192 2193 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2194 { 2195 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2196 WREG32(RADEON_PCIE_DATA, (v)); 2197 } 2198 2199 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) 2200 { 2201 u32 r; 2202 2203 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2204 r = RREG32(TN_SMC_IND_DATA_0); 2205 return r; 2206 } 2207 2208 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2209 { 2210 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2211 WREG32(TN_SMC_IND_DATA_0, (v)); 2212 } 2213 2214 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) 2215 { 2216 u32 r; 2217 2218 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2219 r = RREG32(R600_RCU_DATA); 2220 return r; 2221 } 2222 2223 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2224 { 2225 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2226 WREG32(R600_RCU_DATA, (v)); 2227 } 2228 2229 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) 2230 { 2231 u32 r; 2232 2233 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2234 r = RREG32(EVERGREEN_CG_IND_DATA); 2235 return r; 2236 } 2237 2238 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2239 { 2240 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2241 WREG32(EVERGREEN_CG_IND_DATA, (v)); 2242 } 2243 2244 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) 2245 { 2246 u32 r; 2247 2248 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2249 r = RREG32(EVERGREEN_PIF_PHY0_DATA); 2250 return r; 2251 } 2252 2253 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2254 { 2255 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2256 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); 2257 } 2258 2259 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) 2260 { 2261 u32 r; 2262 2263 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2264 r = RREG32(EVERGREEN_PIF_PHY1_DATA); 2265 return r; 2266 } 2267 2268 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2269 { 2270 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2271 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); 2272 } 2273 2274 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) 2275 { 2276 u32 r; 2277 2278 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2279 r = RREG32(R600_UVD_CTX_DATA); 2280 return r; 2281 } 2282 2283 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2284 { 2285 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2286 WREG32(R600_UVD_CTX_DATA, (v)); 2287 } 2288 2289 void r100_pll_errata_after_index(struct radeon_device *rdev); 2290 2291 2292 /* 2293 * ASICs helpers. 2294 */ 2295 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2296 (rdev->pdev->device == 0x5969)) 2297 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2298 (rdev->family == CHIP_RV200) || \ 2299 (rdev->family == CHIP_RS100) || \ 2300 (rdev->family == CHIP_RS200) || \ 2301 (rdev->family == CHIP_RV250) || \ 2302 (rdev->family == CHIP_RV280) || \ 2303 (rdev->family == CHIP_RS300)) 2304 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2305 (rdev->family == CHIP_RV350) || \ 2306 (rdev->family == CHIP_R350) || \ 2307 (rdev->family == CHIP_RV380) || \ 2308 (rdev->family == CHIP_R420) || \ 2309 (rdev->family == CHIP_R423) || \ 2310 (rdev->family == CHIP_RV410) || \ 2311 (rdev->family == CHIP_RS400) || \ 2312 (rdev->family == CHIP_RS480)) 2313 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2314 (rdev->ddev->pdev->device == 0x9443) || \ 2315 (rdev->ddev->pdev->device == 0x944B) || \ 2316 (rdev->ddev->pdev->device == 0x9506) || \ 2317 (rdev->ddev->pdev->device == 0x9509) || \ 2318 (rdev->ddev->pdev->device == 0x950F) || \ 2319 (rdev->ddev->pdev->device == 0x689C) || \ 2320 (rdev->ddev->pdev->device == 0x689D)) 2321 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2322 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2323 (rdev->family == CHIP_RS690) || \ 2324 (rdev->family == CHIP_RS740) || \ 2325 (rdev->family >= CHIP_R600)) 2326 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2327 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2328 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2329 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2330 (rdev->flags & RADEON_IS_IGP)) 2331 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2332 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2333 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2334 (rdev->flags & RADEON_IS_IGP)) 2335 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2336 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2337 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2338 2339 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2340 (rdev->ddev->pdev->device == 0x6850) || \ 2341 (rdev->ddev->pdev->device == 0x6858) || \ 2342 (rdev->ddev->pdev->device == 0x6859) || \ 2343 (rdev->ddev->pdev->device == 0x6840) || \ 2344 (rdev->ddev->pdev->device == 0x6841) || \ 2345 (rdev->ddev->pdev->device == 0x6842) || \ 2346 (rdev->ddev->pdev->device == 0x6843)) 2347 2348 /* 2349 * BIOS helpers. 2350 */ 2351 #define RBIOS8(i) (rdev->bios[i]) 2352 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2353 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2354 2355 int radeon_combios_init(struct radeon_device *rdev); 2356 void radeon_combios_fini(struct radeon_device *rdev); 2357 int radeon_atombios_init(struct radeon_device *rdev); 2358 void radeon_atombios_fini(struct radeon_device *rdev); 2359 2360 2361 /* 2362 * RING helpers. 2363 */ 2364 #if DRM_DEBUG_CODE == 0 2365 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2366 { 2367 ring->ring[ring->wptr++] = v; 2368 ring->wptr &= ring->ptr_mask; 2369 ring->count_dw--; 2370 ring->ring_free_dw--; 2371 } 2372 #else 2373 /* With debugging this is just too big to inline */ 2374 void radeon_ring_write(struct radeon_ring *ring, uint32_t v); 2375 #endif 2376 2377 /* 2378 * ASICs macro. 2379 */ 2380 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2381 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2382 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2383 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2384 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p)) 2385 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2386 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 2387 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2388 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) 2389 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2390 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2391 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2392 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) 2393 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) 2394 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) 2395 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) 2396 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) 2397 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) 2398 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm)) 2399 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_rptr((rdev), (r)) 2400 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_wptr((rdev), (r)) 2401 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].set_wptr((rdev), (r)) 2402 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2403 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2404 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2405 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2406 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2407 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2408 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2409 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) 2410 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2411 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 2412 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) 2413 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) 2414 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2415 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2416 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2417 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2418 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2419 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2420 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2421 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2422 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2423 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2424 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2425 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2426 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2427 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2428 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2429 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2430 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2431 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2432 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2433 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2434 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2435 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2436 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2437 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2438 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2439 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc)) 2440 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 2441 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) 2442 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2443 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2444 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2445 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2446 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2447 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2448 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2449 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2450 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2451 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2452 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2453 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2454 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2455 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2456 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2457 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2458 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2459 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2460 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2461 2462 /* Common functions */ 2463 /* AGP */ 2464 extern int radeon_gpu_reset(struct radeon_device *rdev); 2465 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2466 extern void radeon_agp_disable(struct radeon_device *rdev); 2467 extern int radeon_modeset_init(struct radeon_device *rdev); 2468 extern void radeon_modeset_fini(struct radeon_device *rdev); 2469 extern bool radeon_card_posted(struct radeon_device *rdev); 2470 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2471 extern void radeon_update_display_priority(struct radeon_device *rdev); 2472 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2473 extern void radeon_scratch_init(struct radeon_device *rdev); 2474 extern void radeon_wb_fini(struct radeon_device *rdev); 2475 extern int radeon_wb_init(struct radeon_device *rdev); 2476 extern void radeon_wb_disable(struct radeon_device *rdev); 2477 extern void radeon_surface_init(struct radeon_device *rdev); 2478 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2479 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 2480 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 2481 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2482 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2483 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2484 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2485 extern int radeon_resume_kms(struct drm_device *dev); 2486 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); 2487 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2488 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2489 const u32 *registers, 2490 const u32 array_size); 2491 2492 /* 2493 * vm 2494 */ 2495 int radeon_vm_manager_init(struct radeon_device *rdev); 2496 void radeon_vm_manager_fini(struct radeon_device *rdev); 2497 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2498 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2499 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm); 2500 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm); 2501 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2502 struct radeon_vm *vm, int ring); 2503 void radeon_vm_fence(struct radeon_device *rdev, 2504 struct radeon_vm *vm, 2505 struct radeon_fence *fence); 2506 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2507 int radeon_vm_bo_update_pte(struct radeon_device *rdev, 2508 struct radeon_vm *vm, 2509 struct radeon_bo *bo, 2510 struct ttm_mem_reg *mem); 2511 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2512 struct radeon_bo *bo); 2513 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2514 struct radeon_bo *bo); 2515 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2516 struct radeon_vm *vm, 2517 struct radeon_bo *bo); 2518 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2519 struct radeon_bo_va *bo_va, 2520 uint64_t offset, 2521 uint32_t flags); 2522 int radeon_vm_bo_rmv(struct radeon_device *rdev, 2523 struct radeon_bo_va *bo_va); 2524 2525 /* audio */ 2526 void r600_audio_update_hdmi(struct work_struct *work); 2527 2528 /* 2529 * R600 vram scratch functions 2530 */ 2531 int r600_vram_scratch_init(struct radeon_device *rdev); 2532 void r600_vram_scratch_fini(struct radeon_device *rdev); 2533 2534 /* 2535 * r600 cs checking helper 2536 */ 2537 unsigned r600_mip_minify(unsigned size, unsigned level); 2538 bool r600_fmt_is_valid_color(u32 format); 2539 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2540 int r600_fmt_get_blocksize(u32 format); 2541 int r600_fmt_get_nblocksx(u32 format, u32 w); 2542 int r600_fmt_get_nblocksy(u32 format, u32 h); 2543 2544 /* 2545 * r600 functions used by radeon_encoder.c 2546 */ 2547 struct radeon_hdmi_acr { 2548 u32 clock; 2549 2550 int n_32khz; 2551 int cts_32khz; 2552 2553 int n_44_1khz; 2554 int cts_44_1khz; 2555 2556 int n_48khz; 2557 int cts_48khz; 2558 2559 }; 2560 2561 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 2562 2563 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2564 u32 tiling_pipe_num, 2565 u32 max_rb_num, 2566 u32 total_max_rb_num, 2567 u32 enabled_rb_mask); 2568 2569 /* 2570 * evergreen functions used by radeon_encoder.c 2571 */ 2572 2573 extern int ni_init_microcode(struct radeon_device *rdev); 2574 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2575 2576 /* radeon_acpi.c */ 2577 #if defined(CONFIG_ACPI) 2578 extern int radeon_acpi_init(struct radeon_device *rdev); 2579 extern void radeon_acpi_fini(struct radeon_device *rdev); 2580 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 2581 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 2582 u8 perf_req, bool advertise); 2583 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 2584 #else 2585 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 2586 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 2587 #endif 2588 2589 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 2590 struct radeon_cs_packet *pkt, 2591 unsigned idx); 2592 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 2593 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 2594 struct radeon_cs_packet *pkt); 2595 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 2596 struct radeon_cs_reloc **cs_reloc, 2597 int nomm); 2598 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 2599 uint32_t *vline_start_end, 2600 uint32_t *vline_status); 2601 2602 #include "radeon_object.h" 2603 2604 #endif 2605