1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 #include "radeon_object.h" 32 33 /* TODO: Here are things that needs to be done : 34 * - surface allocator & initializer : (bit like scratch reg) should 35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 36 * related to surface 37 * - WB : write back stuff (do it bit like scratch reg things) 38 * - Vblank : look at Jesse's rework and what we should do 39 * - r600/r700: gart & cp 40 * - cs : clean cs ioctl use bitmap & things like that. 41 * - power management stuff 42 * - Barrier in gart code 43 * - Unmappabled vram ? 44 * - TESTING, TESTING, TESTING 45 */ 46 47 /* Initialization path: 48 * We expect that acceleration initialization might fail for various 49 * reasons even thought we work hard to make it works on most 50 * configurations. In order to still have a working userspace in such 51 * situation the init path must succeed up to the memory controller 52 * initialization point. Failure before this point are considered as 53 * fatal error. Here is the init callchain : 54 * radeon_device_init perform common structure, mutex initialization 55 * asic_init setup the GPU memory layout and perform all 56 * one time initialization (failure in this 57 * function are considered fatal) 58 * asic_startup setup the GPU acceleration, in order to 59 * follow guideline the first thing this 60 * function should do is setting the GPU 61 * memory controller (only MC setup failure 62 * are considered as fatal) 63 */ 64 65 #include <asm/atomic.h> 66 #include <linux/wait.h> 67 #include <linux/list.h> 68 #include <linux/kref.h> 69 70 #include "radeon_family.h" 71 #include "radeon_mode.h" 72 #include "radeon_reg.h" 73 74 /* 75 * Modules parameters. 76 */ 77 extern int radeon_no_wb; 78 extern int radeon_modeset; 79 extern int radeon_dynclks; 80 extern int radeon_r4xx_atom; 81 extern int radeon_agpmode; 82 extern int radeon_vram_limit; 83 extern int radeon_gart_size; 84 extern int radeon_benchmarking; 85 extern int radeon_testing; 86 extern int radeon_connector_table; 87 extern int radeon_tv; 88 89 /* 90 * Copy from radeon_drv.h so we don't have to include both and have conflicting 91 * symbol; 92 */ 93 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 94 #define RADEON_IB_POOL_SIZE 16 95 #define RADEON_DEBUGFS_MAX_NUM_FILES 32 96 #define RADEONFB_CONN_LIMIT 4 97 #define RADEON_BIOS_NUM_SCRATCH 8 98 99 /* 100 * Errata workarounds. 101 */ 102 enum radeon_pll_errata { 103 CHIP_ERRATA_R300_CG = 0x00000001, 104 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 105 CHIP_ERRATA_PLL_DELAY = 0x00000004 106 }; 107 108 109 struct radeon_device; 110 111 112 /* 113 * BIOS. 114 */ 115 bool radeon_get_bios(struct radeon_device *rdev); 116 117 118 /* 119 * Dummy page 120 */ 121 struct radeon_dummy_page { 122 struct page *page; 123 dma_addr_t addr; 124 }; 125 int radeon_dummy_page_init(struct radeon_device *rdev); 126 void radeon_dummy_page_fini(struct radeon_device *rdev); 127 128 129 /* 130 * Clocks 131 */ 132 struct radeon_clock { 133 struct radeon_pll p1pll; 134 struct radeon_pll p2pll; 135 struct radeon_pll spll; 136 struct radeon_pll mpll; 137 /* 10 Khz units */ 138 uint32_t default_mclk; 139 uint32_t default_sclk; 140 }; 141 142 143 /* 144 * Fences. 145 */ 146 struct radeon_fence_driver { 147 uint32_t scratch_reg; 148 atomic_t seq; 149 uint32_t last_seq; 150 unsigned long count_timeout; 151 wait_queue_head_t queue; 152 rwlock_t lock; 153 struct list_head created; 154 struct list_head emited; 155 struct list_head signaled; 156 }; 157 158 struct radeon_fence { 159 struct radeon_device *rdev; 160 struct kref kref; 161 struct list_head list; 162 /* protected by radeon_fence.lock */ 163 uint32_t seq; 164 unsigned long timeout; 165 bool emited; 166 bool signaled; 167 }; 168 169 int radeon_fence_driver_init(struct radeon_device *rdev); 170 void radeon_fence_driver_fini(struct radeon_device *rdev); 171 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); 172 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); 173 void radeon_fence_process(struct radeon_device *rdev); 174 bool radeon_fence_signaled(struct radeon_fence *fence); 175 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 176 int radeon_fence_wait_next(struct radeon_device *rdev); 177 int radeon_fence_wait_last(struct radeon_device *rdev); 178 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 179 void radeon_fence_unref(struct radeon_fence **fence); 180 181 /* 182 * Tiling registers 183 */ 184 struct radeon_surface_reg { 185 struct radeon_object *robj; 186 }; 187 188 #define RADEON_GEM_MAX_SURFACES 8 189 190 /* 191 * Radeon buffer. 192 */ 193 struct radeon_object; 194 195 struct radeon_object_list { 196 struct list_head list; 197 struct radeon_object *robj; 198 uint64_t gpu_offset; 199 unsigned rdomain; 200 unsigned wdomain; 201 uint32_t tiling_flags; 202 }; 203 204 int radeon_object_init(struct radeon_device *rdev); 205 void radeon_object_fini(struct radeon_device *rdev); 206 int radeon_object_create(struct radeon_device *rdev, 207 struct drm_gem_object *gobj, 208 unsigned long size, 209 bool kernel, 210 uint32_t domain, 211 bool interruptible, 212 struct radeon_object **robj_ptr); 213 int radeon_object_kmap(struct radeon_object *robj, void **ptr); 214 void radeon_object_kunmap(struct radeon_object *robj); 215 void radeon_object_unref(struct radeon_object **robj); 216 int radeon_object_pin(struct radeon_object *robj, uint32_t domain, 217 uint64_t *gpu_addr); 218 void radeon_object_unpin(struct radeon_object *robj); 219 int radeon_object_wait(struct radeon_object *robj); 220 int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement); 221 int radeon_object_evict_vram(struct radeon_device *rdev); 222 int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset); 223 void radeon_object_force_delete(struct radeon_device *rdev); 224 void radeon_object_list_add_object(struct radeon_object_list *lobj, 225 struct list_head *head); 226 int radeon_object_list_validate(struct list_head *head, void *fence); 227 void radeon_object_list_unvalidate(struct list_head *head); 228 void radeon_object_list_clean(struct list_head *head); 229 int radeon_object_fbdev_mmap(struct radeon_object *robj, 230 struct vm_area_struct *vma); 231 unsigned long radeon_object_size(struct radeon_object *robj); 232 void radeon_object_clear_surface_reg(struct radeon_object *robj); 233 int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved, 234 bool force_drop); 235 void radeon_object_set_tiling_flags(struct radeon_object *robj, 236 uint32_t tiling_flags, uint32_t pitch); 237 void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch); 238 void radeon_bo_move_notify(struct ttm_buffer_object *bo, 239 struct ttm_mem_reg *mem); 240 void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo); 241 /* 242 * GEM objects. 243 */ 244 struct radeon_gem { 245 struct list_head objects; 246 }; 247 248 int radeon_gem_init(struct radeon_device *rdev); 249 void radeon_gem_fini(struct radeon_device *rdev); 250 int radeon_gem_object_create(struct radeon_device *rdev, int size, 251 int alignment, int initial_domain, 252 bool discardable, bool kernel, 253 bool interruptible, 254 struct drm_gem_object **obj); 255 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, 256 uint64_t *gpu_addr); 257 void radeon_gem_object_unpin(struct drm_gem_object *obj); 258 259 260 /* 261 * GART structures, functions & helpers 262 */ 263 struct radeon_mc; 264 265 struct radeon_gart_table_ram { 266 volatile uint32_t *ptr; 267 }; 268 269 struct radeon_gart_table_vram { 270 struct radeon_object *robj; 271 volatile uint32_t *ptr; 272 }; 273 274 union radeon_gart_table { 275 struct radeon_gart_table_ram ram; 276 struct radeon_gart_table_vram vram; 277 }; 278 279 struct radeon_gart { 280 dma_addr_t table_addr; 281 unsigned num_gpu_pages; 282 unsigned num_cpu_pages; 283 unsigned table_size; 284 union radeon_gart_table table; 285 struct page **pages; 286 dma_addr_t *pages_addr; 287 bool ready; 288 }; 289 290 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 291 void radeon_gart_table_ram_free(struct radeon_device *rdev); 292 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 293 void radeon_gart_table_vram_free(struct radeon_device *rdev); 294 int radeon_gart_init(struct radeon_device *rdev); 295 void radeon_gart_fini(struct radeon_device *rdev); 296 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 297 int pages); 298 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 299 int pages, struct page **pagelist); 300 301 302 /* 303 * GPU MC structures, functions & helpers 304 */ 305 struct radeon_mc { 306 resource_size_t aper_size; 307 resource_size_t aper_base; 308 resource_size_t agp_base; 309 /* for some chips with <= 32MB we need to lie 310 * about vram size near mc fb location */ 311 u64 mc_vram_size; 312 u64 gtt_location; 313 u64 gtt_size; 314 u64 gtt_start; 315 u64 gtt_end; 316 u64 vram_location; 317 u64 vram_start; 318 u64 vram_end; 319 unsigned vram_width; 320 u64 real_vram_size; 321 int vram_mtrr; 322 bool vram_is_ddr; 323 }; 324 325 int radeon_mc_setup(struct radeon_device *rdev); 326 327 328 /* 329 * GPU scratch registers structures, functions & helpers 330 */ 331 struct radeon_scratch { 332 unsigned num_reg; 333 bool free[32]; 334 uint32_t reg[32]; 335 }; 336 337 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 338 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 339 340 341 /* 342 * IRQS. 343 */ 344 struct radeon_irq { 345 bool installed; 346 bool sw_int; 347 /* FIXME: use a define max crtc rather than hardcode it */ 348 bool crtc_vblank_int[2]; 349 }; 350 351 int radeon_irq_kms_init(struct radeon_device *rdev); 352 void radeon_irq_kms_fini(struct radeon_device *rdev); 353 354 355 /* 356 * CP & ring. 357 */ 358 struct radeon_ib { 359 struct list_head list; 360 unsigned long idx; 361 uint64_t gpu_addr; 362 struct radeon_fence *fence; 363 uint32_t *ptr; 364 uint32_t length_dw; 365 }; 366 367 /* 368 * locking - 369 * mutex protects scheduled_ibs, ready, alloc_bm 370 */ 371 struct radeon_ib_pool { 372 struct mutex mutex; 373 struct radeon_object *robj; 374 struct list_head scheduled_ibs; 375 struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; 376 bool ready; 377 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE); 378 }; 379 380 struct radeon_cp { 381 struct radeon_object *ring_obj; 382 volatile uint32_t *ring; 383 unsigned rptr; 384 unsigned wptr; 385 unsigned wptr_old; 386 unsigned ring_size; 387 unsigned ring_free_dw; 388 int count_dw; 389 uint64_t gpu_addr; 390 uint32_t align_mask; 391 uint32_t ptr_mask; 392 struct mutex mutex; 393 bool ready; 394 }; 395 396 struct r600_blit { 397 struct radeon_object *shader_obj; 398 u64 shader_gpu_addr; 399 u32 vs_offset, ps_offset; 400 u32 state_offset; 401 u32 state_len; 402 u32 vb_used, vb_total; 403 struct radeon_ib *vb_ib; 404 }; 405 406 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); 407 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); 408 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); 409 int radeon_ib_pool_init(struct radeon_device *rdev); 410 void radeon_ib_pool_fini(struct radeon_device *rdev); 411 int radeon_ib_test(struct radeon_device *rdev); 412 /* Ring access between begin & end cannot sleep */ 413 void radeon_ring_free_size(struct radeon_device *rdev); 414 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); 415 void radeon_ring_unlock_commit(struct radeon_device *rdev); 416 void radeon_ring_unlock_undo(struct radeon_device *rdev); 417 int radeon_ring_test(struct radeon_device *rdev); 418 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); 419 void radeon_ring_fini(struct radeon_device *rdev); 420 421 422 /* 423 * CS. 424 */ 425 struct radeon_cs_reloc { 426 struct drm_gem_object *gobj; 427 struct radeon_object *robj; 428 struct radeon_object_list lobj; 429 uint32_t handle; 430 uint32_t flags; 431 }; 432 433 struct radeon_cs_chunk { 434 uint32_t chunk_id; 435 uint32_t length_dw; 436 int kpage_idx[2]; 437 uint32_t *kpage[2]; 438 uint32_t *kdata; 439 void __user *user_ptr; 440 int last_copied_page; 441 int last_page_index; 442 }; 443 444 struct radeon_cs_parser { 445 struct radeon_device *rdev; 446 struct drm_file *filp; 447 /* chunks */ 448 unsigned nchunks; 449 struct radeon_cs_chunk *chunks; 450 uint64_t *chunks_array; 451 /* IB */ 452 unsigned idx; 453 /* relocations */ 454 unsigned nrelocs; 455 struct radeon_cs_reloc *relocs; 456 struct radeon_cs_reloc **relocs_ptr; 457 struct list_head validated; 458 /* indices of various chunks */ 459 int chunk_ib_idx; 460 int chunk_relocs_idx; 461 struct radeon_ib *ib; 462 void *track; 463 unsigned family; 464 int parser_error; 465 }; 466 467 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); 468 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); 469 470 471 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 472 { 473 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 474 u32 pg_idx, pg_offset; 475 u32 idx_value = 0; 476 int new_page; 477 478 pg_idx = (idx * 4) / PAGE_SIZE; 479 pg_offset = (idx * 4) % PAGE_SIZE; 480 481 if (ibc->kpage_idx[0] == pg_idx) 482 return ibc->kpage[0][pg_offset/4]; 483 if (ibc->kpage_idx[1] == pg_idx) 484 return ibc->kpage[1][pg_offset/4]; 485 486 new_page = radeon_cs_update_pages(p, pg_idx); 487 if (new_page < 0) { 488 p->parser_error = new_page; 489 return 0; 490 } 491 492 idx_value = ibc->kpage[new_page][pg_offset/4]; 493 return idx_value; 494 } 495 496 struct radeon_cs_packet { 497 unsigned idx; 498 unsigned type; 499 unsigned reg; 500 unsigned opcode; 501 int count; 502 unsigned one_reg_wr; 503 }; 504 505 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 506 struct radeon_cs_packet *pkt, 507 unsigned idx, unsigned reg); 508 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 509 struct radeon_cs_packet *pkt); 510 511 512 /* 513 * AGP 514 */ 515 int radeon_agp_init(struct radeon_device *rdev); 516 void radeon_agp_fini(struct radeon_device *rdev); 517 518 519 /* 520 * Writeback 521 */ 522 struct radeon_wb { 523 struct radeon_object *wb_obj; 524 volatile uint32_t *wb; 525 uint64_t gpu_addr; 526 }; 527 528 /** 529 * struct radeon_pm - power management datas 530 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 531 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 532 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 533 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 534 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 535 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 536 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 537 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 538 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 539 * @sclk: GPU clock Mhz (core bandwith depends of this clock) 540 * @needed_bandwidth: current bandwidth needs 541 * 542 * It keeps track of various data needed to take powermanagement decision. 543 * Bandwith need is used to determine minimun clock of the GPU and memory. 544 * Equation between gpu/memory clock and available bandwidth is hw dependent 545 * (type of memory, bus size, efficiency, ...) 546 */ 547 struct radeon_pm { 548 fixed20_12 max_bandwidth; 549 fixed20_12 igp_sideport_mclk; 550 fixed20_12 igp_system_mclk; 551 fixed20_12 igp_ht_link_clk; 552 fixed20_12 igp_ht_link_width; 553 fixed20_12 k8_bandwidth; 554 fixed20_12 sideport_bandwidth; 555 fixed20_12 ht_bandwidth; 556 fixed20_12 core_bandwidth; 557 fixed20_12 sclk; 558 fixed20_12 needed_bandwidth; 559 }; 560 561 562 /* 563 * Benchmarking 564 */ 565 void radeon_benchmark(struct radeon_device *rdev); 566 567 568 /* 569 * Testing 570 */ 571 void radeon_test_moves(struct radeon_device *rdev); 572 573 574 /* 575 * Debugfs 576 */ 577 int radeon_debugfs_add_files(struct radeon_device *rdev, 578 struct drm_info_list *files, 579 unsigned nfiles); 580 int radeon_debugfs_fence_init(struct radeon_device *rdev); 581 int r100_debugfs_rbbm_init(struct radeon_device *rdev); 582 int r100_debugfs_cp_init(struct radeon_device *rdev); 583 584 585 /* 586 * ASIC specific functions. 587 */ 588 struct radeon_asic { 589 int (*init)(struct radeon_device *rdev); 590 void (*fini)(struct radeon_device *rdev); 591 int (*resume)(struct radeon_device *rdev); 592 int (*suspend)(struct radeon_device *rdev); 593 void (*errata)(struct radeon_device *rdev); 594 void (*vram_info)(struct radeon_device *rdev); 595 void (*vga_set_state)(struct radeon_device *rdev, bool state); 596 int (*gpu_reset)(struct radeon_device *rdev); 597 int (*mc_init)(struct radeon_device *rdev); 598 void (*mc_fini)(struct radeon_device *rdev); 599 int (*wb_init)(struct radeon_device *rdev); 600 void (*wb_fini)(struct radeon_device *rdev); 601 int (*gart_init)(struct radeon_device *rdev); 602 void (*gart_fini)(struct radeon_device *rdev); 603 int (*gart_enable)(struct radeon_device *rdev); 604 void (*gart_disable)(struct radeon_device *rdev); 605 void (*gart_tlb_flush)(struct radeon_device *rdev); 606 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); 607 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); 608 void (*cp_fini)(struct radeon_device *rdev); 609 void (*cp_disable)(struct radeon_device *rdev); 610 void (*cp_commit)(struct radeon_device *rdev); 611 void (*ring_start)(struct radeon_device *rdev); 612 int (*ring_test)(struct radeon_device *rdev); 613 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 614 int (*ib_test)(struct radeon_device *rdev); 615 int (*irq_set)(struct radeon_device *rdev); 616 int (*irq_process)(struct radeon_device *rdev); 617 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 618 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); 619 int (*cs_parse)(struct radeon_cs_parser *p); 620 int (*copy_blit)(struct radeon_device *rdev, 621 uint64_t src_offset, 622 uint64_t dst_offset, 623 unsigned num_pages, 624 struct radeon_fence *fence); 625 int (*copy_dma)(struct radeon_device *rdev, 626 uint64_t src_offset, 627 uint64_t dst_offset, 628 unsigned num_pages, 629 struct radeon_fence *fence); 630 int (*copy)(struct radeon_device *rdev, 631 uint64_t src_offset, 632 uint64_t dst_offset, 633 unsigned num_pages, 634 struct radeon_fence *fence); 635 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 636 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 637 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 638 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 639 int (*set_surface_reg)(struct radeon_device *rdev, int reg, 640 uint32_t tiling_flags, uint32_t pitch, 641 uint32_t offset, uint32_t obj_size); 642 int (*clear_surface_reg)(struct radeon_device *rdev, int reg); 643 void (*bandwidth_update)(struct radeon_device *rdev); 644 }; 645 646 /* 647 * Asic structures 648 */ 649 struct r100_asic { 650 const unsigned *reg_safe_bm; 651 unsigned reg_safe_bm_size; 652 }; 653 654 struct r300_asic { 655 const unsigned *reg_safe_bm; 656 unsigned reg_safe_bm_size; 657 }; 658 659 struct r600_asic { 660 unsigned max_pipes; 661 unsigned max_tile_pipes; 662 unsigned max_simds; 663 unsigned max_backends; 664 unsigned max_gprs; 665 unsigned max_threads; 666 unsigned max_stack_entries; 667 unsigned max_hw_contexts; 668 unsigned max_gs_threads; 669 unsigned sx_max_export_size; 670 unsigned sx_max_export_pos_size; 671 unsigned sx_max_export_smx_size; 672 unsigned sq_num_cf_insts; 673 }; 674 675 struct rv770_asic { 676 unsigned max_pipes; 677 unsigned max_tile_pipes; 678 unsigned max_simds; 679 unsigned max_backends; 680 unsigned max_gprs; 681 unsigned max_threads; 682 unsigned max_stack_entries; 683 unsigned max_hw_contexts; 684 unsigned max_gs_threads; 685 unsigned sx_max_export_size; 686 unsigned sx_max_export_pos_size; 687 unsigned sx_max_export_smx_size; 688 unsigned sq_num_cf_insts; 689 unsigned sx_num_of_sets; 690 unsigned sc_prim_fifo_size; 691 unsigned sc_hiz_tile_fifo_size; 692 unsigned sc_earlyz_tile_fifo_fize; 693 }; 694 695 union radeon_asic_config { 696 struct r300_asic r300; 697 struct r100_asic r100; 698 struct r600_asic r600; 699 struct rv770_asic rv770; 700 }; 701 702 703 /* 704 * IOCTL. 705 */ 706 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 707 struct drm_file *filp); 708 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 709 struct drm_file *filp); 710 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 711 struct drm_file *file_priv); 712 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 713 struct drm_file *file_priv); 714 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 715 struct drm_file *file_priv); 716 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 717 struct drm_file *file_priv); 718 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 719 struct drm_file *filp); 720 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 721 struct drm_file *filp); 722 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 723 struct drm_file *filp); 724 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 725 struct drm_file *filp); 726 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 727 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 728 struct drm_file *filp); 729 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 730 struct drm_file *filp); 731 732 733 /* 734 * Core structure, functions and helpers. 735 */ 736 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 737 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 738 739 struct radeon_device { 740 struct device *dev; 741 struct drm_device *ddev; 742 struct pci_dev *pdev; 743 /* ASIC */ 744 union radeon_asic_config config; 745 enum radeon_family family; 746 unsigned long flags; 747 int usec_timeout; 748 enum radeon_pll_errata pll_errata; 749 int num_gb_pipes; 750 int num_z_pipes; 751 int disp_priority; 752 /* BIOS */ 753 uint8_t *bios; 754 bool is_atom_bios; 755 uint16_t bios_header_start; 756 struct radeon_object *stollen_vga_memory; 757 struct fb_info *fbdev_info; 758 struct radeon_object *fbdev_robj; 759 struct radeon_framebuffer *fbdev_rfb; 760 /* Register mmio */ 761 resource_size_t rmmio_base; 762 resource_size_t rmmio_size; 763 void *rmmio; 764 radeon_rreg_t mc_rreg; 765 radeon_wreg_t mc_wreg; 766 radeon_rreg_t pll_rreg; 767 radeon_wreg_t pll_wreg; 768 uint32_t pcie_reg_mask; 769 radeon_rreg_t pciep_rreg; 770 radeon_wreg_t pciep_wreg; 771 struct radeon_clock clock; 772 struct radeon_mc mc; 773 struct radeon_gart gart; 774 struct radeon_mode_info mode_info; 775 struct radeon_scratch scratch; 776 struct radeon_mman mman; 777 struct radeon_fence_driver fence_drv; 778 struct radeon_cp cp; 779 struct radeon_ib_pool ib_pool; 780 struct radeon_irq irq; 781 struct radeon_asic *asic; 782 struct radeon_gem gem; 783 struct radeon_pm pm; 784 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 785 struct mutex cs_mutex; 786 struct radeon_wb wb; 787 struct radeon_dummy_page dummy_page; 788 bool gpu_lockup; 789 bool shutdown; 790 bool suspend; 791 bool need_dma32; 792 bool new_init_path; 793 bool accel_working; 794 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 795 const struct firmware *me_fw; /* all family ME firmware */ 796 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 797 struct r600_blit r600_blit; 798 }; 799 800 int radeon_device_init(struct radeon_device *rdev, 801 struct drm_device *ddev, 802 struct pci_dev *pdev, 803 uint32_t flags); 804 void radeon_device_fini(struct radeon_device *rdev); 805 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 806 807 /* r600 blit */ 808 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); 809 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); 810 void r600_kms_blit_copy(struct radeon_device *rdev, 811 u64 src_gpu_addr, u64 dst_gpu_addr, 812 int size_bytes); 813 814 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) 815 { 816 if (reg < 0x10000) 817 return readl(((void __iomem *)rdev->rmmio) + reg); 818 else { 819 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 820 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 821 } 822 } 823 824 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 825 { 826 if (reg < 0x10000) 827 writel(v, ((void __iomem *)rdev->rmmio) + reg); 828 else { 829 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 830 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 831 } 832 } 833 834 835 /* 836 * Registers read & write functions. 837 */ 838 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) 839 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) 840 #define RREG32(reg) r100_mm_rreg(rdev, (reg)) 841 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) 842 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) 843 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 844 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 845 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 846 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 847 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 848 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 849 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 850 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 851 #define WREG32_P(reg, val, mask) \ 852 do { \ 853 uint32_t tmp_ = RREG32(reg); \ 854 tmp_ &= (mask); \ 855 tmp_ |= ((val) & ~(mask)); \ 856 WREG32(reg, tmp_); \ 857 } while (0) 858 #define WREG32_PLL_P(reg, val, mask) \ 859 do { \ 860 uint32_t tmp_ = RREG32_PLL(reg); \ 861 tmp_ &= (mask); \ 862 tmp_ |= ((val) & ~(mask)); \ 863 WREG32_PLL(reg, tmp_); \ 864 } while (0) 865 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) 866 867 /* 868 * Indirect registers accessor 869 */ 870 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 871 { 872 uint32_t r; 873 874 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 875 r = RREG32(RADEON_PCIE_DATA); 876 return r; 877 } 878 879 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 880 { 881 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 882 WREG32(RADEON_PCIE_DATA, (v)); 883 } 884 885 void r100_pll_errata_after_index(struct radeon_device *rdev); 886 887 888 /* 889 * ASICs helpers. 890 */ 891 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 892 (rdev->pdev->device == 0x5969)) 893 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 894 (rdev->family == CHIP_RV200) || \ 895 (rdev->family == CHIP_RS100) || \ 896 (rdev->family == CHIP_RS200) || \ 897 (rdev->family == CHIP_RV250) || \ 898 (rdev->family == CHIP_RV280) || \ 899 (rdev->family == CHIP_RS300)) 900 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 901 (rdev->family == CHIP_RV350) || \ 902 (rdev->family == CHIP_R350) || \ 903 (rdev->family == CHIP_RV380) || \ 904 (rdev->family == CHIP_R420) || \ 905 (rdev->family == CHIP_R423) || \ 906 (rdev->family == CHIP_RV410) || \ 907 (rdev->family == CHIP_RS400) || \ 908 (rdev->family == CHIP_RS480)) 909 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 910 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 911 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 912 913 914 /* 915 * BIOS helpers. 916 */ 917 #define RBIOS8(i) (rdev->bios[i]) 918 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 919 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 920 921 int radeon_combios_init(struct radeon_device *rdev); 922 void radeon_combios_fini(struct radeon_device *rdev); 923 int radeon_atombios_init(struct radeon_device *rdev); 924 void radeon_atombios_fini(struct radeon_device *rdev); 925 926 927 /* 928 * RING helpers. 929 */ 930 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) 931 { 932 #if DRM_DEBUG_CODE 933 if (rdev->cp.count_dw <= 0) { 934 DRM_ERROR("radeon: writting more dword to ring than expected !\n"); 935 } 936 #endif 937 rdev->cp.ring[rdev->cp.wptr++] = v; 938 rdev->cp.wptr &= rdev->cp.ptr_mask; 939 rdev->cp.count_dw--; 940 rdev->cp.ring_free_dw--; 941 } 942 943 944 /* 945 * ASICs macro. 946 */ 947 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 948 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 949 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 950 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 951 #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) 952 #define radeon_errata(rdev) (rdev)->asic->errata((rdev)) 953 #define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev)) 954 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 955 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) 956 #define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev)) 957 #define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev)) 958 #define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev)) 959 #define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev)) 960 #define radeon_gpu_gart_init(rdev) (rdev)->asic->gart_init((rdev)) 961 #define radeon_gpu_gart_fini(rdev) (rdev)->asic->gart_fini((rdev)) 962 #define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev)) 963 #define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev)) 964 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) 965 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) 966 #define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize)) 967 #define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev)) 968 #define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev)) 969 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) 970 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) 971 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) 972 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) 973 #define radeon_ib_test(rdev) (rdev)->asic->ib_test((rdev)) 974 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) 975 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) 976 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) 977 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) 978 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) 979 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) 980 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) 981 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) 982 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) 983 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) 984 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) 985 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) 986 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) 987 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) 988 989 /* Common functions */ 990 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); 991 extern int radeon_modeset_init(struct radeon_device *rdev); 992 extern void radeon_modeset_fini(struct radeon_device *rdev); 993 extern bool radeon_card_posted(struct radeon_device *rdev); 994 extern int radeon_clocks_init(struct radeon_device *rdev); 995 extern void radeon_clocks_fini(struct radeon_device *rdev); 996 extern void radeon_scratch_init(struct radeon_device *rdev); 997 extern void radeon_surface_init(struct radeon_device *rdev); 998 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 999 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 1000 1001 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ 1002 struct r100_mc_save { 1003 u32 GENMO_WT; 1004 u32 CRTC_EXT_CNTL; 1005 u32 CRTC_GEN_CNTL; 1006 u32 CRTC2_GEN_CNTL; 1007 u32 CUR_OFFSET; 1008 u32 CUR2_OFFSET; 1009 }; 1010 extern void r100_cp_disable(struct radeon_device *rdev); 1011 extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 1012 extern void r100_cp_fini(struct radeon_device *rdev); 1013 extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 1014 extern int r100_pci_gart_init(struct radeon_device *rdev); 1015 extern void r100_pci_gart_fini(struct radeon_device *rdev); 1016 extern int r100_pci_gart_enable(struct radeon_device *rdev); 1017 extern void r100_pci_gart_disable(struct radeon_device *rdev); 1018 extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 1019 extern int r100_debugfs_mc_info_init(struct radeon_device *rdev); 1020 extern int r100_gui_wait_for_idle(struct radeon_device *rdev); 1021 extern void r100_ib_fini(struct radeon_device *rdev); 1022 extern int r100_ib_init(struct radeon_device *rdev); 1023 extern void r100_irq_disable(struct radeon_device *rdev); 1024 extern int r100_irq_set(struct radeon_device *rdev); 1025 extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); 1026 extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); 1027 extern void r100_vram_init_sizes(struct radeon_device *rdev); 1028 extern void r100_wb_disable(struct radeon_device *rdev); 1029 extern void r100_wb_fini(struct radeon_device *rdev); 1030 extern int r100_wb_init(struct radeon_device *rdev); 1031 extern void r100_hdp_reset(struct radeon_device *rdev); 1032 extern int r100_rb2d_reset(struct radeon_device *rdev); 1033 extern int r100_cp_reset(struct radeon_device *rdev); 1034 1035 /* r300,r350,rv350,rv370,rv380 */ 1036 extern void r300_set_reg_safe(struct radeon_device *rdev); 1037 extern void r300_mc_program(struct radeon_device *rdev); 1038 extern void r300_vram_info(struct radeon_device *rdev); 1039 extern int rv370_pcie_gart_init(struct radeon_device *rdev); 1040 extern void rv370_pcie_gart_fini(struct radeon_device *rdev); 1041 extern int rv370_pcie_gart_enable(struct radeon_device *rdev); 1042 extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 1043 1044 /* r420,r423,rv410 */ 1045 extern int r420_mc_init(struct radeon_device *rdev); 1046 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 1047 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 1048 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 1049 extern void r420_pipes_init(struct radeon_device *rdev); 1050 1051 /* rv515 */ 1052 struct rv515_mc_save { 1053 u32 d1vga_control; 1054 u32 d2vga_control; 1055 u32 vga_render_control; 1056 u32 vga_hdp_control; 1057 u32 d1crtc_control; 1058 u32 d2crtc_control; 1059 }; 1060 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 1061 extern void rv515_vga_render_disable(struct radeon_device *rdev); 1062 extern void rv515_set_safe_registers(struct radeon_device *rdev); 1063 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); 1064 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); 1065 extern void rv515_clock_startup(struct radeon_device *rdev); 1066 extern void rv515_debugfs(struct radeon_device *rdev); 1067 extern int rv515_suspend(struct radeon_device *rdev); 1068 1069 /* rs690, rs740 */ 1070 extern void rs690_line_buffer_adjust(struct radeon_device *rdev, 1071 struct drm_display_mode *mode1, 1072 struct drm_display_mode *mode2); 1073 1074 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ 1075 extern bool r600_card_posted(struct radeon_device *rdev); 1076 extern void r600_cp_stop(struct radeon_device *rdev); 1077 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); 1078 extern int r600_cp_resume(struct radeon_device *rdev); 1079 extern int r600_count_pipe_bits(uint32_t val); 1080 extern int r600_gart_clear_page(struct radeon_device *rdev, int i); 1081 extern int r600_mc_wait_for_idle(struct radeon_device *rdev); 1082 extern int r600_pcie_gart_init(struct radeon_device *rdev); 1083 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 1084 extern int r600_ib_test(struct radeon_device *rdev); 1085 extern int r600_ring_test(struct radeon_device *rdev); 1086 extern int r600_wb_init(struct radeon_device *rdev); 1087 extern void r600_wb_fini(struct radeon_device *rdev); 1088 extern void r600_scratch_init(struct radeon_device *rdev); 1089 extern int r600_blit_init(struct radeon_device *rdev); 1090 extern void r600_blit_fini(struct radeon_device *rdev); 1091 extern int r600_cp_init_microcode(struct radeon_device *rdev); 1092 extern int r600_gpu_reset(struct radeon_device *rdev); 1093 1094 #endif 1095