1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 /* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45 /* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63 #include <linux/agp_backend.h> 64 #include <linux/atomic.h> 65 #include <linux/wait.h> 66 #include <linux/list.h> 67 #include <linux/kref.h> 68 #include <linux/interval_tree.h> 69 #include <linux/hashtable.h> 70 #include <linux/dma-fence.h> 71 72 #ifdef CONFIG_MMU_NOTIFIER 73 #include <linux/mmu_notifier.h> 74 #endif 75 76 #include <drm/ttm/ttm_bo.h> 77 #include <drm/ttm/ttm_placement.h> 78 #include <drm/ttm/ttm_execbuf_util.h> 79 80 #include <drm/drm_gem.h> 81 #include <drm/drm_audio_component.h> 82 83 #include "radeon_family.h" 84 #include "radeon_mode.h" 85 #include "radeon_reg.h" 86 87 /* 88 * Modules parameters. 89 */ 90 extern int radeon_no_wb; 91 extern int radeon_modeset; 92 extern int radeon_dynclks; 93 extern int radeon_r4xx_atom; 94 extern int radeon_agpmode; 95 extern int radeon_vram_limit; 96 extern int radeon_gart_size; 97 extern int radeon_benchmarking; 98 extern int radeon_testing; 99 extern int radeon_connector_table; 100 extern int radeon_tv; 101 extern int radeon_audio; 102 extern int radeon_disp_priority; 103 extern int radeon_hw_i2c; 104 extern int radeon_pcie_gen2; 105 extern int radeon_msi; 106 extern int radeon_lockup_timeout; 107 extern int radeon_fastfb; 108 extern int radeon_dpm; 109 extern int radeon_aspm; 110 extern int radeon_runtime_pm; 111 extern int radeon_hard_reset; 112 extern int radeon_vm_size; 113 extern int radeon_vm_block_size; 114 extern int radeon_deep_color; 115 extern int radeon_use_pflipirq; 116 extern int radeon_bapm; 117 extern int radeon_backlight; 118 extern int radeon_auxch; 119 extern int radeon_uvd; 120 extern int radeon_vce; 121 extern int radeon_si_support; 122 extern int radeon_cik_support; 123 124 /* 125 * Copy from radeon_drv.h so we don't have to include both and have conflicting 126 * symbol; 127 */ 128 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 129 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 130 #define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */ 131 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 132 #define RADEON_IB_POOL_SIZE 16 133 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 134 #define RADEONFB_CONN_LIMIT 4 135 #define RADEON_BIOS_NUM_SCRATCH 8 136 137 /* internal ring indices */ 138 /* r1xx+ has gfx CP ring */ 139 #define RADEON_RING_TYPE_GFX_INDEX 0 140 141 /* cayman has 2 compute CP rings */ 142 #define CAYMAN_RING_TYPE_CP1_INDEX 1 143 #define CAYMAN_RING_TYPE_CP2_INDEX 2 144 145 /* R600+ has an async dma ring */ 146 #define R600_RING_TYPE_DMA_INDEX 3 147 /* cayman add a second async dma ring */ 148 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 149 150 /* R600+ */ 151 #define R600_RING_TYPE_UVD_INDEX 5 152 153 /* TN+ */ 154 #define TN_RING_TYPE_VCE1_INDEX 6 155 #define TN_RING_TYPE_VCE2_INDEX 7 156 157 /* max number of rings */ 158 #define RADEON_NUM_RINGS 8 159 160 /* number of hw syncs before falling back on blocking */ 161 #define RADEON_NUM_SYNCS 4 162 163 /* hardcode those limit for now */ 164 #define RADEON_VA_IB_OFFSET (1 << 20) 165 #define RADEON_VA_RESERVED_SIZE (8 << 20) 166 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 167 168 /* hard reset data */ 169 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 170 171 /* reset flags */ 172 #define RADEON_RESET_GFX (1 << 0) 173 #define RADEON_RESET_COMPUTE (1 << 1) 174 #define RADEON_RESET_DMA (1 << 2) 175 #define RADEON_RESET_CP (1 << 3) 176 #define RADEON_RESET_GRBM (1 << 4) 177 #define RADEON_RESET_DMA1 (1 << 5) 178 #define RADEON_RESET_RLC (1 << 6) 179 #define RADEON_RESET_SEM (1 << 7) 180 #define RADEON_RESET_IH (1 << 8) 181 #define RADEON_RESET_VMC (1 << 9) 182 #define RADEON_RESET_MC (1 << 10) 183 #define RADEON_RESET_DISPLAY (1 << 11) 184 185 /* CG block flags */ 186 #define RADEON_CG_BLOCK_GFX (1 << 0) 187 #define RADEON_CG_BLOCK_MC (1 << 1) 188 #define RADEON_CG_BLOCK_SDMA (1 << 2) 189 #define RADEON_CG_BLOCK_UVD (1 << 3) 190 #define RADEON_CG_BLOCK_VCE (1 << 4) 191 #define RADEON_CG_BLOCK_HDP (1 << 5) 192 #define RADEON_CG_BLOCK_BIF (1 << 6) 193 194 /* CG flags */ 195 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 196 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 197 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 198 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 199 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 200 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 201 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 202 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 203 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 204 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 205 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 206 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 207 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 208 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 209 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 210 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 211 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 212 213 /* PG flags */ 214 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 215 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 216 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 217 #define RADEON_PG_SUPPORT_UVD (1 << 3) 218 #define RADEON_PG_SUPPORT_VCE (1 << 4) 219 #define RADEON_PG_SUPPORT_CP (1 << 5) 220 #define RADEON_PG_SUPPORT_GDS (1 << 6) 221 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 222 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 223 #define RADEON_PG_SUPPORT_ACP (1 << 9) 224 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 225 226 /* max cursor sizes (in pixels) */ 227 #define CURSOR_WIDTH 64 228 #define CURSOR_HEIGHT 64 229 230 #define CIK_CURSOR_WIDTH 128 231 #define CIK_CURSOR_HEIGHT 128 232 233 /* 234 * Errata workarounds. 235 */ 236 enum radeon_pll_errata { 237 CHIP_ERRATA_R300_CG = 0x00000001, 238 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 239 CHIP_ERRATA_PLL_DELAY = 0x00000004 240 }; 241 242 243 struct radeon_device; 244 245 246 /* 247 * BIOS. 248 */ 249 bool radeon_get_bios(struct radeon_device *rdev); 250 251 /* 252 * Dummy page 253 */ 254 struct radeon_dummy_page { 255 uint64_t entry; 256 struct page *page; 257 dma_addr_t addr; 258 }; 259 int radeon_dummy_page_init(struct radeon_device *rdev); 260 void radeon_dummy_page_fini(struct radeon_device *rdev); 261 262 263 /* 264 * Clocks 265 */ 266 struct radeon_clock { 267 struct radeon_pll p1pll; 268 struct radeon_pll p2pll; 269 struct radeon_pll dcpll; 270 struct radeon_pll spll; 271 struct radeon_pll mpll; 272 /* 10 Khz units */ 273 uint32_t default_mclk; 274 uint32_t default_sclk; 275 uint32_t default_dispclk; 276 uint32_t current_dispclk; 277 uint32_t dp_extclk; 278 uint32_t max_pixel_clock; 279 uint32_t vco_freq; 280 }; 281 282 /* 283 * Power management 284 */ 285 int radeon_pm_init(struct radeon_device *rdev); 286 int radeon_pm_late_init(struct radeon_device *rdev); 287 void radeon_pm_fini(struct radeon_device *rdev); 288 void radeon_pm_compute_clocks(struct radeon_device *rdev); 289 void radeon_pm_suspend(struct radeon_device *rdev); 290 void radeon_pm_resume(struct radeon_device *rdev); 291 void radeon_combios_get_power_modes(struct radeon_device *rdev); 292 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 293 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 294 u8 clock_type, 295 u32 clock, 296 bool strobe_mode, 297 struct atom_clock_dividers *dividers); 298 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 299 u32 clock, 300 bool strobe_mode, 301 struct atom_mpll_param *mpll_param); 302 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 303 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 304 u16 voltage_level, u8 voltage_type, 305 u32 *gpio_value, u32 *gpio_mask); 306 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 307 u32 eng_clock, u32 mem_clock); 308 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 309 u8 voltage_type, u16 *voltage_step); 310 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 311 u16 voltage_id, u16 *voltage); 312 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 313 u16 *voltage, 314 u16 leakage_idx); 315 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 316 u16 *leakage_id); 317 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 318 u16 *vddc, u16 *vddci, 319 u16 virtual_voltage_id, 320 u16 vbios_voltage_id); 321 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 322 u16 virtual_voltage_id, 323 u16 *voltage); 324 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 325 u8 voltage_type, 326 u16 nominal_voltage, 327 u16 *true_voltage); 328 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 329 u8 voltage_type, u16 *min_voltage); 330 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 331 u8 voltage_type, u16 *max_voltage); 332 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 333 u8 voltage_type, u8 voltage_mode, 334 struct atom_voltage_table *voltage_table); 335 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 336 u8 voltage_type, u8 voltage_mode); 337 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 338 u8 voltage_type, 339 u8 *svd_gpio_id, u8 *svc_gpio_id); 340 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 341 u32 mem_clock); 342 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 343 u32 mem_clock); 344 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 345 u8 module_index, 346 struct atom_mc_reg_table *reg_table); 347 int radeon_atom_get_memory_info(struct radeon_device *rdev, 348 u8 module_index, struct atom_memory_info *mem_info); 349 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 350 bool gddr5, u8 module_index, 351 struct atom_memory_clock_range_table *mclk_range_table); 352 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 353 u16 voltage_id, u16 *voltage); 354 void rs690_pm_info(struct radeon_device *rdev); 355 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 356 unsigned *bankh, unsigned *mtaspect, 357 unsigned *tile_split); 358 359 /* 360 * Fences. 361 */ 362 struct radeon_fence_driver { 363 struct radeon_device *rdev; 364 uint32_t scratch_reg; 365 uint64_t gpu_addr; 366 volatile uint32_t *cpu_addr; 367 /* sync_seq is protected by ring emission lock */ 368 uint64_t sync_seq[RADEON_NUM_RINGS]; 369 atomic64_t last_seq; 370 bool initialized, delayed_irq; 371 struct delayed_work lockup_work; 372 }; 373 374 struct radeon_fence { 375 struct dma_fence base; 376 377 struct radeon_device *rdev; 378 uint64_t seq; 379 /* RB, DMA, etc. */ 380 unsigned ring; 381 bool is_vm_update; 382 383 wait_queue_entry_t fence_wake; 384 }; 385 386 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 387 void radeon_fence_driver_init(struct radeon_device *rdev); 388 void radeon_fence_driver_fini(struct radeon_device *rdev); 389 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 390 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 391 void radeon_fence_process(struct radeon_device *rdev, int ring); 392 bool radeon_fence_signaled(struct radeon_fence *fence); 393 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout); 394 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 395 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 396 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 397 int radeon_fence_wait_any(struct radeon_device *rdev, 398 struct radeon_fence **fences, 399 bool intr); 400 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 401 void radeon_fence_unref(struct radeon_fence **fence); 402 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 403 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 404 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 405 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 406 struct radeon_fence *b) 407 { 408 if (!a) { 409 return b; 410 } 411 412 if (!b) { 413 return a; 414 } 415 416 BUG_ON(a->ring != b->ring); 417 418 if (a->seq > b->seq) { 419 return a; 420 } else { 421 return b; 422 } 423 } 424 425 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 426 struct radeon_fence *b) 427 { 428 if (!a) { 429 return false; 430 } 431 432 if (!b) { 433 return true; 434 } 435 436 BUG_ON(a->ring != b->ring); 437 438 return a->seq < b->seq; 439 } 440 441 /* 442 * Tiling registers 443 */ 444 struct radeon_surface_reg { 445 struct radeon_bo *bo; 446 }; 447 448 #define RADEON_GEM_MAX_SURFACES 8 449 450 /* 451 * TTM. 452 */ 453 struct radeon_mman { 454 struct ttm_device bdev; 455 bool initialized; 456 }; 457 458 struct radeon_bo_list { 459 struct radeon_bo *robj; 460 struct ttm_validate_buffer tv; 461 uint64_t gpu_offset; 462 unsigned preferred_domains; 463 unsigned allowed_domains; 464 uint32_t tiling_flags; 465 }; 466 467 /* bo virtual address in a specific vm */ 468 struct radeon_bo_va { 469 /* protected by bo being reserved */ 470 struct list_head bo_list; 471 uint32_t flags; 472 struct radeon_fence *last_pt_update; 473 unsigned ref_count; 474 475 /* protected by vm mutex */ 476 struct interval_tree_node it; 477 struct list_head vm_status; 478 479 /* constant after initialization */ 480 struct radeon_vm *vm; 481 struct radeon_bo *bo; 482 }; 483 484 struct radeon_bo { 485 /* Protected by gem.mutex */ 486 struct list_head list; 487 /* Protected by tbo.reserved */ 488 u32 initial_domain; 489 struct ttm_place placements[4]; 490 struct ttm_placement placement; 491 struct ttm_buffer_object tbo; 492 struct ttm_bo_kmap_obj kmap; 493 u32 flags; 494 void *kptr; 495 u32 tiling_flags; 496 u32 pitch; 497 int surface_reg; 498 unsigned prime_shared_count; 499 /* list of all virtual address to which this bo 500 * is associated to 501 */ 502 struct list_head va; 503 /* Constant after initialization */ 504 struct radeon_device *rdev; 505 506 pid_t pid; 507 508 #ifdef CONFIG_MMU_NOTIFIER 509 struct mmu_interval_notifier notifier; 510 #endif 511 }; 512 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, tbo.base) 513 514 /* sub-allocation manager, it has to be protected by another lock. 515 * By conception this is an helper for other part of the driver 516 * like the indirect buffer or semaphore, which both have their 517 * locking. 518 * 519 * Principe is simple, we keep a list of sub allocation in offset 520 * order (first entry has offset == 0, last entry has the highest 521 * offset). 522 * 523 * When allocating new object we first check if there is room at 524 * the end total_size - (last_object_offset + last_object_size) >= 525 * alloc_size. If so we allocate new object there. 526 * 527 * When there is not enough room at the end, we start waiting for 528 * each sub object until we reach object_offset+object_size >= 529 * alloc_size, this object then become the sub object we return. 530 * 531 * Alignment can't be bigger than page size. 532 * 533 * Hole are not considered for allocation to keep things simple. 534 * Assumption is that there won't be hole (all object on same 535 * alignment). 536 */ 537 struct radeon_sa_manager { 538 wait_queue_head_t wq; 539 struct radeon_bo *bo; 540 struct list_head *hole; 541 struct list_head flist[RADEON_NUM_RINGS]; 542 struct list_head olist; 543 unsigned size; 544 uint64_t gpu_addr; 545 void *cpu_ptr; 546 uint32_t domain; 547 uint32_t align; 548 }; 549 550 struct radeon_sa_bo; 551 552 /* sub-allocation buffer */ 553 struct radeon_sa_bo { 554 struct list_head olist; 555 struct list_head flist; 556 struct radeon_sa_manager *manager; 557 unsigned soffset; 558 unsigned eoffset; 559 struct radeon_fence *fence; 560 }; 561 562 /* 563 * GEM objects. 564 */ 565 struct radeon_gem { 566 struct mutex mutex; 567 struct list_head objects; 568 }; 569 570 extern const struct drm_gem_object_funcs radeon_gem_object_funcs; 571 572 int radeon_gem_init(struct radeon_device *rdev); 573 void radeon_gem_fini(struct radeon_device *rdev); 574 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 575 int alignment, int initial_domain, 576 u32 flags, bool kernel, 577 struct drm_gem_object **obj); 578 579 int radeon_mode_dumb_create(struct drm_file *file_priv, 580 struct drm_device *dev, 581 struct drm_mode_create_dumb *args); 582 int radeon_mode_dumb_mmap(struct drm_file *filp, 583 struct drm_device *dev, 584 uint32_t handle, uint64_t *offset_p); 585 586 /* 587 * Semaphores. 588 */ 589 struct radeon_semaphore { 590 struct radeon_sa_bo *sa_bo; 591 signed waiters; 592 uint64_t gpu_addr; 593 }; 594 595 int radeon_semaphore_create(struct radeon_device *rdev, 596 struct radeon_semaphore **semaphore); 597 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 598 struct radeon_semaphore *semaphore); 599 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 600 struct radeon_semaphore *semaphore); 601 void radeon_semaphore_free(struct radeon_device *rdev, 602 struct radeon_semaphore **semaphore, 603 struct radeon_fence *fence); 604 605 /* 606 * Synchronization 607 */ 608 struct radeon_sync { 609 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS]; 610 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 611 struct radeon_fence *last_vm_update; 612 }; 613 614 void radeon_sync_create(struct radeon_sync *sync); 615 void radeon_sync_fence(struct radeon_sync *sync, 616 struct radeon_fence *fence); 617 int radeon_sync_resv(struct radeon_device *rdev, 618 struct radeon_sync *sync, 619 struct dma_resv *resv, 620 bool shared); 621 int radeon_sync_rings(struct radeon_device *rdev, 622 struct radeon_sync *sync, 623 int waiting_ring); 624 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync, 625 struct radeon_fence *fence); 626 627 /* 628 * GART structures, functions & helpers 629 */ 630 struct radeon_mc; 631 632 #define RADEON_GPU_PAGE_SIZE 4096 633 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 634 #define RADEON_GPU_PAGE_SHIFT 12 635 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 636 637 #define RADEON_GART_PAGE_DUMMY 0 638 #define RADEON_GART_PAGE_VALID (1 << 0) 639 #define RADEON_GART_PAGE_READ (1 << 1) 640 #define RADEON_GART_PAGE_WRITE (1 << 2) 641 #define RADEON_GART_PAGE_SNOOP (1 << 3) 642 643 struct radeon_gart { 644 dma_addr_t table_addr; 645 struct radeon_bo *robj; 646 void *ptr; 647 unsigned num_gpu_pages; 648 unsigned num_cpu_pages; 649 unsigned table_size; 650 struct page **pages; 651 uint64_t *pages_entry; 652 bool ready; 653 }; 654 655 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 656 void radeon_gart_table_ram_free(struct radeon_device *rdev); 657 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 658 void radeon_gart_table_vram_free(struct radeon_device *rdev); 659 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 660 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 661 int radeon_gart_init(struct radeon_device *rdev); 662 void radeon_gart_fini(struct radeon_device *rdev); 663 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 664 int pages); 665 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 666 int pages, struct page **pagelist, 667 dma_addr_t *dma_addr, uint32_t flags); 668 669 670 /* 671 * GPU MC structures, functions & helpers 672 */ 673 struct radeon_mc { 674 resource_size_t aper_size; 675 resource_size_t aper_base; 676 resource_size_t agp_base; 677 /* for some chips with <= 32MB we need to lie 678 * about vram size near mc fb location */ 679 u64 mc_vram_size; 680 u64 visible_vram_size; 681 u64 gtt_size; 682 u64 gtt_start; 683 u64 gtt_end; 684 u64 vram_start; 685 u64 vram_end; 686 unsigned vram_width; 687 u64 real_vram_size; 688 int vram_mtrr; 689 bool vram_is_ddr; 690 bool igp_sideport_enabled; 691 u64 gtt_base_align; 692 u64 mc_mask; 693 }; 694 695 bool radeon_combios_sideport_present(struct radeon_device *rdev); 696 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 697 698 /* 699 * GPU scratch registers structures, functions & helpers 700 */ 701 struct radeon_scratch { 702 unsigned num_reg; 703 uint32_t reg_base; 704 bool free[32]; 705 uint32_t reg[32]; 706 }; 707 708 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 709 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 710 711 /* 712 * GPU doorbell structures, functions & helpers 713 */ 714 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 715 716 struct radeon_doorbell { 717 /* doorbell mmio */ 718 resource_size_t base; 719 resource_size_t size; 720 u32 __iomem *ptr; 721 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 722 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS); 723 }; 724 725 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 726 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 727 728 /* 729 * IRQS. 730 */ 731 732 struct radeon_flip_work { 733 struct work_struct flip_work; 734 struct work_struct unpin_work; 735 struct radeon_device *rdev; 736 int crtc_id; 737 u32 target_vblank; 738 uint64_t base; 739 struct drm_pending_vblank_event *event; 740 struct radeon_bo *old_rbo; 741 struct dma_fence *fence; 742 bool async; 743 }; 744 745 struct r500_irq_stat_regs { 746 u32 disp_int; 747 u32 hdmi0_status; 748 }; 749 750 struct r600_irq_stat_regs { 751 u32 disp_int; 752 u32 disp_int_cont; 753 u32 disp_int_cont2; 754 u32 d1grph_int; 755 u32 d2grph_int; 756 u32 hdmi0_status; 757 u32 hdmi1_status; 758 }; 759 760 struct evergreen_irq_stat_regs { 761 u32 disp_int[6]; 762 u32 grph_int[6]; 763 u32 afmt_status[6]; 764 }; 765 766 struct cik_irq_stat_regs { 767 u32 disp_int; 768 u32 disp_int_cont; 769 u32 disp_int_cont2; 770 u32 disp_int_cont3; 771 u32 disp_int_cont4; 772 u32 disp_int_cont5; 773 u32 disp_int_cont6; 774 u32 d1grph_int; 775 u32 d2grph_int; 776 u32 d3grph_int; 777 u32 d4grph_int; 778 u32 d5grph_int; 779 u32 d6grph_int; 780 }; 781 782 union radeon_irq_stat_regs { 783 struct r500_irq_stat_regs r500; 784 struct r600_irq_stat_regs r600; 785 struct evergreen_irq_stat_regs evergreen; 786 struct cik_irq_stat_regs cik; 787 }; 788 789 struct radeon_irq { 790 bool installed; 791 spinlock_t lock; 792 atomic_t ring_int[RADEON_NUM_RINGS]; 793 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 794 atomic_t pflip[RADEON_MAX_CRTCS]; 795 wait_queue_head_t vblank_queue; 796 bool hpd[RADEON_MAX_HPD_PINS]; 797 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 798 union radeon_irq_stat_regs stat_regs; 799 bool dpm_thermal; 800 }; 801 802 int radeon_irq_kms_init(struct radeon_device *rdev); 803 void radeon_irq_kms_fini(struct radeon_device *rdev); 804 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 805 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); 806 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 807 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 808 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 809 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 810 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 811 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 812 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 813 814 /* 815 * CP & rings. 816 */ 817 818 struct radeon_ib { 819 struct radeon_sa_bo *sa_bo; 820 uint32_t length_dw; 821 uint64_t gpu_addr; 822 uint32_t *ptr; 823 int ring; 824 struct radeon_fence *fence; 825 struct radeon_vm *vm; 826 bool is_const_ib; 827 struct radeon_sync sync; 828 }; 829 830 struct radeon_ring { 831 struct radeon_device *rdev; 832 struct radeon_bo *ring_obj; 833 volatile uint32_t *ring; 834 unsigned rptr_offs; 835 unsigned rptr_save_reg; 836 u64 next_rptr_gpu_addr; 837 volatile u32 *next_rptr_cpu_addr; 838 unsigned wptr; 839 unsigned wptr_old; 840 unsigned ring_size; 841 unsigned ring_free_dw; 842 int count_dw; 843 atomic_t last_rptr; 844 atomic64_t last_activity; 845 uint64_t gpu_addr; 846 uint32_t align_mask; 847 uint32_t ptr_mask; 848 bool ready; 849 u32 nop; 850 u32 idx; 851 u64 last_semaphore_signal_addr; 852 u64 last_semaphore_wait_addr; 853 /* for CIK queues */ 854 u32 me; 855 u32 pipe; 856 u32 queue; 857 struct radeon_bo *mqd_obj; 858 u32 doorbell_index; 859 unsigned wptr_offs; 860 }; 861 862 struct radeon_mec { 863 struct radeon_bo *hpd_eop_obj; 864 u64 hpd_eop_gpu_addr; 865 u32 num_pipe; 866 u32 num_mec; 867 u32 num_queue; 868 }; 869 870 /* 871 * VM 872 */ 873 874 /* maximum number of VMIDs */ 875 #define RADEON_NUM_VM 16 876 877 /* number of entries in page table */ 878 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 879 880 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 881 #define RADEON_VM_PTB_ALIGN_SIZE 32768 882 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 883 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 884 885 #define R600_PTE_VALID (1 << 0) 886 #define R600_PTE_SYSTEM (1 << 1) 887 #define R600_PTE_SNOOPED (1 << 2) 888 #define R600_PTE_READABLE (1 << 5) 889 #define R600_PTE_WRITEABLE (1 << 6) 890 891 /* PTE (Page Table Entry) fragment field for different page sizes */ 892 #define R600_PTE_FRAG_4KB (0 << 7) 893 #define R600_PTE_FRAG_64KB (4 << 7) 894 #define R600_PTE_FRAG_256KB (6 << 7) 895 896 /* flags needed to be set so we can copy directly from the GART table */ 897 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 898 R600_PTE_SYSTEM | R600_PTE_VALID ) 899 900 struct radeon_vm_pt { 901 struct radeon_bo *bo; 902 uint64_t addr; 903 }; 904 905 struct radeon_vm_id { 906 unsigned id; 907 uint64_t pd_gpu_addr; 908 /* last flushed PD/PT update */ 909 struct radeon_fence *flushed_updates; 910 /* last use of vmid */ 911 struct radeon_fence *last_id_use; 912 }; 913 914 struct radeon_vm { 915 struct mutex mutex; 916 917 struct rb_root_cached va; 918 919 /* protecting invalidated and freed */ 920 spinlock_t status_lock; 921 922 /* BOs moved, but not yet updated in the PT */ 923 struct list_head invalidated; 924 925 /* BOs freed, but not yet updated in the PT */ 926 struct list_head freed; 927 928 /* BOs cleared in the PT */ 929 struct list_head cleared; 930 931 /* contains the page directory */ 932 struct radeon_bo *page_directory; 933 unsigned max_pde_used; 934 935 /* array of page tables, one for each page directory entry */ 936 struct radeon_vm_pt *page_tables; 937 938 struct radeon_bo_va *ib_bo_va; 939 940 /* for id and flush management per ring */ 941 struct radeon_vm_id ids[RADEON_NUM_RINGS]; 942 }; 943 944 struct radeon_vm_manager { 945 struct radeon_fence *active[RADEON_NUM_VM]; 946 uint32_t max_pfn; 947 /* number of VMIDs */ 948 unsigned nvm; 949 /* vram base address for page table entry */ 950 u64 vram_base_offset; 951 /* is vm enabled? */ 952 bool enabled; 953 /* for hw to save the PD addr on suspend/resume */ 954 uint32_t saved_table_addr[RADEON_NUM_VM]; 955 }; 956 957 /* 958 * file private structure 959 */ 960 struct radeon_fpriv { 961 struct radeon_vm vm; 962 }; 963 964 /* 965 * R6xx+ IH ring 966 */ 967 struct r600_ih { 968 struct radeon_bo *ring_obj; 969 volatile uint32_t *ring; 970 unsigned rptr; 971 unsigned ring_size; 972 uint64_t gpu_addr; 973 uint32_t ptr_mask; 974 atomic_t lock; 975 bool enabled; 976 }; 977 978 /* 979 * RLC stuff 980 */ 981 #include "clearstate_defs.h" 982 983 struct radeon_rlc { 984 /* for power gating */ 985 struct radeon_bo *save_restore_obj; 986 uint64_t save_restore_gpu_addr; 987 volatile uint32_t *sr_ptr; 988 const u32 *reg_list; 989 u32 reg_list_size; 990 /* for clear state */ 991 struct radeon_bo *clear_state_obj; 992 uint64_t clear_state_gpu_addr; 993 volatile uint32_t *cs_ptr; 994 const struct cs_section_def *cs_data; 995 u32 clear_state_size; 996 /* for cp tables */ 997 struct radeon_bo *cp_table_obj; 998 uint64_t cp_table_gpu_addr; 999 volatile uint32_t *cp_table_ptr; 1000 u32 cp_table_size; 1001 }; 1002 1003 int radeon_ib_get(struct radeon_device *rdev, int ring, 1004 struct radeon_ib *ib, struct radeon_vm *vm, 1005 unsigned size); 1006 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 1007 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 1008 struct radeon_ib *const_ib, bool hdp_flush); 1009 int radeon_ib_pool_init(struct radeon_device *rdev); 1010 void radeon_ib_pool_fini(struct radeon_device *rdev); 1011 int radeon_ib_ring_tests(struct radeon_device *rdev); 1012 /* Ring access between begin & end cannot sleep */ 1013 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 1014 struct radeon_ring *ring); 1015 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 1016 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1017 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1018 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1019 bool hdp_flush); 1020 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1021 bool hdp_flush); 1022 void radeon_ring_undo(struct radeon_ring *ring); 1023 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 1024 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 1025 void radeon_ring_lockup_update(struct radeon_device *rdev, 1026 struct radeon_ring *ring); 1027 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1028 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1029 uint32_t **data); 1030 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1031 unsigned size, uint32_t *data); 1032 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1033 unsigned rptr_offs, u32 nop); 1034 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1035 1036 1037 /* r600 async dma */ 1038 void r600_dma_stop(struct radeon_device *rdev); 1039 int r600_dma_resume(struct radeon_device *rdev); 1040 void r600_dma_fini(struct radeon_device *rdev); 1041 1042 void cayman_dma_stop(struct radeon_device *rdev); 1043 int cayman_dma_resume(struct radeon_device *rdev); 1044 void cayman_dma_fini(struct radeon_device *rdev); 1045 1046 /* 1047 * CS. 1048 */ 1049 struct radeon_cs_chunk { 1050 uint32_t length_dw; 1051 uint32_t *kdata; 1052 void __user *user_ptr; 1053 }; 1054 1055 struct radeon_cs_parser { 1056 struct device *dev; 1057 struct radeon_device *rdev; 1058 struct drm_file *filp; 1059 /* chunks */ 1060 unsigned nchunks; 1061 struct radeon_cs_chunk *chunks; 1062 uint64_t *chunks_array; 1063 /* IB */ 1064 unsigned idx; 1065 /* relocations */ 1066 unsigned nrelocs; 1067 struct radeon_bo_list *relocs; 1068 struct radeon_bo_list *vm_bos; 1069 struct list_head validated; 1070 unsigned dma_reloc_idx; 1071 /* indices of various chunks */ 1072 struct radeon_cs_chunk *chunk_ib; 1073 struct radeon_cs_chunk *chunk_relocs; 1074 struct radeon_cs_chunk *chunk_flags; 1075 struct radeon_cs_chunk *chunk_const_ib; 1076 struct radeon_ib ib; 1077 struct radeon_ib const_ib; 1078 void *track; 1079 unsigned family; 1080 int parser_error; 1081 u32 cs_flags; 1082 u32 ring; 1083 s32 priority; 1084 struct ww_acquire_ctx ticket; 1085 }; 1086 1087 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1088 { 1089 struct radeon_cs_chunk *ibc = p->chunk_ib; 1090 1091 if (ibc->kdata) 1092 return ibc->kdata[idx]; 1093 return p->ib.ptr[idx]; 1094 } 1095 1096 1097 struct radeon_cs_packet { 1098 unsigned idx; 1099 unsigned type; 1100 unsigned reg; 1101 unsigned opcode; 1102 int count; 1103 unsigned one_reg_wr; 1104 }; 1105 1106 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1107 struct radeon_cs_packet *pkt, 1108 unsigned idx, unsigned reg); 1109 1110 /* 1111 * AGP 1112 */ 1113 1114 struct radeon_agp_mode { 1115 unsigned long mode; /**< AGP mode */ 1116 }; 1117 1118 struct radeon_agp_info { 1119 int agp_version_major; 1120 int agp_version_minor; 1121 unsigned long mode; 1122 unsigned long aperture_base; /* physical address */ 1123 unsigned long aperture_size; /* bytes */ 1124 unsigned long memory_allowed; /* bytes */ 1125 unsigned long memory_used; 1126 1127 /* PCI information */ 1128 unsigned short id_vendor; 1129 unsigned short id_device; 1130 }; 1131 1132 struct radeon_agp_head { 1133 struct agp_kern_info agp_info; 1134 struct list_head memory; 1135 unsigned long mode; 1136 struct agp_bridge_data *bridge; 1137 int enabled; 1138 int acquired; 1139 unsigned long base; 1140 int agp_mtrr; 1141 int cant_use_aperture; 1142 unsigned long page_mask; 1143 }; 1144 1145 #if IS_ENABLED(CONFIG_AGP) 1146 struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev); 1147 #else 1148 static inline struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev) 1149 { 1150 return NULL; 1151 } 1152 #endif 1153 int radeon_agp_init(struct radeon_device *rdev); 1154 void radeon_agp_resume(struct radeon_device *rdev); 1155 void radeon_agp_suspend(struct radeon_device *rdev); 1156 void radeon_agp_fini(struct radeon_device *rdev); 1157 1158 1159 /* 1160 * Writeback 1161 */ 1162 struct radeon_wb { 1163 struct radeon_bo *wb_obj; 1164 volatile uint32_t *wb; 1165 uint64_t gpu_addr; 1166 bool enabled; 1167 bool use_event; 1168 }; 1169 1170 #define RADEON_WB_SCRATCH_OFFSET 0 1171 #define RADEON_WB_RING0_NEXT_RPTR 256 1172 #define RADEON_WB_CP_RPTR_OFFSET 1024 1173 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1174 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1175 #define R600_WB_DMA_RPTR_OFFSET 1792 1176 #define R600_WB_IH_WPTR_OFFSET 2048 1177 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1178 #define R600_WB_EVENT_OFFSET 3072 1179 #define CIK_WB_CP1_WPTR_OFFSET 3328 1180 #define CIK_WB_CP2_WPTR_OFFSET 3584 1181 #define R600_WB_DMA_RING_TEST_OFFSET 3588 1182 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 1183 1184 /** 1185 * struct radeon_pm - power management datas 1186 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1187 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1188 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1189 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1190 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1191 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1192 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1193 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1194 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1195 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1196 * @needed_bandwidth: current bandwidth needs 1197 * 1198 * It keeps track of various data needed to take powermanagement decision. 1199 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1200 * Equation between gpu/memory clock and available bandwidth is hw dependent 1201 * (type of memory, bus size, efficiency, ...) 1202 */ 1203 1204 enum radeon_pm_method { 1205 PM_METHOD_PROFILE, 1206 PM_METHOD_DYNPM, 1207 PM_METHOD_DPM, 1208 }; 1209 1210 enum radeon_dynpm_state { 1211 DYNPM_STATE_DISABLED, 1212 DYNPM_STATE_MINIMUM, 1213 DYNPM_STATE_PAUSED, 1214 DYNPM_STATE_ACTIVE, 1215 DYNPM_STATE_SUSPENDED, 1216 }; 1217 enum radeon_dynpm_action { 1218 DYNPM_ACTION_NONE, 1219 DYNPM_ACTION_MINIMUM, 1220 DYNPM_ACTION_DOWNCLOCK, 1221 DYNPM_ACTION_UPCLOCK, 1222 DYNPM_ACTION_DEFAULT 1223 }; 1224 1225 enum radeon_voltage_type { 1226 VOLTAGE_NONE = 0, 1227 VOLTAGE_GPIO, 1228 VOLTAGE_VDDC, 1229 VOLTAGE_SW 1230 }; 1231 1232 enum radeon_pm_state_type { 1233 /* not used for dpm */ 1234 POWER_STATE_TYPE_DEFAULT, 1235 POWER_STATE_TYPE_POWERSAVE, 1236 /* user selectable states */ 1237 POWER_STATE_TYPE_BATTERY, 1238 POWER_STATE_TYPE_BALANCED, 1239 POWER_STATE_TYPE_PERFORMANCE, 1240 /* internal states */ 1241 POWER_STATE_TYPE_INTERNAL_UVD, 1242 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1243 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1244 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1245 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1246 POWER_STATE_TYPE_INTERNAL_BOOT, 1247 POWER_STATE_TYPE_INTERNAL_THERMAL, 1248 POWER_STATE_TYPE_INTERNAL_ACPI, 1249 POWER_STATE_TYPE_INTERNAL_ULV, 1250 POWER_STATE_TYPE_INTERNAL_3DPERF, 1251 }; 1252 1253 enum radeon_pm_profile_type { 1254 PM_PROFILE_DEFAULT, 1255 PM_PROFILE_AUTO, 1256 PM_PROFILE_LOW, 1257 PM_PROFILE_MID, 1258 PM_PROFILE_HIGH, 1259 }; 1260 1261 #define PM_PROFILE_DEFAULT_IDX 0 1262 #define PM_PROFILE_LOW_SH_IDX 1 1263 #define PM_PROFILE_MID_SH_IDX 2 1264 #define PM_PROFILE_HIGH_SH_IDX 3 1265 #define PM_PROFILE_LOW_MH_IDX 4 1266 #define PM_PROFILE_MID_MH_IDX 5 1267 #define PM_PROFILE_HIGH_MH_IDX 6 1268 #define PM_PROFILE_MAX 7 1269 1270 struct radeon_pm_profile { 1271 int dpms_off_ps_idx; 1272 int dpms_on_ps_idx; 1273 int dpms_off_cm_idx; 1274 int dpms_on_cm_idx; 1275 }; 1276 1277 enum radeon_int_thermal_type { 1278 THERMAL_TYPE_NONE, 1279 THERMAL_TYPE_EXTERNAL, 1280 THERMAL_TYPE_EXTERNAL_GPIO, 1281 THERMAL_TYPE_RV6XX, 1282 THERMAL_TYPE_RV770, 1283 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1284 THERMAL_TYPE_EVERGREEN, 1285 THERMAL_TYPE_SUMO, 1286 THERMAL_TYPE_NI, 1287 THERMAL_TYPE_SI, 1288 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1289 THERMAL_TYPE_CI, 1290 THERMAL_TYPE_KV, 1291 }; 1292 1293 struct radeon_voltage { 1294 enum radeon_voltage_type type; 1295 /* gpio voltage */ 1296 struct radeon_gpio_rec gpio; 1297 u32 delay; /* delay in usec from voltage drop to sclk change */ 1298 bool active_high; /* voltage drop is active when bit is high */ 1299 /* VDDC voltage */ 1300 u8 vddc_id; /* index into vddc voltage table */ 1301 u8 vddci_id; /* index into vddci voltage table */ 1302 bool vddci_enabled; 1303 /* r6xx+ sw */ 1304 u16 voltage; 1305 /* evergreen+ vddci */ 1306 u16 vddci; 1307 }; 1308 1309 /* clock mode flags */ 1310 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1311 1312 struct radeon_pm_clock_info { 1313 /* memory clock */ 1314 u32 mclk; 1315 /* engine clock */ 1316 u32 sclk; 1317 /* voltage info */ 1318 struct radeon_voltage voltage; 1319 /* standardized clock flags */ 1320 u32 flags; 1321 }; 1322 1323 /* state flags */ 1324 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1325 1326 struct radeon_power_state { 1327 enum radeon_pm_state_type type; 1328 struct radeon_pm_clock_info *clock_info; 1329 /* number of valid clock modes in this power state */ 1330 int num_clock_modes; 1331 struct radeon_pm_clock_info *default_clock_mode; 1332 /* standardized state flags */ 1333 u32 flags; 1334 u32 misc; /* vbios specific flags */ 1335 u32 misc2; /* vbios specific flags */ 1336 int pcie_lanes; /* pcie lanes */ 1337 }; 1338 1339 /* 1340 * Some modes are overclocked by very low value, accept them 1341 */ 1342 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1343 1344 enum radeon_dpm_auto_throttle_src { 1345 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1346 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1347 }; 1348 1349 enum radeon_dpm_event_src { 1350 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1351 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1352 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1353 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1354 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1355 }; 1356 1357 #define RADEON_MAX_VCE_LEVELS 6 1358 1359 enum radeon_vce_level { 1360 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1361 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1362 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1363 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1364 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1365 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1366 }; 1367 1368 struct radeon_ps { 1369 u32 caps; /* vbios flags */ 1370 u32 class; /* vbios flags */ 1371 u32 class2; /* vbios flags */ 1372 /* UVD clocks */ 1373 u32 vclk; 1374 u32 dclk; 1375 /* VCE clocks */ 1376 u32 evclk; 1377 u32 ecclk; 1378 bool vce_active; 1379 enum radeon_vce_level vce_level; 1380 /* asic priv */ 1381 void *ps_priv; 1382 }; 1383 1384 struct radeon_dpm_thermal { 1385 /* thermal interrupt work */ 1386 struct work_struct work; 1387 /* low temperature threshold */ 1388 int min_temp; 1389 /* high temperature threshold */ 1390 int max_temp; 1391 /* was interrupt low to high or high to low */ 1392 bool high_to_low; 1393 }; 1394 1395 enum radeon_clk_action 1396 { 1397 RADEON_SCLK_UP = 1, 1398 RADEON_SCLK_DOWN 1399 }; 1400 1401 struct radeon_blacklist_clocks 1402 { 1403 u32 sclk; 1404 u32 mclk; 1405 enum radeon_clk_action action; 1406 }; 1407 1408 struct radeon_clock_and_voltage_limits { 1409 u32 sclk; 1410 u32 mclk; 1411 u16 vddc; 1412 u16 vddci; 1413 }; 1414 1415 struct radeon_clock_array { 1416 u32 count; 1417 u32 *values; 1418 }; 1419 1420 struct radeon_clock_voltage_dependency_entry { 1421 u32 clk; 1422 u16 v; 1423 }; 1424 1425 struct radeon_clock_voltage_dependency_table { 1426 u32 count; 1427 struct radeon_clock_voltage_dependency_entry *entries; 1428 }; 1429 1430 union radeon_cac_leakage_entry { 1431 struct { 1432 u16 vddc; 1433 u32 leakage; 1434 }; 1435 struct { 1436 u16 vddc1; 1437 u16 vddc2; 1438 u16 vddc3; 1439 }; 1440 }; 1441 1442 struct radeon_cac_leakage_table { 1443 u32 count; 1444 union radeon_cac_leakage_entry *entries; 1445 }; 1446 1447 struct radeon_phase_shedding_limits_entry { 1448 u16 voltage; 1449 u32 sclk; 1450 u32 mclk; 1451 }; 1452 1453 struct radeon_phase_shedding_limits_table { 1454 u32 count; 1455 struct radeon_phase_shedding_limits_entry *entries; 1456 }; 1457 1458 struct radeon_uvd_clock_voltage_dependency_entry { 1459 u32 vclk; 1460 u32 dclk; 1461 u16 v; 1462 }; 1463 1464 struct radeon_uvd_clock_voltage_dependency_table { 1465 u8 count; 1466 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1467 }; 1468 1469 struct radeon_vce_clock_voltage_dependency_entry { 1470 u32 ecclk; 1471 u32 evclk; 1472 u16 v; 1473 }; 1474 1475 struct radeon_vce_clock_voltage_dependency_table { 1476 u8 count; 1477 struct radeon_vce_clock_voltage_dependency_entry *entries; 1478 }; 1479 1480 struct radeon_ppm_table { 1481 u8 ppm_design; 1482 u16 cpu_core_number; 1483 u32 platform_tdp; 1484 u32 small_ac_platform_tdp; 1485 u32 platform_tdc; 1486 u32 small_ac_platform_tdc; 1487 u32 apu_tdp; 1488 u32 dgpu_tdp; 1489 u32 dgpu_ulv_power; 1490 u32 tj_max; 1491 }; 1492 1493 struct radeon_cac_tdp_table { 1494 u16 tdp; 1495 u16 configurable_tdp; 1496 u16 tdc; 1497 u16 battery_power_limit; 1498 u16 small_power_limit; 1499 u16 low_cac_leakage; 1500 u16 high_cac_leakage; 1501 u16 maximum_power_delivery_limit; 1502 }; 1503 1504 struct radeon_dpm_dynamic_state { 1505 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1506 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1507 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1508 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1509 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1510 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1511 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1512 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1513 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1514 struct radeon_clock_array valid_sclk_values; 1515 struct radeon_clock_array valid_mclk_values; 1516 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1517 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1518 u32 mclk_sclk_ratio; 1519 u32 sclk_mclk_delta; 1520 u16 vddc_vddci_delta; 1521 u16 min_vddc_for_pcie_gen2; 1522 struct radeon_cac_leakage_table cac_leakage_table; 1523 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1524 struct radeon_ppm_table *ppm_table; 1525 struct radeon_cac_tdp_table *cac_tdp_table; 1526 }; 1527 1528 struct radeon_dpm_fan { 1529 u16 t_min; 1530 u16 t_med; 1531 u16 t_high; 1532 u16 pwm_min; 1533 u16 pwm_med; 1534 u16 pwm_high; 1535 u8 t_hyst; 1536 u32 cycle_delay; 1537 u16 t_max; 1538 u8 control_mode; 1539 u16 default_max_fan_pwm; 1540 u16 default_fan_output_sensitivity; 1541 u16 fan_output_sensitivity; 1542 bool ucode_fan_control; 1543 }; 1544 1545 enum radeon_pcie_gen { 1546 RADEON_PCIE_GEN1 = 0, 1547 RADEON_PCIE_GEN2 = 1, 1548 RADEON_PCIE_GEN3 = 2, 1549 RADEON_PCIE_GEN_INVALID = 0xffff 1550 }; 1551 1552 enum radeon_dpm_forced_level { 1553 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1554 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1555 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1556 }; 1557 1558 struct radeon_vce_state { 1559 /* vce clocks */ 1560 u32 evclk; 1561 u32 ecclk; 1562 /* gpu clocks */ 1563 u32 sclk; 1564 u32 mclk; 1565 u8 clk_idx; 1566 u8 pstate; 1567 }; 1568 1569 struct radeon_dpm { 1570 struct radeon_ps *ps; 1571 /* number of valid power states */ 1572 int num_ps; 1573 /* current power state that is active */ 1574 struct radeon_ps *current_ps; 1575 /* requested power state */ 1576 struct radeon_ps *requested_ps; 1577 /* boot up power state */ 1578 struct radeon_ps *boot_ps; 1579 /* default uvd power state */ 1580 struct radeon_ps *uvd_ps; 1581 /* vce requirements */ 1582 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1583 enum radeon_vce_level vce_level; 1584 enum radeon_pm_state_type state; 1585 enum radeon_pm_state_type user_state; 1586 u32 platform_caps; 1587 u32 voltage_response_time; 1588 u32 backbias_response_time; 1589 void *priv; 1590 u32 new_active_crtcs; 1591 int new_active_crtc_count; 1592 int high_pixelclock_count; 1593 u32 current_active_crtcs; 1594 int current_active_crtc_count; 1595 bool single_display; 1596 struct radeon_dpm_dynamic_state dyn_state; 1597 struct radeon_dpm_fan fan; 1598 u32 tdp_limit; 1599 u32 near_tdp_limit; 1600 u32 near_tdp_limit_adjusted; 1601 u32 sq_ramping_threshold; 1602 u32 cac_leakage; 1603 u16 tdp_od_limit; 1604 u32 tdp_adjustment; 1605 u16 load_line_slope; 1606 bool power_control; 1607 bool ac_power; 1608 /* special states active */ 1609 bool thermal_active; 1610 bool uvd_active; 1611 bool vce_active; 1612 /* thermal handling */ 1613 struct radeon_dpm_thermal thermal; 1614 /* forced levels */ 1615 enum radeon_dpm_forced_level forced_level; 1616 /* track UVD streams */ 1617 unsigned sd; 1618 unsigned hd; 1619 }; 1620 1621 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1622 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1623 1624 struct radeon_pm { 1625 struct mutex mutex; 1626 /* write locked while reprogramming mclk */ 1627 struct rw_semaphore mclk_lock; 1628 u32 active_crtcs; 1629 int active_crtc_count; 1630 int req_vblank; 1631 bool vblank_sync; 1632 fixed20_12 max_bandwidth; 1633 fixed20_12 igp_sideport_mclk; 1634 fixed20_12 igp_system_mclk; 1635 fixed20_12 igp_ht_link_clk; 1636 fixed20_12 igp_ht_link_width; 1637 fixed20_12 k8_bandwidth; 1638 fixed20_12 sideport_bandwidth; 1639 fixed20_12 ht_bandwidth; 1640 fixed20_12 core_bandwidth; 1641 fixed20_12 sclk; 1642 fixed20_12 mclk; 1643 fixed20_12 needed_bandwidth; 1644 struct radeon_power_state *power_state; 1645 /* number of valid power states */ 1646 int num_power_states; 1647 int current_power_state_index; 1648 int current_clock_mode_index; 1649 int requested_power_state_index; 1650 int requested_clock_mode_index; 1651 int default_power_state_index; 1652 u32 current_sclk; 1653 u32 current_mclk; 1654 u16 current_vddc; 1655 u16 current_vddci; 1656 u32 default_sclk; 1657 u32 default_mclk; 1658 u16 default_vddc; 1659 u16 default_vddci; 1660 struct radeon_i2c_chan *i2c_bus; 1661 /* selected pm method */ 1662 enum radeon_pm_method pm_method; 1663 /* dynpm power management */ 1664 struct delayed_work dynpm_idle_work; 1665 enum radeon_dynpm_state dynpm_state; 1666 enum radeon_dynpm_action dynpm_planned_action; 1667 unsigned long dynpm_action_timeout; 1668 bool dynpm_can_upclock; 1669 bool dynpm_can_downclock; 1670 /* profile-based power management */ 1671 enum radeon_pm_profile_type profile; 1672 int profile_index; 1673 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1674 /* internal thermal controller on rv6xx+ */ 1675 enum radeon_int_thermal_type int_thermal_type; 1676 struct device *int_hwmon_dev; 1677 /* fan control parameters */ 1678 bool no_fan; 1679 u8 fan_pulses_per_revolution; 1680 u8 fan_min_rpm; 1681 u8 fan_max_rpm; 1682 /* dpm */ 1683 bool dpm_enabled; 1684 bool sysfs_initialized; 1685 struct radeon_dpm dpm; 1686 }; 1687 1688 #define RADEON_PCIE_SPEED_25 1 1689 #define RADEON_PCIE_SPEED_50 2 1690 #define RADEON_PCIE_SPEED_80 4 1691 1692 int radeon_pm_get_type_index(struct radeon_device *rdev, 1693 enum radeon_pm_state_type ps_type, 1694 int instance); 1695 /* 1696 * UVD 1697 */ 1698 #define RADEON_DEFAULT_UVD_HANDLES 10 1699 #define RADEON_MAX_UVD_HANDLES 30 1700 #define RADEON_UVD_STACK_SIZE (200*1024) 1701 #define RADEON_UVD_HEAP_SIZE (256*1024) 1702 #define RADEON_UVD_SESSION_SIZE (50*1024) 1703 1704 struct radeon_uvd { 1705 bool fw_header_present; 1706 struct radeon_bo *vcpu_bo; 1707 void *cpu_addr; 1708 uint64_t gpu_addr; 1709 unsigned max_handles; 1710 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1711 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1712 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1713 struct delayed_work idle_work; 1714 }; 1715 1716 int radeon_uvd_init(struct radeon_device *rdev); 1717 void radeon_uvd_fini(struct radeon_device *rdev); 1718 int radeon_uvd_suspend(struct radeon_device *rdev); 1719 int radeon_uvd_resume(struct radeon_device *rdev); 1720 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1721 uint32_t handle, struct radeon_fence **fence); 1722 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1723 uint32_t handle, struct radeon_fence **fence); 1724 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1725 uint32_t allowed_domains); 1726 void radeon_uvd_free_handles(struct radeon_device *rdev, 1727 struct drm_file *filp); 1728 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1729 void radeon_uvd_note_usage(struct radeon_device *rdev); 1730 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1731 unsigned vclk, unsigned dclk, 1732 unsigned vco_min, unsigned vco_max, 1733 unsigned fb_factor, unsigned fb_mask, 1734 unsigned pd_min, unsigned pd_max, 1735 unsigned pd_even, 1736 unsigned *optimal_fb_div, 1737 unsigned *optimal_vclk_div, 1738 unsigned *optimal_dclk_div); 1739 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1740 unsigned cg_upll_func_cntl); 1741 1742 /* 1743 * VCE 1744 */ 1745 #define RADEON_MAX_VCE_HANDLES 16 1746 1747 struct radeon_vce { 1748 struct radeon_bo *vcpu_bo; 1749 uint64_t gpu_addr; 1750 unsigned fw_version; 1751 unsigned fb_version; 1752 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1753 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1754 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1755 struct delayed_work idle_work; 1756 uint32_t keyselect; 1757 }; 1758 1759 int radeon_vce_init(struct radeon_device *rdev); 1760 void radeon_vce_fini(struct radeon_device *rdev); 1761 int radeon_vce_suspend(struct radeon_device *rdev); 1762 int radeon_vce_resume(struct radeon_device *rdev); 1763 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1764 uint32_t handle, struct radeon_fence **fence); 1765 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1766 uint32_t handle, struct radeon_fence **fence); 1767 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1768 void radeon_vce_note_usage(struct radeon_device *rdev); 1769 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1770 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1771 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1772 struct radeon_ring *ring, 1773 struct radeon_semaphore *semaphore, 1774 bool emit_wait); 1775 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1776 void radeon_vce_fence_emit(struct radeon_device *rdev, 1777 struct radeon_fence *fence); 1778 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1779 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1780 1781 struct r600_audio_pin { 1782 int channels; 1783 int rate; 1784 int bits_per_sample; 1785 u8 status_bits; 1786 u8 category_code; 1787 u32 offset; 1788 bool connected; 1789 u32 id; 1790 }; 1791 1792 struct r600_audio { 1793 bool enabled; 1794 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1795 int num_pins; 1796 struct radeon_audio_funcs *hdmi_funcs; 1797 struct radeon_audio_funcs *dp_funcs; 1798 struct radeon_audio_basic_funcs *funcs; 1799 struct drm_audio_component *component; 1800 bool component_registered; 1801 struct mutex component_mutex; 1802 }; 1803 1804 /* 1805 * Benchmarking 1806 */ 1807 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1808 1809 1810 /* 1811 * Testing 1812 */ 1813 void radeon_test_moves(struct radeon_device *rdev); 1814 void radeon_test_ring_sync(struct radeon_device *rdev, 1815 struct radeon_ring *cpA, 1816 struct radeon_ring *cpB); 1817 void radeon_test_syncing(struct radeon_device *rdev); 1818 1819 /* 1820 * MMU Notifier 1821 */ 1822 #if defined(CONFIG_MMU_NOTIFIER) 1823 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); 1824 void radeon_mn_unregister(struct radeon_bo *bo); 1825 #else 1826 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr) 1827 { 1828 return -ENODEV; 1829 } 1830 static inline void radeon_mn_unregister(struct radeon_bo *bo) {} 1831 #endif 1832 1833 /* 1834 * Debugfs 1835 */ 1836 void radeon_debugfs_fence_init(struct radeon_device *rdev); 1837 void radeon_gem_debugfs_init(struct radeon_device *rdev); 1838 1839 /* 1840 * ASIC ring specific functions. 1841 */ 1842 struct radeon_asic_ring { 1843 /* ring read/write ptr handling */ 1844 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1845 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1846 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1847 1848 /* validating and patching of IBs */ 1849 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1850 int (*cs_parse)(struct radeon_cs_parser *p); 1851 1852 /* command emmit functions */ 1853 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1854 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1855 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1856 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1857 struct radeon_semaphore *semaphore, bool emit_wait); 1858 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring, 1859 unsigned vm_id, uint64_t pd_addr); 1860 1861 /* testing functions */ 1862 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1863 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1864 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1865 1866 /* deprecated */ 1867 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1868 }; 1869 1870 /* 1871 * ASIC specific functions. 1872 */ 1873 struct radeon_asic { 1874 int (*init)(struct radeon_device *rdev); 1875 void (*fini)(struct radeon_device *rdev); 1876 int (*resume)(struct radeon_device *rdev); 1877 int (*suspend)(struct radeon_device *rdev); 1878 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1879 int (*asic_reset)(struct radeon_device *rdev, bool hard); 1880 /* Flush the HDP cache via MMIO */ 1881 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1882 /* check if 3D engine is idle */ 1883 bool (*gui_idle)(struct radeon_device *rdev); 1884 /* wait for mc_idle */ 1885 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1886 /* get the reference clock */ 1887 u32 (*get_xclk)(struct radeon_device *rdev); 1888 /* get the gpu clock counter */ 1889 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1890 /* get register for info ioctl */ 1891 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val); 1892 /* gart */ 1893 struct { 1894 void (*tlb_flush)(struct radeon_device *rdev); 1895 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags); 1896 void (*set_page)(struct radeon_device *rdev, unsigned i, 1897 uint64_t entry); 1898 } gart; 1899 struct { 1900 int (*init)(struct radeon_device *rdev); 1901 void (*fini)(struct radeon_device *rdev); 1902 void (*copy_pages)(struct radeon_device *rdev, 1903 struct radeon_ib *ib, 1904 uint64_t pe, uint64_t src, 1905 unsigned count); 1906 void (*write_pages)(struct radeon_device *rdev, 1907 struct radeon_ib *ib, 1908 uint64_t pe, 1909 uint64_t addr, unsigned count, 1910 uint32_t incr, uint32_t flags); 1911 void (*set_pages)(struct radeon_device *rdev, 1912 struct radeon_ib *ib, 1913 uint64_t pe, 1914 uint64_t addr, unsigned count, 1915 uint32_t incr, uint32_t flags); 1916 void (*pad_ib)(struct radeon_ib *ib); 1917 } vm; 1918 /* ring specific callbacks */ 1919 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1920 /* irqs */ 1921 struct { 1922 int (*set)(struct radeon_device *rdev); 1923 int (*process)(struct radeon_device *rdev); 1924 } irq; 1925 /* displays */ 1926 struct { 1927 /* display watermarks */ 1928 void (*bandwidth_update)(struct radeon_device *rdev); 1929 /* get frame count */ 1930 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1931 /* wait for vblank */ 1932 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1933 /* set backlight level */ 1934 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1935 /* get backlight level */ 1936 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1937 /* audio callbacks */ 1938 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1939 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1940 } display; 1941 /* copy functions for bo handling */ 1942 struct { 1943 struct radeon_fence *(*blit)(struct radeon_device *rdev, 1944 uint64_t src_offset, 1945 uint64_t dst_offset, 1946 unsigned num_gpu_pages, 1947 struct dma_resv *resv); 1948 u32 blit_ring_index; 1949 struct radeon_fence *(*dma)(struct radeon_device *rdev, 1950 uint64_t src_offset, 1951 uint64_t dst_offset, 1952 unsigned num_gpu_pages, 1953 struct dma_resv *resv); 1954 u32 dma_ring_index; 1955 /* method used for bo copy */ 1956 struct radeon_fence *(*copy)(struct radeon_device *rdev, 1957 uint64_t src_offset, 1958 uint64_t dst_offset, 1959 unsigned num_gpu_pages, 1960 struct dma_resv *resv); 1961 /* ring used for bo copies */ 1962 u32 copy_ring_index; 1963 } copy; 1964 /* surfaces */ 1965 struct { 1966 int (*set_reg)(struct radeon_device *rdev, int reg, 1967 uint32_t tiling_flags, uint32_t pitch, 1968 uint32_t offset, uint32_t obj_size); 1969 void (*clear_reg)(struct radeon_device *rdev, int reg); 1970 } surface; 1971 /* hotplug detect */ 1972 struct { 1973 void (*init)(struct radeon_device *rdev); 1974 void (*fini)(struct radeon_device *rdev); 1975 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1976 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1977 } hpd; 1978 /* static power management */ 1979 struct { 1980 void (*misc)(struct radeon_device *rdev); 1981 void (*prepare)(struct radeon_device *rdev); 1982 void (*finish)(struct radeon_device *rdev); 1983 void (*init_profile)(struct radeon_device *rdev); 1984 void (*get_dynpm_state)(struct radeon_device *rdev); 1985 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1986 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1987 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1988 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1989 int (*get_pcie_lanes)(struct radeon_device *rdev); 1990 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1991 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1992 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1993 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1994 int (*get_temperature)(struct radeon_device *rdev); 1995 } pm; 1996 /* dynamic power management */ 1997 struct { 1998 int (*init)(struct radeon_device *rdev); 1999 void (*setup_asic)(struct radeon_device *rdev); 2000 int (*enable)(struct radeon_device *rdev); 2001 int (*late_enable)(struct radeon_device *rdev); 2002 void (*disable)(struct radeon_device *rdev); 2003 int (*pre_set_power_state)(struct radeon_device *rdev); 2004 int (*set_power_state)(struct radeon_device *rdev); 2005 void (*post_set_power_state)(struct radeon_device *rdev); 2006 void (*display_configuration_changed)(struct radeon_device *rdev); 2007 void (*fini)(struct radeon_device *rdev); 2008 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 2009 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 2010 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 2011 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 2012 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 2013 bool (*vblank_too_short)(struct radeon_device *rdev); 2014 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 2015 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 2016 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode); 2017 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev); 2018 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed); 2019 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed); 2020 u32 (*get_current_sclk)(struct radeon_device *rdev); 2021 u32 (*get_current_mclk)(struct radeon_device *rdev); 2022 u16 (*get_current_vddc)(struct radeon_device *rdev); 2023 } dpm; 2024 /* pageflipping */ 2025 struct { 2026 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async); 2027 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 2028 } pflip; 2029 }; 2030 2031 /* 2032 * Asic structures 2033 */ 2034 struct r100_asic { 2035 const unsigned *reg_safe_bm; 2036 unsigned reg_safe_bm_size; 2037 u32 hdp_cntl; 2038 }; 2039 2040 struct r300_asic { 2041 const unsigned *reg_safe_bm; 2042 unsigned reg_safe_bm_size; 2043 u32 resync_scratch; 2044 u32 hdp_cntl; 2045 }; 2046 2047 struct r600_asic { 2048 unsigned max_pipes; 2049 unsigned max_tile_pipes; 2050 unsigned max_simds; 2051 unsigned max_backends; 2052 unsigned max_gprs; 2053 unsigned max_threads; 2054 unsigned max_stack_entries; 2055 unsigned max_hw_contexts; 2056 unsigned max_gs_threads; 2057 unsigned sx_max_export_size; 2058 unsigned sx_max_export_pos_size; 2059 unsigned sx_max_export_smx_size; 2060 unsigned sq_num_cf_insts; 2061 unsigned tiling_nbanks; 2062 unsigned tiling_npipes; 2063 unsigned tiling_group_size; 2064 unsigned tile_config; 2065 unsigned backend_map; 2066 unsigned active_simds; 2067 }; 2068 2069 struct rv770_asic { 2070 unsigned max_pipes; 2071 unsigned max_tile_pipes; 2072 unsigned max_simds; 2073 unsigned max_backends; 2074 unsigned max_gprs; 2075 unsigned max_threads; 2076 unsigned max_stack_entries; 2077 unsigned max_hw_contexts; 2078 unsigned max_gs_threads; 2079 unsigned sx_max_export_size; 2080 unsigned sx_max_export_pos_size; 2081 unsigned sx_max_export_smx_size; 2082 unsigned sq_num_cf_insts; 2083 unsigned sx_num_of_sets; 2084 unsigned sc_prim_fifo_size; 2085 unsigned sc_hiz_tile_fifo_size; 2086 unsigned sc_earlyz_tile_fifo_fize; 2087 unsigned tiling_nbanks; 2088 unsigned tiling_npipes; 2089 unsigned tiling_group_size; 2090 unsigned tile_config; 2091 unsigned backend_map; 2092 unsigned active_simds; 2093 }; 2094 2095 struct evergreen_asic { 2096 unsigned num_ses; 2097 unsigned max_pipes; 2098 unsigned max_tile_pipes; 2099 unsigned max_simds; 2100 unsigned max_backends; 2101 unsigned max_gprs; 2102 unsigned max_threads; 2103 unsigned max_stack_entries; 2104 unsigned max_hw_contexts; 2105 unsigned max_gs_threads; 2106 unsigned sx_max_export_size; 2107 unsigned sx_max_export_pos_size; 2108 unsigned sx_max_export_smx_size; 2109 unsigned sq_num_cf_insts; 2110 unsigned sx_num_of_sets; 2111 unsigned sc_prim_fifo_size; 2112 unsigned sc_hiz_tile_fifo_size; 2113 unsigned sc_earlyz_tile_fifo_size; 2114 unsigned tiling_nbanks; 2115 unsigned tiling_npipes; 2116 unsigned tiling_group_size; 2117 unsigned tile_config; 2118 unsigned backend_map; 2119 unsigned active_simds; 2120 }; 2121 2122 struct cayman_asic { 2123 unsigned max_shader_engines; 2124 unsigned max_pipes_per_simd; 2125 unsigned max_tile_pipes; 2126 unsigned max_simds_per_se; 2127 unsigned max_backends_per_se; 2128 unsigned max_texture_channel_caches; 2129 unsigned max_gprs; 2130 unsigned max_threads; 2131 unsigned max_gs_threads; 2132 unsigned max_stack_entries; 2133 unsigned sx_num_of_sets; 2134 unsigned sx_max_export_size; 2135 unsigned sx_max_export_pos_size; 2136 unsigned sx_max_export_smx_size; 2137 unsigned max_hw_contexts; 2138 unsigned sq_num_cf_insts; 2139 unsigned sc_prim_fifo_size; 2140 unsigned sc_hiz_tile_fifo_size; 2141 unsigned sc_earlyz_tile_fifo_size; 2142 2143 unsigned num_shader_engines; 2144 unsigned num_shader_pipes_per_simd; 2145 unsigned num_tile_pipes; 2146 unsigned num_simds_per_se; 2147 unsigned num_backends_per_se; 2148 unsigned backend_disable_mask_per_asic; 2149 unsigned backend_map; 2150 unsigned num_texture_channel_caches; 2151 unsigned mem_max_burst_length_bytes; 2152 unsigned mem_row_size_in_kb; 2153 unsigned shader_engine_tile_size; 2154 unsigned num_gpus; 2155 unsigned multi_gpu_tile_size; 2156 2157 unsigned tile_config; 2158 unsigned active_simds; 2159 }; 2160 2161 struct si_asic { 2162 unsigned max_shader_engines; 2163 unsigned max_tile_pipes; 2164 unsigned max_cu_per_sh; 2165 unsigned max_sh_per_se; 2166 unsigned max_backends_per_se; 2167 unsigned max_texture_channel_caches; 2168 unsigned max_gprs; 2169 unsigned max_gs_threads; 2170 unsigned max_hw_contexts; 2171 unsigned sc_prim_fifo_size_frontend; 2172 unsigned sc_prim_fifo_size_backend; 2173 unsigned sc_hiz_tile_fifo_size; 2174 unsigned sc_earlyz_tile_fifo_size; 2175 2176 unsigned num_tile_pipes; 2177 unsigned backend_enable_mask; 2178 unsigned backend_disable_mask_per_asic; 2179 unsigned backend_map; 2180 unsigned num_texture_channel_caches; 2181 unsigned mem_max_burst_length_bytes; 2182 unsigned mem_row_size_in_kb; 2183 unsigned shader_engine_tile_size; 2184 unsigned num_gpus; 2185 unsigned multi_gpu_tile_size; 2186 2187 unsigned tile_config; 2188 uint32_t tile_mode_array[32]; 2189 uint32_t active_cus; 2190 }; 2191 2192 struct cik_asic { 2193 unsigned max_shader_engines; 2194 unsigned max_tile_pipes; 2195 unsigned max_cu_per_sh; 2196 unsigned max_sh_per_se; 2197 unsigned max_backends_per_se; 2198 unsigned max_texture_channel_caches; 2199 unsigned max_gprs; 2200 unsigned max_gs_threads; 2201 unsigned max_hw_contexts; 2202 unsigned sc_prim_fifo_size_frontend; 2203 unsigned sc_prim_fifo_size_backend; 2204 unsigned sc_hiz_tile_fifo_size; 2205 unsigned sc_earlyz_tile_fifo_size; 2206 2207 unsigned num_tile_pipes; 2208 unsigned backend_enable_mask; 2209 unsigned backend_disable_mask_per_asic; 2210 unsigned backend_map; 2211 unsigned num_texture_channel_caches; 2212 unsigned mem_max_burst_length_bytes; 2213 unsigned mem_row_size_in_kb; 2214 unsigned shader_engine_tile_size; 2215 unsigned num_gpus; 2216 unsigned multi_gpu_tile_size; 2217 2218 unsigned tile_config; 2219 uint32_t tile_mode_array[32]; 2220 uint32_t macrotile_mode_array[16]; 2221 uint32_t active_cus; 2222 }; 2223 2224 union radeon_asic_config { 2225 struct r300_asic r300; 2226 struct r100_asic r100; 2227 struct r600_asic r600; 2228 struct rv770_asic rv770; 2229 struct evergreen_asic evergreen; 2230 struct cayman_asic cayman; 2231 struct si_asic si; 2232 struct cik_asic cik; 2233 }; 2234 2235 /* 2236 * asic initizalization from radeon_asic.c 2237 */ 2238 void radeon_agp_disable(struct radeon_device *rdev); 2239 int radeon_asic_init(struct radeon_device *rdev); 2240 2241 2242 /* 2243 * IOCTL. 2244 */ 2245 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2246 struct drm_file *filp); 2247 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2248 struct drm_file *filp); 2249 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, 2250 struct drm_file *filp); 2251 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2252 struct drm_file *file_priv); 2253 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2254 struct drm_file *file_priv); 2255 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2256 struct drm_file *file_priv); 2257 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2258 struct drm_file *file_priv); 2259 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2260 struct drm_file *filp); 2261 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2262 struct drm_file *filp); 2263 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2264 struct drm_file *filp); 2265 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2266 struct drm_file *filp); 2267 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2268 struct drm_file *filp); 2269 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2270 struct drm_file *filp); 2271 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2272 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2273 struct drm_file *filp); 2274 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2275 struct drm_file *filp); 2276 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2277 2278 /* VRAM scratch page for HDP bug, default vram page */ 2279 struct r600_vram_scratch { 2280 struct radeon_bo *robj; 2281 volatile uint32_t *ptr; 2282 u64 gpu_addr; 2283 }; 2284 2285 /* 2286 * ACPI 2287 */ 2288 struct radeon_atif_notification_cfg { 2289 bool enabled; 2290 int command_code; 2291 }; 2292 2293 struct radeon_atif_notifications { 2294 bool display_switch; 2295 bool expansion_mode_change; 2296 bool thermal_state; 2297 bool forced_power_state; 2298 bool system_power_state; 2299 bool display_conf_change; 2300 bool px_gfx_switch; 2301 bool brightness_change; 2302 bool dgpu_display_event; 2303 }; 2304 2305 struct radeon_atif_functions { 2306 bool system_params; 2307 bool sbios_requests; 2308 bool select_active_disp; 2309 bool lid_state; 2310 bool get_tv_standard; 2311 bool set_tv_standard; 2312 bool get_panel_expansion_mode; 2313 bool set_panel_expansion_mode; 2314 bool temperature_change; 2315 bool graphics_device_types; 2316 }; 2317 2318 struct radeon_atif { 2319 struct radeon_atif_notifications notifications; 2320 struct radeon_atif_functions functions; 2321 struct radeon_atif_notification_cfg notification_cfg; 2322 struct radeon_encoder *encoder_for_bl; 2323 }; 2324 2325 struct radeon_atcs_functions { 2326 bool get_ext_state; 2327 bool pcie_perf_req; 2328 bool pcie_dev_rdy; 2329 bool pcie_bus_width; 2330 }; 2331 2332 struct radeon_atcs { 2333 struct radeon_atcs_functions functions; 2334 }; 2335 2336 /* 2337 * Core structure, functions and helpers. 2338 */ 2339 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2340 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2341 2342 struct radeon_device { 2343 struct device *dev; 2344 struct drm_device *ddev; 2345 struct pci_dev *pdev; 2346 #ifdef __alpha__ 2347 struct pci_controller *hose; 2348 #endif 2349 struct radeon_agp_head *agp; 2350 struct rw_semaphore exclusive_lock; 2351 /* ASIC */ 2352 union radeon_asic_config config; 2353 enum radeon_family family; 2354 unsigned long flags; 2355 int usec_timeout; 2356 enum radeon_pll_errata pll_errata; 2357 int num_gb_pipes; 2358 int num_z_pipes; 2359 int disp_priority; 2360 /* BIOS */ 2361 uint8_t *bios; 2362 bool is_atom_bios; 2363 uint16_t bios_header_start; 2364 struct radeon_bo *stolen_vga_memory; 2365 /* Register mmio */ 2366 resource_size_t rmmio_base; 2367 resource_size_t rmmio_size; 2368 /* protects concurrent MM_INDEX/DATA based register access */ 2369 spinlock_t mmio_idx_lock; 2370 /* protects concurrent SMC based register access */ 2371 spinlock_t smc_idx_lock; 2372 /* protects concurrent PLL register access */ 2373 spinlock_t pll_idx_lock; 2374 /* protects concurrent MC register access */ 2375 spinlock_t mc_idx_lock; 2376 /* protects concurrent PCIE register access */ 2377 spinlock_t pcie_idx_lock; 2378 /* protects concurrent PCIE_PORT register access */ 2379 spinlock_t pciep_idx_lock; 2380 /* protects concurrent PIF register access */ 2381 spinlock_t pif_idx_lock; 2382 /* protects concurrent CG register access */ 2383 spinlock_t cg_idx_lock; 2384 /* protects concurrent UVD register access */ 2385 spinlock_t uvd_idx_lock; 2386 /* protects concurrent RCU register access */ 2387 spinlock_t rcu_idx_lock; 2388 /* protects concurrent DIDT register access */ 2389 spinlock_t didt_idx_lock; 2390 /* protects concurrent ENDPOINT (audio) register access */ 2391 spinlock_t end_idx_lock; 2392 void __iomem *rmmio; 2393 radeon_rreg_t mc_rreg; 2394 radeon_wreg_t mc_wreg; 2395 radeon_rreg_t pll_rreg; 2396 radeon_wreg_t pll_wreg; 2397 uint32_t pcie_reg_mask; 2398 radeon_rreg_t pciep_rreg; 2399 radeon_wreg_t pciep_wreg; 2400 /* io port */ 2401 void __iomem *rio_mem; 2402 resource_size_t rio_mem_size; 2403 struct radeon_clock clock; 2404 struct radeon_mc mc; 2405 struct radeon_gart gart; 2406 struct radeon_mode_info mode_info; 2407 struct radeon_scratch scratch; 2408 struct radeon_doorbell doorbell; 2409 struct radeon_mman mman; 2410 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2411 wait_queue_head_t fence_queue; 2412 u64 fence_context; 2413 struct mutex ring_lock; 2414 struct radeon_ring ring[RADEON_NUM_RINGS]; 2415 bool ib_pool_ready; 2416 struct radeon_sa_manager ring_tmp_bo; 2417 struct radeon_irq irq; 2418 struct radeon_asic *asic; 2419 struct radeon_gem gem; 2420 struct radeon_pm pm; 2421 struct radeon_uvd uvd; 2422 struct radeon_vce vce; 2423 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2424 struct radeon_wb wb; 2425 struct radeon_dummy_page dummy_page; 2426 bool shutdown; 2427 bool need_swiotlb; 2428 bool accel_working; 2429 bool fastfb_working; /* IGP feature*/ 2430 bool needs_reset, in_reset; 2431 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2432 const struct firmware *me_fw; /* all family ME firmware */ 2433 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2434 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2435 const struct firmware *mc_fw; /* NI MC firmware */ 2436 const struct firmware *ce_fw; /* SI CE firmware */ 2437 const struct firmware *mec_fw; /* CIK MEC firmware */ 2438 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2439 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2440 const struct firmware *smc_fw; /* SMC firmware */ 2441 const struct firmware *uvd_fw; /* UVD firmware */ 2442 const struct firmware *vce_fw; /* VCE firmware */ 2443 bool new_fw; 2444 struct r600_vram_scratch vram_scratch; 2445 int msi_enabled; /* msi enabled */ 2446 struct r600_ih ih; /* r6/700 interrupt ring */ 2447 struct radeon_rlc rlc; 2448 struct radeon_mec mec; 2449 struct delayed_work hotplug_work; 2450 struct work_struct dp_work; 2451 struct work_struct audio_work; 2452 int num_crtc; /* number of crtcs */ 2453 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2454 bool has_uvd; 2455 bool has_vce; 2456 struct r600_audio audio; /* audio stuff */ 2457 struct notifier_block acpi_nb; 2458 /* only one userspace can use Hyperz features or CMASK at a time */ 2459 struct drm_file *hyperz_filp; 2460 struct drm_file *cmask_filp; 2461 /* i2c buses */ 2462 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2463 /* virtual memory */ 2464 struct radeon_vm_manager vm_manager; 2465 struct mutex gpu_clock_mutex; 2466 /* memory stats */ 2467 atomic64_t num_bytes_moved; 2468 atomic_t gpu_reset_counter; 2469 /* ACPI interface */ 2470 struct radeon_atif atif; 2471 struct radeon_atcs atcs; 2472 /* srbm instance registers */ 2473 struct mutex srbm_mutex; 2474 /* clock, powergating flags */ 2475 u32 cg_flags; 2476 u32 pg_flags; 2477 2478 struct dev_pm_domain vga_pm_domain; 2479 bool have_disp_power_ref; 2480 u32 px_quirk_flags; 2481 2482 /* tracking pinned memory */ 2483 u64 vram_pin_size; 2484 u64 gart_pin_size; 2485 }; 2486 2487 bool radeon_is_px(struct drm_device *dev); 2488 int radeon_device_init(struct radeon_device *rdev, 2489 struct drm_device *ddev, 2490 struct pci_dev *pdev, 2491 uint32_t flags); 2492 void radeon_device_fini(struct radeon_device *rdev); 2493 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2494 2495 #define RADEON_MIN_MMIO_SIZE 0x10000 2496 2497 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg); 2498 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2499 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2500 bool always_indirect) 2501 { 2502 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ 2503 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2504 return readl(((void __iomem *)rdev->rmmio) + reg); 2505 else 2506 return r100_mm_rreg_slow(rdev, reg); 2507 } 2508 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2509 bool always_indirect) 2510 { 2511 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2512 writel(v, ((void __iomem *)rdev->rmmio) + reg); 2513 else 2514 r100_mm_wreg_slow(rdev, reg, v); 2515 } 2516 2517 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2518 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2519 2520 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2521 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2522 2523 /* 2524 * Cast helper 2525 */ 2526 extern const struct dma_fence_ops radeon_fence_ops; 2527 2528 static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f) 2529 { 2530 struct radeon_fence *__f = container_of(f, struct radeon_fence, base); 2531 2532 if (__f->base.ops == &radeon_fence_ops) 2533 return __f; 2534 2535 return NULL; 2536 } 2537 2538 /* 2539 * Registers read & write functions. 2540 */ 2541 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 2542 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 2543 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 2544 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 2545 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2546 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2547 #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \ 2548 r100_mm_rreg(rdev, (reg), false)) 2549 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2550 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2551 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2552 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2553 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2554 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2555 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2556 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2557 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2558 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2559 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2560 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2561 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2562 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2563 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2564 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2565 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2566 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2567 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2568 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2569 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2570 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2571 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2572 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2573 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2574 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2575 #define WREG32_P(reg, val, mask) \ 2576 do { \ 2577 uint32_t tmp_ = RREG32(reg); \ 2578 tmp_ &= (mask); \ 2579 tmp_ |= ((val) & ~(mask)); \ 2580 WREG32(reg, tmp_); \ 2581 } while (0) 2582 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2583 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2584 #define WREG32_PLL_P(reg, val, mask) \ 2585 do { \ 2586 uint32_t tmp_ = RREG32_PLL(reg); \ 2587 tmp_ &= (mask); \ 2588 tmp_ |= ((val) & ~(mask)); \ 2589 WREG32_PLL(reg, tmp_); \ 2590 } while (0) 2591 #define WREG32_SMC_P(reg, val, mask) \ 2592 do { \ 2593 uint32_t tmp_ = RREG32_SMC(reg); \ 2594 tmp_ &= (mask); \ 2595 tmp_ |= ((val) & ~(mask)); \ 2596 WREG32_SMC(reg, tmp_); \ 2597 } while (0) 2598 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2599 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2600 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2601 2602 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2603 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2604 2605 /* 2606 * Indirect registers accessors. 2607 * They used to be inlined, but this increases code size by ~65 kbytes. 2608 * Since each performs a pair of MMIO ops 2609 * within a spin_lock_irqsave/spin_unlock_irqrestore region, 2610 * the cost of call+ret is almost negligible. MMIO and locking 2611 * costs several dozens of cycles each at best, call+ret is ~5 cycles. 2612 */ 2613 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); 2614 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2615 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg); 2616 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2617 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg); 2618 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2619 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg); 2620 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2621 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg); 2622 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2623 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg); 2624 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2625 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg); 2626 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2627 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg); 2628 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2629 2630 void r100_pll_errata_after_index(struct radeon_device *rdev); 2631 2632 2633 /* 2634 * ASICs helpers. 2635 */ 2636 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2637 (rdev->pdev->device == 0x5969)) 2638 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2639 (rdev->family == CHIP_RV200) || \ 2640 (rdev->family == CHIP_RS100) || \ 2641 (rdev->family == CHIP_RS200) || \ 2642 (rdev->family == CHIP_RV250) || \ 2643 (rdev->family == CHIP_RV280) || \ 2644 (rdev->family == CHIP_RS300)) 2645 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2646 (rdev->family == CHIP_RV350) || \ 2647 (rdev->family == CHIP_R350) || \ 2648 (rdev->family == CHIP_RV380) || \ 2649 (rdev->family == CHIP_R420) || \ 2650 (rdev->family == CHIP_R423) || \ 2651 (rdev->family == CHIP_RV410) || \ 2652 (rdev->family == CHIP_RS400) || \ 2653 (rdev->family == CHIP_RS480)) 2654 #define ASIC_IS_X2(rdev) ((rdev->pdev->device == 0x9441) || \ 2655 (rdev->pdev->device == 0x9443) || \ 2656 (rdev->pdev->device == 0x944B) || \ 2657 (rdev->pdev->device == 0x9506) || \ 2658 (rdev->pdev->device == 0x9509) || \ 2659 (rdev->pdev->device == 0x950F) || \ 2660 (rdev->pdev->device == 0x689C) || \ 2661 (rdev->pdev->device == 0x689D)) 2662 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2663 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2664 (rdev->family == CHIP_RS690) || \ 2665 (rdev->family == CHIP_RS740) || \ 2666 (rdev->family >= CHIP_R600)) 2667 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2668 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2669 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2670 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2671 (rdev->flags & RADEON_IS_IGP)) 2672 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2673 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2674 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2675 (rdev->flags & RADEON_IS_IGP)) 2676 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2677 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2678 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2679 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2680 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2681 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2682 (rdev->family == CHIP_MULLINS)) 2683 2684 #define ASIC_IS_LOMBOK(rdev) ((rdev->pdev->device == 0x6849) || \ 2685 (rdev->pdev->device == 0x6850) || \ 2686 (rdev->pdev->device == 0x6858) || \ 2687 (rdev->pdev->device == 0x6859) || \ 2688 (rdev->pdev->device == 0x6840) || \ 2689 (rdev->pdev->device == 0x6841) || \ 2690 (rdev->pdev->device == 0x6842) || \ 2691 (rdev->pdev->device == 0x6843)) 2692 2693 /* 2694 * BIOS helpers. 2695 */ 2696 #define RBIOS8(i) (rdev->bios[i]) 2697 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2698 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2699 2700 int radeon_combios_init(struct radeon_device *rdev); 2701 void radeon_combios_fini(struct radeon_device *rdev); 2702 int radeon_atombios_init(struct radeon_device *rdev); 2703 void radeon_atombios_fini(struct radeon_device *rdev); 2704 2705 2706 /* 2707 * RING helpers. 2708 */ 2709 2710 /** 2711 * radeon_ring_write - write a value to the ring 2712 * 2713 * @ring: radeon_ring structure holding ring information 2714 * @v: dword (dw) value to write 2715 * 2716 * Write a value to the requested ring buffer (all asics). 2717 */ 2718 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2719 { 2720 if (ring->count_dw <= 0) 2721 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2722 2723 ring->ring[ring->wptr++] = v; 2724 ring->wptr &= ring->ptr_mask; 2725 ring->count_dw--; 2726 ring->ring_free_dw--; 2727 } 2728 2729 /* 2730 * ASICs macro. 2731 */ 2732 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2733 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2734 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2735 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2736 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2737 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2738 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false) 2739 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2740 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f)) 2741 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e)) 2742 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2743 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2744 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2745 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2746 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2747 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2748 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2749 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2750 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2751 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2752 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2753 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2754 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr)) 2755 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2756 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2757 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2758 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2759 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2760 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2761 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2762 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2763 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2764 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2765 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2766 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2767 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) 2768 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) 2769 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) 2770 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2771 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2772 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2773 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2774 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2775 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2776 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2777 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2778 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2779 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2780 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2781 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2782 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2783 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2784 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2785 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2786 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2787 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2788 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2789 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2790 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2791 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2792 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2793 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2794 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2795 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2796 #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async)) 2797 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2798 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2799 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2800 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2801 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2802 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v)) 2803 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2804 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2805 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2806 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2807 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2808 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2809 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2810 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2811 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2812 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2813 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2814 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2815 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2816 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2817 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2818 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2819 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2820 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2821 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev)) 2822 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev)) 2823 2824 /* Common functions */ 2825 /* AGP */ 2826 extern int radeon_gpu_reset(struct radeon_device *rdev); 2827 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2828 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2829 extern void radeon_agp_disable(struct radeon_device *rdev); 2830 extern int radeon_modeset_init(struct radeon_device *rdev); 2831 extern void radeon_modeset_fini(struct radeon_device *rdev); 2832 extern bool radeon_card_posted(struct radeon_device *rdev); 2833 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2834 extern void radeon_update_display_priority(struct radeon_device *rdev); 2835 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2836 extern void radeon_scratch_init(struct radeon_device *rdev); 2837 extern void radeon_wb_fini(struct radeon_device *rdev); 2838 extern int radeon_wb_init(struct radeon_device *rdev); 2839 extern void radeon_wb_disable(struct radeon_device *rdev); 2840 extern void radeon_surface_init(struct radeon_device *rdev); 2841 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2842 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 2843 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 2844 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2845 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2846 extern int radeon_ttm_tt_set_userptr(struct radeon_device *rdev, 2847 struct ttm_tt *ttm, uint64_t addr, 2848 uint32_t flags); 2849 extern bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev, struct ttm_tt *ttm); 2850 extern bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev, struct ttm_tt *ttm); 2851 bool radeon_ttm_tt_is_bound(struct ttm_device *bdev, struct ttm_tt *ttm); 2852 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2853 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2854 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2855 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, 2856 bool fbcon, bool freeze); 2857 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2858 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2859 const u32 *registers, 2860 const u32 array_size); 2861 struct radeon_device *radeon_get_rdev(struct ttm_device *bdev); 2862 2863 /* KMS */ 2864 2865 u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc); 2866 int radeon_enable_vblank_kms(struct drm_crtc *crtc); 2867 void radeon_disable_vblank_kms(struct drm_crtc *crtc); 2868 2869 /* 2870 * vm 2871 */ 2872 int radeon_vm_manager_init(struct radeon_device *rdev); 2873 void radeon_vm_manager_fini(struct radeon_device *rdev); 2874 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2875 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2876 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, 2877 struct radeon_vm *vm, 2878 struct list_head *head); 2879 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2880 struct radeon_vm *vm, int ring); 2881 void radeon_vm_flush(struct radeon_device *rdev, 2882 struct radeon_vm *vm, 2883 int ring, struct radeon_fence *fence); 2884 void radeon_vm_fence(struct radeon_device *rdev, 2885 struct radeon_vm *vm, 2886 struct radeon_fence *fence); 2887 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2888 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2889 struct radeon_vm *vm); 2890 int radeon_vm_clear_freed(struct radeon_device *rdev, 2891 struct radeon_vm *vm); 2892 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2893 struct radeon_vm *vm); 2894 int radeon_vm_bo_update(struct radeon_device *rdev, 2895 struct radeon_bo_va *bo_va, 2896 struct ttm_resource *mem); 2897 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2898 struct radeon_bo *bo); 2899 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2900 struct radeon_bo *bo); 2901 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2902 struct radeon_vm *vm, 2903 struct radeon_bo *bo); 2904 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2905 struct radeon_bo_va *bo_va, 2906 uint64_t offset, 2907 uint32_t flags); 2908 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2909 struct radeon_bo_va *bo_va); 2910 2911 /* audio */ 2912 void r600_audio_update_hdmi(struct work_struct *work); 2913 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2914 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2915 void r600_audio_enable(struct radeon_device *rdev, 2916 struct r600_audio_pin *pin, 2917 u8 enable_mask); 2918 void dce6_audio_enable(struct radeon_device *rdev, 2919 struct r600_audio_pin *pin, 2920 u8 enable_mask); 2921 2922 /* 2923 * R600 vram scratch functions 2924 */ 2925 int r600_vram_scratch_init(struct radeon_device *rdev); 2926 void r600_vram_scratch_fini(struct radeon_device *rdev); 2927 2928 /* 2929 * r600 cs checking helper 2930 */ 2931 unsigned r600_mip_minify(unsigned size, unsigned level); 2932 bool r600_fmt_is_valid_color(u32 format); 2933 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2934 int r600_fmt_get_blocksize(u32 format); 2935 int r600_fmt_get_nblocksx(u32 format, u32 w); 2936 int r600_fmt_get_nblocksy(u32 format, u32 h); 2937 2938 /* 2939 * r600 functions used by radeon_encoder.c 2940 */ 2941 struct radeon_hdmi_acr { 2942 u32 clock; 2943 2944 int n_32khz; 2945 int cts_32khz; 2946 2947 int n_44_1khz; 2948 int cts_44_1khz; 2949 2950 int n_48khz; 2951 int cts_48khz; 2952 2953 }; 2954 2955 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2956 u32 tiling_pipe_num, 2957 u32 max_rb_num, 2958 u32 total_max_rb_num, 2959 u32 enabled_rb_mask); 2960 2961 /* 2962 * evergreen functions used by radeon_encoder.c 2963 */ 2964 2965 extern int ni_init_microcode(struct radeon_device *rdev); 2966 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2967 2968 /* radeon_acpi.c */ 2969 #if defined(CONFIG_ACPI) 2970 extern int radeon_acpi_init(struct radeon_device *rdev); 2971 extern void radeon_acpi_fini(struct radeon_device *rdev); 2972 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 2973 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 2974 u8 perf_req, bool advertise); 2975 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 2976 #else 2977 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 2978 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 2979 #endif 2980 2981 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 2982 struct radeon_cs_packet *pkt, 2983 unsigned idx); 2984 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 2985 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 2986 struct radeon_cs_packet *pkt); 2987 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 2988 struct radeon_bo_list **cs_reloc, 2989 int nomm); 2990 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 2991 uint32_t *vline_start_end, 2992 uint32_t *vline_status); 2993 2994 /* interrupt control register helpers */ 2995 void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev, 2996 u32 reg, u32 mask, 2997 bool enable, const char *name, 2998 unsigned n); 2999 3000 /* Audio component binding */ 3001 void radeon_audio_component_init(struct radeon_device *rdev); 3002 void radeon_audio_component_fini(struct radeon_device *rdev); 3003 3004 #include "radeon_object.h" 3005 3006 #endif 3007