1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 /* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45 /* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63 #include <linux/atomic.h> 64 #include <linux/wait.h> 65 #include <linux/list.h> 66 #include <linux/kref.h> 67 #include <linux/interval_tree.h> 68 #include <linux/hashtable.h> 69 #include <linux/dma-fence.h> 70 71 #ifdef CONFIG_MMU_NOTIFIER 72 #include <linux/mmu_notifier.h> 73 #endif 74 75 #include <drm/ttm/ttm_bo_api.h> 76 #include <drm/ttm/ttm_bo_driver.h> 77 #include <drm/ttm/ttm_placement.h> 78 #include <drm/ttm/ttm_execbuf_util.h> 79 80 #include <drm/drm_gem.h> 81 82 #include "radeon_family.h" 83 #include "radeon_mode.h" 84 #include "radeon_reg.h" 85 86 /* 87 * Modules parameters. 88 */ 89 extern int radeon_no_wb; 90 extern int radeon_modeset; 91 extern int radeon_dynclks; 92 extern int radeon_r4xx_atom; 93 extern int radeon_agpmode; 94 extern int radeon_vram_limit; 95 extern int radeon_gart_size; 96 extern int radeon_benchmarking; 97 extern int radeon_testing; 98 extern int radeon_connector_table; 99 extern int radeon_tv; 100 extern int radeon_audio; 101 extern int radeon_disp_priority; 102 extern int radeon_hw_i2c; 103 extern int radeon_pcie_gen2; 104 extern int radeon_msi; 105 extern int radeon_lockup_timeout; 106 extern int radeon_fastfb; 107 extern int radeon_dpm; 108 extern int radeon_aspm; 109 extern int radeon_runtime_pm; 110 extern int radeon_hard_reset; 111 extern int radeon_vm_size; 112 extern int radeon_vm_block_size; 113 extern int radeon_deep_color; 114 extern int radeon_use_pflipirq; 115 extern int radeon_bapm; 116 extern int radeon_backlight; 117 extern int radeon_auxch; 118 extern int radeon_mst; 119 extern int radeon_uvd; 120 extern int radeon_vce; 121 extern int radeon_si_support; 122 extern int radeon_cik_support; 123 124 /* 125 * Copy from radeon_drv.h so we don't have to include both and have conflicting 126 * symbol; 127 */ 128 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 129 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 130 #define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */ 131 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 132 #define RADEON_IB_POOL_SIZE 16 133 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 134 #define RADEONFB_CONN_LIMIT 4 135 #define RADEON_BIOS_NUM_SCRATCH 8 136 137 /* internal ring indices */ 138 /* r1xx+ has gfx CP ring */ 139 #define RADEON_RING_TYPE_GFX_INDEX 0 140 141 /* cayman has 2 compute CP rings */ 142 #define CAYMAN_RING_TYPE_CP1_INDEX 1 143 #define CAYMAN_RING_TYPE_CP2_INDEX 2 144 145 /* R600+ has an async dma ring */ 146 #define R600_RING_TYPE_DMA_INDEX 3 147 /* cayman add a second async dma ring */ 148 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 149 150 /* R600+ */ 151 #define R600_RING_TYPE_UVD_INDEX 5 152 153 /* TN+ */ 154 #define TN_RING_TYPE_VCE1_INDEX 6 155 #define TN_RING_TYPE_VCE2_INDEX 7 156 157 /* max number of rings */ 158 #define RADEON_NUM_RINGS 8 159 160 /* number of hw syncs before falling back on blocking */ 161 #define RADEON_NUM_SYNCS 4 162 163 /* hardcode those limit for now */ 164 #define RADEON_VA_IB_OFFSET (1 << 20) 165 #define RADEON_VA_RESERVED_SIZE (8 << 20) 166 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 167 168 /* hard reset data */ 169 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 170 171 /* reset flags */ 172 #define RADEON_RESET_GFX (1 << 0) 173 #define RADEON_RESET_COMPUTE (1 << 1) 174 #define RADEON_RESET_DMA (1 << 2) 175 #define RADEON_RESET_CP (1 << 3) 176 #define RADEON_RESET_GRBM (1 << 4) 177 #define RADEON_RESET_DMA1 (1 << 5) 178 #define RADEON_RESET_RLC (1 << 6) 179 #define RADEON_RESET_SEM (1 << 7) 180 #define RADEON_RESET_IH (1 << 8) 181 #define RADEON_RESET_VMC (1 << 9) 182 #define RADEON_RESET_MC (1 << 10) 183 #define RADEON_RESET_DISPLAY (1 << 11) 184 185 /* CG block flags */ 186 #define RADEON_CG_BLOCK_GFX (1 << 0) 187 #define RADEON_CG_BLOCK_MC (1 << 1) 188 #define RADEON_CG_BLOCK_SDMA (1 << 2) 189 #define RADEON_CG_BLOCK_UVD (1 << 3) 190 #define RADEON_CG_BLOCK_VCE (1 << 4) 191 #define RADEON_CG_BLOCK_HDP (1 << 5) 192 #define RADEON_CG_BLOCK_BIF (1 << 6) 193 194 /* CG flags */ 195 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 196 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 197 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 198 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 199 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 200 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 201 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 202 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 203 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 204 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 205 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 206 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 207 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 208 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 209 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 210 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 211 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 212 213 /* PG flags */ 214 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 215 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 216 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 217 #define RADEON_PG_SUPPORT_UVD (1 << 3) 218 #define RADEON_PG_SUPPORT_VCE (1 << 4) 219 #define RADEON_PG_SUPPORT_CP (1 << 5) 220 #define RADEON_PG_SUPPORT_GDS (1 << 6) 221 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 222 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 223 #define RADEON_PG_SUPPORT_ACP (1 << 9) 224 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 225 226 /* max cursor sizes (in pixels) */ 227 #define CURSOR_WIDTH 64 228 #define CURSOR_HEIGHT 64 229 230 #define CIK_CURSOR_WIDTH 128 231 #define CIK_CURSOR_HEIGHT 128 232 233 /* 234 * Errata workarounds. 235 */ 236 enum radeon_pll_errata { 237 CHIP_ERRATA_R300_CG = 0x00000001, 238 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 239 CHIP_ERRATA_PLL_DELAY = 0x00000004 240 }; 241 242 243 struct radeon_device; 244 245 246 /* 247 * BIOS. 248 */ 249 bool radeon_get_bios(struct radeon_device *rdev); 250 251 /* 252 * Dummy page 253 */ 254 struct radeon_dummy_page { 255 uint64_t entry; 256 struct page *page; 257 dma_addr_t addr; 258 }; 259 int radeon_dummy_page_init(struct radeon_device *rdev); 260 void radeon_dummy_page_fini(struct radeon_device *rdev); 261 262 263 /* 264 * Clocks 265 */ 266 struct radeon_clock { 267 struct radeon_pll p1pll; 268 struct radeon_pll p2pll; 269 struct radeon_pll dcpll; 270 struct radeon_pll spll; 271 struct radeon_pll mpll; 272 /* 10 Khz units */ 273 uint32_t default_mclk; 274 uint32_t default_sclk; 275 uint32_t default_dispclk; 276 uint32_t current_dispclk; 277 uint32_t dp_extclk; 278 uint32_t max_pixel_clock; 279 uint32_t vco_freq; 280 }; 281 282 /* 283 * Power management 284 */ 285 int radeon_pm_init(struct radeon_device *rdev); 286 int radeon_pm_late_init(struct radeon_device *rdev); 287 void radeon_pm_fini(struct radeon_device *rdev); 288 void radeon_pm_compute_clocks(struct radeon_device *rdev); 289 void radeon_pm_suspend(struct radeon_device *rdev); 290 void radeon_pm_resume(struct radeon_device *rdev); 291 void radeon_combios_get_power_modes(struct radeon_device *rdev); 292 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 293 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 294 u8 clock_type, 295 u32 clock, 296 bool strobe_mode, 297 struct atom_clock_dividers *dividers); 298 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 299 u32 clock, 300 bool strobe_mode, 301 struct atom_mpll_param *mpll_param); 302 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 303 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 304 u16 voltage_level, u8 voltage_type, 305 u32 *gpio_value, u32 *gpio_mask); 306 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 307 u32 eng_clock, u32 mem_clock); 308 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 309 u8 voltage_type, u16 *voltage_step); 310 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 311 u16 voltage_id, u16 *voltage); 312 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 313 u16 *voltage, 314 u16 leakage_idx); 315 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 316 u16 *leakage_id); 317 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 318 u16 *vddc, u16 *vddci, 319 u16 virtual_voltage_id, 320 u16 vbios_voltage_id); 321 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 322 u16 virtual_voltage_id, 323 u16 *voltage); 324 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 325 u8 voltage_type, 326 u16 nominal_voltage, 327 u16 *true_voltage); 328 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 329 u8 voltage_type, u16 *min_voltage); 330 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 331 u8 voltage_type, u16 *max_voltage); 332 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 333 u8 voltage_type, u8 voltage_mode, 334 struct atom_voltage_table *voltage_table); 335 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 336 u8 voltage_type, u8 voltage_mode); 337 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 338 u8 voltage_type, 339 u8 *svd_gpio_id, u8 *svc_gpio_id); 340 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 341 u32 mem_clock); 342 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 343 u32 mem_clock); 344 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 345 u8 module_index, 346 struct atom_mc_reg_table *reg_table); 347 int radeon_atom_get_memory_info(struct radeon_device *rdev, 348 u8 module_index, struct atom_memory_info *mem_info); 349 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 350 bool gddr5, u8 module_index, 351 struct atom_memory_clock_range_table *mclk_range_table); 352 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 353 u16 voltage_id, u16 *voltage); 354 void rs690_pm_info(struct radeon_device *rdev); 355 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 356 unsigned *bankh, unsigned *mtaspect, 357 unsigned *tile_split); 358 359 /* 360 * Fences. 361 */ 362 struct radeon_fence_driver { 363 struct radeon_device *rdev; 364 uint32_t scratch_reg; 365 uint64_t gpu_addr; 366 volatile uint32_t *cpu_addr; 367 /* sync_seq is protected by ring emission lock */ 368 uint64_t sync_seq[RADEON_NUM_RINGS]; 369 atomic64_t last_seq; 370 bool initialized, delayed_irq; 371 struct delayed_work lockup_work; 372 }; 373 374 struct radeon_fence { 375 struct dma_fence base; 376 377 struct radeon_device *rdev; 378 uint64_t seq; 379 /* RB, DMA, etc. */ 380 unsigned ring; 381 bool is_vm_update; 382 383 wait_queue_entry_t fence_wake; 384 }; 385 386 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 387 int radeon_fence_driver_init(struct radeon_device *rdev); 388 void radeon_fence_driver_fini(struct radeon_device *rdev); 389 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 390 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 391 void radeon_fence_process(struct radeon_device *rdev, int ring); 392 bool radeon_fence_signaled(struct radeon_fence *fence); 393 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout); 394 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 395 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 396 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 397 int radeon_fence_wait_any(struct radeon_device *rdev, 398 struct radeon_fence **fences, 399 bool intr); 400 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 401 void radeon_fence_unref(struct radeon_fence **fence); 402 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 403 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 404 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 405 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 406 struct radeon_fence *b) 407 { 408 if (!a) { 409 return b; 410 } 411 412 if (!b) { 413 return a; 414 } 415 416 BUG_ON(a->ring != b->ring); 417 418 if (a->seq > b->seq) { 419 return a; 420 } else { 421 return b; 422 } 423 } 424 425 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 426 struct radeon_fence *b) 427 { 428 if (!a) { 429 return false; 430 } 431 432 if (!b) { 433 return true; 434 } 435 436 BUG_ON(a->ring != b->ring); 437 438 return a->seq < b->seq; 439 } 440 441 /* 442 * Tiling registers 443 */ 444 struct radeon_surface_reg { 445 struct radeon_bo *bo; 446 }; 447 448 #define RADEON_GEM_MAX_SURFACES 8 449 450 /* 451 * TTM. 452 */ 453 struct radeon_mman { 454 struct ttm_bo_device bdev; 455 bool initialized; 456 457 #if defined(CONFIG_DEBUG_FS) 458 struct dentry *vram; 459 struct dentry *gtt; 460 #endif 461 }; 462 463 struct radeon_bo_list { 464 struct radeon_bo *robj; 465 struct ttm_validate_buffer tv; 466 uint64_t gpu_offset; 467 unsigned preferred_domains; 468 unsigned allowed_domains; 469 uint32_t tiling_flags; 470 }; 471 472 /* bo virtual address in a specific vm */ 473 struct radeon_bo_va { 474 /* protected by bo being reserved */ 475 struct list_head bo_list; 476 uint32_t flags; 477 struct radeon_fence *last_pt_update; 478 unsigned ref_count; 479 480 /* protected by vm mutex */ 481 struct interval_tree_node it; 482 struct list_head vm_status; 483 484 /* constant after initialization */ 485 struct radeon_vm *vm; 486 struct radeon_bo *bo; 487 }; 488 489 struct radeon_bo { 490 /* Protected by gem.mutex */ 491 struct list_head list; 492 /* Protected by tbo.reserved */ 493 u32 initial_domain; 494 struct ttm_place placements[4]; 495 struct ttm_placement placement; 496 struct ttm_buffer_object tbo; 497 struct ttm_bo_kmap_obj kmap; 498 u32 flags; 499 void *kptr; 500 u32 tiling_flags; 501 u32 pitch; 502 int surface_reg; 503 unsigned prime_shared_count; 504 /* list of all virtual address to which this bo 505 * is associated to 506 */ 507 struct list_head va; 508 /* Constant after initialization */ 509 struct radeon_device *rdev; 510 511 pid_t pid; 512 513 #ifdef CONFIG_MMU_NOTIFIER 514 struct mmu_interval_notifier notifier; 515 #endif 516 }; 517 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, tbo.base) 518 519 int radeon_gem_debugfs_init(struct radeon_device *rdev); 520 521 /* sub-allocation manager, it has to be protected by another lock. 522 * By conception this is an helper for other part of the driver 523 * like the indirect buffer or semaphore, which both have their 524 * locking. 525 * 526 * Principe is simple, we keep a list of sub allocation in offset 527 * order (first entry has offset == 0, last entry has the highest 528 * offset). 529 * 530 * When allocating new object we first check if there is room at 531 * the end total_size - (last_object_offset + last_object_size) >= 532 * alloc_size. If so we allocate new object there. 533 * 534 * When there is not enough room at the end, we start waiting for 535 * each sub object until we reach object_offset+object_size >= 536 * alloc_size, this object then become the sub object we return. 537 * 538 * Alignment can't be bigger than page size. 539 * 540 * Hole are not considered for allocation to keep things simple. 541 * Assumption is that there won't be hole (all object on same 542 * alignment). 543 */ 544 struct radeon_sa_manager { 545 wait_queue_head_t wq; 546 struct radeon_bo *bo; 547 struct list_head *hole; 548 struct list_head flist[RADEON_NUM_RINGS]; 549 struct list_head olist; 550 unsigned size; 551 uint64_t gpu_addr; 552 void *cpu_ptr; 553 uint32_t domain; 554 uint32_t align; 555 }; 556 557 struct radeon_sa_bo; 558 559 /* sub-allocation buffer */ 560 struct radeon_sa_bo { 561 struct list_head olist; 562 struct list_head flist; 563 struct radeon_sa_manager *manager; 564 unsigned soffset; 565 unsigned eoffset; 566 struct radeon_fence *fence; 567 }; 568 569 /* 570 * GEM objects. 571 */ 572 struct radeon_gem { 573 struct mutex mutex; 574 struct list_head objects; 575 }; 576 577 int radeon_gem_init(struct radeon_device *rdev); 578 void radeon_gem_fini(struct radeon_device *rdev); 579 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 580 int alignment, int initial_domain, 581 u32 flags, bool kernel, 582 struct drm_gem_object **obj); 583 584 int radeon_mode_dumb_create(struct drm_file *file_priv, 585 struct drm_device *dev, 586 struct drm_mode_create_dumb *args); 587 int radeon_mode_dumb_mmap(struct drm_file *filp, 588 struct drm_device *dev, 589 uint32_t handle, uint64_t *offset_p); 590 591 /* 592 * Semaphores. 593 */ 594 struct radeon_semaphore { 595 struct radeon_sa_bo *sa_bo; 596 signed waiters; 597 uint64_t gpu_addr; 598 }; 599 600 int radeon_semaphore_create(struct radeon_device *rdev, 601 struct radeon_semaphore **semaphore); 602 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 603 struct radeon_semaphore *semaphore); 604 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 605 struct radeon_semaphore *semaphore); 606 void radeon_semaphore_free(struct radeon_device *rdev, 607 struct radeon_semaphore **semaphore, 608 struct radeon_fence *fence); 609 610 /* 611 * Synchronization 612 */ 613 struct radeon_sync { 614 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS]; 615 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 616 struct radeon_fence *last_vm_update; 617 }; 618 619 void radeon_sync_create(struct radeon_sync *sync); 620 void radeon_sync_fence(struct radeon_sync *sync, 621 struct radeon_fence *fence); 622 int radeon_sync_resv(struct radeon_device *rdev, 623 struct radeon_sync *sync, 624 struct dma_resv *resv, 625 bool shared); 626 int radeon_sync_rings(struct radeon_device *rdev, 627 struct radeon_sync *sync, 628 int waiting_ring); 629 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync, 630 struct radeon_fence *fence); 631 632 /* 633 * GART structures, functions & helpers 634 */ 635 struct radeon_mc; 636 637 #define RADEON_GPU_PAGE_SIZE 4096 638 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 639 #define RADEON_GPU_PAGE_SHIFT 12 640 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 641 642 #define RADEON_GART_PAGE_DUMMY 0 643 #define RADEON_GART_PAGE_VALID (1 << 0) 644 #define RADEON_GART_PAGE_READ (1 << 1) 645 #define RADEON_GART_PAGE_WRITE (1 << 2) 646 #define RADEON_GART_PAGE_SNOOP (1 << 3) 647 648 struct radeon_gart { 649 dma_addr_t table_addr; 650 struct radeon_bo *robj; 651 void *ptr; 652 unsigned num_gpu_pages; 653 unsigned num_cpu_pages; 654 unsigned table_size; 655 struct page **pages; 656 uint64_t *pages_entry; 657 bool ready; 658 }; 659 660 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 661 void radeon_gart_table_ram_free(struct radeon_device *rdev); 662 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 663 void radeon_gart_table_vram_free(struct radeon_device *rdev); 664 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 665 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 666 int radeon_gart_init(struct radeon_device *rdev); 667 void radeon_gart_fini(struct radeon_device *rdev); 668 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 669 int pages); 670 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 671 int pages, struct page **pagelist, 672 dma_addr_t *dma_addr, uint32_t flags); 673 674 675 /* 676 * GPU MC structures, functions & helpers 677 */ 678 struct radeon_mc { 679 resource_size_t aper_size; 680 resource_size_t aper_base; 681 resource_size_t agp_base; 682 /* for some chips with <= 32MB we need to lie 683 * about vram size near mc fb location */ 684 u64 mc_vram_size; 685 u64 visible_vram_size; 686 u64 gtt_size; 687 u64 gtt_start; 688 u64 gtt_end; 689 u64 vram_start; 690 u64 vram_end; 691 unsigned vram_width; 692 u64 real_vram_size; 693 int vram_mtrr; 694 bool vram_is_ddr; 695 bool igp_sideport_enabled; 696 u64 gtt_base_align; 697 u64 mc_mask; 698 }; 699 700 bool radeon_combios_sideport_present(struct radeon_device *rdev); 701 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 702 703 /* 704 * GPU scratch registers structures, functions & helpers 705 */ 706 struct radeon_scratch { 707 unsigned num_reg; 708 uint32_t reg_base; 709 bool free[32]; 710 uint32_t reg[32]; 711 }; 712 713 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 714 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 715 716 /* 717 * GPU doorbell structures, functions & helpers 718 */ 719 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 720 721 struct radeon_doorbell { 722 /* doorbell mmio */ 723 resource_size_t base; 724 resource_size_t size; 725 u32 __iomem *ptr; 726 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 727 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS); 728 }; 729 730 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 731 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 732 733 /* 734 * IRQS. 735 */ 736 737 struct radeon_flip_work { 738 struct work_struct flip_work; 739 struct work_struct unpin_work; 740 struct radeon_device *rdev; 741 int crtc_id; 742 u32 target_vblank; 743 uint64_t base; 744 struct drm_pending_vblank_event *event; 745 struct radeon_bo *old_rbo; 746 struct dma_fence *fence; 747 bool async; 748 }; 749 750 struct r500_irq_stat_regs { 751 u32 disp_int; 752 u32 hdmi0_status; 753 }; 754 755 struct r600_irq_stat_regs { 756 u32 disp_int; 757 u32 disp_int_cont; 758 u32 disp_int_cont2; 759 u32 d1grph_int; 760 u32 d2grph_int; 761 u32 hdmi0_status; 762 u32 hdmi1_status; 763 }; 764 765 struct evergreen_irq_stat_regs { 766 u32 disp_int[6]; 767 u32 grph_int[6]; 768 u32 afmt_status[6]; 769 }; 770 771 struct cik_irq_stat_regs { 772 u32 disp_int; 773 u32 disp_int_cont; 774 u32 disp_int_cont2; 775 u32 disp_int_cont3; 776 u32 disp_int_cont4; 777 u32 disp_int_cont5; 778 u32 disp_int_cont6; 779 u32 d1grph_int; 780 u32 d2grph_int; 781 u32 d3grph_int; 782 u32 d4grph_int; 783 u32 d5grph_int; 784 u32 d6grph_int; 785 }; 786 787 union radeon_irq_stat_regs { 788 struct r500_irq_stat_regs r500; 789 struct r600_irq_stat_regs r600; 790 struct evergreen_irq_stat_regs evergreen; 791 struct cik_irq_stat_regs cik; 792 }; 793 794 struct radeon_irq { 795 bool installed; 796 spinlock_t lock; 797 atomic_t ring_int[RADEON_NUM_RINGS]; 798 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 799 atomic_t pflip[RADEON_MAX_CRTCS]; 800 wait_queue_head_t vblank_queue; 801 bool hpd[RADEON_MAX_HPD_PINS]; 802 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 803 union radeon_irq_stat_regs stat_regs; 804 bool dpm_thermal; 805 }; 806 807 int radeon_irq_kms_init(struct radeon_device *rdev); 808 void radeon_irq_kms_fini(struct radeon_device *rdev); 809 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 810 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); 811 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 812 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 813 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 814 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 815 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 816 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 817 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 818 819 /* 820 * CP & rings. 821 */ 822 823 struct radeon_ib { 824 struct radeon_sa_bo *sa_bo; 825 uint32_t length_dw; 826 uint64_t gpu_addr; 827 uint32_t *ptr; 828 int ring; 829 struct radeon_fence *fence; 830 struct radeon_vm *vm; 831 bool is_const_ib; 832 struct radeon_sync sync; 833 }; 834 835 struct radeon_ring { 836 struct radeon_bo *ring_obj; 837 volatile uint32_t *ring; 838 unsigned rptr_offs; 839 unsigned rptr_save_reg; 840 u64 next_rptr_gpu_addr; 841 volatile u32 *next_rptr_cpu_addr; 842 unsigned wptr; 843 unsigned wptr_old; 844 unsigned ring_size; 845 unsigned ring_free_dw; 846 int count_dw; 847 atomic_t last_rptr; 848 atomic64_t last_activity; 849 uint64_t gpu_addr; 850 uint32_t align_mask; 851 uint32_t ptr_mask; 852 bool ready; 853 u32 nop; 854 u32 idx; 855 u64 last_semaphore_signal_addr; 856 u64 last_semaphore_wait_addr; 857 /* for CIK queues */ 858 u32 me; 859 u32 pipe; 860 u32 queue; 861 struct radeon_bo *mqd_obj; 862 u32 doorbell_index; 863 unsigned wptr_offs; 864 }; 865 866 struct radeon_mec { 867 struct radeon_bo *hpd_eop_obj; 868 u64 hpd_eop_gpu_addr; 869 u32 num_pipe; 870 u32 num_mec; 871 u32 num_queue; 872 }; 873 874 /* 875 * VM 876 */ 877 878 /* maximum number of VMIDs */ 879 #define RADEON_NUM_VM 16 880 881 /* number of entries in page table */ 882 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 883 884 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 885 #define RADEON_VM_PTB_ALIGN_SIZE 32768 886 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 887 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 888 889 #define R600_PTE_VALID (1 << 0) 890 #define R600_PTE_SYSTEM (1 << 1) 891 #define R600_PTE_SNOOPED (1 << 2) 892 #define R600_PTE_READABLE (1 << 5) 893 #define R600_PTE_WRITEABLE (1 << 6) 894 895 /* PTE (Page Table Entry) fragment field for different page sizes */ 896 #define R600_PTE_FRAG_4KB (0 << 7) 897 #define R600_PTE_FRAG_64KB (4 << 7) 898 #define R600_PTE_FRAG_256KB (6 << 7) 899 900 /* flags needed to be set so we can copy directly from the GART table */ 901 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 902 R600_PTE_SYSTEM | R600_PTE_VALID ) 903 904 struct radeon_vm_pt { 905 struct radeon_bo *bo; 906 uint64_t addr; 907 }; 908 909 struct radeon_vm_id { 910 unsigned id; 911 uint64_t pd_gpu_addr; 912 /* last flushed PD/PT update */ 913 struct radeon_fence *flushed_updates; 914 /* last use of vmid */ 915 struct radeon_fence *last_id_use; 916 }; 917 918 struct radeon_vm { 919 struct mutex mutex; 920 921 struct rb_root_cached va; 922 923 /* protecting invalidated and freed */ 924 spinlock_t status_lock; 925 926 /* BOs moved, but not yet updated in the PT */ 927 struct list_head invalidated; 928 929 /* BOs freed, but not yet updated in the PT */ 930 struct list_head freed; 931 932 /* BOs cleared in the PT */ 933 struct list_head cleared; 934 935 /* contains the page directory */ 936 struct radeon_bo *page_directory; 937 unsigned max_pde_used; 938 939 /* array of page tables, one for each page directory entry */ 940 struct radeon_vm_pt *page_tables; 941 942 struct radeon_bo_va *ib_bo_va; 943 944 /* for id and flush management per ring */ 945 struct radeon_vm_id ids[RADEON_NUM_RINGS]; 946 }; 947 948 struct radeon_vm_manager { 949 struct radeon_fence *active[RADEON_NUM_VM]; 950 uint32_t max_pfn; 951 /* number of VMIDs */ 952 unsigned nvm; 953 /* vram base address for page table entry */ 954 u64 vram_base_offset; 955 /* is vm enabled? */ 956 bool enabled; 957 /* for hw to save the PD addr on suspend/resume */ 958 uint32_t saved_table_addr[RADEON_NUM_VM]; 959 }; 960 961 /* 962 * file private structure 963 */ 964 struct radeon_fpriv { 965 struct radeon_vm vm; 966 }; 967 968 /* 969 * R6xx+ IH ring 970 */ 971 struct r600_ih { 972 struct radeon_bo *ring_obj; 973 volatile uint32_t *ring; 974 unsigned rptr; 975 unsigned ring_size; 976 uint64_t gpu_addr; 977 uint32_t ptr_mask; 978 atomic_t lock; 979 bool enabled; 980 }; 981 982 /* 983 * RLC stuff 984 */ 985 #include "clearstate_defs.h" 986 987 struct radeon_rlc { 988 /* for power gating */ 989 struct radeon_bo *save_restore_obj; 990 uint64_t save_restore_gpu_addr; 991 volatile uint32_t *sr_ptr; 992 const u32 *reg_list; 993 u32 reg_list_size; 994 /* for clear state */ 995 struct radeon_bo *clear_state_obj; 996 uint64_t clear_state_gpu_addr; 997 volatile uint32_t *cs_ptr; 998 const struct cs_section_def *cs_data; 999 u32 clear_state_size; 1000 /* for cp tables */ 1001 struct radeon_bo *cp_table_obj; 1002 uint64_t cp_table_gpu_addr; 1003 volatile uint32_t *cp_table_ptr; 1004 u32 cp_table_size; 1005 }; 1006 1007 int radeon_ib_get(struct radeon_device *rdev, int ring, 1008 struct radeon_ib *ib, struct radeon_vm *vm, 1009 unsigned size); 1010 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 1011 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 1012 struct radeon_ib *const_ib, bool hdp_flush); 1013 int radeon_ib_pool_init(struct radeon_device *rdev); 1014 void radeon_ib_pool_fini(struct radeon_device *rdev); 1015 int radeon_ib_ring_tests(struct radeon_device *rdev); 1016 /* Ring access between begin & end cannot sleep */ 1017 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 1018 struct radeon_ring *ring); 1019 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 1020 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1021 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1022 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1023 bool hdp_flush); 1024 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1025 bool hdp_flush); 1026 void radeon_ring_undo(struct radeon_ring *ring); 1027 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 1028 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 1029 void radeon_ring_lockup_update(struct radeon_device *rdev, 1030 struct radeon_ring *ring); 1031 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1032 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1033 uint32_t **data); 1034 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1035 unsigned size, uint32_t *data); 1036 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1037 unsigned rptr_offs, u32 nop); 1038 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1039 1040 1041 /* r600 async dma */ 1042 void r600_dma_stop(struct radeon_device *rdev); 1043 int r600_dma_resume(struct radeon_device *rdev); 1044 void r600_dma_fini(struct radeon_device *rdev); 1045 1046 void cayman_dma_stop(struct radeon_device *rdev); 1047 int cayman_dma_resume(struct radeon_device *rdev); 1048 void cayman_dma_fini(struct radeon_device *rdev); 1049 1050 /* 1051 * CS. 1052 */ 1053 struct radeon_cs_chunk { 1054 uint32_t length_dw; 1055 uint32_t *kdata; 1056 void __user *user_ptr; 1057 }; 1058 1059 struct radeon_cs_parser { 1060 struct device *dev; 1061 struct radeon_device *rdev; 1062 struct drm_file *filp; 1063 /* chunks */ 1064 unsigned nchunks; 1065 struct radeon_cs_chunk *chunks; 1066 uint64_t *chunks_array; 1067 /* IB */ 1068 unsigned idx; 1069 /* relocations */ 1070 unsigned nrelocs; 1071 struct radeon_bo_list *relocs; 1072 struct radeon_bo_list *vm_bos; 1073 struct list_head validated; 1074 unsigned dma_reloc_idx; 1075 /* indices of various chunks */ 1076 struct radeon_cs_chunk *chunk_ib; 1077 struct radeon_cs_chunk *chunk_relocs; 1078 struct radeon_cs_chunk *chunk_flags; 1079 struct radeon_cs_chunk *chunk_const_ib; 1080 struct radeon_ib ib; 1081 struct radeon_ib const_ib; 1082 void *track; 1083 unsigned family; 1084 int parser_error; 1085 u32 cs_flags; 1086 u32 ring; 1087 s32 priority; 1088 struct ww_acquire_ctx ticket; 1089 }; 1090 1091 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1092 { 1093 struct radeon_cs_chunk *ibc = p->chunk_ib; 1094 1095 if (ibc->kdata) 1096 return ibc->kdata[idx]; 1097 return p->ib.ptr[idx]; 1098 } 1099 1100 1101 struct radeon_cs_packet { 1102 unsigned idx; 1103 unsigned type; 1104 unsigned reg; 1105 unsigned opcode; 1106 int count; 1107 unsigned one_reg_wr; 1108 }; 1109 1110 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1111 struct radeon_cs_packet *pkt, 1112 unsigned idx, unsigned reg); 1113 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1114 struct radeon_cs_packet *pkt); 1115 1116 1117 /* 1118 * AGP 1119 */ 1120 int radeon_agp_init(struct radeon_device *rdev); 1121 void radeon_agp_resume(struct radeon_device *rdev); 1122 void radeon_agp_suspend(struct radeon_device *rdev); 1123 void radeon_agp_fini(struct radeon_device *rdev); 1124 1125 1126 /* 1127 * Writeback 1128 */ 1129 struct radeon_wb { 1130 struct radeon_bo *wb_obj; 1131 volatile uint32_t *wb; 1132 uint64_t gpu_addr; 1133 bool enabled; 1134 bool use_event; 1135 }; 1136 1137 #define RADEON_WB_SCRATCH_OFFSET 0 1138 #define RADEON_WB_RING0_NEXT_RPTR 256 1139 #define RADEON_WB_CP_RPTR_OFFSET 1024 1140 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1141 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1142 #define R600_WB_DMA_RPTR_OFFSET 1792 1143 #define R600_WB_IH_WPTR_OFFSET 2048 1144 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1145 #define R600_WB_EVENT_OFFSET 3072 1146 #define CIK_WB_CP1_WPTR_OFFSET 3328 1147 #define CIK_WB_CP2_WPTR_OFFSET 3584 1148 #define R600_WB_DMA_RING_TEST_OFFSET 3588 1149 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 1150 1151 /** 1152 * struct radeon_pm - power management datas 1153 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1154 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1155 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1156 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1157 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1158 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1159 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1160 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1161 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1162 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1163 * @needed_bandwidth: current bandwidth needs 1164 * 1165 * It keeps track of various data needed to take powermanagement decision. 1166 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1167 * Equation between gpu/memory clock and available bandwidth is hw dependent 1168 * (type of memory, bus size, efficiency, ...) 1169 */ 1170 1171 enum radeon_pm_method { 1172 PM_METHOD_PROFILE, 1173 PM_METHOD_DYNPM, 1174 PM_METHOD_DPM, 1175 }; 1176 1177 enum radeon_dynpm_state { 1178 DYNPM_STATE_DISABLED, 1179 DYNPM_STATE_MINIMUM, 1180 DYNPM_STATE_PAUSED, 1181 DYNPM_STATE_ACTIVE, 1182 DYNPM_STATE_SUSPENDED, 1183 }; 1184 enum radeon_dynpm_action { 1185 DYNPM_ACTION_NONE, 1186 DYNPM_ACTION_MINIMUM, 1187 DYNPM_ACTION_DOWNCLOCK, 1188 DYNPM_ACTION_UPCLOCK, 1189 DYNPM_ACTION_DEFAULT 1190 }; 1191 1192 enum radeon_voltage_type { 1193 VOLTAGE_NONE = 0, 1194 VOLTAGE_GPIO, 1195 VOLTAGE_VDDC, 1196 VOLTAGE_SW 1197 }; 1198 1199 enum radeon_pm_state_type { 1200 /* not used for dpm */ 1201 POWER_STATE_TYPE_DEFAULT, 1202 POWER_STATE_TYPE_POWERSAVE, 1203 /* user selectable states */ 1204 POWER_STATE_TYPE_BATTERY, 1205 POWER_STATE_TYPE_BALANCED, 1206 POWER_STATE_TYPE_PERFORMANCE, 1207 /* internal states */ 1208 POWER_STATE_TYPE_INTERNAL_UVD, 1209 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1210 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1211 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1212 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1213 POWER_STATE_TYPE_INTERNAL_BOOT, 1214 POWER_STATE_TYPE_INTERNAL_THERMAL, 1215 POWER_STATE_TYPE_INTERNAL_ACPI, 1216 POWER_STATE_TYPE_INTERNAL_ULV, 1217 POWER_STATE_TYPE_INTERNAL_3DPERF, 1218 }; 1219 1220 enum radeon_pm_profile_type { 1221 PM_PROFILE_DEFAULT, 1222 PM_PROFILE_AUTO, 1223 PM_PROFILE_LOW, 1224 PM_PROFILE_MID, 1225 PM_PROFILE_HIGH, 1226 }; 1227 1228 #define PM_PROFILE_DEFAULT_IDX 0 1229 #define PM_PROFILE_LOW_SH_IDX 1 1230 #define PM_PROFILE_MID_SH_IDX 2 1231 #define PM_PROFILE_HIGH_SH_IDX 3 1232 #define PM_PROFILE_LOW_MH_IDX 4 1233 #define PM_PROFILE_MID_MH_IDX 5 1234 #define PM_PROFILE_HIGH_MH_IDX 6 1235 #define PM_PROFILE_MAX 7 1236 1237 struct radeon_pm_profile { 1238 int dpms_off_ps_idx; 1239 int dpms_on_ps_idx; 1240 int dpms_off_cm_idx; 1241 int dpms_on_cm_idx; 1242 }; 1243 1244 enum radeon_int_thermal_type { 1245 THERMAL_TYPE_NONE, 1246 THERMAL_TYPE_EXTERNAL, 1247 THERMAL_TYPE_EXTERNAL_GPIO, 1248 THERMAL_TYPE_RV6XX, 1249 THERMAL_TYPE_RV770, 1250 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1251 THERMAL_TYPE_EVERGREEN, 1252 THERMAL_TYPE_SUMO, 1253 THERMAL_TYPE_NI, 1254 THERMAL_TYPE_SI, 1255 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1256 THERMAL_TYPE_CI, 1257 THERMAL_TYPE_KV, 1258 }; 1259 1260 struct radeon_voltage { 1261 enum radeon_voltage_type type; 1262 /* gpio voltage */ 1263 struct radeon_gpio_rec gpio; 1264 u32 delay; /* delay in usec from voltage drop to sclk change */ 1265 bool active_high; /* voltage drop is active when bit is high */ 1266 /* VDDC voltage */ 1267 u8 vddc_id; /* index into vddc voltage table */ 1268 u8 vddci_id; /* index into vddci voltage table */ 1269 bool vddci_enabled; 1270 /* r6xx+ sw */ 1271 u16 voltage; 1272 /* evergreen+ vddci */ 1273 u16 vddci; 1274 }; 1275 1276 /* clock mode flags */ 1277 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1278 1279 struct radeon_pm_clock_info { 1280 /* memory clock */ 1281 u32 mclk; 1282 /* engine clock */ 1283 u32 sclk; 1284 /* voltage info */ 1285 struct radeon_voltage voltage; 1286 /* standardized clock flags */ 1287 u32 flags; 1288 }; 1289 1290 /* state flags */ 1291 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1292 1293 struct radeon_power_state { 1294 enum radeon_pm_state_type type; 1295 struct radeon_pm_clock_info *clock_info; 1296 /* number of valid clock modes in this power state */ 1297 int num_clock_modes; 1298 struct radeon_pm_clock_info *default_clock_mode; 1299 /* standardized state flags */ 1300 u32 flags; 1301 u32 misc; /* vbios specific flags */ 1302 u32 misc2; /* vbios specific flags */ 1303 int pcie_lanes; /* pcie lanes */ 1304 }; 1305 1306 /* 1307 * Some modes are overclocked by very low value, accept them 1308 */ 1309 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1310 1311 enum radeon_dpm_auto_throttle_src { 1312 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1313 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1314 }; 1315 1316 enum radeon_dpm_event_src { 1317 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1318 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1319 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1320 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1321 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1322 }; 1323 1324 #define RADEON_MAX_VCE_LEVELS 6 1325 1326 enum radeon_vce_level { 1327 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1328 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1329 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1330 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1331 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1332 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1333 }; 1334 1335 struct radeon_ps { 1336 u32 caps; /* vbios flags */ 1337 u32 class; /* vbios flags */ 1338 u32 class2; /* vbios flags */ 1339 /* UVD clocks */ 1340 u32 vclk; 1341 u32 dclk; 1342 /* VCE clocks */ 1343 u32 evclk; 1344 u32 ecclk; 1345 bool vce_active; 1346 enum radeon_vce_level vce_level; 1347 /* asic priv */ 1348 void *ps_priv; 1349 }; 1350 1351 struct radeon_dpm_thermal { 1352 /* thermal interrupt work */ 1353 struct work_struct work; 1354 /* low temperature threshold */ 1355 int min_temp; 1356 /* high temperature threshold */ 1357 int max_temp; 1358 /* was interrupt low to high or high to low */ 1359 bool high_to_low; 1360 }; 1361 1362 enum radeon_clk_action 1363 { 1364 RADEON_SCLK_UP = 1, 1365 RADEON_SCLK_DOWN 1366 }; 1367 1368 struct radeon_blacklist_clocks 1369 { 1370 u32 sclk; 1371 u32 mclk; 1372 enum radeon_clk_action action; 1373 }; 1374 1375 struct radeon_clock_and_voltage_limits { 1376 u32 sclk; 1377 u32 mclk; 1378 u16 vddc; 1379 u16 vddci; 1380 }; 1381 1382 struct radeon_clock_array { 1383 u32 count; 1384 u32 *values; 1385 }; 1386 1387 struct radeon_clock_voltage_dependency_entry { 1388 u32 clk; 1389 u16 v; 1390 }; 1391 1392 struct radeon_clock_voltage_dependency_table { 1393 u32 count; 1394 struct radeon_clock_voltage_dependency_entry *entries; 1395 }; 1396 1397 union radeon_cac_leakage_entry { 1398 struct { 1399 u16 vddc; 1400 u32 leakage; 1401 }; 1402 struct { 1403 u16 vddc1; 1404 u16 vddc2; 1405 u16 vddc3; 1406 }; 1407 }; 1408 1409 struct radeon_cac_leakage_table { 1410 u32 count; 1411 union radeon_cac_leakage_entry *entries; 1412 }; 1413 1414 struct radeon_phase_shedding_limits_entry { 1415 u16 voltage; 1416 u32 sclk; 1417 u32 mclk; 1418 }; 1419 1420 struct radeon_phase_shedding_limits_table { 1421 u32 count; 1422 struct radeon_phase_shedding_limits_entry *entries; 1423 }; 1424 1425 struct radeon_uvd_clock_voltage_dependency_entry { 1426 u32 vclk; 1427 u32 dclk; 1428 u16 v; 1429 }; 1430 1431 struct radeon_uvd_clock_voltage_dependency_table { 1432 u8 count; 1433 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1434 }; 1435 1436 struct radeon_vce_clock_voltage_dependency_entry { 1437 u32 ecclk; 1438 u32 evclk; 1439 u16 v; 1440 }; 1441 1442 struct radeon_vce_clock_voltage_dependency_table { 1443 u8 count; 1444 struct radeon_vce_clock_voltage_dependency_entry *entries; 1445 }; 1446 1447 struct radeon_ppm_table { 1448 u8 ppm_design; 1449 u16 cpu_core_number; 1450 u32 platform_tdp; 1451 u32 small_ac_platform_tdp; 1452 u32 platform_tdc; 1453 u32 small_ac_platform_tdc; 1454 u32 apu_tdp; 1455 u32 dgpu_tdp; 1456 u32 dgpu_ulv_power; 1457 u32 tj_max; 1458 }; 1459 1460 struct radeon_cac_tdp_table { 1461 u16 tdp; 1462 u16 configurable_tdp; 1463 u16 tdc; 1464 u16 battery_power_limit; 1465 u16 small_power_limit; 1466 u16 low_cac_leakage; 1467 u16 high_cac_leakage; 1468 u16 maximum_power_delivery_limit; 1469 }; 1470 1471 struct radeon_dpm_dynamic_state { 1472 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1473 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1474 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1475 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1476 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1477 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1478 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1479 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1480 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1481 struct radeon_clock_array valid_sclk_values; 1482 struct radeon_clock_array valid_mclk_values; 1483 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1484 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1485 u32 mclk_sclk_ratio; 1486 u32 sclk_mclk_delta; 1487 u16 vddc_vddci_delta; 1488 u16 min_vddc_for_pcie_gen2; 1489 struct radeon_cac_leakage_table cac_leakage_table; 1490 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1491 struct radeon_ppm_table *ppm_table; 1492 struct radeon_cac_tdp_table *cac_tdp_table; 1493 }; 1494 1495 struct radeon_dpm_fan { 1496 u16 t_min; 1497 u16 t_med; 1498 u16 t_high; 1499 u16 pwm_min; 1500 u16 pwm_med; 1501 u16 pwm_high; 1502 u8 t_hyst; 1503 u32 cycle_delay; 1504 u16 t_max; 1505 u8 control_mode; 1506 u16 default_max_fan_pwm; 1507 u16 default_fan_output_sensitivity; 1508 u16 fan_output_sensitivity; 1509 bool ucode_fan_control; 1510 }; 1511 1512 enum radeon_pcie_gen { 1513 RADEON_PCIE_GEN1 = 0, 1514 RADEON_PCIE_GEN2 = 1, 1515 RADEON_PCIE_GEN3 = 2, 1516 RADEON_PCIE_GEN_INVALID = 0xffff 1517 }; 1518 1519 enum radeon_dpm_forced_level { 1520 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1521 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1522 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1523 }; 1524 1525 struct radeon_vce_state { 1526 /* vce clocks */ 1527 u32 evclk; 1528 u32 ecclk; 1529 /* gpu clocks */ 1530 u32 sclk; 1531 u32 mclk; 1532 u8 clk_idx; 1533 u8 pstate; 1534 }; 1535 1536 struct radeon_dpm { 1537 struct radeon_ps *ps; 1538 /* number of valid power states */ 1539 int num_ps; 1540 /* current power state that is active */ 1541 struct radeon_ps *current_ps; 1542 /* requested power state */ 1543 struct radeon_ps *requested_ps; 1544 /* boot up power state */ 1545 struct radeon_ps *boot_ps; 1546 /* default uvd power state */ 1547 struct radeon_ps *uvd_ps; 1548 /* vce requirements */ 1549 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1550 enum radeon_vce_level vce_level; 1551 enum radeon_pm_state_type state; 1552 enum radeon_pm_state_type user_state; 1553 u32 platform_caps; 1554 u32 voltage_response_time; 1555 u32 backbias_response_time; 1556 void *priv; 1557 u32 new_active_crtcs; 1558 int new_active_crtc_count; 1559 u32 current_active_crtcs; 1560 int current_active_crtc_count; 1561 bool single_display; 1562 struct radeon_dpm_dynamic_state dyn_state; 1563 struct radeon_dpm_fan fan; 1564 u32 tdp_limit; 1565 u32 near_tdp_limit; 1566 u32 near_tdp_limit_adjusted; 1567 u32 sq_ramping_threshold; 1568 u32 cac_leakage; 1569 u16 tdp_od_limit; 1570 u32 tdp_adjustment; 1571 u16 load_line_slope; 1572 bool power_control; 1573 bool ac_power; 1574 /* special states active */ 1575 bool thermal_active; 1576 bool uvd_active; 1577 bool vce_active; 1578 /* thermal handling */ 1579 struct radeon_dpm_thermal thermal; 1580 /* forced levels */ 1581 enum radeon_dpm_forced_level forced_level; 1582 /* track UVD streams */ 1583 unsigned sd; 1584 unsigned hd; 1585 }; 1586 1587 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1588 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1589 1590 struct radeon_pm { 1591 struct mutex mutex; 1592 /* write locked while reprogramming mclk */ 1593 struct rw_semaphore mclk_lock; 1594 u32 active_crtcs; 1595 int active_crtc_count; 1596 int req_vblank; 1597 bool vblank_sync; 1598 fixed20_12 max_bandwidth; 1599 fixed20_12 igp_sideport_mclk; 1600 fixed20_12 igp_system_mclk; 1601 fixed20_12 igp_ht_link_clk; 1602 fixed20_12 igp_ht_link_width; 1603 fixed20_12 k8_bandwidth; 1604 fixed20_12 sideport_bandwidth; 1605 fixed20_12 ht_bandwidth; 1606 fixed20_12 core_bandwidth; 1607 fixed20_12 sclk; 1608 fixed20_12 mclk; 1609 fixed20_12 needed_bandwidth; 1610 struct radeon_power_state *power_state; 1611 /* number of valid power states */ 1612 int num_power_states; 1613 int current_power_state_index; 1614 int current_clock_mode_index; 1615 int requested_power_state_index; 1616 int requested_clock_mode_index; 1617 int default_power_state_index; 1618 u32 current_sclk; 1619 u32 current_mclk; 1620 u16 current_vddc; 1621 u16 current_vddci; 1622 u32 default_sclk; 1623 u32 default_mclk; 1624 u16 default_vddc; 1625 u16 default_vddci; 1626 struct radeon_i2c_chan *i2c_bus; 1627 /* selected pm method */ 1628 enum radeon_pm_method pm_method; 1629 /* dynpm power management */ 1630 struct delayed_work dynpm_idle_work; 1631 enum radeon_dynpm_state dynpm_state; 1632 enum radeon_dynpm_action dynpm_planned_action; 1633 unsigned long dynpm_action_timeout; 1634 bool dynpm_can_upclock; 1635 bool dynpm_can_downclock; 1636 /* profile-based power management */ 1637 enum radeon_pm_profile_type profile; 1638 int profile_index; 1639 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1640 /* internal thermal controller on rv6xx+ */ 1641 enum radeon_int_thermal_type int_thermal_type; 1642 struct device *int_hwmon_dev; 1643 /* fan control parameters */ 1644 bool no_fan; 1645 u8 fan_pulses_per_revolution; 1646 u8 fan_min_rpm; 1647 u8 fan_max_rpm; 1648 /* dpm */ 1649 bool dpm_enabled; 1650 bool sysfs_initialized; 1651 struct radeon_dpm dpm; 1652 }; 1653 1654 #define RADEON_PCIE_SPEED_25 1 1655 #define RADEON_PCIE_SPEED_50 2 1656 #define RADEON_PCIE_SPEED_80 4 1657 1658 int radeon_pm_get_type_index(struct radeon_device *rdev, 1659 enum radeon_pm_state_type ps_type, 1660 int instance); 1661 /* 1662 * UVD 1663 */ 1664 #define RADEON_DEFAULT_UVD_HANDLES 10 1665 #define RADEON_MAX_UVD_HANDLES 30 1666 #define RADEON_UVD_STACK_SIZE (200*1024) 1667 #define RADEON_UVD_HEAP_SIZE (256*1024) 1668 #define RADEON_UVD_SESSION_SIZE (50*1024) 1669 1670 struct radeon_uvd { 1671 bool fw_header_present; 1672 struct radeon_bo *vcpu_bo; 1673 void *cpu_addr; 1674 uint64_t gpu_addr; 1675 unsigned max_handles; 1676 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1677 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1678 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1679 struct delayed_work idle_work; 1680 }; 1681 1682 int radeon_uvd_init(struct radeon_device *rdev); 1683 void radeon_uvd_fini(struct radeon_device *rdev); 1684 int radeon_uvd_suspend(struct radeon_device *rdev); 1685 int radeon_uvd_resume(struct radeon_device *rdev); 1686 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1687 uint32_t handle, struct radeon_fence **fence); 1688 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1689 uint32_t handle, struct radeon_fence **fence); 1690 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1691 uint32_t allowed_domains); 1692 void radeon_uvd_free_handles(struct radeon_device *rdev, 1693 struct drm_file *filp); 1694 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1695 void radeon_uvd_note_usage(struct radeon_device *rdev); 1696 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1697 unsigned vclk, unsigned dclk, 1698 unsigned vco_min, unsigned vco_max, 1699 unsigned fb_factor, unsigned fb_mask, 1700 unsigned pd_min, unsigned pd_max, 1701 unsigned pd_even, 1702 unsigned *optimal_fb_div, 1703 unsigned *optimal_vclk_div, 1704 unsigned *optimal_dclk_div); 1705 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1706 unsigned cg_upll_func_cntl); 1707 1708 /* 1709 * VCE 1710 */ 1711 #define RADEON_MAX_VCE_HANDLES 16 1712 1713 struct radeon_vce { 1714 struct radeon_bo *vcpu_bo; 1715 uint64_t gpu_addr; 1716 unsigned fw_version; 1717 unsigned fb_version; 1718 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1719 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1720 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1721 struct delayed_work idle_work; 1722 uint32_t keyselect; 1723 }; 1724 1725 int radeon_vce_init(struct radeon_device *rdev); 1726 void radeon_vce_fini(struct radeon_device *rdev); 1727 int radeon_vce_suspend(struct radeon_device *rdev); 1728 int radeon_vce_resume(struct radeon_device *rdev); 1729 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1730 uint32_t handle, struct radeon_fence **fence); 1731 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1732 uint32_t handle, struct radeon_fence **fence); 1733 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1734 void radeon_vce_note_usage(struct radeon_device *rdev); 1735 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1736 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1737 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1738 struct radeon_ring *ring, 1739 struct radeon_semaphore *semaphore, 1740 bool emit_wait); 1741 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1742 void radeon_vce_fence_emit(struct radeon_device *rdev, 1743 struct radeon_fence *fence); 1744 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1745 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1746 1747 struct r600_audio_pin { 1748 int channels; 1749 int rate; 1750 int bits_per_sample; 1751 u8 status_bits; 1752 u8 category_code; 1753 u32 offset; 1754 bool connected; 1755 u32 id; 1756 }; 1757 1758 struct r600_audio { 1759 bool enabled; 1760 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1761 int num_pins; 1762 struct radeon_audio_funcs *hdmi_funcs; 1763 struct radeon_audio_funcs *dp_funcs; 1764 struct radeon_audio_basic_funcs *funcs; 1765 }; 1766 1767 /* 1768 * Benchmarking 1769 */ 1770 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1771 1772 1773 /* 1774 * Testing 1775 */ 1776 void radeon_test_moves(struct radeon_device *rdev); 1777 void radeon_test_ring_sync(struct radeon_device *rdev, 1778 struct radeon_ring *cpA, 1779 struct radeon_ring *cpB); 1780 void radeon_test_syncing(struct radeon_device *rdev); 1781 1782 /* 1783 * MMU Notifier 1784 */ 1785 #if defined(CONFIG_MMU_NOTIFIER) 1786 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); 1787 void radeon_mn_unregister(struct radeon_bo *bo); 1788 #else 1789 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr) 1790 { 1791 return -ENODEV; 1792 } 1793 static inline void radeon_mn_unregister(struct radeon_bo *bo) {} 1794 #endif 1795 1796 /* 1797 * Debugfs 1798 */ 1799 struct radeon_debugfs { 1800 struct drm_info_list *files; 1801 unsigned num_files; 1802 }; 1803 1804 int radeon_debugfs_add_files(struct radeon_device *rdev, 1805 struct drm_info_list *files, 1806 unsigned nfiles); 1807 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1808 1809 /* 1810 * ASIC ring specific functions. 1811 */ 1812 struct radeon_asic_ring { 1813 /* ring read/write ptr handling */ 1814 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1815 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1816 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1817 1818 /* validating and patching of IBs */ 1819 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1820 int (*cs_parse)(struct radeon_cs_parser *p); 1821 1822 /* command emmit functions */ 1823 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1824 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1825 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1826 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1827 struct radeon_semaphore *semaphore, bool emit_wait); 1828 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring, 1829 unsigned vm_id, uint64_t pd_addr); 1830 1831 /* testing functions */ 1832 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1833 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1834 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1835 1836 /* deprecated */ 1837 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1838 }; 1839 1840 /* 1841 * ASIC specific functions. 1842 */ 1843 struct radeon_asic { 1844 int (*init)(struct radeon_device *rdev); 1845 void (*fini)(struct radeon_device *rdev); 1846 int (*resume)(struct radeon_device *rdev); 1847 int (*suspend)(struct radeon_device *rdev); 1848 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1849 int (*asic_reset)(struct radeon_device *rdev, bool hard); 1850 /* Flush the HDP cache via MMIO */ 1851 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1852 /* check if 3D engine is idle */ 1853 bool (*gui_idle)(struct radeon_device *rdev); 1854 /* wait for mc_idle */ 1855 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1856 /* get the reference clock */ 1857 u32 (*get_xclk)(struct radeon_device *rdev); 1858 /* get the gpu clock counter */ 1859 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1860 /* get register for info ioctl */ 1861 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val); 1862 /* gart */ 1863 struct { 1864 void (*tlb_flush)(struct radeon_device *rdev); 1865 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags); 1866 void (*set_page)(struct radeon_device *rdev, unsigned i, 1867 uint64_t entry); 1868 } gart; 1869 struct { 1870 int (*init)(struct radeon_device *rdev); 1871 void (*fini)(struct radeon_device *rdev); 1872 void (*copy_pages)(struct radeon_device *rdev, 1873 struct radeon_ib *ib, 1874 uint64_t pe, uint64_t src, 1875 unsigned count); 1876 void (*write_pages)(struct radeon_device *rdev, 1877 struct radeon_ib *ib, 1878 uint64_t pe, 1879 uint64_t addr, unsigned count, 1880 uint32_t incr, uint32_t flags); 1881 void (*set_pages)(struct radeon_device *rdev, 1882 struct radeon_ib *ib, 1883 uint64_t pe, 1884 uint64_t addr, unsigned count, 1885 uint32_t incr, uint32_t flags); 1886 void (*pad_ib)(struct radeon_ib *ib); 1887 } vm; 1888 /* ring specific callbacks */ 1889 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1890 /* irqs */ 1891 struct { 1892 int (*set)(struct radeon_device *rdev); 1893 int (*process)(struct radeon_device *rdev); 1894 } irq; 1895 /* displays */ 1896 struct { 1897 /* display watermarks */ 1898 void (*bandwidth_update)(struct radeon_device *rdev); 1899 /* get frame count */ 1900 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1901 /* wait for vblank */ 1902 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1903 /* set backlight level */ 1904 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1905 /* get backlight level */ 1906 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1907 /* audio callbacks */ 1908 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1909 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1910 } display; 1911 /* copy functions for bo handling */ 1912 struct { 1913 struct radeon_fence *(*blit)(struct radeon_device *rdev, 1914 uint64_t src_offset, 1915 uint64_t dst_offset, 1916 unsigned num_gpu_pages, 1917 struct dma_resv *resv); 1918 u32 blit_ring_index; 1919 struct radeon_fence *(*dma)(struct radeon_device *rdev, 1920 uint64_t src_offset, 1921 uint64_t dst_offset, 1922 unsigned num_gpu_pages, 1923 struct dma_resv *resv); 1924 u32 dma_ring_index; 1925 /* method used for bo copy */ 1926 struct radeon_fence *(*copy)(struct radeon_device *rdev, 1927 uint64_t src_offset, 1928 uint64_t dst_offset, 1929 unsigned num_gpu_pages, 1930 struct dma_resv *resv); 1931 /* ring used for bo copies */ 1932 u32 copy_ring_index; 1933 } copy; 1934 /* surfaces */ 1935 struct { 1936 int (*set_reg)(struct radeon_device *rdev, int reg, 1937 uint32_t tiling_flags, uint32_t pitch, 1938 uint32_t offset, uint32_t obj_size); 1939 void (*clear_reg)(struct radeon_device *rdev, int reg); 1940 } surface; 1941 /* hotplug detect */ 1942 struct { 1943 void (*init)(struct radeon_device *rdev); 1944 void (*fini)(struct radeon_device *rdev); 1945 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1946 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1947 } hpd; 1948 /* static power management */ 1949 struct { 1950 void (*misc)(struct radeon_device *rdev); 1951 void (*prepare)(struct radeon_device *rdev); 1952 void (*finish)(struct radeon_device *rdev); 1953 void (*init_profile)(struct radeon_device *rdev); 1954 void (*get_dynpm_state)(struct radeon_device *rdev); 1955 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1956 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1957 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1958 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1959 int (*get_pcie_lanes)(struct radeon_device *rdev); 1960 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1961 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1962 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1963 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1964 int (*get_temperature)(struct radeon_device *rdev); 1965 } pm; 1966 /* dynamic power management */ 1967 struct { 1968 int (*init)(struct radeon_device *rdev); 1969 void (*setup_asic)(struct radeon_device *rdev); 1970 int (*enable)(struct radeon_device *rdev); 1971 int (*late_enable)(struct radeon_device *rdev); 1972 void (*disable)(struct radeon_device *rdev); 1973 int (*pre_set_power_state)(struct radeon_device *rdev); 1974 int (*set_power_state)(struct radeon_device *rdev); 1975 void (*post_set_power_state)(struct radeon_device *rdev); 1976 void (*display_configuration_changed)(struct radeon_device *rdev); 1977 void (*fini)(struct radeon_device *rdev); 1978 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1979 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1980 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1981 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1982 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 1983 bool (*vblank_too_short)(struct radeon_device *rdev); 1984 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 1985 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 1986 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode); 1987 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev); 1988 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed); 1989 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed); 1990 u32 (*get_current_sclk)(struct radeon_device *rdev); 1991 u32 (*get_current_mclk)(struct radeon_device *rdev); 1992 u16 (*get_current_vddc)(struct radeon_device *rdev); 1993 } dpm; 1994 /* pageflipping */ 1995 struct { 1996 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async); 1997 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 1998 } pflip; 1999 }; 2000 2001 /* 2002 * Asic structures 2003 */ 2004 struct r100_asic { 2005 const unsigned *reg_safe_bm; 2006 unsigned reg_safe_bm_size; 2007 u32 hdp_cntl; 2008 }; 2009 2010 struct r300_asic { 2011 const unsigned *reg_safe_bm; 2012 unsigned reg_safe_bm_size; 2013 u32 resync_scratch; 2014 u32 hdp_cntl; 2015 }; 2016 2017 struct r600_asic { 2018 unsigned max_pipes; 2019 unsigned max_tile_pipes; 2020 unsigned max_simds; 2021 unsigned max_backends; 2022 unsigned max_gprs; 2023 unsigned max_threads; 2024 unsigned max_stack_entries; 2025 unsigned max_hw_contexts; 2026 unsigned max_gs_threads; 2027 unsigned sx_max_export_size; 2028 unsigned sx_max_export_pos_size; 2029 unsigned sx_max_export_smx_size; 2030 unsigned sq_num_cf_insts; 2031 unsigned tiling_nbanks; 2032 unsigned tiling_npipes; 2033 unsigned tiling_group_size; 2034 unsigned tile_config; 2035 unsigned backend_map; 2036 unsigned active_simds; 2037 }; 2038 2039 struct rv770_asic { 2040 unsigned max_pipes; 2041 unsigned max_tile_pipes; 2042 unsigned max_simds; 2043 unsigned max_backends; 2044 unsigned max_gprs; 2045 unsigned max_threads; 2046 unsigned max_stack_entries; 2047 unsigned max_hw_contexts; 2048 unsigned max_gs_threads; 2049 unsigned sx_max_export_size; 2050 unsigned sx_max_export_pos_size; 2051 unsigned sx_max_export_smx_size; 2052 unsigned sq_num_cf_insts; 2053 unsigned sx_num_of_sets; 2054 unsigned sc_prim_fifo_size; 2055 unsigned sc_hiz_tile_fifo_size; 2056 unsigned sc_earlyz_tile_fifo_fize; 2057 unsigned tiling_nbanks; 2058 unsigned tiling_npipes; 2059 unsigned tiling_group_size; 2060 unsigned tile_config; 2061 unsigned backend_map; 2062 unsigned active_simds; 2063 }; 2064 2065 struct evergreen_asic { 2066 unsigned num_ses; 2067 unsigned max_pipes; 2068 unsigned max_tile_pipes; 2069 unsigned max_simds; 2070 unsigned max_backends; 2071 unsigned max_gprs; 2072 unsigned max_threads; 2073 unsigned max_stack_entries; 2074 unsigned max_hw_contexts; 2075 unsigned max_gs_threads; 2076 unsigned sx_max_export_size; 2077 unsigned sx_max_export_pos_size; 2078 unsigned sx_max_export_smx_size; 2079 unsigned sq_num_cf_insts; 2080 unsigned sx_num_of_sets; 2081 unsigned sc_prim_fifo_size; 2082 unsigned sc_hiz_tile_fifo_size; 2083 unsigned sc_earlyz_tile_fifo_size; 2084 unsigned tiling_nbanks; 2085 unsigned tiling_npipes; 2086 unsigned tiling_group_size; 2087 unsigned tile_config; 2088 unsigned backend_map; 2089 unsigned active_simds; 2090 }; 2091 2092 struct cayman_asic { 2093 unsigned max_shader_engines; 2094 unsigned max_pipes_per_simd; 2095 unsigned max_tile_pipes; 2096 unsigned max_simds_per_se; 2097 unsigned max_backends_per_se; 2098 unsigned max_texture_channel_caches; 2099 unsigned max_gprs; 2100 unsigned max_threads; 2101 unsigned max_gs_threads; 2102 unsigned max_stack_entries; 2103 unsigned sx_num_of_sets; 2104 unsigned sx_max_export_size; 2105 unsigned sx_max_export_pos_size; 2106 unsigned sx_max_export_smx_size; 2107 unsigned max_hw_contexts; 2108 unsigned sq_num_cf_insts; 2109 unsigned sc_prim_fifo_size; 2110 unsigned sc_hiz_tile_fifo_size; 2111 unsigned sc_earlyz_tile_fifo_size; 2112 2113 unsigned num_shader_engines; 2114 unsigned num_shader_pipes_per_simd; 2115 unsigned num_tile_pipes; 2116 unsigned num_simds_per_se; 2117 unsigned num_backends_per_se; 2118 unsigned backend_disable_mask_per_asic; 2119 unsigned backend_map; 2120 unsigned num_texture_channel_caches; 2121 unsigned mem_max_burst_length_bytes; 2122 unsigned mem_row_size_in_kb; 2123 unsigned shader_engine_tile_size; 2124 unsigned num_gpus; 2125 unsigned multi_gpu_tile_size; 2126 2127 unsigned tile_config; 2128 unsigned active_simds; 2129 }; 2130 2131 struct si_asic { 2132 unsigned max_shader_engines; 2133 unsigned max_tile_pipes; 2134 unsigned max_cu_per_sh; 2135 unsigned max_sh_per_se; 2136 unsigned max_backends_per_se; 2137 unsigned max_texture_channel_caches; 2138 unsigned max_gprs; 2139 unsigned max_gs_threads; 2140 unsigned max_hw_contexts; 2141 unsigned sc_prim_fifo_size_frontend; 2142 unsigned sc_prim_fifo_size_backend; 2143 unsigned sc_hiz_tile_fifo_size; 2144 unsigned sc_earlyz_tile_fifo_size; 2145 2146 unsigned num_tile_pipes; 2147 unsigned backend_enable_mask; 2148 unsigned backend_disable_mask_per_asic; 2149 unsigned backend_map; 2150 unsigned num_texture_channel_caches; 2151 unsigned mem_max_burst_length_bytes; 2152 unsigned mem_row_size_in_kb; 2153 unsigned shader_engine_tile_size; 2154 unsigned num_gpus; 2155 unsigned multi_gpu_tile_size; 2156 2157 unsigned tile_config; 2158 uint32_t tile_mode_array[32]; 2159 uint32_t active_cus; 2160 }; 2161 2162 struct cik_asic { 2163 unsigned max_shader_engines; 2164 unsigned max_tile_pipes; 2165 unsigned max_cu_per_sh; 2166 unsigned max_sh_per_se; 2167 unsigned max_backends_per_se; 2168 unsigned max_texture_channel_caches; 2169 unsigned max_gprs; 2170 unsigned max_gs_threads; 2171 unsigned max_hw_contexts; 2172 unsigned sc_prim_fifo_size_frontend; 2173 unsigned sc_prim_fifo_size_backend; 2174 unsigned sc_hiz_tile_fifo_size; 2175 unsigned sc_earlyz_tile_fifo_size; 2176 2177 unsigned num_tile_pipes; 2178 unsigned backend_enable_mask; 2179 unsigned backend_disable_mask_per_asic; 2180 unsigned backend_map; 2181 unsigned num_texture_channel_caches; 2182 unsigned mem_max_burst_length_bytes; 2183 unsigned mem_row_size_in_kb; 2184 unsigned shader_engine_tile_size; 2185 unsigned num_gpus; 2186 unsigned multi_gpu_tile_size; 2187 2188 unsigned tile_config; 2189 uint32_t tile_mode_array[32]; 2190 uint32_t macrotile_mode_array[16]; 2191 uint32_t active_cus; 2192 }; 2193 2194 union radeon_asic_config { 2195 struct r300_asic r300; 2196 struct r100_asic r100; 2197 struct r600_asic r600; 2198 struct rv770_asic rv770; 2199 struct evergreen_asic evergreen; 2200 struct cayman_asic cayman; 2201 struct si_asic si; 2202 struct cik_asic cik; 2203 }; 2204 2205 /* 2206 * asic initizalization from radeon_asic.c 2207 */ 2208 void radeon_agp_disable(struct radeon_device *rdev); 2209 int radeon_asic_init(struct radeon_device *rdev); 2210 2211 2212 /* 2213 * IOCTL. 2214 */ 2215 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2216 struct drm_file *filp); 2217 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2218 struct drm_file *filp); 2219 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, 2220 struct drm_file *filp); 2221 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2222 struct drm_file *file_priv); 2223 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2224 struct drm_file *file_priv); 2225 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2226 struct drm_file *file_priv); 2227 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2228 struct drm_file *file_priv); 2229 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2230 struct drm_file *filp); 2231 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2232 struct drm_file *filp); 2233 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2234 struct drm_file *filp); 2235 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2236 struct drm_file *filp); 2237 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2238 struct drm_file *filp); 2239 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2240 struct drm_file *filp); 2241 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2242 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2243 struct drm_file *filp); 2244 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2245 struct drm_file *filp); 2246 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2247 2248 /* VRAM scratch page for HDP bug, default vram page */ 2249 struct r600_vram_scratch { 2250 struct radeon_bo *robj; 2251 volatile uint32_t *ptr; 2252 u64 gpu_addr; 2253 }; 2254 2255 /* 2256 * ACPI 2257 */ 2258 struct radeon_atif_notification_cfg { 2259 bool enabled; 2260 int command_code; 2261 }; 2262 2263 struct radeon_atif_notifications { 2264 bool display_switch; 2265 bool expansion_mode_change; 2266 bool thermal_state; 2267 bool forced_power_state; 2268 bool system_power_state; 2269 bool display_conf_change; 2270 bool px_gfx_switch; 2271 bool brightness_change; 2272 bool dgpu_display_event; 2273 }; 2274 2275 struct radeon_atif_functions { 2276 bool system_params; 2277 bool sbios_requests; 2278 bool select_active_disp; 2279 bool lid_state; 2280 bool get_tv_standard; 2281 bool set_tv_standard; 2282 bool get_panel_expansion_mode; 2283 bool set_panel_expansion_mode; 2284 bool temperature_change; 2285 bool graphics_device_types; 2286 }; 2287 2288 struct radeon_atif { 2289 struct radeon_atif_notifications notifications; 2290 struct radeon_atif_functions functions; 2291 struct radeon_atif_notification_cfg notification_cfg; 2292 struct radeon_encoder *encoder_for_bl; 2293 }; 2294 2295 struct radeon_atcs_functions { 2296 bool get_ext_state; 2297 bool pcie_perf_req; 2298 bool pcie_dev_rdy; 2299 bool pcie_bus_width; 2300 }; 2301 2302 struct radeon_atcs { 2303 struct radeon_atcs_functions functions; 2304 }; 2305 2306 /* 2307 * Core structure, functions and helpers. 2308 */ 2309 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2310 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2311 2312 struct radeon_device { 2313 struct device *dev; 2314 struct drm_device *ddev; 2315 struct pci_dev *pdev; 2316 #ifdef __alpha__ 2317 struct pci_controller *hose; 2318 #endif 2319 struct rw_semaphore exclusive_lock; 2320 /* ASIC */ 2321 union radeon_asic_config config; 2322 enum radeon_family family; 2323 unsigned long flags; 2324 int usec_timeout; 2325 enum radeon_pll_errata pll_errata; 2326 int num_gb_pipes; 2327 int num_z_pipes; 2328 int disp_priority; 2329 /* BIOS */ 2330 uint8_t *bios; 2331 bool is_atom_bios; 2332 uint16_t bios_header_start; 2333 struct radeon_bo *stolen_vga_memory; 2334 /* Register mmio */ 2335 resource_size_t rmmio_base; 2336 resource_size_t rmmio_size; 2337 /* protects concurrent MM_INDEX/DATA based register access */ 2338 spinlock_t mmio_idx_lock; 2339 /* protects concurrent SMC based register access */ 2340 spinlock_t smc_idx_lock; 2341 /* protects concurrent PLL register access */ 2342 spinlock_t pll_idx_lock; 2343 /* protects concurrent MC register access */ 2344 spinlock_t mc_idx_lock; 2345 /* protects concurrent PCIE register access */ 2346 spinlock_t pcie_idx_lock; 2347 /* protects concurrent PCIE_PORT register access */ 2348 spinlock_t pciep_idx_lock; 2349 /* protects concurrent PIF register access */ 2350 spinlock_t pif_idx_lock; 2351 /* protects concurrent CG register access */ 2352 spinlock_t cg_idx_lock; 2353 /* protects concurrent UVD register access */ 2354 spinlock_t uvd_idx_lock; 2355 /* protects concurrent RCU register access */ 2356 spinlock_t rcu_idx_lock; 2357 /* protects concurrent DIDT register access */ 2358 spinlock_t didt_idx_lock; 2359 /* protects concurrent ENDPOINT (audio) register access */ 2360 spinlock_t end_idx_lock; 2361 void __iomem *rmmio; 2362 radeon_rreg_t mc_rreg; 2363 radeon_wreg_t mc_wreg; 2364 radeon_rreg_t pll_rreg; 2365 radeon_wreg_t pll_wreg; 2366 uint32_t pcie_reg_mask; 2367 radeon_rreg_t pciep_rreg; 2368 radeon_wreg_t pciep_wreg; 2369 /* io port */ 2370 void __iomem *rio_mem; 2371 resource_size_t rio_mem_size; 2372 struct radeon_clock clock; 2373 struct radeon_mc mc; 2374 struct radeon_gart gart; 2375 struct radeon_mode_info mode_info; 2376 struct radeon_scratch scratch; 2377 struct radeon_doorbell doorbell; 2378 struct radeon_mman mman; 2379 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2380 wait_queue_head_t fence_queue; 2381 u64 fence_context; 2382 struct mutex ring_lock; 2383 struct radeon_ring ring[RADEON_NUM_RINGS]; 2384 bool ib_pool_ready; 2385 struct radeon_sa_manager ring_tmp_bo; 2386 struct radeon_irq irq; 2387 struct radeon_asic *asic; 2388 struct radeon_gem gem; 2389 struct radeon_pm pm; 2390 struct radeon_uvd uvd; 2391 struct radeon_vce vce; 2392 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2393 struct radeon_wb wb; 2394 struct radeon_dummy_page dummy_page; 2395 bool shutdown; 2396 bool need_swiotlb; 2397 bool accel_working; 2398 bool fastfb_working; /* IGP feature*/ 2399 bool needs_reset, in_reset; 2400 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2401 const struct firmware *me_fw; /* all family ME firmware */ 2402 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2403 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2404 const struct firmware *mc_fw; /* NI MC firmware */ 2405 const struct firmware *ce_fw; /* SI CE firmware */ 2406 const struct firmware *mec_fw; /* CIK MEC firmware */ 2407 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2408 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2409 const struct firmware *smc_fw; /* SMC firmware */ 2410 const struct firmware *uvd_fw; /* UVD firmware */ 2411 const struct firmware *vce_fw; /* VCE firmware */ 2412 bool new_fw; 2413 struct r600_vram_scratch vram_scratch; 2414 int msi_enabled; /* msi enabled */ 2415 struct r600_ih ih; /* r6/700 interrupt ring */ 2416 struct radeon_rlc rlc; 2417 struct radeon_mec mec; 2418 struct delayed_work hotplug_work; 2419 struct work_struct dp_work; 2420 struct work_struct audio_work; 2421 int num_crtc; /* number of crtcs */ 2422 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2423 bool has_uvd; 2424 bool has_vce; 2425 struct r600_audio audio; /* audio stuff */ 2426 struct notifier_block acpi_nb; 2427 /* only one userspace can use Hyperz features or CMASK at a time */ 2428 struct drm_file *hyperz_filp; 2429 struct drm_file *cmask_filp; 2430 /* i2c buses */ 2431 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2432 /* debugfs */ 2433 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2434 unsigned debugfs_count; 2435 /* virtual memory */ 2436 struct radeon_vm_manager vm_manager; 2437 struct mutex gpu_clock_mutex; 2438 /* memory stats */ 2439 atomic64_t vram_usage; 2440 atomic64_t gtt_usage; 2441 atomic64_t num_bytes_moved; 2442 atomic_t gpu_reset_counter; 2443 /* ACPI interface */ 2444 struct radeon_atif atif; 2445 struct radeon_atcs atcs; 2446 /* srbm instance registers */ 2447 struct mutex srbm_mutex; 2448 /* clock, powergating flags */ 2449 u32 cg_flags; 2450 u32 pg_flags; 2451 2452 struct dev_pm_domain vga_pm_domain; 2453 bool have_disp_power_ref; 2454 u32 px_quirk_flags; 2455 2456 /* tracking pinned memory */ 2457 u64 vram_pin_size; 2458 u64 gart_pin_size; 2459 }; 2460 2461 bool radeon_is_px(struct drm_device *dev); 2462 int radeon_device_init(struct radeon_device *rdev, 2463 struct drm_device *ddev, 2464 struct pci_dev *pdev, 2465 uint32_t flags); 2466 void radeon_device_fini(struct radeon_device *rdev); 2467 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2468 2469 #define RADEON_MIN_MMIO_SIZE 0x10000 2470 2471 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg); 2472 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2473 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2474 bool always_indirect) 2475 { 2476 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ 2477 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2478 return readl(((void __iomem *)rdev->rmmio) + reg); 2479 else 2480 return r100_mm_rreg_slow(rdev, reg); 2481 } 2482 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2483 bool always_indirect) 2484 { 2485 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2486 writel(v, ((void __iomem *)rdev->rmmio) + reg); 2487 else 2488 r100_mm_wreg_slow(rdev, reg, v); 2489 } 2490 2491 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2492 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2493 2494 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2495 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2496 2497 /* 2498 * Cast helper 2499 */ 2500 extern const struct dma_fence_ops radeon_fence_ops; 2501 2502 static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f) 2503 { 2504 struct radeon_fence *__f = container_of(f, struct radeon_fence, base); 2505 2506 if (__f->base.ops == &radeon_fence_ops) 2507 return __f; 2508 2509 return NULL; 2510 } 2511 2512 /* 2513 * Registers read & write functions. 2514 */ 2515 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 2516 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 2517 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 2518 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 2519 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2520 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2521 #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \ 2522 r100_mm_rreg(rdev, (reg), false)) 2523 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2524 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2525 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2526 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2527 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2528 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2529 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2530 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2531 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2532 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2533 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2534 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2535 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2536 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2537 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2538 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2539 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2540 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2541 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2542 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2543 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2544 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2545 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2546 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2547 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2548 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2549 #define WREG32_P(reg, val, mask) \ 2550 do { \ 2551 uint32_t tmp_ = RREG32(reg); \ 2552 tmp_ &= (mask); \ 2553 tmp_ |= ((val) & ~(mask)); \ 2554 WREG32(reg, tmp_); \ 2555 } while (0) 2556 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2557 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2558 #define WREG32_PLL_P(reg, val, mask) \ 2559 do { \ 2560 uint32_t tmp_ = RREG32_PLL(reg); \ 2561 tmp_ &= (mask); \ 2562 tmp_ |= ((val) & ~(mask)); \ 2563 WREG32_PLL(reg, tmp_); \ 2564 } while (0) 2565 #define WREG32_SMC_P(reg, val, mask) \ 2566 do { \ 2567 uint32_t tmp_ = RREG32_SMC(reg); \ 2568 tmp_ &= (mask); \ 2569 tmp_ |= ((val) & ~(mask)); \ 2570 WREG32_SMC(reg, tmp_); \ 2571 } while (0) 2572 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2573 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2574 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2575 2576 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2577 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2578 2579 /* 2580 * Indirect registers accessors. 2581 * They used to be inlined, but this increases code size by ~65 kbytes. 2582 * Since each performs a pair of MMIO ops 2583 * within a spin_lock_irqsave/spin_unlock_irqrestore region, 2584 * the cost of call+ret is almost negligible. MMIO and locking 2585 * costs several dozens of cycles each at best, call+ret is ~5 cycles. 2586 */ 2587 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); 2588 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2589 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg); 2590 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2591 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg); 2592 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2593 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg); 2594 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2595 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg); 2596 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2597 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg); 2598 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2599 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg); 2600 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2601 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg); 2602 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2603 2604 void r100_pll_errata_after_index(struct radeon_device *rdev); 2605 2606 2607 /* 2608 * ASICs helpers. 2609 */ 2610 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2611 (rdev->pdev->device == 0x5969)) 2612 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2613 (rdev->family == CHIP_RV200) || \ 2614 (rdev->family == CHIP_RS100) || \ 2615 (rdev->family == CHIP_RS200) || \ 2616 (rdev->family == CHIP_RV250) || \ 2617 (rdev->family == CHIP_RV280) || \ 2618 (rdev->family == CHIP_RS300)) 2619 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2620 (rdev->family == CHIP_RV350) || \ 2621 (rdev->family == CHIP_R350) || \ 2622 (rdev->family == CHIP_RV380) || \ 2623 (rdev->family == CHIP_R420) || \ 2624 (rdev->family == CHIP_R423) || \ 2625 (rdev->family == CHIP_RV410) || \ 2626 (rdev->family == CHIP_RS400) || \ 2627 (rdev->family == CHIP_RS480)) 2628 #define ASIC_IS_X2(rdev) ((rdev->pdev->device == 0x9441) || \ 2629 (rdev->pdev->device == 0x9443) || \ 2630 (rdev->pdev->device == 0x944B) || \ 2631 (rdev->pdev->device == 0x9506) || \ 2632 (rdev->pdev->device == 0x9509) || \ 2633 (rdev->pdev->device == 0x950F) || \ 2634 (rdev->pdev->device == 0x689C) || \ 2635 (rdev->pdev->device == 0x689D)) 2636 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2637 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2638 (rdev->family == CHIP_RS690) || \ 2639 (rdev->family == CHIP_RS740) || \ 2640 (rdev->family >= CHIP_R600)) 2641 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2642 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2643 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2644 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2645 (rdev->flags & RADEON_IS_IGP)) 2646 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2647 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2648 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2649 (rdev->flags & RADEON_IS_IGP)) 2650 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2651 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2652 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2653 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2654 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2655 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2656 (rdev->family == CHIP_MULLINS)) 2657 2658 #define ASIC_IS_LOMBOK(rdev) ((rdev->pdev->device == 0x6849) || \ 2659 (rdev->pdev->device == 0x6850) || \ 2660 (rdev->pdev->device == 0x6858) || \ 2661 (rdev->pdev->device == 0x6859) || \ 2662 (rdev->pdev->device == 0x6840) || \ 2663 (rdev->pdev->device == 0x6841) || \ 2664 (rdev->pdev->device == 0x6842) || \ 2665 (rdev->pdev->device == 0x6843)) 2666 2667 /* 2668 * BIOS helpers. 2669 */ 2670 #define RBIOS8(i) (rdev->bios[i]) 2671 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2672 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2673 2674 int radeon_combios_init(struct radeon_device *rdev); 2675 void radeon_combios_fini(struct radeon_device *rdev); 2676 int radeon_atombios_init(struct radeon_device *rdev); 2677 void radeon_atombios_fini(struct radeon_device *rdev); 2678 2679 2680 /* 2681 * RING helpers. 2682 */ 2683 2684 /** 2685 * radeon_ring_write - write a value to the ring 2686 * 2687 * @ring: radeon_ring structure holding ring information 2688 * @v: dword (dw) value to write 2689 * 2690 * Write a value to the requested ring buffer (all asics). 2691 */ 2692 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2693 { 2694 if (ring->count_dw <= 0) 2695 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2696 2697 ring->ring[ring->wptr++] = v; 2698 ring->wptr &= ring->ptr_mask; 2699 ring->count_dw--; 2700 ring->ring_free_dw--; 2701 } 2702 2703 /* 2704 * ASICs macro. 2705 */ 2706 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2707 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2708 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2709 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2710 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2711 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2712 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false) 2713 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2714 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f)) 2715 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e)) 2716 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2717 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2718 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2719 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2720 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2721 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2722 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2723 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2724 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2725 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2726 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2727 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2728 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr)) 2729 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2730 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2731 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2732 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2733 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2734 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2735 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2736 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2737 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2738 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2739 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2740 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2741 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) 2742 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) 2743 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) 2744 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2745 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2746 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2747 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2748 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2749 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2750 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2751 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2752 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2753 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2754 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2755 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2756 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2757 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2758 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2759 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2760 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2761 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2762 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2763 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2764 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2765 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2766 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2767 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2768 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2769 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2770 #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async)) 2771 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2772 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2773 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2774 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2775 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2776 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v)) 2777 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2778 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2779 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2780 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2781 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2782 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2783 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2784 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2785 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2786 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2787 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2788 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2789 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2790 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2791 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2792 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2793 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2794 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2795 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev)) 2796 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev)) 2797 2798 /* Common functions */ 2799 /* AGP */ 2800 extern int radeon_gpu_reset(struct radeon_device *rdev); 2801 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2802 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2803 extern void radeon_agp_disable(struct radeon_device *rdev); 2804 extern int radeon_modeset_init(struct radeon_device *rdev); 2805 extern void radeon_modeset_fini(struct radeon_device *rdev); 2806 extern bool radeon_card_posted(struct radeon_device *rdev); 2807 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2808 extern void radeon_update_display_priority(struct radeon_device *rdev); 2809 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2810 extern void radeon_scratch_init(struct radeon_device *rdev); 2811 extern void radeon_wb_fini(struct radeon_device *rdev); 2812 extern int radeon_wb_init(struct radeon_device *rdev); 2813 extern void radeon_wb_disable(struct radeon_device *rdev); 2814 extern void radeon_surface_init(struct radeon_device *rdev); 2815 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2816 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 2817 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 2818 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2819 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2820 extern int radeon_ttm_tt_set_userptr(struct radeon_device *rdev, 2821 struct ttm_tt *ttm, uint64_t addr, 2822 uint32_t flags); 2823 extern bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev, struct ttm_tt *ttm); 2824 extern bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev, struct ttm_tt *ttm); 2825 bool radeon_ttm_tt_is_bound(struct ttm_bo_device *bdev, struct ttm_tt *ttm); 2826 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2827 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2828 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2829 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, 2830 bool fbcon, bool freeze); 2831 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2832 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2833 const u32 *registers, 2834 const u32 array_size); 2835 struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev); 2836 2837 /* KMS */ 2838 2839 u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc); 2840 int radeon_enable_vblank_kms(struct drm_crtc *crtc); 2841 void radeon_disable_vblank_kms(struct drm_crtc *crtc); 2842 2843 /* 2844 * vm 2845 */ 2846 int radeon_vm_manager_init(struct radeon_device *rdev); 2847 void radeon_vm_manager_fini(struct radeon_device *rdev); 2848 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2849 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2850 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, 2851 struct radeon_vm *vm, 2852 struct list_head *head); 2853 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2854 struct radeon_vm *vm, int ring); 2855 void radeon_vm_flush(struct radeon_device *rdev, 2856 struct radeon_vm *vm, 2857 int ring, struct radeon_fence *fence); 2858 void radeon_vm_fence(struct radeon_device *rdev, 2859 struct radeon_vm *vm, 2860 struct radeon_fence *fence); 2861 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2862 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2863 struct radeon_vm *vm); 2864 int radeon_vm_clear_freed(struct radeon_device *rdev, 2865 struct radeon_vm *vm); 2866 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2867 struct radeon_vm *vm); 2868 int radeon_vm_bo_update(struct radeon_device *rdev, 2869 struct radeon_bo_va *bo_va, 2870 struct ttm_resource *mem); 2871 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2872 struct radeon_bo *bo); 2873 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2874 struct radeon_bo *bo); 2875 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2876 struct radeon_vm *vm, 2877 struct radeon_bo *bo); 2878 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2879 struct radeon_bo_va *bo_va, 2880 uint64_t offset, 2881 uint32_t flags); 2882 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2883 struct radeon_bo_va *bo_va); 2884 2885 /* audio */ 2886 void r600_audio_update_hdmi(struct work_struct *work); 2887 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2888 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2889 void r600_audio_enable(struct radeon_device *rdev, 2890 struct r600_audio_pin *pin, 2891 u8 enable_mask); 2892 void dce6_audio_enable(struct radeon_device *rdev, 2893 struct r600_audio_pin *pin, 2894 u8 enable_mask); 2895 2896 /* 2897 * R600 vram scratch functions 2898 */ 2899 int r600_vram_scratch_init(struct radeon_device *rdev); 2900 void r600_vram_scratch_fini(struct radeon_device *rdev); 2901 2902 /* 2903 * r600 cs checking helper 2904 */ 2905 unsigned r600_mip_minify(unsigned size, unsigned level); 2906 bool r600_fmt_is_valid_color(u32 format); 2907 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2908 int r600_fmt_get_blocksize(u32 format); 2909 int r600_fmt_get_nblocksx(u32 format, u32 w); 2910 int r600_fmt_get_nblocksy(u32 format, u32 h); 2911 2912 /* 2913 * r600 functions used by radeon_encoder.c 2914 */ 2915 struct radeon_hdmi_acr { 2916 u32 clock; 2917 2918 int n_32khz; 2919 int cts_32khz; 2920 2921 int n_44_1khz; 2922 int cts_44_1khz; 2923 2924 int n_48khz; 2925 int cts_48khz; 2926 2927 }; 2928 2929 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 2930 2931 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2932 u32 tiling_pipe_num, 2933 u32 max_rb_num, 2934 u32 total_max_rb_num, 2935 u32 enabled_rb_mask); 2936 2937 /* 2938 * evergreen functions used by radeon_encoder.c 2939 */ 2940 2941 extern int ni_init_microcode(struct radeon_device *rdev); 2942 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2943 2944 /* radeon_acpi.c */ 2945 #if defined(CONFIG_ACPI) 2946 extern int radeon_acpi_init(struct radeon_device *rdev); 2947 extern void radeon_acpi_fini(struct radeon_device *rdev); 2948 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 2949 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 2950 u8 perf_req, bool advertise); 2951 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 2952 #else 2953 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 2954 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 2955 #endif 2956 2957 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 2958 struct radeon_cs_packet *pkt, 2959 unsigned idx); 2960 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 2961 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 2962 struct radeon_cs_packet *pkt); 2963 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 2964 struct radeon_bo_list **cs_reloc, 2965 int nomm); 2966 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 2967 uint32_t *vline_start_end, 2968 uint32_t *vline_status); 2969 2970 /* interrupt control register helpers */ 2971 void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev, 2972 u32 reg, u32 mask, 2973 bool enable, const char *name, 2974 unsigned n); 2975 2976 #include "radeon_object.h" 2977 2978 #endif 2979