1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 /* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45 /* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63 #include <linux/atomic.h> 64 #include <linux/wait.h> 65 #include <linux/list.h> 66 #include <linux/kref.h> 67 68 #include <ttm/ttm_bo_api.h> 69 #include <ttm/ttm_bo_driver.h> 70 #include <ttm/ttm_placement.h> 71 #include <ttm/ttm_module.h> 72 #include <ttm/ttm_execbuf_util.h> 73 74 #include "radeon_family.h" 75 #include "radeon_mode.h" 76 #include "radeon_reg.h" 77 78 /* 79 * Modules parameters. 80 */ 81 extern int radeon_no_wb; 82 extern int radeon_modeset; 83 extern int radeon_dynclks; 84 extern int radeon_r4xx_atom; 85 extern int radeon_agpmode; 86 extern int radeon_vram_limit; 87 extern int radeon_gart_size; 88 extern int radeon_benchmarking; 89 extern int radeon_testing; 90 extern int radeon_connector_table; 91 extern int radeon_tv; 92 extern int radeon_audio; 93 extern int radeon_disp_priority; 94 extern int radeon_hw_i2c; 95 extern int radeon_pcie_gen2; 96 extern int radeon_msi; 97 extern int radeon_lockup_timeout; 98 extern int radeon_fastfb; 99 extern int radeon_dpm; 100 extern int radeon_aspm; 101 extern int radeon_runtime_pm; 102 extern int radeon_hard_reset; 103 extern int radeon_vm_size; 104 extern int radeon_vm_block_size; 105 106 /* 107 * Copy from radeon_drv.h so we don't have to include both and have conflicting 108 * symbol; 109 */ 110 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 111 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 112 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 113 #define RADEON_IB_POOL_SIZE 16 114 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 115 #define RADEONFB_CONN_LIMIT 4 116 #define RADEON_BIOS_NUM_SCRATCH 8 117 118 /* fence seq are set to this number when signaled */ 119 #define RADEON_FENCE_SIGNALED_SEQ 0LL 120 121 /* internal ring indices */ 122 /* r1xx+ has gfx CP ring */ 123 #define RADEON_RING_TYPE_GFX_INDEX 0 124 125 /* cayman has 2 compute CP rings */ 126 #define CAYMAN_RING_TYPE_CP1_INDEX 1 127 #define CAYMAN_RING_TYPE_CP2_INDEX 2 128 129 /* R600+ has an async dma ring */ 130 #define R600_RING_TYPE_DMA_INDEX 3 131 /* cayman add a second async dma ring */ 132 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 133 134 /* R600+ */ 135 #define R600_RING_TYPE_UVD_INDEX 5 136 137 /* TN+ */ 138 #define TN_RING_TYPE_VCE1_INDEX 6 139 #define TN_RING_TYPE_VCE2_INDEX 7 140 141 /* max number of rings */ 142 #define RADEON_NUM_RINGS 8 143 144 /* number of hw syncs before falling back on blocking */ 145 #define RADEON_NUM_SYNCS 4 146 147 /* number of hw syncs before falling back on blocking */ 148 #define RADEON_NUM_SYNCS 4 149 150 /* hardcode those limit for now */ 151 #define RADEON_VA_IB_OFFSET (1 << 20) 152 #define RADEON_VA_RESERVED_SIZE (8 << 20) 153 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 154 155 /* hard reset data */ 156 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 157 158 /* reset flags */ 159 #define RADEON_RESET_GFX (1 << 0) 160 #define RADEON_RESET_COMPUTE (1 << 1) 161 #define RADEON_RESET_DMA (1 << 2) 162 #define RADEON_RESET_CP (1 << 3) 163 #define RADEON_RESET_GRBM (1 << 4) 164 #define RADEON_RESET_DMA1 (1 << 5) 165 #define RADEON_RESET_RLC (1 << 6) 166 #define RADEON_RESET_SEM (1 << 7) 167 #define RADEON_RESET_IH (1 << 8) 168 #define RADEON_RESET_VMC (1 << 9) 169 #define RADEON_RESET_MC (1 << 10) 170 #define RADEON_RESET_DISPLAY (1 << 11) 171 172 /* CG block flags */ 173 #define RADEON_CG_BLOCK_GFX (1 << 0) 174 #define RADEON_CG_BLOCK_MC (1 << 1) 175 #define RADEON_CG_BLOCK_SDMA (1 << 2) 176 #define RADEON_CG_BLOCK_UVD (1 << 3) 177 #define RADEON_CG_BLOCK_VCE (1 << 4) 178 #define RADEON_CG_BLOCK_HDP (1 << 5) 179 #define RADEON_CG_BLOCK_BIF (1 << 6) 180 181 /* CG flags */ 182 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 183 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 184 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 185 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 186 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 187 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 188 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 189 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 190 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 191 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 192 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 193 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 194 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 195 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 196 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 197 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 198 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 199 200 /* PG flags */ 201 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 202 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 203 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 204 #define RADEON_PG_SUPPORT_UVD (1 << 3) 205 #define RADEON_PG_SUPPORT_VCE (1 << 4) 206 #define RADEON_PG_SUPPORT_CP (1 << 5) 207 #define RADEON_PG_SUPPORT_GDS (1 << 6) 208 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 209 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 210 #define RADEON_PG_SUPPORT_ACP (1 << 9) 211 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 212 213 /* max cursor sizes (in pixels) */ 214 #define CURSOR_WIDTH 64 215 #define CURSOR_HEIGHT 64 216 217 #define CIK_CURSOR_WIDTH 128 218 #define CIK_CURSOR_HEIGHT 128 219 220 /* 221 * Errata workarounds. 222 */ 223 enum radeon_pll_errata { 224 CHIP_ERRATA_R300_CG = 0x00000001, 225 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 226 CHIP_ERRATA_PLL_DELAY = 0x00000004 227 }; 228 229 230 struct radeon_device; 231 232 233 /* 234 * BIOS. 235 */ 236 bool radeon_get_bios(struct radeon_device *rdev); 237 238 /* 239 * Dummy page 240 */ 241 struct radeon_dummy_page { 242 struct page *page; 243 dma_addr_t addr; 244 }; 245 int radeon_dummy_page_init(struct radeon_device *rdev); 246 void radeon_dummy_page_fini(struct radeon_device *rdev); 247 248 249 /* 250 * Clocks 251 */ 252 struct radeon_clock { 253 struct radeon_pll p1pll; 254 struct radeon_pll p2pll; 255 struct radeon_pll dcpll; 256 struct radeon_pll spll; 257 struct radeon_pll mpll; 258 /* 10 Khz units */ 259 uint32_t default_mclk; 260 uint32_t default_sclk; 261 uint32_t default_dispclk; 262 uint32_t current_dispclk; 263 uint32_t dp_extclk; 264 uint32_t max_pixel_clock; 265 }; 266 267 /* 268 * Power management 269 */ 270 int radeon_pm_init(struct radeon_device *rdev); 271 int radeon_pm_late_init(struct radeon_device *rdev); 272 void radeon_pm_fini(struct radeon_device *rdev); 273 void radeon_pm_compute_clocks(struct radeon_device *rdev); 274 void radeon_pm_suspend(struct radeon_device *rdev); 275 void radeon_pm_resume(struct radeon_device *rdev); 276 void radeon_combios_get_power_modes(struct radeon_device *rdev); 277 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 278 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 279 u8 clock_type, 280 u32 clock, 281 bool strobe_mode, 282 struct atom_clock_dividers *dividers); 283 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 284 u32 clock, 285 bool strobe_mode, 286 struct atom_mpll_param *mpll_param); 287 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 288 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 289 u16 voltage_level, u8 voltage_type, 290 u32 *gpio_value, u32 *gpio_mask); 291 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 292 u32 eng_clock, u32 mem_clock); 293 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 294 u8 voltage_type, u16 *voltage_step); 295 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 296 u16 voltage_id, u16 *voltage); 297 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 298 u16 *voltage, 299 u16 leakage_idx); 300 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 301 u16 *leakage_id); 302 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 303 u16 *vddc, u16 *vddci, 304 u16 virtual_voltage_id, 305 u16 vbios_voltage_id); 306 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 307 u8 voltage_type, 308 u16 nominal_voltage, 309 u16 *true_voltage); 310 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 311 u8 voltage_type, u16 *min_voltage); 312 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 313 u8 voltage_type, u16 *max_voltage); 314 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 315 u8 voltage_type, u8 voltage_mode, 316 struct atom_voltage_table *voltage_table); 317 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 318 u8 voltage_type, u8 voltage_mode); 319 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 320 u32 mem_clock); 321 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 322 u32 mem_clock); 323 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 324 u8 module_index, 325 struct atom_mc_reg_table *reg_table); 326 int radeon_atom_get_memory_info(struct radeon_device *rdev, 327 u8 module_index, struct atom_memory_info *mem_info); 328 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 329 bool gddr5, u8 module_index, 330 struct atom_memory_clock_range_table *mclk_range_table); 331 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 332 u16 voltage_id, u16 *voltage); 333 void rs690_pm_info(struct radeon_device *rdev); 334 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 335 unsigned *bankh, unsigned *mtaspect, 336 unsigned *tile_split); 337 338 /* 339 * Fences. 340 */ 341 struct radeon_fence_driver { 342 uint32_t scratch_reg; 343 uint64_t gpu_addr; 344 volatile uint32_t *cpu_addr; 345 /* sync_seq is protected by ring emission lock */ 346 uint64_t sync_seq[RADEON_NUM_RINGS]; 347 atomic64_t last_seq; 348 bool initialized; 349 }; 350 351 struct radeon_fence { 352 struct radeon_device *rdev; 353 struct kref kref; 354 /* protected by radeon_fence.lock */ 355 uint64_t seq; 356 /* RB, DMA, etc. */ 357 unsigned ring; 358 }; 359 360 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 361 int radeon_fence_driver_init(struct radeon_device *rdev); 362 void radeon_fence_driver_fini(struct radeon_device *rdev); 363 void radeon_fence_driver_force_completion(struct radeon_device *rdev); 364 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 365 void radeon_fence_process(struct radeon_device *rdev, int ring); 366 bool radeon_fence_signaled(struct radeon_fence *fence); 367 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 368 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 369 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 370 int radeon_fence_wait_any(struct radeon_device *rdev, 371 struct radeon_fence **fences, 372 bool intr); 373 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 374 void radeon_fence_unref(struct radeon_fence **fence); 375 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 376 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 377 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 378 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 379 struct radeon_fence *b) 380 { 381 if (!a) { 382 return b; 383 } 384 385 if (!b) { 386 return a; 387 } 388 389 BUG_ON(a->ring != b->ring); 390 391 if (a->seq > b->seq) { 392 return a; 393 } else { 394 return b; 395 } 396 } 397 398 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 399 struct radeon_fence *b) 400 { 401 if (!a) { 402 return false; 403 } 404 405 if (!b) { 406 return true; 407 } 408 409 BUG_ON(a->ring != b->ring); 410 411 return a->seq < b->seq; 412 } 413 414 /* 415 * Tiling registers 416 */ 417 struct radeon_surface_reg { 418 struct radeon_bo *bo; 419 }; 420 421 #define RADEON_GEM_MAX_SURFACES 8 422 423 /* 424 * TTM. 425 */ 426 struct radeon_mman { 427 struct ttm_bo_global_ref bo_global_ref; 428 struct drm_global_reference mem_global_ref; 429 struct ttm_bo_device bdev; 430 bool mem_global_referenced; 431 bool initialized; 432 433 #if defined(CONFIG_DEBUG_FS) 434 struct dentry *vram; 435 struct dentry *gtt; 436 #endif 437 }; 438 439 /* bo virtual address in a specific vm */ 440 struct radeon_bo_va { 441 /* protected by bo being reserved */ 442 struct list_head bo_list; 443 uint64_t soffset; 444 uint64_t eoffset; 445 uint32_t flags; 446 bool valid; 447 unsigned ref_count; 448 449 /* protected by vm mutex */ 450 struct list_head vm_list; 451 452 /* constant after initialization */ 453 struct radeon_vm *vm; 454 struct radeon_bo *bo; 455 }; 456 457 struct radeon_bo { 458 /* Protected by gem.mutex */ 459 struct list_head list; 460 /* Protected by tbo.reserved */ 461 u32 initial_domain; 462 u32 placements[3]; 463 struct ttm_placement placement; 464 struct ttm_buffer_object tbo; 465 struct ttm_bo_kmap_obj kmap; 466 unsigned pin_count; 467 void *kptr; 468 u32 tiling_flags; 469 u32 pitch; 470 int surface_reg; 471 /* list of all virtual address to which this bo 472 * is associated to 473 */ 474 struct list_head va; 475 /* Constant after initialization */ 476 struct radeon_device *rdev; 477 struct drm_gem_object gem_base; 478 479 struct ttm_bo_kmap_obj dma_buf_vmap; 480 pid_t pid; 481 }; 482 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 483 484 int radeon_gem_debugfs_init(struct radeon_device *rdev); 485 486 /* sub-allocation manager, it has to be protected by another lock. 487 * By conception this is an helper for other part of the driver 488 * like the indirect buffer or semaphore, which both have their 489 * locking. 490 * 491 * Principe is simple, we keep a list of sub allocation in offset 492 * order (first entry has offset == 0, last entry has the highest 493 * offset). 494 * 495 * When allocating new object we first check if there is room at 496 * the end total_size - (last_object_offset + last_object_size) >= 497 * alloc_size. If so we allocate new object there. 498 * 499 * When there is not enough room at the end, we start waiting for 500 * each sub object until we reach object_offset+object_size >= 501 * alloc_size, this object then become the sub object we return. 502 * 503 * Alignment can't be bigger than page size. 504 * 505 * Hole are not considered for allocation to keep things simple. 506 * Assumption is that there won't be hole (all object on same 507 * alignment). 508 */ 509 struct radeon_sa_manager { 510 wait_queue_head_t wq; 511 struct radeon_bo *bo; 512 struct list_head *hole; 513 struct list_head flist[RADEON_NUM_RINGS]; 514 struct list_head olist; 515 unsigned size; 516 uint64_t gpu_addr; 517 void *cpu_ptr; 518 uint32_t domain; 519 uint32_t align; 520 }; 521 522 struct radeon_sa_bo; 523 524 /* sub-allocation buffer */ 525 struct radeon_sa_bo { 526 struct list_head olist; 527 struct list_head flist; 528 struct radeon_sa_manager *manager; 529 unsigned soffset; 530 unsigned eoffset; 531 struct radeon_fence *fence; 532 }; 533 534 /* 535 * GEM objects. 536 */ 537 struct radeon_gem { 538 struct mutex mutex; 539 struct list_head objects; 540 }; 541 542 int radeon_gem_init(struct radeon_device *rdev); 543 void radeon_gem_fini(struct radeon_device *rdev); 544 int radeon_gem_object_create(struct radeon_device *rdev, int size, 545 int alignment, int initial_domain, 546 bool discardable, bool kernel, 547 struct drm_gem_object **obj); 548 549 int radeon_mode_dumb_create(struct drm_file *file_priv, 550 struct drm_device *dev, 551 struct drm_mode_create_dumb *args); 552 int radeon_mode_dumb_mmap(struct drm_file *filp, 553 struct drm_device *dev, 554 uint32_t handle, uint64_t *offset_p); 555 556 /* 557 * Semaphores. 558 */ 559 struct radeon_semaphore { 560 struct radeon_sa_bo *sa_bo; 561 signed waiters; 562 uint64_t gpu_addr; 563 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 564 }; 565 566 int radeon_semaphore_create(struct radeon_device *rdev, 567 struct radeon_semaphore **semaphore); 568 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 569 struct radeon_semaphore *semaphore); 570 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 571 struct radeon_semaphore *semaphore); 572 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore, 573 struct radeon_fence *fence); 574 int radeon_semaphore_sync_rings(struct radeon_device *rdev, 575 struct radeon_semaphore *semaphore, 576 int waiting_ring); 577 void radeon_semaphore_free(struct radeon_device *rdev, 578 struct radeon_semaphore **semaphore, 579 struct radeon_fence *fence); 580 581 /* 582 * GART structures, functions & helpers 583 */ 584 struct radeon_mc; 585 586 #define RADEON_GPU_PAGE_SIZE 4096 587 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 588 #define RADEON_GPU_PAGE_SHIFT 12 589 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 590 591 struct radeon_gart { 592 dma_addr_t table_addr; 593 struct radeon_bo *robj; 594 void *ptr; 595 unsigned num_gpu_pages; 596 unsigned num_cpu_pages; 597 unsigned table_size; 598 struct page **pages; 599 dma_addr_t *pages_addr; 600 bool ready; 601 }; 602 603 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 604 void radeon_gart_table_ram_free(struct radeon_device *rdev); 605 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 606 void radeon_gart_table_vram_free(struct radeon_device *rdev); 607 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 608 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 609 int radeon_gart_init(struct radeon_device *rdev); 610 void radeon_gart_fini(struct radeon_device *rdev); 611 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 612 int pages); 613 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 614 int pages, struct page **pagelist, 615 dma_addr_t *dma_addr); 616 void radeon_gart_restore(struct radeon_device *rdev); 617 618 619 /* 620 * GPU MC structures, functions & helpers 621 */ 622 struct radeon_mc { 623 resource_size_t aper_size; 624 resource_size_t aper_base; 625 resource_size_t agp_base; 626 /* for some chips with <= 32MB we need to lie 627 * about vram size near mc fb location */ 628 u64 mc_vram_size; 629 u64 visible_vram_size; 630 u64 gtt_size; 631 u64 gtt_start; 632 u64 gtt_end; 633 u64 vram_start; 634 u64 vram_end; 635 unsigned vram_width; 636 u64 real_vram_size; 637 int vram_mtrr; 638 bool vram_is_ddr; 639 bool igp_sideport_enabled; 640 u64 gtt_base_align; 641 u64 mc_mask; 642 }; 643 644 bool radeon_combios_sideport_present(struct radeon_device *rdev); 645 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 646 647 /* 648 * GPU scratch registers structures, functions & helpers 649 */ 650 struct radeon_scratch { 651 unsigned num_reg; 652 uint32_t reg_base; 653 bool free[32]; 654 uint32_t reg[32]; 655 }; 656 657 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 658 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 659 660 /* 661 * GPU doorbell structures, functions & helpers 662 */ 663 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 664 665 struct radeon_doorbell { 666 /* doorbell mmio */ 667 resource_size_t base; 668 resource_size_t size; 669 u32 __iomem *ptr; 670 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 671 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)]; 672 }; 673 674 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 675 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 676 677 /* 678 * IRQS. 679 */ 680 681 struct radeon_flip_work { 682 struct work_struct flip_work; 683 struct work_struct unpin_work; 684 struct radeon_device *rdev; 685 int crtc_id; 686 struct drm_framebuffer *fb; 687 struct drm_pending_vblank_event *event; 688 struct radeon_bo *old_rbo; 689 struct radeon_bo *new_rbo; 690 struct radeon_fence *fence; 691 }; 692 693 struct r500_irq_stat_regs { 694 u32 disp_int; 695 u32 hdmi0_status; 696 }; 697 698 struct r600_irq_stat_regs { 699 u32 disp_int; 700 u32 disp_int_cont; 701 u32 disp_int_cont2; 702 u32 d1grph_int; 703 u32 d2grph_int; 704 u32 hdmi0_status; 705 u32 hdmi1_status; 706 }; 707 708 struct evergreen_irq_stat_regs { 709 u32 disp_int; 710 u32 disp_int_cont; 711 u32 disp_int_cont2; 712 u32 disp_int_cont3; 713 u32 disp_int_cont4; 714 u32 disp_int_cont5; 715 u32 d1grph_int; 716 u32 d2grph_int; 717 u32 d3grph_int; 718 u32 d4grph_int; 719 u32 d5grph_int; 720 u32 d6grph_int; 721 u32 afmt_status1; 722 u32 afmt_status2; 723 u32 afmt_status3; 724 u32 afmt_status4; 725 u32 afmt_status5; 726 u32 afmt_status6; 727 }; 728 729 struct cik_irq_stat_regs { 730 u32 disp_int; 731 u32 disp_int_cont; 732 u32 disp_int_cont2; 733 u32 disp_int_cont3; 734 u32 disp_int_cont4; 735 u32 disp_int_cont5; 736 u32 disp_int_cont6; 737 u32 d1grph_int; 738 u32 d2grph_int; 739 u32 d3grph_int; 740 u32 d4grph_int; 741 u32 d5grph_int; 742 u32 d6grph_int; 743 }; 744 745 union radeon_irq_stat_regs { 746 struct r500_irq_stat_regs r500; 747 struct r600_irq_stat_regs r600; 748 struct evergreen_irq_stat_regs evergreen; 749 struct cik_irq_stat_regs cik; 750 }; 751 752 #define RADEON_MAX_HPD_PINS 7 753 #define RADEON_MAX_CRTCS 6 754 #define RADEON_MAX_AFMT_BLOCKS 7 755 756 struct radeon_irq { 757 bool installed; 758 spinlock_t lock; 759 atomic_t ring_int[RADEON_NUM_RINGS]; 760 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 761 atomic_t pflip[RADEON_MAX_CRTCS]; 762 wait_queue_head_t vblank_queue; 763 bool hpd[RADEON_MAX_HPD_PINS]; 764 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 765 union radeon_irq_stat_regs stat_regs; 766 bool dpm_thermal; 767 }; 768 769 int radeon_irq_kms_init(struct radeon_device *rdev); 770 void radeon_irq_kms_fini(struct radeon_device *rdev); 771 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 772 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 773 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 774 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 775 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 776 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 777 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 778 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 779 780 /* 781 * CP & rings. 782 */ 783 784 struct radeon_ib { 785 struct radeon_sa_bo *sa_bo; 786 uint32_t length_dw; 787 uint64_t gpu_addr; 788 uint32_t *ptr; 789 int ring; 790 struct radeon_fence *fence; 791 struct radeon_vm *vm; 792 bool is_const_ib; 793 struct radeon_semaphore *semaphore; 794 }; 795 796 struct radeon_ring { 797 struct radeon_bo *ring_obj; 798 volatile uint32_t *ring; 799 unsigned rptr_offs; 800 unsigned rptr_save_reg; 801 u64 next_rptr_gpu_addr; 802 volatile u32 *next_rptr_cpu_addr; 803 unsigned wptr; 804 unsigned wptr_old; 805 unsigned ring_size; 806 unsigned ring_free_dw; 807 int count_dw; 808 atomic_t last_rptr; 809 atomic64_t last_activity; 810 uint64_t gpu_addr; 811 uint32_t align_mask; 812 uint32_t ptr_mask; 813 bool ready; 814 u32 nop; 815 u32 idx; 816 u64 last_semaphore_signal_addr; 817 u64 last_semaphore_wait_addr; 818 /* for CIK queues */ 819 u32 me; 820 u32 pipe; 821 u32 queue; 822 struct radeon_bo *mqd_obj; 823 u32 doorbell_index; 824 unsigned wptr_offs; 825 }; 826 827 struct radeon_mec { 828 struct radeon_bo *hpd_eop_obj; 829 u64 hpd_eop_gpu_addr; 830 u32 num_pipe; 831 u32 num_mec; 832 u32 num_queue; 833 }; 834 835 /* 836 * VM 837 */ 838 839 /* maximum number of VMIDs */ 840 #define RADEON_NUM_VM 16 841 842 /* number of entries in page table */ 843 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 844 845 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 846 #define RADEON_VM_PTB_ALIGN_SIZE 32768 847 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 848 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 849 850 #define R600_PTE_VALID (1 << 0) 851 #define R600_PTE_SYSTEM (1 << 1) 852 #define R600_PTE_SNOOPED (1 << 2) 853 #define R600_PTE_READABLE (1 << 5) 854 #define R600_PTE_WRITEABLE (1 << 6) 855 856 /* PTE (Page Table Entry) fragment field for different page sizes */ 857 #define R600_PTE_FRAG_4KB (0 << 7) 858 #define R600_PTE_FRAG_64KB (4 << 7) 859 #define R600_PTE_FRAG_256KB (6 << 7) 860 861 /* flags used for GART page table entries on R600+ */ 862 #define R600_PTE_GART ( R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED \ 863 | R600_PTE_READABLE | R600_PTE_WRITEABLE) 864 865 struct radeon_vm_pt { 866 struct radeon_bo *bo; 867 uint64_t addr; 868 }; 869 870 struct radeon_vm { 871 struct list_head va; 872 unsigned id; 873 874 /* contains the page directory */ 875 struct radeon_bo *page_directory; 876 uint64_t pd_gpu_addr; 877 unsigned max_pde_used; 878 879 /* array of page tables, one for each page directory entry */ 880 struct radeon_vm_pt *page_tables; 881 882 struct mutex mutex; 883 /* last fence for cs using this vm */ 884 struct radeon_fence *fence; 885 /* last flush or NULL if we still need to flush */ 886 struct radeon_fence *last_flush; 887 /* last use of vmid */ 888 struct radeon_fence *last_id_use; 889 }; 890 891 struct radeon_vm_manager { 892 struct radeon_fence *active[RADEON_NUM_VM]; 893 uint32_t max_pfn; 894 /* number of VMIDs */ 895 unsigned nvm; 896 /* vram base address for page table entry */ 897 u64 vram_base_offset; 898 /* is vm enabled? */ 899 bool enabled; 900 }; 901 902 /* 903 * file private structure 904 */ 905 struct radeon_fpriv { 906 struct radeon_vm vm; 907 }; 908 909 /* 910 * R6xx+ IH ring 911 */ 912 struct r600_ih { 913 struct radeon_bo *ring_obj; 914 volatile uint32_t *ring; 915 unsigned rptr; 916 unsigned ring_size; 917 uint64_t gpu_addr; 918 uint32_t ptr_mask; 919 atomic_t lock; 920 bool enabled; 921 }; 922 923 /* 924 * RLC stuff 925 */ 926 #include "clearstate_defs.h" 927 928 struct radeon_rlc { 929 /* for power gating */ 930 struct radeon_bo *save_restore_obj; 931 uint64_t save_restore_gpu_addr; 932 volatile uint32_t *sr_ptr; 933 const u32 *reg_list; 934 u32 reg_list_size; 935 /* for clear state */ 936 struct radeon_bo *clear_state_obj; 937 uint64_t clear_state_gpu_addr; 938 volatile uint32_t *cs_ptr; 939 const struct cs_section_def *cs_data; 940 u32 clear_state_size; 941 /* for cp tables */ 942 struct radeon_bo *cp_table_obj; 943 uint64_t cp_table_gpu_addr; 944 volatile uint32_t *cp_table_ptr; 945 u32 cp_table_size; 946 }; 947 948 int radeon_ib_get(struct radeon_device *rdev, int ring, 949 struct radeon_ib *ib, struct radeon_vm *vm, 950 unsigned size); 951 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 952 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 953 struct radeon_ib *const_ib); 954 int radeon_ib_pool_init(struct radeon_device *rdev); 955 void radeon_ib_pool_fini(struct radeon_device *rdev); 956 int radeon_ib_ring_tests(struct radeon_device *rdev); 957 /* Ring access between begin & end cannot sleep */ 958 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 959 struct radeon_ring *ring); 960 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 961 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 962 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 963 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); 964 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); 965 void radeon_ring_undo(struct radeon_ring *ring); 966 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 967 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 968 void radeon_ring_lockup_update(struct radeon_device *rdev, 969 struct radeon_ring *ring); 970 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 971 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 972 uint32_t **data); 973 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 974 unsigned size, uint32_t *data); 975 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 976 unsigned rptr_offs, u32 nop); 977 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 978 979 980 /* r600 async dma */ 981 void r600_dma_stop(struct radeon_device *rdev); 982 int r600_dma_resume(struct radeon_device *rdev); 983 void r600_dma_fini(struct radeon_device *rdev); 984 985 void cayman_dma_stop(struct radeon_device *rdev); 986 int cayman_dma_resume(struct radeon_device *rdev); 987 void cayman_dma_fini(struct radeon_device *rdev); 988 989 /* 990 * CS. 991 */ 992 struct radeon_cs_reloc { 993 struct drm_gem_object *gobj; 994 struct radeon_bo *robj; 995 struct ttm_validate_buffer tv; 996 uint64_t gpu_offset; 997 unsigned prefered_domains; 998 unsigned allowed_domains; 999 uint32_t tiling_flags; 1000 uint32_t handle; 1001 }; 1002 1003 struct radeon_cs_chunk { 1004 uint32_t chunk_id; 1005 uint32_t length_dw; 1006 uint32_t *kdata; 1007 void __user *user_ptr; 1008 }; 1009 1010 struct radeon_cs_parser { 1011 struct device *dev; 1012 struct radeon_device *rdev; 1013 struct drm_file *filp; 1014 /* chunks */ 1015 unsigned nchunks; 1016 struct radeon_cs_chunk *chunks; 1017 uint64_t *chunks_array; 1018 /* IB */ 1019 unsigned idx; 1020 /* relocations */ 1021 unsigned nrelocs; 1022 struct radeon_cs_reloc *relocs; 1023 struct radeon_cs_reloc **relocs_ptr; 1024 struct radeon_cs_reloc *vm_bos; 1025 struct list_head validated; 1026 unsigned dma_reloc_idx; 1027 /* indices of various chunks */ 1028 int chunk_ib_idx; 1029 int chunk_relocs_idx; 1030 int chunk_flags_idx; 1031 int chunk_const_ib_idx; 1032 struct radeon_ib ib; 1033 struct radeon_ib const_ib; 1034 void *track; 1035 unsigned family; 1036 int parser_error; 1037 u32 cs_flags; 1038 u32 ring; 1039 s32 priority; 1040 struct ww_acquire_ctx ticket; 1041 }; 1042 1043 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1044 { 1045 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 1046 1047 if (ibc->kdata) 1048 return ibc->kdata[idx]; 1049 return p->ib.ptr[idx]; 1050 } 1051 1052 1053 struct radeon_cs_packet { 1054 unsigned idx; 1055 unsigned type; 1056 unsigned reg; 1057 unsigned opcode; 1058 int count; 1059 unsigned one_reg_wr; 1060 }; 1061 1062 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1063 struct radeon_cs_packet *pkt, 1064 unsigned idx, unsigned reg); 1065 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1066 struct radeon_cs_packet *pkt); 1067 1068 1069 /* 1070 * AGP 1071 */ 1072 int radeon_agp_init(struct radeon_device *rdev); 1073 void radeon_agp_resume(struct radeon_device *rdev); 1074 void radeon_agp_suspend(struct radeon_device *rdev); 1075 void radeon_agp_fini(struct radeon_device *rdev); 1076 1077 1078 /* 1079 * Writeback 1080 */ 1081 struct radeon_wb { 1082 struct radeon_bo *wb_obj; 1083 volatile uint32_t *wb; 1084 uint64_t gpu_addr; 1085 bool enabled; 1086 bool use_event; 1087 }; 1088 1089 #define RADEON_WB_SCRATCH_OFFSET 0 1090 #define RADEON_WB_RING0_NEXT_RPTR 256 1091 #define RADEON_WB_CP_RPTR_OFFSET 1024 1092 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1093 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1094 #define R600_WB_DMA_RPTR_OFFSET 1792 1095 #define R600_WB_IH_WPTR_OFFSET 2048 1096 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1097 #define R600_WB_EVENT_OFFSET 3072 1098 #define CIK_WB_CP1_WPTR_OFFSET 3328 1099 #define CIK_WB_CP2_WPTR_OFFSET 3584 1100 1101 /** 1102 * struct radeon_pm - power management datas 1103 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1104 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1105 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1106 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1107 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1108 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1109 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1110 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1111 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1112 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1113 * @needed_bandwidth: current bandwidth needs 1114 * 1115 * It keeps track of various data needed to take powermanagement decision. 1116 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1117 * Equation between gpu/memory clock and available bandwidth is hw dependent 1118 * (type of memory, bus size, efficiency, ...) 1119 */ 1120 1121 enum radeon_pm_method { 1122 PM_METHOD_PROFILE, 1123 PM_METHOD_DYNPM, 1124 PM_METHOD_DPM, 1125 }; 1126 1127 enum radeon_dynpm_state { 1128 DYNPM_STATE_DISABLED, 1129 DYNPM_STATE_MINIMUM, 1130 DYNPM_STATE_PAUSED, 1131 DYNPM_STATE_ACTIVE, 1132 DYNPM_STATE_SUSPENDED, 1133 }; 1134 enum radeon_dynpm_action { 1135 DYNPM_ACTION_NONE, 1136 DYNPM_ACTION_MINIMUM, 1137 DYNPM_ACTION_DOWNCLOCK, 1138 DYNPM_ACTION_UPCLOCK, 1139 DYNPM_ACTION_DEFAULT 1140 }; 1141 1142 enum radeon_voltage_type { 1143 VOLTAGE_NONE = 0, 1144 VOLTAGE_GPIO, 1145 VOLTAGE_VDDC, 1146 VOLTAGE_SW 1147 }; 1148 1149 enum radeon_pm_state_type { 1150 /* not used for dpm */ 1151 POWER_STATE_TYPE_DEFAULT, 1152 POWER_STATE_TYPE_POWERSAVE, 1153 /* user selectable states */ 1154 POWER_STATE_TYPE_BATTERY, 1155 POWER_STATE_TYPE_BALANCED, 1156 POWER_STATE_TYPE_PERFORMANCE, 1157 /* internal states */ 1158 POWER_STATE_TYPE_INTERNAL_UVD, 1159 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1160 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1161 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1162 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1163 POWER_STATE_TYPE_INTERNAL_BOOT, 1164 POWER_STATE_TYPE_INTERNAL_THERMAL, 1165 POWER_STATE_TYPE_INTERNAL_ACPI, 1166 POWER_STATE_TYPE_INTERNAL_ULV, 1167 POWER_STATE_TYPE_INTERNAL_3DPERF, 1168 }; 1169 1170 enum radeon_pm_profile_type { 1171 PM_PROFILE_DEFAULT, 1172 PM_PROFILE_AUTO, 1173 PM_PROFILE_LOW, 1174 PM_PROFILE_MID, 1175 PM_PROFILE_HIGH, 1176 }; 1177 1178 #define PM_PROFILE_DEFAULT_IDX 0 1179 #define PM_PROFILE_LOW_SH_IDX 1 1180 #define PM_PROFILE_MID_SH_IDX 2 1181 #define PM_PROFILE_HIGH_SH_IDX 3 1182 #define PM_PROFILE_LOW_MH_IDX 4 1183 #define PM_PROFILE_MID_MH_IDX 5 1184 #define PM_PROFILE_HIGH_MH_IDX 6 1185 #define PM_PROFILE_MAX 7 1186 1187 struct radeon_pm_profile { 1188 int dpms_off_ps_idx; 1189 int dpms_on_ps_idx; 1190 int dpms_off_cm_idx; 1191 int dpms_on_cm_idx; 1192 }; 1193 1194 enum radeon_int_thermal_type { 1195 THERMAL_TYPE_NONE, 1196 THERMAL_TYPE_EXTERNAL, 1197 THERMAL_TYPE_EXTERNAL_GPIO, 1198 THERMAL_TYPE_RV6XX, 1199 THERMAL_TYPE_RV770, 1200 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1201 THERMAL_TYPE_EVERGREEN, 1202 THERMAL_TYPE_SUMO, 1203 THERMAL_TYPE_NI, 1204 THERMAL_TYPE_SI, 1205 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1206 THERMAL_TYPE_CI, 1207 THERMAL_TYPE_KV, 1208 }; 1209 1210 struct radeon_voltage { 1211 enum radeon_voltage_type type; 1212 /* gpio voltage */ 1213 struct radeon_gpio_rec gpio; 1214 u32 delay; /* delay in usec from voltage drop to sclk change */ 1215 bool active_high; /* voltage drop is active when bit is high */ 1216 /* VDDC voltage */ 1217 u8 vddc_id; /* index into vddc voltage table */ 1218 u8 vddci_id; /* index into vddci voltage table */ 1219 bool vddci_enabled; 1220 /* r6xx+ sw */ 1221 u16 voltage; 1222 /* evergreen+ vddci */ 1223 u16 vddci; 1224 }; 1225 1226 /* clock mode flags */ 1227 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1228 1229 struct radeon_pm_clock_info { 1230 /* memory clock */ 1231 u32 mclk; 1232 /* engine clock */ 1233 u32 sclk; 1234 /* voltage info */ 1235 struct radeon_voltage voltage; 1236 /* standardized clock flags */ 1237 u32 flags; 1238 }; 1239 1240 /* state flags */ 1241 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1242 1243 struct radeon_power_state { 1244 enum radeon_pm_state_type type; 1245 struct radeon_pm_clock_info *clock_info; 1246 /* number of valid clock modes in this power state */ 1247 int num_clock_modes; 1248 struct radeon_pm_clock_info *default_clock_mode; 1249 /* standardized state flags */ 1250 u32 flags; 1251 u32 misc; /* vbios specific flags */ 1252 u32 misc2; /* vbios specific flags */ 1253 int pcie_lanes; /* pcie lanes */ 1254 }; 1255 1256 /* 1257 * Some modes are overclocked by very low value, accept them 1258 */ 1259 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1260 1261 enum radeon_dpm_auto_throttle_src { 1262 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1263 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1264 }; 1265 1266 enum radeon_dpm_event_src { 1267 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1268 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1269 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1270 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1271 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1272 }; 1273 1274 #define RADEON_MAX_VCE_LEVELS 6 1275 1276 enum radeon_vce_level { 1277 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1278 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1279 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1280 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1281 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1282 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1283 }; 1284 1285 struct radeon_ps { 1286 u32 caps; /* vbios flags */ 1287 u32 class; /* vbios flags */ 1288 u32 class2; /* vbios flags */ 1289 /* UVD clocks */ 1290 u32 vclk; 1291 u32 dclk; 1292 /* VCE clocks */ 1293 u32 evclk; 1294 u32 ecclk; 1295 bool vce_active; 1296 enum radeon_vce_level vce_level; 1297 /* asic priv */ 1298 void *ps_priv; 1299 }; 1300 1301 struct radeon_dpm_thermal { 1302 /* thermal interrupt work */ 1303 struct work_struct work; 1304 /* low temperature threshold */ 1305 int min_temp; 1306 /* high temperature threshold */ 1307 int max_temp; 1308 /* was interrupt low to high or high to low */ 1309 bool high_to_low; 1310 }; 1311 1312 enum radeon_clk_action 1313 { 1314 RADEON_SCLK_UP = 1, 1315 RADEON_SCLK_DOWN 1316 }; 1317 1318 struct radeon_blacklist_clocks 1319 { 1320 u32 sclk; 1321 u32 mclk; 1322 enum radeon_clk_action action; 1323 }; 1324 1325 struct radeon_clock_and_voltage_limits { 1326 u32 sclk; 1327 u32 mclk; 1328 u16 vddc; 1329 u16 vddci; 1330 }; 1331 1332 struct radeon_clock_array { 1333 u32 count; 1334 u32 *values; 1335 }; 1336 1337 struct radeon_clock_voltage_dependency_entry { 1338 u32 clk; 1339 u16 v; 1340 }; 1341 1342 struct radeon_clock_voltage_dependency_table { 1343 u32 count; 1344 struct radeon_clock_voltage_dependency_entry *entries; 1345 }; 1346 1347 union radeon_cac_leakage_entry { 1348 struct { 1349 u16 vddc; 1350 u32 leakage; 1351 }; 1352 struct { 1353 u16 vddc1; 1354 u16 vddc2; 1355 u16 vddc3; 1356 }; 1357 }; 1358 1359 struct radeon_cac_leakage_table { 1360 u32 count; 1361 union radeon_cac_leakage_entry *entries; 1362 }; 1363 1364 struct radeon_phase_shedding_limits_entry { 1365 u16 voltage; 1366 u32 sclk; 1367 u32 mclk; 1368 }; 1369 1370 struct radeon_phase_shedding_limits_table { 1371 u32 count; 1372 struct radeon_phase_shedding_limits_entry *entries; 1373 }; 1374 1375 struct radeon_uvd_clock_voltage_dependency_entry { 1376 u32 vclk; 1377 u32 dclk; 1378 u16 v; 1379 }; 1380 1381 struct radeon_uvd_clock_voltage_dependency_table { 1382 u8 count; 1383 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1384 }; 1385 1386 struct radeon_vce_clock_voltage_dependency_entry { 1387 u32 ecclk; 1388 u32 evclk; 1389 u16 v; 1390 }; 1391 1392 struct radeon_vce_clock_voltage_dependency_table { 1393 u8 count; 1394 struct radeon_vce_clock_voltage_dependency_entry *entries; 1395 }; 1396 1397 struct radeon_ppm_table { 1398 u8 ppm_design; 1399 u16 cpu_core_number; 1400 u32 platform_tdp; 1401 u32 small_ac_platform_tdp; 1402 u32 platform_tdc; 1403 u32 small_ac_platform_tdc; 1404 u32 apu_tdp; 1405 u32 dgpu_tdp; 1406 u32 dgpu_ulv_power; 1407 u32 tj_max; 1408 }; 1409 1410 struct radeon_cac_tdp_table { 1411 u16 tdp; 1412 u16 configurable_tdp; 1413 u16 tdc; 1414 u16 battery_power_limit; 1415 u16 small_power_limit; 1416 u16 low_cac_leakage; 1417 u16 high_cac_leakage; 1418 u16 maximum_power_delivery_limit; 1419 }; 1420 1421 struct radeon_dpm_dynamic_state { 1422 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1423 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1424 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1425 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1426 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1427 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1428 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1429 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1430 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1431 struct radeon_clock_array valid_sclk_values; 1432 struct radeon_clock_array valid_mclk_values; 1433 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1434 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1435 u32 mclk_sclk_ratio; 1436 u32 sclk_mclk_delta; 1437 u16 vddc_vddci_delta; 1438 u16 min_vddc_for_pcie_gen2; 1439 struct radeon_cac_leakage_table cac_leakage_table; 1440 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1441 struct radeon_ppm_table *ppm_table; 1442 struct radeon_cac_tdp_table *cac_tdp_table; 1443 }; 1444 1445 struct radeon_dpm_fan { 1446 u16 t_min; 1447 u16 t_med; 1448 u16 t_high; 1449 u16 pwm_min; 1450 u16 pwm_med; 1451 u16 pwm_high; 1452 u8 t_hyst; 1453 u32 cycle_delay; 1454 u16 t_max; 1455 bool ucode_fan_control; 1456 }; 1457 1458 enum radeon_pcie_gen { 1459 RADEON_PCIE_GEN1 = 0, 1460 RADEON_PCIE_GEN2 = 1, 1461 RADEON_PCIE_GEN3 = 2, 1462 RADEON_PCIE_GEN_INVALID = 0xffff 1463 }; 1464 1465 enum radeon_dpm_forced_level { 1466 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1467 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1468 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1469 }; 1470 1471 struct radeon_vce_state { 1472 /* vce clocks */ 1473 u32 evclk; 1474 u32 ecclk; 1475 /* gpu clocks */ 1476 u32 sclk; 1477 u32 mclk; 1478 u8 clk_idx; 1479 u8 pstate; 1480 }; 1481 1482 struct radeon_dpm { 1483 struct radeon_ps *ps; 1484 /* number of valid power states */ 1485 int num_ps; 1486 /* current power state that is active */ 1487 struct radeon_ps *current_ps; 1488 /* requested power state */ 1489 struct radeon_ps *requested_ps; 1490 /* boot up power state */ 1491 struct radeon_ps *boot_ps; 1492 /* default uvd power state */ 1493 struct radeon_ps *uvd_ps; 1494 /* vce requirements */ 1495 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1496 enum radeon_vce_level vce_level; 1497 enum radeon_pm_state_type state; 1498 enum radeon_pm_state_type user_state; 1499 u32 platform_caps; 1500 u32 voltage_response_time; 1501 u32 backbias_response_time; 1502 void *priv; 1503 u32 new_active_crtcs; 1504 int new_active_crtc_count; 1505 u32 current_active_crtcs; 1506 int current_active_crtc_count; 1507 struct radeon_dpm_dynamic_state dyn_state; 1508 struct radeon_dpm_fan fan; 1509 u32 tdp_limit; 1510 u32 near_tdp_limit; 1511 u32 near_tdp_limit_adjusted; 1512 u32 sq_ramping_threshold; 1513 u32 cac_leakage; 1514 u16 tdp_od_limit; 1515 u32 tdp_adjustment; 1516 u16 load_line_slope; 1517 bool power_control; 1518 bool ac_power; 1519 /* special states active */ 1520 bool thermal_active; 1521 bool uvd_active; 1522 bool vce_active; 1523 /* thermal handling */ 1524 struct radeon_dpm_thermal thermal; 1525 /* forced levels */ 1526 enum radeon_dpm_forced_level forced_level; 1527 /* track UVD streams */ 1528 unsigned sd; 1529 unsigned hd; 1530 }; 1531 1532 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1533 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1534 1535 struct radeon_pm { 1536 struct mutex mutex; 1537 /* write locked while reprogramming mclk */ 1538 struct rw_semaphore mclk_lock; 1539 u32 active_crtcs; 1540 int active_crtc_count; 1541 int req_vblank; 1542 bool vblank_sync; 1543 fixed20_12 max_bandwidth; 1544 fixed20_12 igp_sideport_mclk; 1545 fixed20_12 igp_system_mclk; 1546 fixed20_12 igp_ht_link_clk; 1547 fixed20_12 igp_ht_link_width; 1548 fixed20_12 k8_bandwidth; 1549 fixed20_12 sideport_bandwidth; 1550 fixed20_12 ht_bandwidth; 1551 fixed20_12 core_bandwidth; 1552 fixed20_12 sclk; 1553 fixed20_12 mclk; 1554 fixed20_12 needed_bandwidth; 1555 struct radeon_power_state *power_state; 1556 /* number of valid power states */ 1557 int num_power_states; 1558 int current_power_state_index; 1559 int current_clock_mode_index; 1560 int requested_power_state_index; 1561 int requested_clock_mode_index; 1562 int default_power_state_index; 1563 u32 current_sclk; 1564 u32 current_mclk; 1565 u16 current_vddc; 1566 u16 current_vddci; 1567 u32 default_sclk; 1568 u32 default_mclk; 1569 u16 default_vddc; 1570 u16 default_vddci; 1571 struct radeon_i2c_chan *i2c_bus; 1572 /* selected pm method */ 1573 enum radeon_pm_method pm_method; 1574 /* dynpm power management */ 1575 struct delayed_work dynpm_idle_work; 1576 enum radeon_dynpm_state dynpm_state; 1577 enum radeon_dynpm_action dynpm_planned_action; 1578 unsigned long dynpm_action_timeout; 1579 bool dynpm_can_upclock; 1580 bool dynpm_can_downclock; 1581 /* profile-based power management */ 1582 enum radeon_pm_profile_type profile; 1583 int profile_index; 1584 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1585 /* internal thermal controller on rv6xx+ */ 1586 enum radeon_int_thermal_type int_thermal_type; 1587 struct device *int_hwmon_dev; 1588 /* dpm */ 1589 bool dpm_enabled; 1590 struct radeon_dpm dpm; 1591 }; 1592 1593 int radeon_pm_get_type_index(struct radeon_device *rdev, 1594 enum radeon_pm_state_type ps_type, 1595 int instance); 1596 /* 1597 * UVD 1598 */ 1599 #define RADEON_MAX_UVD_HANDLES 10 1600 #define RADEON_UVD_STACK_SIZE (1024*1024) 1601 #define RADEON_UVD_HEAP_SIZE (1024*1024) 1602 1603 struct radeon_uvd { 1604 struct radeon_bo *vcpu_bo; 1605 void *cpu_addr; 1606 uint64_t gpu_addr; 1607 void *saved_bo; 1608 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1609 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1610 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1611 struct delayed_work idle_work; 1612 }; 1613 1614 int radeon_uvd_init(struct radeon_device *rdev); 1615 void radeon_uvd_fini(struct radeon_device *rdev); 1616 int radeon_uvd_suspend(struct radeon_device *rdev); 1617 int radeon_uvd_resume(struct radeon_device *rdev); 1618 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1619 uint32_t handle, struct radeon_fence **fence); 1620 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1621 uint32_t handle, struct radeon_fence **fence); 1622 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo); 1623 void radeon_uvd_free_handles(struct radeon_device *rdev, 1624 struct drm_file *filp); 1625 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1626 void radeon_uvd_note_usage(struct radeon_device *rdev); 1627 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1628 unsigned vclk, unsigned dclk, 1629 unsigned vco_min, unsigned vco_max, 1630 unsigned fb_factor, unsigned fb_mask, 1631 unsigned pd_min, unsigned pd_max, 1632 unsigned pd_even, 1633 unsigned *optimal_fb_div, 1634 unsigned *optimal_vclk_div, 1635 unsigned *optimal_dclk_div); 1636 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1637 unsigned cg_upll_func_cntl); 1638 1639 /* 1640 * VCE 1641 */ 1642 #define RADEON_MAX_VCE_HANDLES 16 1643 #define RADEON_VCE_STACK_SIZE (1024*1024) 1644 #define RADEON_VCE_HEAP_SIZE (4*1024*1024) 1645 1646 struct radeon_vce { 1647 struct radeon_bo *vcpu_bo; 1648 uint64_t gpu_addr; 1649 unsigned fw_version; 1650 unsigned fb_version; 1651 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1652 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1653 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1654 struct delayed_work idle_work; 1655 }; 1656 1657 int radeon_vce_init(struct radeon_device *rdev); 1658 void radeon_vce_fini(struct radeon_device *rdev); 1659 int radeon_vce_suspend(struct radeon_device *rdev); 1660 int radeon_vce_resume(struct radeon_device *rdev); 1661 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1662 uint32_t handle, struct radeon_fence **fence); 1663 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1664 uint32_t handle, struct radeon_fence **fence); 1665 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1666 void radeon_vce_note_usage(struct radeon_device *rdev); 1667 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1668 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1669 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1670 struct radeon_ring *ring, 1671 struct radeon_semaphore *semaphore, 1672 bool emit_wait); 1673 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1674 void radeon_vce_fence_emit(struct radeon_device *rdev, 1675 struct radeon_fence *fence); 1676 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1677 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1678 1679 struct r600_audio_pin { 1680 int channels; 1681 int rate; 1682 int bits_per_sample; 1683 u8 status_bits; 1684 u8 category_code; 1685 u32 offset; 1686 bool connected; 1687 u32 id; 1688 }; 1689 1690 struct r600_audio { 1691 bool enabled; 1692 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1693 int num_pins; 1694 }; 1695 1696 /* 1697 * Benchmarking 1698 */ 1699 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1700 1701 1702 /* 1703 * Testing 1704 */ 1705 void radeon_test_moves(struct radeon_device *rdev); 1706 void radeon_test_ring_sync(struct radeon_device *rdev, 1707 struct radeon_ring *cpA, 1708 struct radeon_ring *cpB); 1709 void radeon_test_syncing(struct radeon_device *rdev); 1710 1711 1712 /* 1713 * Debugfs 1714 */ 1715 struct radeon_debugfs { 1716 struct drm_info_list *files; 1717 unsigned num_files; 1718 }; 1719 1720 int radeon_debugfs_add_files(struct radeon_device *rdev, 1721 struct drm_info_list *files, 1722 unsigned nfiles); 1723 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1724 1725 /* 1726 * ASIC ring specific functions. 1727 */ 1728 struct radeon_asic_ring { 1729 /* ring read/write ptr handling */ 1730 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1731 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1732 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1733 1734 /* validating and patching of IBs */ 1735 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1736 int (*cs_parse)(struct radeon_cs_parser *p); 1737 1738 /* command emmit functions */ 1739 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1740 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1741 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1742 struct radeon_semaphore *semaphore, bool emit_wait); 1743 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 1744 1745 /* testing functions */ 1746 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1747 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1748 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1749 1750 /* deprecated */ 1751 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1752 }; 1753 1754 /* 1755 * ASIC specific functions. 1756 */ 1757 struct radeon_asic { 1758 int (*init)(struct radeon_device *rdev); 1759 void (*fini)(struct radeon_device *rdev); 1760 int (*resume)(struct radeon_device *rdev); 1761 int (*suspend)(struct radeon_device *rdev); 1762 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1763 int (*asic_reset)(struct radeon_device *rdev); 1764 /* ioctl hw specific callback. Some hw might want to perform special 1765 * operation on specific ioctl. For instance on wait idle some hw 1766 * might want to perform and HDP flush through MMIO as it seems that 1767 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed 1768 * through ring. 1769 */ 1770 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); 1771 /* check if 3D engine is idle */ 1772 bool (*gui_idle)(struct radeon_device *rdev); 1773 /* wait for mc_idle */ 1774 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1775 /* get the reference clock */ 1776 u32 (*get_xclk)(struct radeon_device *rdev); 1777 /* get the gpu clock counter */ 1778 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1779 /* gart */ 1780 struct { 1781 void (*tlb_flush)(struct radeon_device *rdev); 1782 void (*set_page)(struct radeon_device *rdev, unsigned i, 1783 uint64_t addr); 1784 } gart; 1785 struct { 1786 int (*init)(struct radeon_device *rdev); 1787 void (*fini)(struct radeon_device *rdev); 1788 void (*set_page)(struct radeon_device *rdev, 1789 struct radeon_ib *ib, 1790 uint64_t pe, 1791 uint64_t addr, unsigned count, 1792 uint32_t incr, uint32_t flags); 1793 } vm; 1794 /* ring specific callbacks */ 1795 struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1796 /* irqs */ 1797 struct { 1798 int (*set)(struct radeon_device *rdev); 1799 int (*process)(struct radeon_device *rdev); 1800 } irq; 1801 /* displays */ 1802 struct { 1803 /* display watermarks */ 1804 void (*bandwidth_update)(struct radeon_device *rdev); 1805 /* get frame count */ 1806 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1807 /* wait for vblank */ 1808 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1809 /* set backlight level */ 1810 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1811 /* get backlight level */ 1812 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1813 /* audio callbacks */ 1814 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1815 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1816 } display; 1817 /* copy functions for bo handling */ 1818 struct { 1819 int (*blit)(struct radeon_device *rdev, 1820 uint64_t src_offset, 1821 uint64_t dst_offset, 1822 unsigned num_gpu_pages, 1823 struct radeon_fence **fence); 1824 u32 blit_ring_index; 1825 int (*dma)(struct radeon_device *rdev, 1826 uint64_t src_offset, 1827 uint64_t dst_offset, 1828 unsigned num_gpu_pages, 1829 struct radeon_fence **fence); 1830 u32 dma_ring_index; 1831 /* method used for bo copy */ 1832 int (*copy)(struct radeon_device *rdev, 1833 uint64_t src_offset, 1834 uint64_t dst_offset, 1835 unsigned num_gpu_pages, 1836 struct radeon_fence **fence); 1837 /* ring used for bo copies */ 1838 u32 copy_ring_index; 1839 } copy; 1840 /* surfaces */ 1841 struct { 1842 int (*set_reg)(struct radeon_device *rdev, int reg, 1843 uint32_t tiling_flags, uint32_t pitch, 1844 uint32_t offset, uint32_t obj_size); 1845 void (*clear_reg)(struct radeon_device *rdev, int reg); 1846 } surface; 1847 /* hotplug detect */ 1848 struct { 1849 void (*init)(struct radeon_device *rdev); 1850 void (*fini)(struct radeon_device *rdev); 1851 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1852 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1853 } hpd; 1854 /* static power management */ 1855 struct { 1856 void (*misc)(struct radeon_device *rdev); 1857 void (*prepare)(struct radeon_device *rdev); 1858 void (*finish)(struct radeon_device *rdev); 1859 void (*init_profile)(struct radeon_device *rdev); 1860 void (*get_dynpm_state)(struct radeon_device *rdev); 1861 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1862 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1863 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1864 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1865 int (*get_pcie_lanes)(struct radeon_device *rdev); 1866 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1867 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1868 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1869 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1870 int (*get_temperature)(struct radeon_device *rdev); 1871 } pm; 1872 /* dynamic power management */ 1873 struct { 1874 int (*init)(struct radeon_device *rdev); 1875 void (*setup_asic)(struct radeon_device *rdev); 1876 int (*enable)(struct radeon_device *rdev); 1877 int (*late_enable)(struct radeon_device *rdev); 1878 void (*disable)(struct radeon_device *rdev); 1879 int (*pre_set_power_state)(struct radeon_device *rdev); 1880 int (*set_power_state)(struct radeon_device *rdev); 1881 void (*post_set_power_state)(struct radeon_device *rdev); 1882 void (*display_configuration_changed)(struct radeon_device *rdev); 1883 void (*fini)(struct radeon_device *rdev); 1884 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1885 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1886 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1887 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1888 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 1889 bool (*vblank_too_short)(struct radeon_device *rdev); 1890 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 1891 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 1892 } dpm; 1893 /* pageflipping */ 1894 struct { 1895 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1896 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 1897 } pflip; 1898 }; 1899 1900 /* 1901 * Asic structures 1902 */ 1903 struct r100_asic { 1904 const unsigned *reg_safe_bm; 1905 unsigned reg_safe_bm_size; 1906 u32 hdp_cntl; 1907 }; 1908 1909 struct r300_asic { 1910 const unsigned *reg_safe_bm; 1911 unsigned reg_safe_bm_size; 1912 u32 resync_scratch; 1913 u32 hdp_cntl; 1914 }; 1915 1916 struct r600_asic { 1917 unsigned max_pipes; 1918 unsigned max_tile_pipes; 1919 unsigned max_simds; 1920 unsigned max_backends; 1921 unsigned max_gprs; 1922 unsigned max_threads; 1923 unsigned max_stack_entries; 1924 unsigned max_hw_contexts; 1925 unsigned max_gs_threads; 1926 unsigned sx_max_export_size; 1927 unsigned sx_max_export_pos_size; 1928 unsigned sx_max_export_smx_size; 1929 unsigned sq_num_cf_insts; 1930 unsigned tiling_nbanks; 1931 unsigned tiling_npipes; 1932 unsigned tiling_group_size; 1933 unsigned tile_config; 1934 unsigned backend_map; 1935 unsigned active_simds; 1936 }; 1937 1938 struct rv770_asic { 1939 unsigned max_pipes; 1940 unsigned max_tile_pipes; 1941 unsigned max_simds; 1942 unsigned max_backends; 1943 unsigned max_gprs; 1944 unsigned max_threads; 1945 unsigned max_stack_entries; 1946 unsigned max_hw_contexts; 1947 unsigned max_gs_threads; 1948 unsigned sx_max_export_size; 1949 unsigned sx_max_export_pos_size; 1950 unsigned sx_max_export_smx_size; 1951 unsigned sq_num_cf_insts; 1952 unsigned sx_num_of_sets; 1953 unsigned sc_prim_fifo_size; 1954 unsigned sc_hiz_tile_fifo_size; 1955 unsigned sc_earlyz_tile_fifo_fize; 1956 unsigned tiling_nbanks; 1957 unsigned tiling_npipes; 1958 unsigned tiling_group_size; 1959 unsigned tile_config; 1960 unsigned backend_map; 1961 unsigned active_simds; 1962 }; 1963 1964 struct evergreen_asic { 1965 unsigned num_ses; 1966 unsigned max_pipes; 1967 unsigned max_tile_pipes; 1968 unsigned max_simds; 1969 unsigned max_backends; 1970 unsigned max_gprs; 1971 unsigned max_threads; 1972 unsigned max_stack_entries; 1973 unsigned max_hw_contexts; 1974 unsigned max_gs_threads; 1975 unsigned sx_max_export_size; 1976 unsigned sx_max_export_pos_size; 1977 unsigned sx_max_export_smx_size; 1978 unsigned sq_num_cf_insts; 1979 unsigned sx_num_of_sets; 1980 unsigned sc_prim_fifo_size; 1981 unsigned sc_hiz_tile_fifo_size; 1982 unsigned sc_earlyz_tile_fifo_size; 1983 unsigned tiling_nbanks; 1984 unsigned tiling_npipes; 1985 unsigned tiling_group_size; 1986 unsigned tile_config; 1987 unsigned backend_map; 1988 unsigned active_simds; 1989 }; 1990 1991 struct cayman_asic { 1992 unsigned max_shader_engines; 1993 unsigned max_pipes_per_simd; 1994 unsigned max_tile_pipes; 1995 unsigned max_simds_per_se; 1996 unsigned max_backends_per_se; 1997 unsigned max_texture_channel_caches; 1998 unsigned max_gprs; 1999 unsigned max_threads; 2000 unsigned max_gs_threads; 2001 unsigned max_stack_entries; 2002 unsigned sx_num_of_sets; 2003 unsigned sx_max_export_size; 2004 unsigned sx_max_export_pos_size; 2005 unsigned sx_max_export_smx_size; 2006 unsigned max_hw_contexts; 2007 unsigned sq_num_cf_insts; 2008 unsigned sc_prim_fifo_size; 2009 unsigned sc_hiz_tile_fifo_size; 2010 unsigned sc_earlyz_tile_fifo_size; 2011 2012 unsigned num_shader_engines; 2013 unsigned num_shader_pipes_per_simd; 2014 unsigned num_tile_pipes; 2015 unsigned num_simds_per_se; 2016 unsigned num_backends_per_se; 2017 unsigned backend_disable_mask_per_asic; 2018 unsigned backend_map; 2019 unsigned num_texture_channel_caches; 2020 unsigned mem_max_burst_length_bytes; 2021 unsigned mem_row_size_in_kb; 2022 unsigned shader_engine_tile_size; 2023 unsigned num_gpus; 2024 unsigned multi_gpu_tile_size; 2025 2026 unsigned tile_config; 2027 unsigned active_simds; 2028 }; 2029 2030 struct si_asic { 2031 unsigned max_shader_engines; 2032 unsigned max_tile_pipes; 2033 unsigned max_cu_per_sh; 2034 unsigned max_sh_per_se; 2035 unsigned max_backends_per_se; 2036 unsigned max_texture_channel_caches; 2037 unsigned max_gprs; 2038 unsigned max_gs_threads; 2039 unsigned max_hw_contexts; 2040 unsigned sc_prim_fifo_size_frontend; 2041 unsigned sc_prim_fifo_size_backend; 2042 unsigned sc_hiz_tile_fifo_size; 2043 unsigned sc_earlyz_tile_fifo_size; 2044 2045 unsigned num_tile_pipes; 2046 unsigned backend_enable_mask; 2047 unsigned backend_disable_mask_per_asic; 2048 unsigned backend_map; 2049 unsigned num_texture_channel_caches; 2050 unsigned mem_max_burst_length_bytes; 2051 unsigned mem_row_size_in_kb; 2052 unsigned shader_engine_tile_size; 2053 unsigned num_gpus; 2054 unsigned multi_gpu_tile_size; 2055 2056 unsigned tile_config; 2057 uint32_t tile_mode_array[32]; 2058 uint32_t active_cus; 2059 }; 2060 2061 struct cik_asic { 2062 unsigned max_shader_engines; 2063 unsigned max_tile_pipes; 2064 unsigned max_cu_per_sh; 2065 unsigned max_sh_per_se; 2066 unsigned max_backends_per_se; 2067 unsigned max_texture_channel_caches; 2068 unsigned max_gprs; 2069 unsigned max_gs_threads; 2070 unsigned max_hw_contexts; 2071 unsigned sc_prim_fifo_size_frontend; 2072 unsigned sc_prim_fifo_size_backend; 2073 unsigned sc_hiz_tile_fifo_size; 2074 unsigned sc_earlyz_tile_fifo_size; 2075 2076 unsigned num_tile_pipes; 2077 unsigned backend_enable_mask; 2078 unsigned backend_disable_mask_per_asic; 2079 unsigned backend_map; 2080 unsigned num_texture_channel_caches; 2081 unsigned mem_max_burst_length_bytes; 2082 unsigned mem_row_size_in_kb; 2083 unsigned shader_engine_tile_size; 2084 unsigned num_gpus; 2085 unsigned multi_gpu_tile_size; 2086 2087 unsigned tile_config; 2088 uint32_t tile_mode_array[32]; 2089 uint32_t macrotile_mode_array[16]; 2090 uint32_t active_cus; 2091 }; 2092 2093 union radeon_asic_config { 2094 struct r300_asic r300; 2095 struct r100_asic r100; 2096 struct r600_asic r600; 2097 struct rv770_asic rv770; 2098 struct evergreen_asic evergreen; 2099 struct cayman_asic cayman; 2100 struct si_asic si; 2101 struct cik_asic cik; 2102 }; 2103 2104 /* 2105 * asic initizalization from radeon_asic.c 2106 */ 2107 void radeon_agp_disable(struct radeon_device *rdev); 2108 int radeon_asic_init(struct radeon_device *rdev); 2109 2110 2111 /* 2112 * IOCTL. 2113 */ 2114 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2115 struct drm_file *filp); 2116 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2117 struct drm_file *filp); 2118 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2119 struct drm_file *file_priv); 2120 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2121 struct drm_file *file_priv); 2122 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2123 struct drm_file *file_priv); 2124 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2125 struct drm_file *file_priv); 2126 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2127 struct drm_file *filp); 2128 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2129 struct drm_file *filp); 2130 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2131 struct drm_file *filp); 2132 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2133 struct drm_file *filp); 2134 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2135 struct drm_file *filp); 2136 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2137 struct drm_file *filp); 2138 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2139 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2140 struct drm_file *filp); 2141 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2142 struct drm_file *filp); 2143 2144 /* VRAM scratch page for HDP bug, default vram page */ 2145 struct r600_vram_scratch { 2146 struct radeon_bo *robj; 2147 volatile uint32_t *ptr; 2148 u64 gpu_addr; 2149 }; 2150 2151 /* 2152 * ACPI 2153 */ 2154 struct radeon_atif_notification_cfg { 2155 bool enabled; 2156 int command_code; 2157 }; 2158 2159 struct radeon_atif_notifications { 2160 bool display_switch; 2161 bool expansion_mode_change; 2162 bool thermal_state; 2163 bool forced_power_state; 2164 bool system_power_state; 2165 bool display_conf_change; 2166 bool px_gfx_switch; 2167 bool brightness_change; 2168 bool dgpu_display_event; 2169 }; 2170 2171 struct radeon_atif_functions { 2172 bool system_params; 2173 bool sbios_requests; 2174 bool select_active_disp; 2175 bool lid_state; 2176 bool get_tv_standard; 2177 bool set_tv_standard; 2178 bool get_panel_expansion_mode; 2179 bool set_panel_expansion_mode; 2180 bool temperature_change; 2181 bool graphics_device_types; 2182 }; 2183 2184 struct radeon_atif { 2185 struct radeon_atif_notifications notifications; 2186 struct radeon_atif_functions functions; 2187 struct radeon_atif_notification_cfg notification_cfg; 2188 struct radeon_encoder *encoder_for_bl; 2189 }; 2190 2191 struct radeon_atcs_functions { 2192 bool get_ext_state; 2193 bool pcie_perf_req; 2194 bool pcie_dev_rdy; 2195 bool pcie_bus_width; 2196 }; 2197 2198 struct radeon_atcs { 2199 struct radeon_atcs_functions functions; 2200 }; 2201 2202 /* 2203 * Core structure, functions and helpers. 2204 */ 2205 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2206 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2207 2208 struct radeon_device { 2209 struct device *dev; 2210 struct drm_device *ddev; 2211 struct pci_dev *pdev; 2212 struct rw_semaphore exclusive_lock; 2213 /* ASIC */ 2214 union radeon_asic_config config; 2215 enum radeon_family family; 2216 unsigned long flags; 2217 int usec_timeout; 2218 enum radeon_pll_errata pll_errata; 2219 int num_gb_pipes; 2220 int num_z_pipes; 2221 int disp_priority; 2222 /* BIOS */ 2223 uint8_t *bios; 2224 bool is_atom_bios; 2225 uint16_t bios_header_start; 2226 struct radeon_bo *stollen_vga_memory; 2227 /* Register mmio */ 2228 resource_size_t rmmio_base; 2229 resource_size_t rmmio_size; 2230 /* protects concurrent MM_INDEX/DATA based register access */ 2231 spinlock_t mmio_idx_lock; 2232 /* protects concurrent SMC based register access */ 2233 spinlock_t smc_idx_lock; 2234 /* protects concurrent PLL register access */ 2235 spinlock_t pll_idx_lock; 2236 /* protects concurrent MC register access */ 2237 spinlock_t mc_idx_lock; 2238 /* protects concurrent PCIE register access */ 2239 spinlock_t pcie_idx_lock; 2240 /* protects concurrent PCIE_PORT register access */ 2241 spinlock_t pciep_idx_lock; 2242 /* protects concurrent PIF register access */ 2243 spinlock_t pif_idx_lock; 2244 /* protects concurrent CG register access */ 2245 spinlock_t cg_idx_lock; 2246 /* protects concurrent UVD register access */ 2247 spinlock_t uvd_idx_lock; 2248 /* protects concurrent RCU register access */ 2249 spinlock_t rcu_idx_lock; 2250 /* protects concurrent DIDT register access */ 2251 spinlock_t didt_idx_lock; 2252 /* protects concurrent ENDPOINT (audio) register access */ 2253 spinlock_t end_idx_lock; 2254 void __iomem *rmmio; 2255 radeon_rreg_t mc_rreg; 2256 radeon_wreg_t mc_wreg; 2257 radeon_rreg_t pll_rreg; 2258 radeon_wreg_t pll_wreg; 2259 uint32_t pcie_reg_mask; 2260 radeon_rreg_t pciep_rreg; 2261 radeon_wreg_t pciep_wreg; 2262 /* io port */ 2263 void __iomem *rio_mem; 2264 resource_size_t rio_mem_size; 2265 struct radeon_clock clock; 2266 struct radeon_mc mc; 2267 struct radeon_gart gart; 2268 struct radeon_mode_info mode_info; 2269 struct radeon_scratch scratch; 2270 struct radeon_doorbell doorbell; 2271 struct radeon_mman mman; 2272 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2273 wait_queue_head_t fence_queue; 2274 struct mutex ring_lock; 2275 struct radeon_ring ring[RADEON_NUM_RINGS]; 2276 bool ib_pool_ready; 2277 struct radeon_sa_manager ring_tmp_bo; 2278 struct radeon_irq irq; 2279 struct radeon_asic *asic; 2280 struct radeon_gem gem; 2281 struct radeon_pm pm; 2282 struct radeon_uvd uvd; 2283 struct radeon_vce vce; 2284 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2285 struct radeon_wb wb; 2286 struct radeon_dummy_page dummy_page; 2287 bool shutdown; 2288 bool suspend; 2289 bool need_dma32; 2290 bool accel_working; 2291 bool fastfb_working; /* IGP feature*/ 2292 bool needs_reset; 2293 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2294 const struct firmware *me_fw; /* all family ME firmware */ 2295 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2296 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2297 const struct firmware *mc_fw; /* NI MC firmware */ 2298 const struct firmware *ce_fw; /* SI CE firmware */ 2299 const struct firmware *mec_fw; /* CIK MEC firmware */ 2300 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2301 const struct firmware *smc_fw; /* SMC firmware */ 2302 const struct firmware *uvd_fw; /* UVD firmware */ 2303 const struct firmware *vce_fw; /* VCE firmware */ 2304 struct r600_vram_scratch vram_scratch; 2305 int msi_enabled; /* msi enabled */ 2306 struct r600_ih ih; /* r6/700 interrupt ring */ 2307 struct radeon_rlc rlc; 2308 struct radeon_mec mec; 2309 struct work_struct hotplug_work; 2310 struct work_struct audio_work; 2311 struct work_struct reset_work; 2312 int num_crtc; /* number of crtcs */ 2313 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2314 bool has_uvd; 2315 struct r600_audio audio; /* audio stuff */ 2316 struct notifier_block acpi_nb; 2317 /* only one userspace can use Hyperz features or CMASK at a time */ 2318 struct drm_file *hyperz_filp; 2319 struct drm_file *cmask_filp; 2320 /* i2c buses */ 2321 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2322 /* debugfs */ 2323 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2324 unsigned debugfs_count; 2325 /* virtual memory */ 2326 struct radeon_vm_manager vm_manager; 2327 struct mutex gpu_clock_mutex; 2328 /* memory stats */ 2329 atomic64_t vram_usage; 2330 atomic64_t gtt_usage; 2331 atomic64_t num_bytes_moved; 2332 /* ACPI interface */ 2333 struct radeon_atif atif; 2334 struct radeon_atcs atcs; 2335 /* srbm instance registers */ 2336 struct mutex srbm_mutex; 2337 /* clock, powergating flags */ 2338 u32 cg_flags; 2339 u32 pg_flags; 2340 2341 struct dev_pm_domain vga_pm_domain; 2342 bool have_disp_power_ref; 2343 }; 2344 2345 bool radeon_is_px(struct drm_device *dev); 2346 int radeon_device_init(struct radeon_device *rdev, 2347 struct drm_device *ddev, 2348 struct pci_dev *pdev, 2349 uint32_t flags); 2350 void radeon_device_fini(struct radeon_device *rdev); 2351 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2352 2353 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2354 bool always_indirect); 2355 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2356 bool always_indirect); 2357 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2358 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2359 2360 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2361 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2362 2363 /* 2364 * Cast helper 2365 */ 2366 #define to_radeon_fence(p) ((struct radeon_fence *)(p)) 2367 2368 /* 2369 * Registers read & write functions. 2370 */ 2371 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 2372 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 2373 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 2374 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 2375 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2376 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2377 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) 2378 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2379 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2380 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2381 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2382 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2383 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2384 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2385 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2386 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2387 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2388 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2389 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2390 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2391 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2392 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2393 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2394 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2395 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2396 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2397 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2398 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2399 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2400 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2401 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2402 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2403 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2404 #define WREG32_P(reg, val, mask) \ 2405 do { \ 2406 uint32_t tmp_ = RREG32(reg); \ 2407 tmp_ &= (mask); \ 2408 tmp_ |= ((val) & ~(mask)); \ 2409 WREG32(reg, tmp_); \ 2410 } while (0) 2411 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2412 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2413 #define WREG32_PLL_P(reg, val, mask) \ 2414 do { \ 2415 uint32_t tmp_ = RREG32_PLL(reg); \ 2416 tmp_ &= (mask); \ 2417 tmp_ |= ((val) & ~(mask)); \ 2418 WREG32_PLL(reg, tmp_); \ 2419 } while (0) 2420 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2421 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2422 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2423 2424 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2425 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2426 2427 /* 2428 * Indirect registers accessor 2429 */ 2430 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 2431 { 2432 unsigned long flags; 2433 uint32_t r; 2434 2435 spin_lock_irqsave(&rdev->pcie_idx_lock, flags); 2436 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2437 r = RREG32(RADEON_PCIE_DATA); 2438 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); 2439 return r; 2440 } 2441 2442 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2443 { 2444 unsigned long flags; 2445 2446 spin_lock_irqsave(&rdev->pcie_idx_lock, flags); 2447 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2448 WREG32(RADEON_PCIE_DATA, (v)); 2449 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); 2450 } 2451 2452 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) 2453 { 2454 unsigned long flags; 2455 u32 r; 2456 2457 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 2458 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2459 r = RREG32(TN_SMC_IND_DATA_0); 2460 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 2461 return r; 2462 } 2463 2464 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2465 { 2466 unsigned long flags; 2467 2468 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 2469 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2470 WREG32(TN_SMC_IND_DATA_0, (v)); 2471 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 2472 } 2473 2474 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) 2475 { 2476 unsigned long flags; 2477 u32 r; 2478 2479 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); 2480 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2481 r = RREG32(R600_RCU_DATA); 2482 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); 2483 return r; 2484 } 2485 2486 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2487 { 2488 unsigned long flags; 2489 2490 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); 2491 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2492 WREG32(R600_RCU_DATA, (v)); 2493 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); 2494 } 2495 2496 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) 2497 { 2498 unsigned long flags; 2499 u32 r; 2500 2501 spin_lock_irqsave(&rdev->cg_idx_lock, flags); 2502 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2503 r = RREG32(EVERGREEN_CG_IND_DATA); 2504 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); 2505 return r; 2506 } 2507 2508 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2509 { 2510 unsigned long flags; 2511 2512 spin_lock_irqsave(&rdev->cg_idx_lock, flags); 2513 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2514 WREG32(EVERGREEN_CG_IND_DATA, (v)); 2515 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); 2516 } 2517 2518 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) 2519 { 2520 unsigned long flags; 2521 u32 r; 2522 2523 spin_lock_irqsave(&rdev->pif_idx_lock, flags); 2524 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2525 r = RREG32(EVERGREEN_PIF_PHY0_DATA); 2526 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); 2527 return r; 2528 } 2529 2530 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2531 { 2532 unsigned long flags; 2533 2534 spin_lock_irqsave(&rdev->pif_idx_lock, flags); 2535 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2536 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); 2537 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); 2538 } 2539 2540 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) 2541 { 2542 unsigned long flags; 2543 u32 r; 2544 2545 spin_lock_irqsave(&rdev->pif_idx_lock, flags); 2546 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2547 r = RREG32(EVERGREEN_PIF_PHY1_DATA); 2548 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); 2549 return r; 2550 } 2551 2552 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2553 { 2554 unsigned long flags; 2555 2556 spin_lock_irqsave(&rdev->pif_idx_lock, flags); 2557 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2558 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); 2559 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); 2560 } 2561 2562 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) 2563 { 2564 unsigned long flags; 2565 u32 r; 2566 2567 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); 2568 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2569 r = RREG32(R600_UVD_CTX_DATA); 2570 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); 2571 return r; 2572 } 2573 2574 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2575 { 2576 unsigned long flags; 2577 2578 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); 2579 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2580 WREG32(R600_UVD_CTX_DATA, (v)); 2581 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); 2582 } 2583 2584 2585 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) 2586 { 2587 unsigned long flags; 2588 u32 r; 2589 2590 spin_lock_irqsave(&rdev->didt_idx_lock, flags); 2591 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2592 r = RREG32(CIK_DIDT_IND_DATA); 2593 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); 2594 return r; 2595 } 2596 2597 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2598 { 2599 unsigned long flags; 2600 2601 spin_lock_irqsave(&rdev->didt_idx_lock, flags); 2602 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2603 WREG32(CIK_DIDT_IND_DATA, (v)); 2604 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); 2605 } 2606 2607 void r100_pll_errata_after_index(struct radeon_device *rdev); 2608 2609 2610 /* 2611 * ASICs helpers. 2612 */ 2613 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2614 (rdev->pdev->device == 0x5969)) 2615 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2616 (rdev->family == CHIP_RV200) || \ 2617 (rdev->family == CHIP_RS100) || \ 2618 (rdev->family == CHIP_RS200) || \ 2619 (rdev->family == CHIP_RV250) || \ 2620 (rdev->family == CHIP_RV280) || \ 2621 (rdev->family == CHIP_RS300)) 2622 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2623 (rdev->family == CHIP_RV350) || \ 2624 (rdev->family == CHIP_R350) || \ 2625 (rdev->family == CHIP_RV380) || \ 2626 (rdev->family == CHIP_R420) || \ 2627 (rdev->family == CHIP_R423) || \ 2628 (rdev->family == CHIP_RV410) || \ 2629 (rdev->family == CHIP_RS400) || \ 2630 (rdev->family == CHIP_RS480)) 2631 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2632 (rdev->ddev->pdev->device == 0x9443) || \ 2633 (rdev->ddev->pdev->device == 0x944B) || \ 2634 (rdev->ddev->pdev->device == 0x9506) || \ 2635 (rdev->ddev->pdev->device == 0x9509) || \ 2636 (rdev->ddev->pdev->device == 0x950F) || \ 2637 (rdev->ddev->pdev->device == 0x689C) || \ 2638 (rdev->ddev->pdev->device == 0x689D)) 2639 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2640 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2641 (rdev->family == CHIP_RS690) || \ 2642 (rdev->family == CHIP_RS740) || \ 2643 (rdev->family >= CHIP_R600)) 2644 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2645 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2646 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2647 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2648 (rdev->flags & RADEON_IS_IGP)) 2649 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2650 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2651 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2652 (rdev->flags & RADEON_IS_IGP)) 2653 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2654 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2655 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2656 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2657 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2658 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2659 (rdev->family == CHIP_MULLINS)) 2660 2661 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2662 (rdev->ddev->pdev->device == 0x6850) || \ 2663 (rdev->ddev->pdev->device == 0x6858) || \ 2664 (rdev->ddev->pdev->device == 0x6859) || \ 2665 (rdev->ddev->pdev->device == 0x6840) || \ 2666 (rdev->ddev->pdev->device == 0x6841) || \ 2667 (rdev->ddev->pdev->device == 0x6842) || \ 2668 (rdev->ddev->pdev->device == 0x6843)) 2669 2670 /* 2671 * BIOS helpers. 2672 */ 2673 #define RBIOS8(i) (rdev->bios[i]) 2674 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2675 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2676 2677 int radeon_combios_init(struct radeon_device *rdev); 2678 void radeon_combios_fini(struct radeon_device *rdev); 2679 int radeon_atombios_init(struct radeon_device *rdev); 2680 void radeon_atombios_fini(struct radeon_device *rdev); 2681 2682 2683 /* 2684 * RING helpers. 2685 */ 2686 #if DRM_DEBUG_CODE == 0 2687 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2688 { 2689 ring->ring[ring->wptr++] = v; 2690 ring->wptr &= ring->ptr_mask; 2691 ring->count_dw--; 2692 ring->ring_free_dw--; 2693 } 2694 #else 2695 /* With debugging this is just too big to inline */ 2696 void radeon_ring_write(struct radeon_ring *ring, uint32_t v); 2697 #endif 2698 2699 /* 2700 * ASICs macro. 2701 */ 2702 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2703 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2704 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2705 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2706 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2707 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2708 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 2709 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2710 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) 2711 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2712 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2713 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2714 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2715 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2716 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2717 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2718 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2719 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2720 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm)) 2721 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2722 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2723 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2724 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2725 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2726 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2727 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2728 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2729 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2730 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2731 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2732 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2733 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 2734 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) 2735 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) 2736 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2737 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2738 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2739 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2740 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2741 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2742 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2743 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2744 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2745 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2746 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2747 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2748 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2749 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2750 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2751 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2752 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2753 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2754 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2755 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2756 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2757 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2758 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2759 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2760 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2761 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2762 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 2763 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2764 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2765 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2766 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2767 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2768 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2769 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2770 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2771 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2772 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2773 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2774 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2775 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2776 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2777 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2778 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2779 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2780 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2781 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2782 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2783 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2784 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2785 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2786 2787 /* Common functions */ 2788 /* AGP */ 2789 extern int radeon_gpu_reset(struct radeon_device *rdev); 2790 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2791 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2792 extern void radeon_agp_disable(struct radeon_device *rdev); 2793 extern int radeon_modeset_init(struct radeon_device *rdev); 2794 extern void radeon_modeset_fini(struct radeon_device *rdev); 2795 extern bool radeon_card_posted(struct radeon_device *rdev); 2796 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2797 extern void radeon_update_display_priority(struct radeon_device *rdev); 2798 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2799 extern void radeon_scratch_init(struct radeon_device *rdev); 2800 extern void radeon_wb_fini(struct radeon_device *rdev); 2801 extern int radeon_wb_init(struct radeon_device *rdev); 2802 extern void radeon_wb_disable(struct radeon_device *rdev); 2803 extern void radeon_surface_init(struct radeon_device *rdev); 2804 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2805 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 2806 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 2807 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2808 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2809 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2810 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2811 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2812 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2813 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2814 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2815 const u32 *registers, 2816 const u32 array_size); 2817 2818 /* 2819 * vm 2820 */ 2821 int radeon_vm_manager_init(struct radeon_device *rdev); 2822 void radeon_vm_manager_fini(struct radeon_device *rdev); 2823 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2824 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2825 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev, 2826 struct radeon_vm *vm, 2827 struct list_head *head); 2828 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2829 struct radeon_vm *vm, int ring); 2830 void radeon_vm_flush(struct radeon_device *rdev, 2831 struct radeon_vm *vm, 2832 int ring); 2833 void radeon_vm_fence(struct radeon_device *rdev, 2834 struct radeon_vm *vm, 2835 struct radeon_fence *fence); 2836 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2837 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2838 struct radeon_vm *vm); 2839 int radeon_vm_bo_update(struct radeon_device *rdev, 2840 struct radeon_vm *vm, 2841 struct radeon_bo *bo, 2842 struct ttm_mem_reg *mem); 2843 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2844 struct radeon_bo *bo); 2845 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2846 struct radeon_bo *bo); 2847 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2848 struct radeon_vm *vm, 2849 struct radeon_bo *bo); 2850 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2851 struct radeon_bo_va *bo_va, 2852 uint64_t offset, 2853 uint32_t flags); 2854 int radeon_vm_bo_rmv(struct radeon_device *rdev, 2855 struct radeon_bo_va *bo_va); 2856 2857 /* audio */ 2858 void r600_audio_update_hdmi(struct work_struct *work); 2859 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2860 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2861 void r600_audio_enable(struct radeon_device *rdev, 2862 struct r600_audio_pin *pin, 2863 bool enable); 2864 void dce6_audio_enable(struct radeon_device *rdev, 2865 struct r600_audio_pin *pin, 2866 bool enable); 2867 2868 /* 2869 * R600 vram scratch functions 2870 */ 2871 int r600_vram_scratch_init(struct radeon_device *rdev); 2872 void r600_vram_scratch_fini(struct radeon_device *rdev); 2873 2874 /* 2875 * r600 cs checking helper 2876 */ 2877 unsigned r600_mip_minify(unsigned size, unsigned level); 2878 bool r600_fmt_is_valid_color(u32 format); 2879 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2880 int r600_fmt_get_blocksize(u32 format); 2881 int r600_fmt_get_nblocksx(u32 format, u32 w); 2882 int r600_fmt_get_nblocksy(u32 format, u32 h); 2883 2884 /* 2885 * r600 functions used by radeon_encoder.c 2886 */ 2887 struct radeon_hdmi_acr { 2888 u32 clock; 2889 2890 int n_32khz; 2891 int cts_32khz; 2892 2893 int n_44_1khz; 2894 int cts_44_1khz; 2895 2896 int n_48khz; 2897 int cts_48khz; 2898 2899 }; 2900 2901 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 2902 2903 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2904 u32 tiling_pipe_num, 2905 u32 max_rb_num, 2906 u32 total_max_rb_num, 2907 u32 enabled_rb_mask); 2908 2909 /* 2910 * evergreen functions used by radeon_encoder.c 2911 */ 2912 2913 extern int ni_init_microcode(struct radeon_device *rdev); 2914 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2915 2916 /* radeon_acpi.c */ 2917 #if defined(CONFIG_ACPI) 2918 extern int radeon_acpi_init(struct radeon_device *rdev); 2919 extern void radeon_acpi_fini(struct radeon_device *rdev); 2920 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 2921 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 2922 u8 perf_req, bool advertise); 2923 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 2924 #else 2925 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 2926 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 2927 #endif 2928 2929 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 2930 struct radeon_cs_packet *pkt, 2931 unsigned idx); 2932 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 2933 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 2934 struct radeon_cs_packet *pkt); 2935 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 2936 struct radeon_cs_reloc **cs_reloc, 2937 int nomm); 2938 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 2939 uint32_t *vline_start_end, 2940 uint32_t *vline_status); 2941 2942 #include "radeon_object.h" 2943 2944 #endif 2945