1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 /* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45 /* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63 #include <linux/atomic.h> 64 #include <linux/wait.h> 65 #include <linux/list.h> 66 #include <linux/kref.h> 67 68 #include <ttm/ttm_bo_api.h> 69 #include <ttm/ttm_bo_driver.h> 70 #include <ttm/ttm_placement.h> 71 #include <ttm/ttm_module.h> 72 #include <ttm/ttm_execbuf_util.h> 73 74 #include "radeon_family.h" 75 #include "radeon_mode.h" 76 #include "radeon_reg.h" 77 78 /* 79 * Modules parameters. 80 */ 81 extern int radeon_no_wb; 82 extern int radeon_modeset; 83 extern int radeon_dynclks; 84 extern int radeon_r4xx_atom; 85 extern int radeon_agpmode; 86 extern int radeon_vram_limit; 87 extern int radeon_gart_size; 88 extern int radeon_benchmarking; 89 extern int radeon_testing; 90 extern int radeon_connector_table; 91 extern int radeon_tv; 92 extern int radeon_audio; 93 extern int radeon_disp_priority; 94 extern int radeon_hw_i2c; 95 extern int radeon_pcie_gen2; 96 extern int radeon_msi; 97 extern int radeon_lockup_timeout; 98 99 /* 100 * Copy from radeon_drv.h so we don't have to include both and have conflicting 101 * symbol; 102 */ 103 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 104 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 105 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 106 #define RADEON_IB_POOL_SIZE 16 107 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 108 #define RADEONFB_CONN_LIMIT 4 109 #define RADEON_BIOS_NUM_SCRATCH 8 110 111 /* max number of rings */ 112 #define RADEON_NUM_RINGS 5 113 114 /* fence seq are set to this number when signaled */ 115 #define RADEON_FENCE_SIGNALED_SEQ 0LL 116 117 /* internal ring indices */ 118 /* r1xx+ has gfx CP ring */ 119 #define RADEON_RING_TYPE_GFX_INDEX 0 120 121 /* cayman has 2 compute CP rings */ 122 #define CAYMAN_RING_TYPE_CP1_INDEX 1 123 #define CAYMAN_RING_TYPE_CP2_INDEX 2 124 125 /* R600+ has an async dma ring */ 126 #define R600_RING_TYPE_DMA_INDEX 3 127 /* cayman add a second async dma ring */ 128 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 129 130 /* hardcode those limit for now */ 131 #define RADEON_VA_IB_OFFSET (1 << 20) 132 #define RADEON_VA_RESERVED_SIZE (8 << 20) 133 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 134 135 /* reset flags */ 136 #define RADEON_RESET_GFX (1 << 0) 137 #define RADEON_RESET_COMPUTE (1 << 1) 138 #define RADEON_RESET_DMA (1 << 2) 139 140 /* 141 * Errata workarounds. 142 */ 143 enum radeon_pll_errata { 144 CHIP_ERRATA_R300_CG = 0x00000001, 145 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 146 CHIP_ERRATA_PLL_DELAY = 0x00000004 147 }; 148 149 150 struct radeon_device; 151 152 153 /* 154 * BIOS. 155 */ 156 bool radeon_get_bios(struct radeon_device *rdev); 157 158 /* 159 * Dummy page 160 */ 161 struct radeon_dummy_page { 162 struct page *page; 163 dma_addr_t addr; 164 }; 165 int radeon_dummy_page_init(struct radeon_device *rdev); 166 void radeon_dummy_page_fini(struct radeon_device *rdev); 167 168 169 /* 170 * Clocks 171 */ 172 struct radeon_clock { 173 struct radeon_pll p1pll; 174 struct radeon_pll p2pll; 175 struct radeon_pll dcpll; 176 struct radeon_pll spll; 177 struct radeon_pll mpll; 178 /* 10 Khz units */ 179 uint32_t default_mclk; 180 uint32_t default_sclk; 181 uint32_t default_dispclk; 182 uint32_t dp_extclk; 183 uint32_t max_pixel_clock; 184 }; 185 186 /* 187 * Power management 188 */ 189 int radeon_pm_init(struct radeon_device *rdev); 190 void radeon_pm_fini(struct radeon_device *rdev); 191 void radeon_pm_compute_clocks(struct radeon_device *rdev); 192 void radeon_pm_suspend(struct radeon_device *rdev); 193 void radeon_pm_resume(struct radeon_device *rdev); 194 void radeon_combios_get_power_modes(struct radeon_device *rdev); 195 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 196 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 197 void rs690_pm_info(struct radeon_device *rdev); 198 extern int rv6xx_get_temp(struct radeon_device *rdev); 199 extern int rv770_get_temp(struct radeon_device *rdev); 200 extern int evergreen_get_temp(struct radeon_device *rdev); 201 extern int sumo_get_temp(struct radeon_device *rdev); 202 extern int si_get_temp(struct radeon_device *rdev); 203 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 204 unsigned *bankh, unsigned *mtaspect, 205 unsigned *tile_split); 206 207 /* 208 * Fences. 209 */ 210 struct radeon_fence_driver { 211 uint32_t scratch_reg; 212 uint64_t gpu_addr; 213 volatile uint32_t *cpu_addr; 214 /* sync_seq is protected by ring emission lock */ 215 uint64_t sync_seq[RADEON_NUM_RINGS]; 216 atomic64_t last_seq; 217 unsigned long last_activity; 218 bool initialized; 219 }; 220 221 struct radeon_fence { 222 struct radeon_device *rdev; 223 struct kref kref; 224 /* protected by radeon_fence.lock */ 225 uint64_t seq; 226 /* RB, DMA, etc. */ 227 unsigned ring; 228 }; 229 230 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 231 int radeon_fence_driver_init(struct radeon_device *rdev); 232 void radeon_fence_driver_fini(struct radeon_device *rdev); 233 void radeon_fence_driver_force_completion(struct radeon_device *rdev); 234 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 235 void radeon_fence_process(struct radeon_device *rdev, int ring); 236 bool radeon_fence_signaled(struct radeon_fence *fence); 237 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 238 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring); 239 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring); 240 int radeon_fence_wait_any(struct radeon_device *rdev, 241 struct radeon_fence **fences, 242 bool intr); 243 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 244 void radeon_fence_unref(struct radeon_fence **fence); 245 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 246 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 247 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 248 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 249 struct radeon_fence *b) 250 { 251 if (!a) { 252 return b; 253 } 254 255 if (!b) { 256 return a; 257 } 258 259 BUG_ON(a->ring != b->ring); 260 261 if (a->seq > b->seq) { 262 return a; 263 } else { 264 return b; 265 } 266 } 267 268 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 269 struct radeon_fence *b) 270 { 271 if (!a) { 272 return false; 273 } 274 275 if (!b) { 276 return true; 277 } 278 279 BUG_ON(a->ring != b->ring); 280 281 return a->seq < b->seq; 282 } 283 284 /* 285 * Tiling registers 286 */ 287 struct radeon_surface_reg { 288 struct radeon_bo *bo; 289 }; 290 291 #define RADEON_GEM_MAX_SURFACES 8 292 293 /* 294 * TTM. 295 */ 296 struct radeon_mman { 297 struct ttm_bo_global_ref bo_global_ref; 298 struct drm_global_reference mem_global_ref; 299 struct ttm_bo_device bdev; 300 bool mem_global_referenced; 301 bool initialized; 302 }; 303 304 /* bo virtual address in a specific vm */ 305 struct radeon_bo_va { 306 /* protected by bo being reserved */ 307 struct list_head bo_list; 308 uint64_t soffset; 309 uint64_t eoffset; 310 uint32_t flags; 311 bool valid; 312 unsigned ref_count; 313 314 /* protected by vm mutex */ 315 struct list_head vm_list; 316 317 /* constant after initialization */ 318 struct radeon_vm *vm; 319 struct radeon_bo *bo; 320 }; 321 322 struct radeon_bo { 323 /* Protected by gem.mutex */ 324 struct list_head list; 325 /* Protected by tbo.reserved */ 326 u32 placements[3]; 327 struct ttm_placement placement; 328 struct ttm_buffer_object tbo; 329 struct ttm_bo_kmap_obj kmap; 330 unsigned pin_count; 331 void *kptr; 332 u32 tiling_flags; 333 u32 pitch; 334 int surface_reg; 335 /* list of all virtual address to which this bo 336 * is associated to 337 */ 338 struct list_head va; 339 /* Constant after initialization */ 340 struct radeon_device *rdev; 341 struct drm_gem_object gem_base; 342 343 struct ttm_bo_kmap_obj dma_buf_vmap; 344 int vmapping_count; 345 }; 346 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 347 348 struct radeon_bo_list { 349 struct ttm_validate_buffer tv; 350 struct radeon_bo *bo; 351 uint64_t gpu_offset; 352 unsigned rdomain; 353 unsigned wdomain; 354 u32 tiling_flags; 355 }; 356 357 /* sub-allocation manager, it has to be protected by another lock. 358 * By conception this is an helper for other part of the driver 359 * like the indirect buffer or semaphore, which both have their 360 * locking. 361 * 362 * Principe is simple, we keep a list of sub allocation in offset 363 * order (first entry has offset == 0, last entry has the highest 364 * offset). 365 * 366 * When allocating new object we first check if there is room at 367 * the end total_size - (last_object_offset + last_object_size) >= 368 * alloc_size. If so we allocate new object there. 369 * 370 * When there is not enough room at the end, we start waiting for 371 * each sub object until we reach object_offset+object_size >= 372 * alloc_size, this object then become the sub object we return. 373 * 374 * Alignment can't be bigger than page size. 375 * 376 * Hole are not considered for allocation to keep things simple. 377 * Assumption is that there won't be hole (all object on same 378 * alignment). 379 */ 380 struct radeon_sa_manager { 381 wait_queue_head_t wq; 382 struct radeon_bo *bo; 383 struct list_head *hole; 384 struct list_head flist[RADEON_NUM_RINGS]; 385 struct list_head olist; 386 unsigned size; 387 uint64_t gpu_addr; 388 void *cpu_ptr; 389 uint32_t domain; 390 }; 391 392 struct radeon_sa_bo; 393 394 /* sub-allocation buffer */ 395 struct radeon_sa_bo { 396 struct list_head olist; 397 struct list_head flist; 398 struct radeon_sa_manager *manager; 399 unsigned soffset; 400 unsigned eoffset; 401 struct radeon_fence *fence; 402 }; 403 404 /* 405 * GEM objects. 406 */ 407 struct radeon_gem { 408 struct mutex mutex; 409 struct list_head objects; 410 }; 411 412 int radeon_gem_init(struct radeon_device *rdev); 413 void radeon_gem_fini(struct radeon_device *rdev); 414 int radeon_gem_object_create(struct radeon_device *rdev, int size, 415 int alignment, int initial_domain, 416 bool discardable, bool kernel, 417 struct drm_gem_object **obj); 418 419 int radeon_mode_dumb_create(struct drm_file *file_priv, 420 struct drm_device *dev, 421 struct drm_mode_create_dumb *args); 422 int radeon_mode_dumb_mmap(struct drm_file *filp, 423 struct drm_device *dev, 424 uint32_t handle, uint64_t *offset_p); 425 int radeon_mode_dumb_destroy(struct drm_file *file_priv, 426 struct drm_device *dev, 427 uint32_t handle); 428 429 /* 430 * Semaphores. 431 */ 432 /* everything here is constant */ 433 struct radeon_semaphore { 434 struct radeon_sa_bo *sa_bo; 435 signed waiters; 436 uint64_t gpu_addr; 437 }; 438 439 int radeon_semaphore_create(struct radeon_device *rdev, 440 struct radeon_semaphore **semaphore); 441 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 442 struct radeon_semaphore *semaphore); 443 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 444 struct radeon_semaphore *semaphore); 445 int radeon_semaphore_sync_rings(struct radeon_device *rdev, 446 struct radeon_semaphore *semaphore, 447 int signaler, int waiter); 448 void radeon_semaphore_free(struct radeon_device *rdev, 449 struct radeon_semaphore **semaphore, 450 struct radeon_fence *fence); 451 452 /* 453 * GART structures, functions & helpers 454 */ 455 struct radeon_mc; 456 457 #define RADEON_GPU_PAGE_SIZE 4096 458 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 459 #define RADEON_GPU_PAGE_SHIFT 12 460 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 461 462 struct radeon_gart { 463 dma_addr_t table_addr; 464 struct radeon_bo *robj; 465 void *ptr; 466 unsigned num_gpu_pages; 467 unsigned num_cpu_pages; 468 unsigned table_size; 469 struct page **pages; 470 dma_addr_t *pages_addr; 471 bool ready; 472 }; 473 474 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 475 void radeon_gart_table_ram_free(struct radeon_device *rdev); 476 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 477 void radeon_gart_table_vram_free(struct radeon_device *rdev); 478 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 479 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 480 int radeon_gart_init(struct radeon_device *rdev); 481 void radeon_gart_fini(struct radeon_device *rdev); 482 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 483 int pages); 484 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 485 int pages, struct page **pagelist, 486 dma_addr_t *dma_addr); 487 void radeon_gart_restore(struct radeon_device *rdev); 488 489 490 /* 491 * GPU MC structures, functions & helpers 492 */ 493 struct radeon_mc { 494 resource_size_t aper_size; 495 resource_size_t aper_base; 496 resource_size_t agp_base; 497 /* for some chips with <= 32MB we need to lie 498 * about vram size near mc fb location */ 499 u64 mc_vram_size; 500 u64 visible_vram_size; 501 u64 gtt_size; 502 u64 gtt_start; 503 u64 gtt_end; 504 u64 vram_start; 505 u64 vram_end; 506 unsigned vram_width; 507 u64 real_vram_size; 508 int vram_mtrr; 509 bool vram_is_ddr; 510 bool igp_sideport_enabled; 511 u64 gtt_base_align; 512 }; 513 514 bool radeon_combios_sideport_present(struct radeon_device *rdev); 515 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 516 517 /* 518 * GPU scratch registers structures, functions & helpers 519 */ 520 struct radeon_scratch { 521 unsigned num_reg; 522 uint32_t reg_base; 523 bool free[32]; 524 uint32_t reg[32]; 525 }; 526 527 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 528 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 529 530 531 /* 532 * IRQS. 533 */ 534 535 struct radeon_unpin_work { 536 struct work_struct work; 537 struct radeon_device *rdev; 538 int crtc_id; 539 struct radeon_fence *fence; 540 struct drm_pending_vblank_event *event; 541 struct radeon_bo *old_rbo; 542 u64 new_crtc_base; 543 }; 544 545 struct r500_irq_stat_regs { 546 u32 disp_int; 547 u32 hdmi0_status; 548 }; 549 550 struct r600_irq_stat_regs { 551 u32 disp_int; 552 u32 disp_int_cont; 553 u32 disp_int_cont2; 554 u32 d1grph_int; 555 u32 d2grph_int; 556 u32 hdmi0_status; 557 u32 hdmi1_status; 558 }; 559 560 struct evergreen_irq_stat_regs { 561 u32 disp_int; 562 u32 disp_int_cont; 563 u32 disp_int_cont2; 564 u32 disp_int_cont3; 565 u32 disp_int_cont4; 566 u32 disp_int_cont5; 567 u32 d1grph_int; 568 u32 d2grph_int; 569 u32 d3grph_int; 570 u32 d4grph_int; 571 u32 d5grph_int; 572 u32 d6grph_int; 573 u32 afmt_status1; 574 u32 afmt_status2; 575 u32 afmt_status3; 576 u32 afmt_status4; 577 u32 afmt_status5; 578 u32 afmt_status6; 579 }; 580 581 union radeon_irq_stat_regs { 582 struct r500_irq_stat_regs r500; 583 struct r600_irq_stat_regs r600; 584 struct evergreen_irq_stat_regs evergreen; 585 }; 586 587 #define RADEON_MAX_HPD_PINS 6 588 #define RADEON_MAX_CRTCS 6 589 #define RADEON_MAX_AFMT_BLOCKS 6 590 591 struct radeon_irq { 592 bool installed; 593 spinlock_t lock; 594 atomic_t ring_int[RADEON_NUM_RINGS]; 595 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 596 atomic_t pflip[RADEON_MAX_CRTCS]; 597 wait_queue_head_t vblank_queue; 598 bool hpd[RADEON_MAX_HPD_PINS]; 599 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 600 union radeon_irq_stat_regs stat_regs; 601 }; 602 603 int radeon_irq_kms_init(struct radeon_device *rdev); 604 void radeon_irq_kms_fini(struct radeon_device *rdev); 605 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 606 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 607 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 608 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 609 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 610 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 611 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 612 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 613 614 /* 615 * CP & rings. 616 */ 617 618 struct radeon_ib { 619 struct radeon_sa_bo *sa_bo; 620 uint32_t length_dw; 621 uint64_t gpu_addr; 622 uint32_t *ptr; 623 int ring; 624 struct radeon_fence *fence; 625 struct radeon_vm *vm; 626 bool is_const_ib; 627 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 628 struct radeon_semaphore *semaphore; 629 }; 630 631 struct radeon_ring { 632 struct radeon_bo *ring_obj; 633 volatile uint32_t *ring; 634 unsigned rptr; 635 unsigned rptr_offs; 636 unsigned rptr_reg; 637 unsigned rptr_save_reg; 638 u64 next_rptr_gpu_addr; 639 volatile u32 *next_rptr_cpu_addr; 640 unsigned wptr; 641 unsigned wptr_old; 642 unsigned wptr_reg; 643 unsigned ring_size; 644 unsigned ring_free_dw; 645 int count_dw; 646 unsigned long last_activity; 647 unsigned last_rptr; 648 uint64_t gpu_addr; 649 uint32_t align_mask; 650 uint32_t ptr_mask; 651 bool ready; 652 u32 ptr_reg_shift; 653 u32 ptr_reg_mask; 654 u32 nop; 655 u32 idx; 656 u64 last_semaphore_signal_addr; 657 u64 last_semaphore_wait_addr; 658 }; 659 660 /* 661 * VM 662 */ 663 664 /* maximum number of VMIDs */ 665 #define RADEON_NUM_VM 16 666 667 /* defines number of bits in page table versus page directory, 668 * a page is 4KB so we have 12 bits offset, 9 bits in the page 669 * table and the remaining 19 bits are in the page directory */ 670 #define RADEON_VM_BLOCK_SIZE 9 671 672 /* number of entries in page table */ 673 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) 674 675 struct radeon_vm { 676 struct list_head list; 677 struct list_head va; 678 unsigned id; 679 680 /* contains the page directory */ 681 struct radeon_sa_bo *page_directory; 682 uint64_t pd_gpu_addr; 683 684 /* array of page tables, one for each page directory entry */ 685 struct radeon_sa_bo **page_tables; 686 687 struct mutex mutex; 688 /* last fence for cs using this vm */ 689 struct radeon_fence *fence; 690 /* last flush or NULL if we still need to flush */ 691 struct radeon_fence *last_flush; 692 }; 693 694 struct radeon_vm_manager { 695 struct mutex lock; 696 struct list_head lru_vm; 697 struct radeon_fence *active[RADEON_NUM_VM]; 698 struct radeon_sa_manager sa_manager; 699 uint32_t max_pfn; 700 /* number of VMIDs */ 701 unsigned nvm; 702 /* vram base address for page table entry */ 703 u64 vram_base_offset; 704 /* is vm enabled? */ 705 bool enabled; 706 }; 707 708 /* 709 * file private structure 710 */ 711 struct radeon_fpriv { 712 struct radeon_vm vm; 713 }; 714 715 /* 716 * R6xx+ IH ring 717 */ 718 struct r600_ih { 719 struct radeon_bo *ring_obj; 720 volatile uint32_t *ring; 721 unsigned rptr; 722 unsigned ring_size; 723 uint64_t gpu_addr; 724 uint32_t ptr_mask; 725 atomic_t lock; 726 bool enabled; 727 }; 728 729 struct r600_blit_cp_primitives { 730 void (*set_render_target)(struct radeon_device *rdev, int format, 731 int w, int h, u64 gpu_addr); 732 void (*cp_set_surface_sync)(struct radeon_device *rdev, 733 u32 sync_type, u32 size, 734 u64 mc_addr); 735 void (*set_shaders)(struct radeon_device *rdev); 736 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr); 737 void (*set_tex_resource)(struct radeon_device *rdev, 738 int format, int w, int h, int pitch, 739 u64 gpu_addr, u32 size); 740 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1, 741 int x2, int y2); 742 void (*draw_auto)(struct radeon_device *rdev); 743 void (*set_default_state)(struct radeon_device *rdev); 744 }; 745 746 struct r600_blit { 747 struct radeon_bo *shader_obj; 748 struct r600_blit_cp_primitives primitives; 749 int max_dim; 750 int ring_size_common; 751 int ring_size_per_loop; 752 u64 shader_gpu_addr; 753 u32 vs_offset, ps_offset; 754 u32 state_offset; 755 u32 state_len; 756 }; 757 758 /* 759 * SI RLC stuff 760 */ 761 struct si_rlc { 762 /* for power gating */ 763 struct radeon_bo *save_restore_obj; 764 uint64_t save_restore_gpu_addr; 765 /* for clear state */ 766 struct radeon_bo *clear_state_obj; 767 uint64_t clear_state_gpu_addr; 768 }; 769 770 int radeon_ib_get(struct radeon_device *rdev, int ring, 771 struct radeon_ib *ib, struct radeon_vm *vm, 772 unsigned size); 773 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 774 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 775 struct radeon_ib *const_ib); 776 int radeon_ib_pool_init(struct radeon_device *rdev); 777 void radeon_ib_pool_fini(struct radeon_device *rdev); 778 int radeon_ib_ring_tests(struct radeon_device *rdev); 779 /* Ring access between begin & end cannot sleep */ 780 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 781 struct radeon_ring *ring); 782 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 783 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 784 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 785 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); 786 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); 787 void radeon_ring_undo(struct radeon_ring *ring); 788 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 789 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 790 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring); 791 void radeon_ring_lockup_update(struct radeon_ring *ring); 792 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 793 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 794 uint32_t **data); 795 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 796 unsigned size, uint32_t *data); 797 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 798 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, 799 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop); 800 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 801 802 803 /* r600 async dma */ 804 void r600_dma_stop(struct radeon_device *rdev); 805 int r600_dma_resume(struct radeon_device *rdev); 806 void r600_dma_fini(struct radeon_device *rdev); 807 808 void cayman_dma_stop(struct radeon_device *rdev); 809 int cayman_dma_resume(struct radeon_device *rdev); 810 void cayman_dma_fini(struct radeon_device *rdev); 811 812 /* 813 * CS. 814 */ 815 struct radeon_cs_reloc { 816 struct drm_gem_object *gobj; 817 struct radeon_bo *robj; 818 struct radeon_bo_list lobj; 819 uint32_t handle; 820 uint32_t flags; 821 }; 822 823 struct radeon_cs_chunk { 824 uint32_t chunk_id; 825 uint32_t length_dw; 826 int kpage_idx[2]; 827 uint32_t *kpage[2]; 828 uint32_t *kdata; 829 void __user *user_ptr; 830 int last_copied_page; 831 int last_page_index; 832 }; 833 834 struct radeon_cs_parser { 835 struct device *dev; 836 struct radeon_device *rdev; 837 struct drm_file *filp; 838 /* chunks */ 839 unsigned nchunks; 840 struct radeon_cs_chunk *chunks; 841 uint64_t *chunks_array; 842 /* IB */ 843 unsigned idx; 844 /* relocations */ 845 unsigned nrelocs; 846 struct radeon_cs_reloc *relocs; 847 struct radeon_cs_reloc **relocs_ptr; 848 struct list_head validated; 849 unsigned dma_reloc_idx; 850 /* indices of various chunks */ 851 int chunk_ib_idx; 852 int chunk_relocs_idx; 853 int chunk_flags_idx; 854 int chunk_const_ib_idx; 855 struct radeon_ib ib; 856 struct radeon_ib const_ib; 857 void *track; 858 unsigned family; 859 int parser_error; 860 u32 cs_flags; 861 u32 ring; 862 s32 priority; 863 }; 864 865 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); 866 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); 867 868 struct radeon_cs_packet { 869 unsigned idx; 870 unsigned type; 871 unsigned reg; 872 unsigned opcode; 873 int count; 874 unsigned one_reg_wr; 875 }; 876 877 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 878 struct radeon_cs_packet *pkt, 879 unsigned idx, unsigned reg); 880 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 881 struct radeon_cs_packet *pkt); 882 883 884 /* 885 * AGP 886 */ 887 int radeon_agp_init(struct radeon_device *rdev); 888 void radeon_agp_resume(struct radeon_device *rdev); 889 void radeon_agp_suspend(struct radeon_device *rdev); 890 void radeon_agp_fini(struct radeon_device *rdev); 891 892 893 /* 894 * Writeback 895 */ 896 struct radeon_wb { 897 struct radeon_bo *wb_obj; 898 volatile uint32_t *wb; 899 uint64_t gpu_addr; 900 bool enabled; 901 bool use_event; 902 }; 903 904 #define RADEON_WB_SCRATCH_OFFSET 0 905 #define RADEON_WB_RING0_NEXT_RPTR 256 906 #define RADEON_WB_CP_RPTR_OFFSET 1024 907 #define RADEON_WB_CP1_RPTR_OFFSET 1280 908 #define RADEON_WB_CP2_RPTR_OFFSET 1536 909 #define R600_WB_DMA_RPTR_OFFSET 1792 910 #define R600_WB_IH_WPTR_OFFSET 2048 911 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 912 #define R600_WB_EVENT_OFFSET 3072 913 914 /** 915 * struct radeon_pm - power management datas 916 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 917 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 918 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 919 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 920 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 921 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 922 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 923 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 924 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 925 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 926 * @needed_bandwidth: current bandwidth needs 927 * 928 * It keeps track of various data needed to take powermanagement decision. 929 * Bandwidth need is used to determine minimun clock of the GPU and memory. 930 * Equation between gpu/memory clock and available bandwidth is hw dependent 931 * (type of memory, bus size, efficiency, ...) 932 */ 933 934 enum radeon_pm_method { 935 PM_METHOD_PROFILE, 936 PM_METHOD_DYNPM, 937 }; 938 939 enum radeon_dynpm_state { 940 DYNPM_STATE_DISABLED, 941 DYNPM_STATE_MINIMUM, 942 DYNPM_STATE_PAUSED, 943 DYNPM_STATE_ACTIVE, 944 DYNPM_STATE_SUSPENDED, 945 }; 946 enum radeon_dynpm_action { 947 DYNPM_ACTION_NONE, 948 DYNPM_ACTION_MINIMUM, 949 DYNPM_ACTION_DOWNCLOCK, 950 DYNPM_ACTION_UPCLOCK, 951 DYNPM_ACTION_DEFAULT 952 }; 953 954 enum radeon_voltage_type { 955 VOLTAGE_NONE = 0, 956 VOLTAGE_GPIO, 957 VOLTAGE_VDDC, 958 VOLTAGE_SW 959 }; 960 961 enum radeon_pm_state_type { 962 POWER_STATE_TYPE_DEFAULT, 963 POWER_STATE_TYPE_POWERSAVE, 964 POWER_STATE_TYPE_BATTERY, 965 POWER_STATE_TYPE_BALANCED, 966 POWER_STATE_TYPE_PERFORMANCE, 967 }; 968 969 enum radeon_pm_profile_type { 970 PM_PROFILE_DEFAULT, 971 PM_PROFILE_AUTO, 972 PM_PROFILE_LOW, 973 PM_PROFILE_MID, 974 PM_PROFILE_HIGH, 975 }; 976 977 #define PM_PROFILE_DEFAULT_IDX 0 978 #define PM_PROFILE_LOW_SH_IDX 1 979 #define PM_PROFILE_MID_SH_IDX 2 980 #define PM_PROFILE_HIGH_SH_IDX 3 981 #define PM_PROFILE_LOW_MH_IDX 4 982 #define PM_PROFILE_MID_MH_IDX 5 983 #define PM_PROFILE_HIGH_MH_IDX 6 984 #define PM_PROFILE_MAX 7 985 986 struct radeon_pm_profile { 987 int dpms_off_ps_idx; 988 int dpms_on_ps_idx; 989 int dpms_off_cm_idx; 990 int dpms_on_cm_idx; 991 }; 992 993 enum radeon_int_thermal_type { 994 THERMAL_TYPE_NONE, 995 THERMAL_TYPE_RV6XX, 996 THERMAL_TYPE_RV770, 997 THERMAL_TYPE_EVERGREEN, 998 THERMAL_TYPE_SUMO, 999 THERMAL_TYPE_NI, 1000 THERMAL_TYPE_SI, 1001 }; 1002 1003 struct radeon_voltage { 1004 enum radeon_voltage_type type; 1005 /* gpio voltage */ 1006 struct radeon_gpio_rec gpio; 1007 u32 delay; /* delay in usec from voltage drop to sclk change */ 1008 bool active_high; /* voltage drop is active when bit is high */ 1009 /* VDDC voltage */ 1010 u8 vddc_id; /* index into vddc voltage table */ 1011 u8 vddci_id; /* index into vddci voltage table */ 1012 bool vddci_enabled; 1013 /* r6xx+ sw */ 1014 u16 voltage; 1015 /* evergreen+ vddci */ 1016 u16 vddci; 1017 }; 1018 1019 /* clock mode flags */ 1020 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1021 1022 struct radeon_pm_clock_info { 1023 /* memory clock */ 1024 u32 mclk; 1025 /* engine clock */ 1026 u32 sclk; 1027 /* voltage info */ 1028 struct radeon_voltage voltage; 1029 /* standardized clock flags */ 1030 u32 flags; 1031 }; 1032 1033 /* state flags */ 1034 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1035 1036 struct radeon_power_state { 1037 enum radeon_pm_state_type type; 1038 struct radeon_pm_clock_info *clock_info; 1039 /* number of valid clock modes in this power state */ 1040 int num_clock_modes; 1041 struct radeon_pm_clock_info *default_clock_mode; 1042 /* standardized state flags */ 1043 u32 flags; 1044 u32 misc; /* vbios specific flags */ 1045 u32 misc2; /* vbios specific flags */ 1046 int pcie_lanes; /* pcie lanes */ 1047 }; 1048 1049 /* 1050 * Some modes are overclocked by very low value, accept them 1051 */ 1052 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1053 1054 struct radeon_pm { 1055 struct mutex mutex; 1056 /* write locked while reprogramming mclk */ 1057 struct rw_semaphore mclk_lock; 1058 u32 active_crtcs; 1059 int active_crtc_count; 1060 int req_vblank; 1061 bool vblank_sync; 1062 fixed20_12 max_bandwidth; 1063 fixed20_12 igp_sideport_mclk; 1064 fixed20_12 igp_system_mclk; 1065 fixed20_12 igp_ht_link_clk; 1066 fixed20_12 igp_ht_link_width; 1067 fixed20_12 k8_bandwidth; 1068 fixed20_12 sideport_bandwidth; 1069 fixed20_12 ht_bandwidth; 1070 fixed20_12 core_bandwidth; 1071 fixed20_12 sclk; 1072 fixed20_12 mclk; 1073 fixed20_12 needed_bandwidth; 1074 struct radeon_power_state *power_state; 1075 /* number of valid power states */ 1076 int num_power_states; 1077 int current_power_state_index; 1078 int current_clock_mode_index; 1079 int requested_power_state_index; 1080 int requested_clock_mode_index; 1081 int default_power_state_index; 1082 u32 current_sclk; 1083 u32 current_mclk; 1084 u16 current_vddc; 1085 u16 current_vddci; 1086 u32 default_sclk; 1087 u32 default_mclk; 1088 u16 default_vddc; 1089 u16 default_vddci; 1090 struct radeon_i2c_chan *i2c_bus; 1091 /* selected pm method */ 1092 enum radeon_pm_method pm_method; 1093 /* dynpm power management */ 1094 struct delayed_work dynpm_idle_work; 1095 enum radeon_dynpm_state dynpm_state; 1096 enum radeon_dynpm_action dynpm_planned_action; 1097 unsigned long dynpm_action_timeout; 1098 bool dynpm_can_upclock; 1099 bool dynpm_can_downclock; 1100 /* profile-based power management */ 1101 enum radeon_pm_profile_type profile; 1102 int profile_index; 1103 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1104 /* internal thermal controller on rv6xx+ */ 1105 enum radeon_int_thermal_type int_thermal_type; 1106 struct device *int_hwmon_dev; 1107 }; 1108 1109 int radeon_pm_get_type_index(struct radeon_device *rdev, 1110 enum radeon_pm_state_type ps_type, 1111 int instance); 1112 1113 struct r600_audio { 1114 int channels; 1115 int rate; 1116 int bits_per_sample; 1117 u8 status_bits; 1118 u8 category_code; 1119 }; 1120 1121 /* 1122 * Benchmarking 1123 */ 1124 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1125 1126 1127 /* 1128 * Testing 1129 */ 1130 void radeon_test_moves(struct radeon_device *rdev); 1131 void radeon_test_ring_sync(struct radeon_device *rdev, 1132 struct radeon_ring *cpA, 1133 struct radeon_ring *cpB); 1134 void radeon_test_syncing(struct radeon_device *rdev); 1135 1136 1137 /* 1138 * Debugfs 1139 */ 1140 struct radeon_debugfs { 1141 struct drm_info_list *files; 1142 unsigned num_files; 1143 }; 1144 1145 int radeon_debugfs_add_files(struct radeon_device *rdev, 1146 struct drm_info_list *files, 1147 unsigned nfiles); 1148 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1149 1150 1151 /* 1152 * ASIC specific functions. 1153 */ 1154 struct radeon_asic { 1155 int (*init)(struct radeon_device *rdev); 1156 void (*fini)(struct radeon_device *rdev); 1157 int (*resume)(struct radeon_device *rdev); 1158 int (*suspend)(struct radeon_device *rdev); 1159 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1160 int (*asic_reset)(struct radeon_device *rdev); 1161 /* ioctl hw specific callback. Some hw might want to perform special 1162 * operation on specific ioctl. For instance on wait idle some hw 1163 * might want to perform and HDP flush through MMIO as it seems that 1164 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed 1165 * through ring. 1166 */ 1167 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); 1168 /* check if 3D engine is idle */ 1169 bool (*gui_idle)(struct radeon_device *rdev); 1170 /* wait for mc_idle */ 1171 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1172 /* gart */ 1173 struct { 1174 void (*tlb_flush)(struct radeon_device *rdev); 1175 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); 1176 } gart; 1177 struct { 1178 int (*init)(struct radeon_device *rdev); 1179 void (*fini)(struct radeon_device *rdev); 1180 1181 u32 pt_ring_index; 1182 void (*set_page)(struct radeon_device *rdev, uint64_t pe, 1183 uint64_t addr, unsigned count, 1184 uint32_t incr, uint32_t flags); 1185 } vm; 1186 /* ring specific callbacks */ 1187 struct { 1188 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1189 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1190 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1191 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1192 struct radeon_semaphore *semaphore, bool emit_wait); 1193 int (*cs_parse)(struct radeon_cs_parser *p); 1194 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1195 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1196 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1197 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1198 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 1199 } ring[RADEON_NUM_RINGS]; 1200 /* irqs */ 1201 struct { 1202 int (*set)(struct radeon_device *rdev); 1203 int (*process)(struct radeon_device *rdev); 1204 } irq; 1205 /* displays */ 1206 struct { 1207 /* display watermarks */ 1208 void (*bandwidth_update)(struct radeon_device *rdev); 1209 /* get frame count */ 1210 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1211 /* wait for vblank */ 1212 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1213 /* set backlight level */ 1214 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1215 /* get backlight level */ 1216 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1217 } display; 1218 /* copy functions for bo handling */ 1219 struct { 1220 int (*blit)(struct radeon_device *rdev, 1221 uint64_t src_offset, 1222 uint64_t dst_offset, 1223 unsigned num_gpu_pages, 1224 struct radeon_fence **fence); 1225 u32 blit_ring_index; 1226 int (*dma)(struct radeon_device *rdev, 1227 uint64_t src_offset, 1228 uint64_t dst_offset, 1229 unsigned num_gpu_pages, 1230 struct radeon_fence **fence); 1231 u32 dma_ring_index; 1232 /* method used for bo copy */ 1233 int (*copy)(struct radeon_device *rdev, 1234 uint64_t src_offset, 1235 uint64_t dst_offset, 1236 unsigned num_gpu_pages, 1237 struct radeon_fence **fence); 1238 /* ring used for bo copies */ 1239 u32 copy_ring_index; 1240 } copy; 1241 /* surfaces */ 1242 struct { 1243 int (*set_reg)(struct radeon_device *rdev, int reg, 1244 uint32_t tiling_flags, uint32_t pitch, 1245 uint32_t offset, uint32_t obj_size); 1246 void (*clear_reg)(struct radeon_device *rdev, int reg); 1247 } surface; 1248 /* hotplug detect */ 1249 struct { 1250 void (*init)(struct radeon_device *rdev); 1251 void (*fini)(struct radeon_device *rdev); 1252 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1253 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1254 } hpd; 1255 /* power management */ 1256 struct { 1257 void (*misc)(struct radeon_device *rdev); 1258 void (*prepare)(struct radeon_device *rdev); 1259 void (*finish)(struct radeon_device *rdev); 1260 void (*init_profile)(struct radeon_device *rdev); 1261 void (*get_dynpm_state)(struct radeon_device *rdev); 1262 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1263 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1264 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1265 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1266 int (*get_pcie_lanes)(struct radeon_device *rdev); 1267 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1268 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1269 } pm; 1270 /* pageflipping */ 1271 struct { 1272 void (*pre_page_flip)(struct radeon_device *rdev, int crtc); 1273 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1274 void (*post_page_flip)(struct radeon_device *rdev, int crtc); 1275 } pflip; 1276 }; 1277 1278 /* 1279 * Asic structures 1280 */ 1281 struct r100_asic { 1282 const unsigned *reg_safe_bm; 1283 unsigned reg_safe_bm_size; 1284 u32 hdp_cntl; 1285 }; 1286 1287 struct r300_asic { 1288 const unsigned *reg_safe_bm; 1289 unsigned reg_safe_bm_size; 1290 u32 resync_scratch; 1291 u32 hdp_cntl; 1292 }; 1293 1294 struct r600_asic { 1295 unsigned max_pipes; 1296 unsigned max_tile_pipes; 1297 unsigned max_simds; 1298 unsigned max_backends; 1299 unsigned max_gprs; 1300 unsigned max_threads; 1301 unsigned max_stack_entries; 1302 unsigned max_hw_contexts; 1303 unsigned max_gs_threads; 1304 unsigned sx_max_export_size; 1305 unsigned sx_max_export_pos_size; 1306 unsigned sx_max_export_smx_size; 1307 unsigned sq_num_cf_insts; 1308 unsigned tiling_nbanks; 1309 unsigned tiling_npipes; 1310 unsigned tiling_group_size; 1311 unsigned tile_config; 1312 unsigned backend_map; 1313 }; 1314 1315 struct rv770_asic { 1316 unsigned max_pipes; 1317 unsigned max_tile_pipes; 1318 unsigned max_simds; 1319 unsigned max_backends; 1320 unsigned max_gprs; 1321 unsigned max_threads; 1322 unsigned max_stack_entries; 1323 unsigned max_hw_contexts; 1324 unsigned max_gs_threads; 1325 unsigned sx_max_export_size; 1326 unsigned sx_max_export_pos_size; 1327 unsigned sx_max_export_smx_size; 1328 unsigned sq_num_cf_insts; 1329 unsigned sx_num_of_sets; 1330 unsigned sc_prim_fifo_size; 1331 unsigned sc_hiz_tile_fifo_size; 1332 unsigned sc_earlyz_tile_fifo_fize; 1333 unsigned tiling_nbanks; 1334 unsigned tiling_npipes; 1335 unsigned tiling_group_size; 1336 unsigned tile_config; 1337 unsigned backend_map; 1338 }; 1339 1340 struct evergreen_asic { 1341 unsigned num_ses; 1342 unsigned max_pipes; 1343 unsigned max_tile_pipes; 1344 unsigned max_simds; 1345 unsigned max_backends; 1346 unsigned max_gprs; 1347 unsigned max_threads; 1348 unsigned max_stack_entries; 1349 unsigned max_hw_contexts; 1350 unsigned max_gs_threads; 1351 unsigned sx_max_export_size; 1352 unsigned sx_max_export_pos_size; 1353 unsigned sx_max_export_smx_size; 1354 unsigned sq_num_cf_insts; 1355 unsigned sx_num_of_sets; 1356 unsigned sc_prim_fifo_size; 1357 unsigned sc_hiz_tile_fifo_size; 1358 unsigned sc_earlyz_tile_fifo_size; 1359 unsigned tiling_nbanks; 1360 unsigned tiling_npipes; 1361 unsigned tiling_group_size; 1362 unsigned tile_config; 1363 unsigned backend_map; 1364 }; 1365 1366 struct cayman_asic { 1367 unsigned max_shader_engines; 1368 unsigned max_pipes_per_simd; 1369 unsigned max_tile_pipes; 1370 unsigned max_simds_per_se; 1371 unsigned max_backends_per_se; 1372 unsigned max_texture_channel_caches; 1373 unsigned max_gprs; 1374 unsigned max_threads; 1375 unsigned max_gs_threads; 1376 unsigned max_stack_entries; 1377 unsigned sx_num_of_sets; 1378 unsigned sx_max_export_size; 1379 unsigned sx_max_export_pos_size; 1380 unsigned sx_max_export_smx_size; 1381 unsigned max_hw_contexts; 1382 unsigned sq_num_cf_insts; 1383 unsigned sc_prim_fifo_size; 1384 unsigned sc_hiz_tile_fifo_size; 1385 unsigned sc_earlyz_tile_fifo_size; 1386 1387 unsigned num_shader_engines; 1388 unsigned num_shader_pipes_per_simd; 1389 unsigned num_tile_pipes; 1390 unsigned num_simds_per_se; 1391 unsigned num_backends_per_se; 1392 unsigned backend_disable_mask_per_asic; 1393 unsigned backend_map; 1394 unsigned num_texture_channel_caches; 1395 unsigned mem_max_burst_length_bytes; 1396 unsigned mem_row_size_in_kb; 1397 unsigned shader_engine_tile_size; 1398 unsigned num_gpus; 1399 unsigned multi_gpu_tile_size; 1400 1401 unsigned tile_config; 1402 }; 1403 1404 struct si_asic { 1405 unsigned max_shader_engines; 1406 unsigned max_tile_pipes; 1407 unsigned max_cu_per_sh; 1408 unsigned max_sh_per_se; 1409 unsigned max_backends_per_se; 1410 unsigned max_texture_channel_caches; 1411 unsigned max_gprs; 1412 unsigned max_gs_threads; 1413 unsigned max_hw_contexts; 1414 unsigned sc_prim_fifo_size_frontend; 1415 unsigned sc_prim_fifo_size_backend; 1416 unsigned sc_hiz_tile_fifo_size; 1417 unsigned sc_earlyz_tile_fifo_size; 1418 1419 unsigned num_tile_pipes; 1420 unsigned num_backends_per_se; 1421 unsigned backend_disable_mask_per_asic; 1422 unsigned backend_map; 1423 unsigned num_texture_channel_caches; 1424 unsigned mem_max_burst_length_bytes; 1425 unsigned mem_row_size_in_kb; 1426 unsigned shader_engine_tile_size; 1427 unsigned num_gpus; 1428 unsigned multi_gpu_tile_size; 1429 1430 unsigned tile_config; 1431 }; 1432 1433 union radeon_asic_config { 1434 struct r300_asic r300; 1435 struct r100_asic r100; 1436 struct r600_asic r600; 1437 struct rv770_asic rv770; 1438 struct evergreen_asic evergreen; 1439 struct cayman_asic cayman; 1440 struct si_asic si; 1441 }; 1442 1443 /* 1444 * asic initizalization from radeon_asic.c 1445 */ 1446 void radeon_agp_disable(struct radeon_device *rdev); 1447 int radeon_asic_init(struct radeon_device *rdev); 1448 1449 1450 /* 1451 * IOCTL. 1452 */ 1453 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 1454 struct drm_file *filp); 1455 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 1456 struct drm_file *filp); 1457 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 1458 struct drm_file *file_priv); 1459 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 1460 struct drm_file *file_priv); 1461 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1462 struct drm_file *file_priv); 1463 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 1464 struct drm_file *file_priv); 1465 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1466 struct drm_file *filp); 1467 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 1468 struct drm_file *filp); 1469 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 1470 struct drm_file *filp); 1471 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1472 struct drm_file *filp); 1473 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 1474 struct drm_file *filp); 1475 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1476 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 1477 struct drm_file *filp); 1478 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 1479 struct drm_file *filp); 1480 1481 /* VRAM scratch page for HDP bug, default vram page */ 1482 struct r600_vram_scratch { 1483 struct radeon_bo *robj; 1484 volatile uint32_t *ptr; 1485 u64 gpu_addr; 1486 }; 1487 1488 /* 1489 * ACPI 1490 */ 1491 struct radeon_atif_notification_cfg { 1492 bool enabled; 1493 int command_code; 1494 }; 1495 1496 struct radeon_atif_notifications { 1497 bool display_switch; 1498 bool expansion_mode_change; 1499 bool thermal_state; 1500 bool forced_power_state; 1501 bool system_power_state; 1502 bool display_conf_change; 1503 bool px_gfx_switch; 1504 bool brightness_change; 1505 bool dgpu_display_event; 1506 }; 1507 1508 struct radeon_atif_functions { 1509 bool system_params; 1510 bool sbios_requests; 1511 bool select_active_disp; 1512 bool lid_state; 1513 bool get_tv_standard; 1514 bool set_tv_standard; 1515 bool get_panel_expansion_mode; 1516 bool set_panel_expansion_mode; 1517 bool temperature_change; 1518 bool graphics_device_types; 1519 }; 1520 1521 struct radeon_atif { 1522 struct radeon_atif_notifications notifications; 1523 struct radeon_atif_functions functions; 1524 struct radeon_atif_notification_cfg notification_cfg; 1525 struct radeon_encoder *encoder_for_bl; 1526 }; 1527 1528 struct radeon_atcs_functions { 1529 bool get_ext_state; 1530 bool pcie_perf_req; 1531 bool pcie_dev_rdy; 1532 bool pcie_bus_width; 1533 }; 1534 1535 struct radeon_atcs { 1536 struct radeon_atcs_functions functions; 1537 }; 1538 1539 /* 1540 * Core structure, functions and helpers. 1541 */ 1542 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 1543 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 1544 1545 struct radeon_device { 1546 struct device *dev; 1547 struct drm_device *ddev; 1548 struct pci_dev *pdev; 1549 struct rw_semaphore exclusive_lock; 1550 /* ASIC */ 1551 union radeon_asic_config config; 1552 enum radeon_family family; 1553 unsigned long flags; 1554 int usec_timeout; 1555 enum radeon_pll_errata pll_errata; 1556 int num_gb_pipes; 1557 int num_z_pipes; 1558 int disp_priority; 1559 /* BIOS */ 1560 uint8_t *bios; 1561 bool is_atom_bios; 1562 uint16_t bios_header_start; 1563 struct radeon_bo *stollen_vga_memory; 1564 /* Register mmio */ 1565 resource_size_t rmmio_base; 1566 resource_size_t rmmio_size; 1567 /* protects concurrent MM_INDEX/DATA based register access */ 1568 spinlock_t mmio_idx_lock; 1569 void __iomem *rmmio; 1570 radeon_rreg_t mc_rreg; 1571 radeon_wreg_t mc_wreg; 1572 radeon_rreg_t pll_rreg; 1573 radeon_wreg_t pll_wreg; 1574 uint32_t pcie_reg_mask; 1575 radeon_rreg_t pciep_rreg; 1576 radeon_wreg_t pciep_wreg; 1577 /* io port */ 1578 void __iomem *rio_mem; 1579 resource_size_t rio_mem_size; 1580 struct radeon_clock clock; 1581 struct radeon_mc mc; 1582 struct radeon_gart gart; 1583 struct radeon_mode_info mode_info; 1584 struct radeon_scratch scratch; 1585 struct radeon_mman mman; 1586 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 1587 wait_queue_head_t fence_queue; 1588 struct mutex ring_lock; 1589 struct radeon_ring ring[RADEON_NUM_RINGS]; 1590 bool ib_pool_ready; 1591 struct radeon_sa_manager ring_tmp_bo; 1592 struct radeon_irq irq; 1593 struct radeon_asic *asic; 1594 struct radeon_gem gem; 1595 struct radeon_pm pm; 1596 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 1597 struct radeon_wb wb; 1598 struct radeon_dummy_page dummy_page; 1599 bool shutdown; 1600 bool suspend; 1601 bool need_dma32; 1602 bool accel_working; 1603 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 1604 const struct firmware *me_fw; /* all family ME firmware */ 1605 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 1606 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 1607 const struct firmware *mc_fw; /* NI MC firmware */ 1608 const struct firmware *ce_fw; /* SI CE firmware */ 1609 struct r600_blit r600_blit; 1610 struct r600_vram_scratch vram_scratch; 1611 int msi_enabled; /* msi enabled */ 1612 struct r600_ih ih; /* r6/700 interrupt ring */ 1613 struct si_rlc rlc; 1614 struct work_struct hotplug_work; 1615 struct work_struct audio_work; 1616 int num_crtc; /* number of crtcs */ 1617 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 1618 bool audio_enabled; 1619 struct r600_audio audio_status; /* audio stuff */ 1620 struct notifier_block acpi_nb; 1621 /* only one userspace can use Hyperz features or CMASK at a time */ 1622 struct drm_file *hyperz_filp; 1623 struct drm_file *cmask_filp; 1624 /* i2c buses */ 1625 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 1626 /* debugfs */ 1627 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 1628 unsigned debugfs_count; 1629 /* virtual memory */ 1630 struct radeon_vm_manager vm_manager; 1631 struct mutex gpu_clock_mutex; 1632 /* ACPI interface */ 1633 struct radeon_atif atif; 1634 struct radeon_atcs atcs; 1635 }; 1636 1637 int radeon_device_init(struct radeon_device *rdev, 1638 struct drm_device *ddev, 1639 struct pci_dev *pdev, 1640 uint32_t flags); 1641 void radeon_device_fini(struct radeon_device *rdev); 1642 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 1643 1644 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 1645 bool always_indirect); 1646 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 1647 bool always_indirect); 1648 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 1649 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 1650 1651 /* 1652 * Cast helper 1653 */ 1654 #define to_radeon_fence(p) ((struct radeon_fence *)(p)) 1655 1656 /* 1657 * Registers read & write functions. 1658 */ 1659 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 1660 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 1661 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 1662 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 1663 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 1664 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 1665 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) 1666 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 1667 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 1668 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1669 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1670 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 1671 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 1672 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 1673 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 1674 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 1675 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 1676 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) 1677 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 1678 #define WREG32_P(reg, val, mask) \ 1679 do { \ 1680 uint32_t tmp_ = RREG32(reg); \ 1681 tmp_ &= (mask); \ 1682 tmp_ |= ((val) & ~(mask)); \ 1683 WREG32(reg, tmp_); \ 1684 } while (0) 1685 #define WREG32_PLL_P(reg, val, mask) \ 1686 do { \ 1687 uint32_t tmp_ = RREG32_PLL(reg); \ 1688 tmp_ &= (mask); \ 1689 tmp_ |= ((val) & ~(mask)); \ 1690 WREG32_PLL(reg, tmp_); \ 1691 } while (0) 1692 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 1693 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 1694 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 1695 1696 /* 1697 * Indirect registers accessor 1698 */ 1699 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 1700 { 1701 uint32_t r; 1702 1703 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 1704 r = RREG32(RADEON_PCIE_DATA); 1705 return r; 1706 } 1707 1708 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1709 { 1710 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 1711 WREG32(RADEON_PCIE_DATA, (v)); 1712 } 1713 1714 void r100_pll_errata_after_index(struct radeon_device *rdev); 1715 1716 1717 /* 1718 * ASICs helpers. 1719 */ 1720 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 1721 (rdev->pdev->device == 0x5969)) 1722 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 1723 (rdev->family == CHIP_RV200) || \ 1724 (rdev->family == CHIP_RS100) || \ 1725 (rdev->family == CHIP_RS200) || \ 1726 (rdev->family == CHIP_RV250) || \ 1727 (rdev->family == CHIP_RV280) || \ 1728 (rdev->family == CHIP_RS300)) 1729 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 1730 (rdev->family == CHIP_RV350) || \ 1731 (rdev->family == CHIP_R350) || \ 1732 (rdev->family == CHIP_RV380) || \ 1733 (rdev->family == CHIP_R420) || \ 1734 (rdev->family == CHIP_R423) || \ 1735 (rdev->family == CHIP_RV410) || \ 1736 (rdev->family == CHIP_RS400) || \ 1737 (rdev->family == CHIP_RS480)) 1738 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 1739 (rdev->ddev->pdev->device == 0x9443) || \ 1740 (rdev->ddev->pdev->device == 0x944B) || \ 1741 (rdev->ddev->pdev->device == 0x9506) || \ 1742 (rdev->ddev->pdev->device == 0x9509) || \ 1743 (rdev->ddev->pdev->device == 0x950F) || \ 1744 (rdev->ddev->pdev->device == 0x689C) || \ 1745 (rdev->ddev->pdev->device == 0x689D)) 1746 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 1747 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 1748 (rdev->family == CHIP_RS690) || \ 1749 (rdev->family == CHIP_RS740) || \ 1750 (rdev->family >= CHIP_R600)) 1751 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 1752 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 1753 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 1754 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 1755 (rdev->flags & RADEON_IS_IGP)) 1756 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 1757 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 1758 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 1759 (rdev->flags & RADEON_IS_IGP)) 1760 1761 /* 1762 * BIOS helpers. 1763 */ 1764 #define RBIOS8(i) (rdev->bios[i]) 1765 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1766 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1767 1768 int radeon_combios_init(struct radeon_device *rdev); 1769 void radeon_combios_fini(struct radeon_device *rdev); 1770 int radeon_atombios_init(struct radeon_device *rdev); 1771 void radeon_atombios_fini(struct radeon_device *rdev); 1772 1773 1774 /* 1775 * RING helpers. 1776 */ 1777 #if DRM_DEBUG_CODE == 0 1778 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 1779 { 1780 ring->ring[ring->wptr++] = v; 1781 ring->wptr &= ring->ptr_mask; 1782 ring->count_dw--; 1783 ring->ring_free_dw--; 1784 } 1785 #else 1786 /* With debugging this is just too big to inline */ 1787 void radeon_ring_write(struct radeon_ring *ring, uint32_t v); 1788 #endif 1789 1790 /* 1791 * ASICs macro. 1792 */ 1793 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 1794 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 1795 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 1796 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 1797 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p)) 1798 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 1799 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 1800 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 1801 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) 1802 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 1803 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 1804 #define radeon_asic_vm_set_page(rdev, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (pe), (addr), (count), (incr), (flags))) 1805 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) 1806 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) 1807 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) 1808 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) 1809 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) 1810 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) 1811 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm)) 1812 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 1813 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 1814 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 1815 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 1816 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 1817 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) 1818 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 1819 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 1820 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) 1821 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) 1822 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 1823 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 1824 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 1825 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 1826 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 1827 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 1828 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 1829 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 1830 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 1831 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 1832 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 1833 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 1834 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 1835 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 1836 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 1837 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 1838 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 1839 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 1840 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 1841 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 1842 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 1843 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 1844 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 1845 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc)) 1846 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 1847 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) 1848 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 1849 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 1850 1851 /* Common functions */ 1852 /* AGP */ 1853 extern int radeon_gpu_reset(struct radeon_device *rdev); 1854 extern void radeon_agp_disable(struct radeon_device *rdev); 1855 extern int radeon_modeset_init(struct radeon_device *rdev); 1856 extern void radeon_modeset_fini(struct radeon_device *rdev); 1857 extern bool radeon_card_posted(struct radeon_device *rdev); 1858 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 1859 extern void radeon_update_display_priority(struct radeon_device *rdev); 1860 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 1861 extern void radeon_scratch_init(struct radeon_device *rdev); 1862 extern void radeon_wb_fini(struct radeon_device *rdev); 1863 extern int radeon_wb_init(struct radeon_device *rdev); 1864 extern void radeon_wb_disable(struct radeon_device *rdev); 1865 extern void radeon_surface_init(struct radeon_device *rdev); 1866 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 1867 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 1868 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 1869 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 1870 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 1871 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 1872 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 1873 extern int radeon_resume_kms(struct drm_device *dev); 1874 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); 1875 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 1876 1877 /* 1878 * vm 1879 */ 1880 int radeon_vm_manager_init(struct radeon_device *rdev); 1881 void radeon_vm_manager_fini(struct radeon_device *rdev); 1882 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 1883 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 1884 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm); 1885 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm); 1886 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 1887 struct radeon_vm *vm, int ring); 1888 void radeon_vm_fence(struct radeon_device *rdev, 1889 struct radeon_vm *vm, 1890 struct radeon_fence *fence); 1891 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 1892 int radeon_vm_bo_update_pte(struct radeon_device *rdev, 1893 struct radeon_vm *vm, 1894 struct radeon_bo *bo, 1895 struct ttm_mem_reg *mem); 1896 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 1897 struct radeon_bo *bo); 1898 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 1899 struct radeon_bo *bo); 1900 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 1901 struct radeon_vm *vm, 1902 struct radeon_bo *bo); 1903 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 1904 struct radeon_bo_va *bo_va, 1905 uint64_t offset, 1906 uint32_t flags); 1907 int radeon_vm_bo_rmv(struct radeon_device *rdev, 1908 struct radeon_bo_va *bo_va); 1909 1910 /* audio */ 1911 void r600_audio_update_hdmi(struct work_struct *work); 1912 1913 /* 1914 * R600 vram scratch functions 1915 */ 1916 int r600_vram_scratch_init(struct radeon_device *rdev); 1917 void r600_vram_scratch_fini(struct radeon_device *rdev); 1918 1919 /* 1920 * r600 cs checking helper 1921 */ 1922 unsigned r600_mip_minify(unsigned size, unsigned level); 1923 bool r600_fmt_is_valid_color(u32 format); 1924 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 1925 int r600_fmt_get_blocksize(u32 format); 1926 int r600_fmt_get_nblocksx(u32 format, u32 w); 1927 int r600_fmt_get_nblocksy(u32 format, u32 h); 1928 1929 /* 1930 * r600 functions used by radeon_encoder.c 1931 */ 1932 struct radeon_hdmi_acr { 1933 u32 clock; 1934 1935 int n_32khz; 1936 int cts_32khz; 1937 1938 int n_44_1khz; 1939 int cts_44_1khz; 1940 1941 int n_48khz; 1942 int cts_48khz; 1943 1944 }; 1945 1946 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 1947 1948 extern void r600_hdmi_enable(struct drm_encoder *encoder); 1949 extern void r600_hdmi_disable(struct drm_encoder *encoder); 1950 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 1951 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1952 u32 tiling_pipe_num, 1953 u32 max_rb_num, 1954 u32 total_max_rb_num, 1955 u32 enabled_rb_mask); 1956 1957 /* 1958 * evergreen functions used by radeon_encoder.c 1959 */ 1960 1961 extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 1962 1963 extern int ni_init_microcode(struct radeon_device *rdev); 1964 extern int ni_mc_load_microcode(struct radeon_device *rdev); 1965 1966 /* radeon_acpi.c */ 1967 #if defined(CONFIG_ACPI) 1968 extern int radeon_acpi_init(struct radeon_device *rdev); 1969 extern void radeon_acpi_fini(struct radeon_device *rdev); 1970 #else 1971 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 1972 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 1973 #endif 1974 1975 #include "radeon_object.h" 1976 1977 #endif 1978