1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 /* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45 /* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63 #include <linux/atomic.h> 64 #include <linux/wait.h> 65 #include <linux/list.h> 66 #include <linux/kref.h> 67 #include <linux/interval_tree.h> 68 #include <linux/hashtable.h> 69 #include <linux/dma-fence.h> 70 71 #include <ttm/ttm_bo_api.h> 72 #include <ttm/ttm_bo_driver.h> 73 #include <ttm/ttm_placement.h> 74 #include <ttm/ttm_module.h> 75 #include <ttm/ttm_execbuf_util.h> 76 77 #include <drm/drm_gem.h> 78 79 #include "radeon_family.h" 80 #include "radeon_mode.h" 81 #include "radeon_reg.h" 82 83 /* 84 * Modules parameters. 85 */ 86 extern int radeon_no_wb; 87 extern int radeon_modeset; 88 extern int radeon_dynclks; 89 extern int radeon_r4xx_atom; 90 extern int radeon_agpmode; 91 extern int radeon_vram_limit; 92 extern int radeon_gart_size; 93 extern int radeon_benchmarking; 94 extern int radeon_testing; 95 extern int radeon_connector_table; 96 extern int radeon_tv; 97 extern int radeon_audio; 98 extern int radeon_disp_priority; 99 extern int radeon_hw_i2c; 100 extern int radeon_pcie_gen2; 101 extern int radeon_msi; 102 extern int radeon_lockup_timeout; 103 extern int radeon_fastfb; 104 extern int radeon_dpm; 105 extern int radeon_aspm; 106 extern int radeon_runtime_pm; 107 extern int radeon_hard_reset; 108 extern int radeon_vm_size; 109 extern int radeon_vm_block_size; 110 extern int radeon_deep_color; 111 extern int radeon_use_pflipirq; 112 extern int radeon_bapm; 113 extern int radeon_backlight; 114 extern int radeon_auxch; 115 extern int radeon_mst; 116 extern int radeon_uvd; 117 extern int radeon_vce; 118 119 /* 120 * Copy from radeon_drv.h so we don't have to include both and have conflicting 121 * symbol; 122 */ 123 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 124 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 125 #define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */ 126 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 127 #define RADEON_IB_POOL_SIZE 16 128 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 129 #define RADEONFB_CONN_LIMIT 4 130 #define RADEON_BIOS_NUM_SCRATCH 8 131 132 /* internal ring indices */ 133 /* r1xx+ has gfx CP ring */ 134 #define RADEON_RING_TYPE_GFX_INDEX 0 135 136 /* cayman has 2 compute CP rings */ 137 #define CAYMAN_RING_TYPE_CP1_INDEX 1 138 #define CAYMAN_RING_TYPE_CP2_INDEX 2 139 140 /* R600+ has an async dma ring */ 141 #define R600_RING_TYPE_DMA_INDEX 3 142 /* cayman add a second async dma ring */ 143 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 144 145 /* R600+ */ 146 #define R600_RING_TYPE_UVD_INDEX 5 147 148 /* TN+ */ 149 #define TN_RING_TYPE_VCE1_INDEX 6 150 #define TN_RING_TYPE_VCE2_INDEX 7 151 152 /* max number of rings */ 153 #define RADEON_NUM_RINGS 8 154 155 /* number of hw syncs before falling back on blocking */ 156 #define RADEON_NUM_SYNCS 4 157 158 /* hardcode those limit for now */ 159 #define RADEON_VA_IB_OFFSET (1 << 20) 160 #define RADEON_VA_RESERVED_SIZE (8 << 20) 161 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 162 163 /* hard reset data */ 164 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 165 166 /* reset flags */ 167 #define RADEON_RESET_GFX (1 << 0) 168 #define RADEON_RESET_COMPUTE (1 << 1) 169 #define RADEON_RESET_DMA (1 << 2) 170 #define RADEON_RESET_CP (1 << 3) 171 #define RADEON_RESET_GRBM (1 << 4) 172 #define RADEON_RESET_DMA1 (1 << 5) 173 #define RADEON_RESET_RLC (1 << 6) 174 #define RADEON_RESET_SEM (1 << 7) 175 #define RADEON_RESET_IH (1 << 8) 176 #define RADEON_RESET_VMC (1 << 9) 177 #define RADEON_RESET_MC (1 << 10) 178 #define RADEON_RESET_DISPLAY (1 << 11) 179 180 /* CG block flags */ 181 #define RADEON_CG_BLOCK_GFX (1 << 0) 182 #define RADEON_CG_BLOCK_MC (1 << 1) 183 #define RADEON_CG_BLOCK_SDMA (1 << 2) 184 #define RADEON_CG_BLOCK_UVD (1 << 3) 185 #define RADEON_CG_BLOCK_VCE (1 << 4) 186 #define RADEON_CG_BLOCK_HDP (1 << 5) 187 #define RADEON_CG_BLOCK_BIF (1 << 6) 188 189 /* CG flags */ 190 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 191 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 192 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 193 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 194 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 195 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 196 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 197 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 198 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 199 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 200 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 201 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 202 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 203 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 204 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 205 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 206 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 207 208 /* PG flags */ 209 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 210 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 211 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 212 #define RADEON_PG_SUPPORT_UVD (1 << 3) 213 #define RADEON_PG_SUPPORT_VCE (1 << 4) 214 #define RADEON_PG_SUPPORT_CP (1 << 5) 215 #define RADEON_PG_SUPPORT_GDS (1 << 6) 216 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 217 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 218 #define RADEON_PG_SUPPORT_ACP (1 << 9) 219 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 220 221 /* max cursor sizes (in pixels) */ 222 #define CURSOR_WIDTH 64 223 #define CURSOR_HEIGHT 64 224 225 #define CIK_CURSOR_WIDTH 128 226 #define CIK_CURSOR_HEIGHT 128 227 228 /* 229 * Errata workarounds. 230 */ 231 enum radeon_pll_errata { 232 CHIP_ERRATA_R300_CG = 0x00000001, 233 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 234 CHIP_ERRATA_PLL_DELAY = 0x00000004 235 }; 236 237 238 struct radeon_device; 239 240 241 /* 242 * BIOS. 243 */ 244 bool radeon_get_bios(struct radeon_device *rdev); 245 246 /* 247 * Dummy page 248 */ 249 struct radeon_dummy_page { 250 uint64_t entry; 251 struct page *page; 252 dma_addr_t addr; 253 }; 254 int radeon_dummy_page_init(struct radeon_device *rdev); 255 void radeon_dummy_page_fini(struct radeon_device *rdev); 256 257 258 /* 259 * Clocks 260 */ 261 struct radeon_clock { 262 struct radeon_pll p1pll; 263 struct radeon_pll p2pll; 264 struct radeon_pll dcpll; 265 struct radeon_pll spll; 266 struct radeon_pll mpll; 267 /* 10 Khz units */ 268 uint32_t default_mclk; 269 uint32_t default_sclk; 270 uint32_t default_dispclk; 271 uint32_t current_dispclk; 272 uint32_t dp_extclk; 273 uint32_t max_pixel_clock; 274 uint32_t vco_freq; 275 }; 276 277 /* 278 * Power management 279 */ 280 int radeon_pm_init(struct radeon_device *rdev); 281 int radeon_pm_late_init(struct radeon_device *rdev); 282 void radeon_pm_fini(struct radeon_device *rdev); 283 void radeon_pm_compute_clocks(struct radeon_device *rdev); 284 void radeon_pm_suspend(struct radeon_device *rdev); 285 void radeon_pm_resume(struct radeon_device *rdev); 286 void radeon_combios_get_power_modes(struct radeon_device *rdev); 287 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 288 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 289 u8 clock_type, 290 u32 clock, 291 bool strobe_mode, 292 struct atom_clock_dividers *dividers); 293 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 294 u32 clock, 295 bool strobe_mode, 296 struct atom_mpll_param *mpll_param); 297 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 298 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 299 u16 voltage_level, u8 voltage_type, 300 u32 *gpio_value, u32 *gpio_mask); 301 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 302 u32 eng_clock, u32 mem_clock); 303 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 304 u8 voltage_type, u16 *voltage_step); 305 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 306 u16 voltage_id, u16 *voltage); 307 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 308 u16 *voltage, 309 u16 leakage_idx); 310 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 311 u16 *leakage_id); 312 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 313 u16 *vddc, u16 *vddci, 314 u16 virtual_voltage_id, 315 u16 vbios_voltage_id); 316 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 317 u16 virtual_voltage_id, 318 u16 *voltage); 319 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 320 u8 voltage_type, 321 u16 nominal_voltage, 322 u16 *true_voltage); 323 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 324 u8 voltage_type, u16 *min_voltage); 325 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 326 u8 voltage_type, u16 *max_voltage); 327 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 328 u8 voltage_type, u8 voltage_mode, 329 struct atom_voltage_table *voltage_table); 330 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 331 u8 voltage_type, u8 voltage_mode); 332 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 333 u8 voltage_type, 334 u8 *svd_gpio_id, u8 *svc_gpio_id); 335 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 336 u32 mem_clock); 337 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 338 u32 mem_clock); 339 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 340 u8 module_index, 341 struct atom_mc_reg_table *reg_table); 342 int radeon_atom_get_memory_info(struct radeon_device *rdev, 343 u8 module_index, struct atom_memory_info *mem_info); 344 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 345 bool gddr5, u8 module_index, 346 struct atom_memory_clock_range_table *mclk_range_table); 347 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 348 u16 voltage_id, u16 *voltage); 349 void rs690_pm_info(struct radeon_device *rdev); 350 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 351 unsigned *bankh, unsigned *mtaspect, 352 unsigned *tile_split); 353 354 /* 355 * Fences. 356 */ 357 struct radeon_fence_driver { 358 struct radeon_device *rdev; 359 uint32_t scratch_reg; 360 uint64_t gpu_addr; 361 volatile uint32_t *cpu_addr; 362 /* sync_seq is protected by ring emission lock */ 363 uint64_t sync_seq[RADEON_NUM_RINGS]; 364 atomic64_t last_seq; 365 bool initialized, delayed_irq; 366 struct delayed_work lockup_work; 367 }; 368 369 struct radeon_fence { 370 struct dma_fence base; 371 372 struct radeon_device *rdev; 373 uint64_t seq; 374 /* RB, DMA, etc. */ 375 unsigned ring; 376 bool is_vm_update; 377 378 wait_queue_t fence_wake; 379 }; 380 381 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 382 int radeon_fence_driver_init(struct radeon_device *rdev); 383 void radeon_fence_driver_fini(struct radeon_device *rdev); 384 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 385 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 386 void radeon_fence_process(struct radeon_device *rdev, int ring); 387 bool radeon_fence_signaled(struct radeon_fence *fence); 388 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout); 389 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 390 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 391 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 392 int radeon_fence_wait_any(struct radeon_device *rdev, 393 struct radeon_fence **fences, 394 bool intr); 395 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 396 void radeon_fence_unref(struct radeon_fence **fence); 397 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 398 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 399 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 400 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 401 struct radeon_fence *b) 402 { 403 if (!a) { 404 return b; 405 } 406 407 if (!b) { 408 return a; 409 } 410 411 BUG_ON(a->ring != b->ring); 412 413 if (a->seq > b->seq) { 414 return a; 415 } else { 416 return b; 417 } 418 } 419 420 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 421 struct radeon_fence *b) 422 { 423 if (!a) { 424 return false; 425 } 426 427 if (!b) { 428 return true; 429 } 430 431 BUG_ON(a->ring != b->ring); 432 433 return a->seq < b->seq; 434 } 435 436 /* 437 * Tiling registers 438 */ 439 struct radeon_surface_reg { 440 struct radeon_bo *bo; 441 }; 442 443 #define RADEON_GEM_MAX_SURFACES 8 444 445 /* 446 * TTM. 447 */ 448 struct radeon_mman { 449 struct ttm_bo_global_ref bo_global_ref; 450 struct drm_global_reference mem_global_ref; 451 struct ttm_bo_device bdev; 452 bool mem_global_referenced; 453 bool initialized; 454 455 #if defined(CONFIG_DEBUG_FS) 456 struct dentry *vram; 457 struct dentry *gtt; 458 #endif 459 }; 460 461 struct radeon_bo_list { 462 struct radeon_bo *robj; 463 struct ttm_validate_buffer tv; 464 uint64_t gpu_offset; 465 unsigned prefered_domains; 466 unsigned allowed_domains; 467 uint32_t tiling_flags; 468 }; 469 470 /* bo virtual address in a specific vm */ 471 struct radeon_bo_va { 472 /* protected by bo being reserved */ 473 struct list_head bo_list; 474 uint32_t flags; 475 struct radeon_fence *last_pt_update; 476 unsigned ref_count; 477 478 /* protected by vm mutex */ 479 struct interval_tree_node it; 480 struct list_head vm_status; 481 482 /* constant after initialization */ 483 struct radeon_vm *vm; 484 struct radeon_bo *bo; 485 }; 486 487 struct radeon_bo { 488 /* Protected by gem.mutex */ 489 struct list_head list; 490 /* Protected by tbo.reserved */ 491 u32 initial_domain; 492 struct ttm_place placements[4]; 493 struct ttm_placement placement; 494 struct ttm_buffer_object tbo; 495 struct ttm_bo_kmap_obj kmap; 496 u32 flags; 497 unsigned pin_count; 498 void *kptr; 499 u32 tiling_flags; 500 u32 pitch; 501 int surface_reg; 502 unsigned prime_shared_count; 503 /* list of all virtual address to which this bo 504 * is associated to 505 */ 506 struct list_head va; 507 /* Constant after initialization */ 508 struct radeon_device *rdev; 509 struct drm_gem_object gem_base; 510 511 struct ttm_bo_kmap_obj dma_buf_vmap; 512 pid_t pid; 513 514 struct radeon_mn *mn; 515 struct list_head mn_list; 516 }; 517 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 518 519 int radeon_gem_debugfs_init(struct radeon_device *rdev); 520 521 /* sub-allocation manager, it has to be protected by another lock. 522 * By conception this is an helper for other part of the driver 523 * like the indirect buffer or semaphore, which both have their 524 * locking. 525 * 526 * Principe is simple, we keep a list of sub allocation in offset 527 * order (first entry has offset == 0, last entry has the highest 528 * offset). 529 * 530 * When allocating new object we first check if there is room at 531 * the end total_size - (last_object_offset + last_object_size) >= 532 * alloc_size. If so we allocate new object there. 533 * 534 * When there is not enough room at the end, we start waiting for 535 * each sub object until we reach object_offset+object_size >= 536 * alloc_size, this object then become the sub object we return. 537 * 538 * Alignment can't be bigger than page size. 539 * 540 * Hole are not considered for allocation to keep things simple. 541 * Assumption is that there won't be hole (all object on same 542 * alignment). 543 */ 544 struct radeon_sa_manager { 545 wait_queue_head_t wq; 546 struct radeon_bo *bo; 547 struct list_head *hole; 548 struct list_head flist[RADEON_NUM_RINGS]; 549 struct list_head olist; 550 unsigned size; 551 uint64_t gpu_addr; 552 void *cpu_ptr; 553 uint32_t domain; 554 uint32_t align; 555 }; 556 557 struct radeon_sa_bo; 558 559 /* sub-allocation buffer */ 560 struct radeon_sa_bo { 561 struct list_head olist; 562 struct list_head flist; 563 struct radeon_sa_manager *manager; 564 unsigned soffset; 565 unsigned eoffset; 566 struct radeon_fence *fence; 567 }; 568 569 /* 570 * GEM objects. 571 */ 572 struct radeon_gem { 573 struct mutex mutex; 574 struct list_head objects; 575 }; 576 577 int radeon_gem_init(struct radeon_device *rdev); 578 void radeon_gem_fini(struct radeon_device *rdev); 579 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 580 int alignment, int initial_domain, 581 u32 flags, bool kernel, 582 struct drm_gem_object **obj); 583 584 int radeon_mode_dumb_create(struct drm_file *file_priv, 585 struct drm_device *dev, 586 struct drm_mode_create_dumb *args); 587 int radeon_mode_dumb_mmap(struct drm_file *filp, 588 struct drm_device *dev, 589 uint32_t handle, uint64_t *offset_p); 590 591 /* 592 * Semaphores. 593 */ 594 struct radeon_semaphore { 595 struct radeon_sa_bo *sa_bo; 596 signed waiters; 597 uint64_t gpu_addr; 598 }; 599 600 int radeon_semaphore_create(struct radeon_device *rdev, 601 struct radeon_semaphore **semaphore); 602 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 603 struct radeon_semaphore *semaphore); 604 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 605 struct radeon_semaphore *semaphore); 606 void radeon_semaphore_free(struct radeon_device *rdev, 607 struct radeon_semaphore **semaphore, 608 struct radeon_fence *fence); 609 610 /* 611 * Synchronization 612 */ 613 struct radeon_sync { 614 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS]; 615 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 616 struct radeon_fence *last_vm_update; 617 }; 618 619 void radeon_sync_create(struct radeon_sync *sync); 620 void radeon_sync_fence(struct radeon_sync *sync, 621 struct radeon_fence *fence); 622 int radeon_sync_resv(struct radeon_device *rdev, 623 struct radeon_sync *sync, 624 struct reservation_object *resv, 625 bool shared); 626 int radeon_sync_rings(struct radeon_device *rdev, 627 struct radeon_sync *sync, 628 int waiting_ring); 629 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync, 630 struct radeon_fence *fence); 631 632 /* 633 * GART structures, functions & helpers 634 */ 635 struct radeon_mc; 636 637 #define RADEON_GPU_PAGE_SIZE 4096 638 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 639 #define RADEON_GPU_PAGE_SHIFT 12 640 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 641 642 #define RADEON_GART_PAGE_DUMMY 0 643 #define RADEON_GART_PAGE_VALID (1 << 0) 644 #define RADEON_GART_PAGE_READ (1 << 1) 645 #define RADEON_GART_PAGE_WRITE (1 << 2) 646 #define RADEON_GART_PAGE_SNOOP (1 << 3) 647 648 struct radeon_gart { 649 dma_addr_t table_addr; 650 struct radeon_bo *robj; 651 void *ptr; 652 unsigned num_gpu_pages; 653 unsigned num_cpu_pages; 654 unsigned table_size; 655 struct page **pages; 656 uint64_t *pages_entry; 657 bool ready; 658 }; 659 660 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 661 void radeon_gart_table_ram_free(struct radeon_device *rdev); 662 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 663 void radeon_gart_table_vram_free(struct radeon_device *rdev); 664 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 665 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 666 int radeon_gart_init(struct radeon_device *rdev); 667 void radeon_gart_fini(struct radeon_device *rdev); 668 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 669 int pages); 670 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 671 int pages, struct page **pagelist, 672 dma_addr_t *dma_addr, uint32_t flags); 673 674 675 /* 676 * GPU MC structures, functions & helpers 677 */ 678 struct radeon_mc { 679 resource_size_t aper_size; 680 resource_size_t aper_base; 681 resource_size_t agp_base; 682 /* for some chips with <= 32MB we need to lie 683 * about vram size near mc fb location */ 684 u64 mc_vram_size; 685 u64 visible_vram_size; 686 u64 gtt_size; 687 u64 gtt_start; 688 u64 gtt_end; 689 u64 vram_start; 690 u64 vram_end; 691 unsigned vram_width; 692 u64 real_vram_size; 693 int vram_mtrr; 694 bool vram_is_ddr; 695 bool igp_sideport_enabled; 696 u64 gtt_base_align; 697 u64 mc_mask; 698 }; 699 700 bool radeon_combios_sideport_present(struct radeon_device *rdev); 701 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 702 703 /* 704 * GPU scratch registers structures, functions & helpers 705 */ 706 struct radeon_scratch { 707 unsigned num_reg; 708 uint32_t reg_base; 709 bool free[32]; 710 uint32_t reg[32]; 711 }; 712 713 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 714 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 715 716 /* 717 * GPU doorbell structures, functions & helpers 718 */ 719 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 720 721 struct radeon_doorbell { 722 /* doorbell mmio */ 723 resource_size_t base; 724 resource_size_t size; 725 u32 __iomem *ptr; 726 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 727 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS); 728 }; 729 730 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 731 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 732 void radeon_doorbell_get_kfd_info(struct radeon_device *rdev, 733 phys_addr_t *aperture_base, 734 size_t *aperture_size, 735 size_t *start_offset); 736 737 /* 738 * IRQS. 739 */ 740 741 struct radeon_flip_work { 742 struct work_struct flip_work; 743 struct work_struct unpin_work; 744 struct radeon_device *rdev; 745 int crtc_id; 746 u32 target_vblank; 747 uint64_t base; 748 struct drm_pending_vblank_event *event; 749 struct radeon_bo *old_rbo; 750 struct dma_fence *fence; 751 bool async; 752 }; 753 754 struct r500_irq_stat_regs { 755 u32 disp_int; 756 u32 hdmi0_status; 757 }; 758 759 struct r600_irq_stat_regs { 760 u32 disp_int; 761 u32 disp_int_cont; 762 u32 disp_int_cont2; 763 u32 d1grph_int; 764 u32 d2grph_int; 765 u32 hdmi0_status; 766 u32 hdmi1_status; 767 }; 768 769 struct evergreen_irq_stat_regs { 770 u32 disp_int; 771 u32 disp_int_cont; 772 u32 disp_int_cont2; 773 u32 disp_int_cont3; 774 u32 disp_int_cont4; 775 u32 disp_int_cont5; 776 u32 d1grph_int; 777 u32 d2grph_int; 778 u32 d3grph_int; 779 u32 d4grph_int; 780 u32 d5grph_int; 781 u32 d6grph_int; 782 u32 afmt_status1; 783 u32 afmt_status2; 784 u32 afmt_status3; 785 u32 afmt_status4; 786 u32 afmt_status5; 787 u32 afmt_status6; 788 }; 789 790 struct cik_irq_stat_regs { 791 u32 disp_int; 792 u32 disp_int_cont; 793 u32 disp_int_cont2; 794 u32 disp_int_cont3; 795 u32 disp_int_cont4; 796 u32 disp_int_cont5; 797 u32 disp_int_cont6; 798 u32 d1grph_int; 799 u32 d2grph_int; 800 u32 d3grph_int; 801 u32 d4grph_int; 802 u32 d5grph_int; 803 u32 d6grph_int; 804 }; 805 806 union radeon_irq_stat_regs { 807 struct r500_irq_stat_regs r500; 808 struct r600_irq_stat_regs r600; 809 struct evergreen_irq_stat_regs evergreen; 810 struct cik_irq_stat_regs cik; 811 }; 812 813 struct radeon_irq { 814 bool installed; 815 spinlock_t lock; 816 atomic_t ring_int[RADEON_NUM_RINGS]; 817 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 818 atomic_t pflip[RADEON_MAX_CRTCS]; 819 wait_queue_head_t vblank_queue; 820 bool hpd[RADEON_MAX_HPD_PINS]; 821 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 822 union radeon_irq_stat_regs stat_regs; 823 bool dpm_thermal; 824 }; 825 826 int radeon_irq_kms_init(struct radeon_device *rdev); 827 void radeon_irq_kms_fini(struct radeon_device *rdev); 828 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 829 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); 830 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 831 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 832 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 833 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 834 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 835 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 836 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 837 838 /* 839 * CP & rings. 840 */ 841 842 struct radeon_ib { 843 struct radeon_sa_bo *sa_bo; 844 uint32_t length_dw; 845 uint64_t gpu_addr; 846 uint32_t *ptr; 847 int ring; 848 struct radeon_fence *fence; 849 struct radeon_vm *vm; 850 bool is_const_ib; 851 struct radeon_sync sync; 852 }; 853 854 struct radeon_ring { 855 struct radeon_bo *ring_obj; 856 volatile uint32_t *ring; 857 unsigned rptr_offs; 858 unsigned rptr_save_reg; 859 u64 next_rptr_gpu_addr; 860 volatile u32 *next_rptr_cpu_addr; 861 unsigned wptr; 862 unsigned wptr_old; 863 unsigned ring_size; 864 unsigned ring_free_dw; 865 int count_dw; 866 atomic_t last_rptr; 867 atomic64_t last_activity; 868 uint64_t gpu_addr; 869 uint32_t align_mask; 870 uint32_t ptr_mask; 871 bool ready; 872 u32 nop; 873 u32 idx; 874 u64 last_semaphore_signal_addr; 875 u64 last_semaphore_wait_addr; 876 /* for CIK queues */ 877 u32 me; 878 u32 pipe; 879 u32 queue; 880 struct radeon_bo *mqd_obj; 881 u32 doorbell_index; 882 unsigned wptr_offs; 883 }; 884 885 struct radeon_mec { 886 struct radeon_bo *hpd_eop_obj; 887 u64 hpd_eop_gpu_addr; 888 u32 num_pipe; 889 u32 num_mec; 890 u32 num_queue; 891 }; 892 893 /* 894 * VM 895 */ 896 897 /* maximum number of VMIDs */ 898 #define RADEON_NUM_VM 16 899 900 /* number of entries in page table */ 901 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 902 903 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 904 #define RADEON_VM_PTB_ALIGN_SIZE 32768 905 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 906 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 907 908 #define R600_PTE_VALID (1 << 0) 909 #define R600_PTE_SYSTEM (1 << 1) 910 #define R600_PTE_SNOOPED (1 << 2) 911 #define R600_PTE_READABLE (1 << 5) 912 #define R600_PTE_WRITEABLE (1 << 6) 913 914 /* PTE (Page Table Entry) fragment field for different page sizes */ 915 #define R600_PTE_FRAG_4KB (0 << 7) 916 #define R600_PTE_FRAG_64KB (4 << 7) 917 #define R600_PTE_FRAG_256KB (6 << 7) 918 919 /* flags needed to be set so we can copy directly from the GART table */ 920 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 921 R600_PTE_SYSTEM | R600_PTE_VALID ) 922 923 struct radeon_vm_pt { 924 struct radeon_bo *bo; 925 uint64_t addr; 926 }; 927 928 struct radeon_vm_id { 929 unsigned id; 930 uint64_t pd_gpu_addr; 931 /* last flushed PD/PT update */ 932 struct radeon_fence *flushed_updates; 933 /* last use of vmid */ 934 struct radeon_fence *last_id_use; 935 }; 936 937 struct radeon_vm { 938 struct mutex mutex; 939 940 struct rb_root va; 941 942 /* protecting invalidated and freed */ 943 spinlock_t status_lock; 944 945 /* BOs moved, but not yet updated in the PT */ 946 struct list_head invalidated; 947 948 /* BOs freed, but not yet updated in the PT */ 949 struct list_head freed; 950 951 /* BOs cleared in the PT */ 952 struct list_head cleared; 953 954 /* contains the page directory */ 955 struct radeon_bo *page_directory; 956 unsigned max_pde_used; 957 958 /* array of page tables, one for each page directory entry */ 959 struct radeon_vm_pt *page_tables; 960 961 struct radeon_bo_va *ib_bo_va; 962 963 /* for id and flush management per ring */ 964 struct radeon_vm_id ids[RADEON_NUM_RINGS]; 965 }; 966 967 struct radeon_vm_manager { 968 struct radeon_fence *active[RADEON_NUM_VM]; 969 uint32_t max_pfn; 970 /* number of VMIDs */ 971 unsigned nvm; 972 /* vram base address for page table entry */ 973 u64 vram_base_offset; 974 /* is vm enabled? */ 975 bool enabled; 976 /* for hw to save the PD addr on suspend/resume */ 977 uint32_t saved_table_addr[RADEON_NUM_VM]; 978 }; 979 980 /* 981 * file private structure 982 */ 983 struct radeon_fpriv { 984 struct radeon_vm vm; 985 }; 986 987 /* 988 * R6xx+ IH ring 989 */ 990 struct r600_ih { 991 struct radeon_bo *ring_obj; 992 volatile uint32_t *ring; 993 unsigned rptr; 994 unsigned ring_size; 995 uint64_t gpu_addr; 996 uint32_t ptr_mask; 997 atomic_t lock; 998 bool enabled; 999 }; 1000 1001 /* 1002 * RLC stuff 1003 */ 1004 #include "clearstate_defs.h" 1005 1006 struct radeon_rlc { 1007 /* for power gating */ 1008 struct radeon_bo *save_restore_obj; 1009 uint64_t save_restore_gpu_addr; 1010 volatile uint32_t *sr_ptr; 1011 const u32 *reg_list; 1012 u32 reg_list_size; 1013 /* for clear state */ 1014 struct radeon_bo *clear_state_obj; 1015 uint64_t clear_state_gpu_addr; 1016 volatile uint32_t *cs_ptr; 1017 const struct cs_section_def *cs_data; 1018 u32 clear_state_size; 1019 /* for cp tables */ 1020 struct radeon_bo *cp_table_obj; 1021 uint64_t cp_table_gpu_addr; 1022 volatile uint32_t *cp_table_ptr; 1023 u32 cp_table_size; 1024 }; 1025 1026 int radeon_ib_get(struct radeon_device *rdev, int ring, 1027 struct radeon_ib *ib, struct radeon_vm *vm, 1028 unsigned size); 1029 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 1030 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 1031 struct radeon_ib *const_ib, bool hdp_flush); 1032 int radeon_ib_pool_init(struct radeon_device *rdev); 1033 void radeon_ib_pool_fini(struct radeon_device *rdev); 1034 int radeon_ib_ring_tests(struct radeon_device *rdev); 1035 /* Ring access between begin & end cannot sleep */ 1036 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 1037 struct radeon_ring *ring); 1038 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 1039 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1040 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1041 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1042 bool hdp_flush); 1043 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1044 bool hdp_flush); 1045 void radeon_ring_undo(struct radeon_ring *ring); 1046 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 1047 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 1048 void radeon_ring_lockup_update(struct radeon_device *rdev, 1049 struct radeon_ring *ring); 1050 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1051 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1052 uint32_t **data); 1053 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1054 unsigned size, uint32_t *data); 1055 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1056 unsigned rptr_offs, u32 nop); 1057 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1058 1059 1060 /* r600 async dma */ 1061 void r600_dma_stop(struct radeon_device *rdev); 1062 int r600_dma_resume(struct radeon_device *rdev); 1063 void r600_dma_fini(struct radeon_device *rdev); 1064 1065 void cayman_dma_stop(struct radeon_device *rdev); 1066 int cayman_dma_resume(struct radeon_device *rdev); 1067 void cayman_dma_fini(struct radeon_device *rdev); 1068 1069 /* 1070 * CS. 1071 */ 1072 struct radeon_cs_chunk { 1073 uint32_t length_dw; 1074 uint32_t *kdata; 1075 void __user *user_ptr; 1076 }; 1077 1078 struct radeon_cs_parser { 1079 struct device *dev; 1080 struct radeon_device *rdev; 1081 struct drm_file *filp; 1082 /* chunks */ 1083 unsigned nchunks; 1084 struct radeon_cs_chunk *chunks; 1085 uint64_t *chunks_array; 1086 /* IB */ 1087 unsigned idx; 1088 /* relocations */ 1089 unsigned nrelocs; 1090 struct radeon_bo_list *relocs; 1091 struct radeon_bo_list *vm_bos; 1092 struct list_head validated; 1093 unsigned dma_reloc_idx; 1094 /* indices of various chunks */ 1095 struct radeon_cs_chunk *chunk_ib; 1096 struct radeon_cs_chunk *chunk_relocs; 1097 struct radeon_cs_chunk *chunk_flags; 1098 struct radeon_cs_chunk *chunk_const_ib; 1099 struct radeon_ib ib; 1100 struct radeon_ib const_ib; 1101 void *track; 1102 unsigned family; 1103 int parser_error; 1104 u32 cs_flags; 1105 u32 ring; 1106 s32 priority; 1107 struct ww_acquire_ctx ticket; 1108 }; 1109 1110 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1111 { 1112 struct radeon_cs_chunk *ibc = p->chunk_ib; 1113 1114 if (ibc->kdata) 1115 return ibc->kdata[idx]; 1116 return p->ib.ptr[idx]; 1117 } 1118 1119 1120 struct radeon_cs_packet { 1121 unsigned idx; 1122 unsigned type; 1123 unsigned reg; 1124 unsigned opcode; 1125 int count; 1126 unsigned one_reg_wr; 1127 }; 1128 1129 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1130 struct radeon_cs_packet *pkt, 1131 unsigned idx, unsigned reg); 1132 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1133 struct radeon_cs_packet *pkt); 1134 1135 1136 /* 1137 * AGP 1138 */ 1139 int radeon_agp_init(struct radeon_device *rdev); 1140 void radeon_agp_resume(struct radeon_device *rdev); 1141 void radeon_agp_suspend(struct radeon_device *rdev); 1142 void radeon_agp_fini(struct radeon_device *rdev); 1143 1144 1145 /* 1146 * Writeback 1147 */ 1148 struct radeon_wb { 1149 struct radeon_bo *wb_obj; 1150 volatile uint32_t *wb; 1151 uint64_t gpu_addr; 1152 bool enabled; 1153 bool use_event; 1154 }; 1155 1156 #define RADEON_WB_SCRATCH_OFFSET 0 1157 #define RADEON_WB_RING0_NEXT_RPTR 256 1158 #define RADEON_WB_CP_RPTR_OFFSET 1024 1159 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1160 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1161 #define R600_WB_DMA_RPTR_OFFSET 1792 1162 #define R600_WB_IH_WPTR_OFFSET 2048 1163 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1164 #define R600_WB_EVENT_OFFSET 3072 1165 #define CIK_WB_CP1_WPTR_OFFSET 3328 1166 #define CIK_WB_CP2_WPTR_OFFSET 3584 1167 #define R600_WB_DMA_RING_TEST_OFFSET 3588 1168 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 1169 1170 /** 1171 * struct radeon_pm - power management datas 1172 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1173 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1174 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1175 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1176 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1177 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1178 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1179 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1180 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1181 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1182 * @needed_bandwidth: current bandwidth needs 1183 * 1184 * It keeps track of various data needed to take powermanagement decision. 1185 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1186 * Equation between gpu/memory clock and available bandwidth is hw dependent 1187 * (type of memory, bus size, efficiency, ...) 1188 */ 1189 1190 enum radeon_pm_method { 1191 PM_METHOD_PROFILE, 1192 PM_METHOD_DYNPM, 1193 PM_METHOD_DPM, 1194 }; 1195 1196 enum radeon_dynpm_state { 1197 DYNPM_STATE_DISABLED, 1198 DYNPM_STATE_MINIMUM, 1199 DYNPM_STATE_PAUSED, 1200 DYNPM_STATE_ACTIVE, 1201 DYNPM_STATE_SUSPENDED, 1202 }; 1203 enum radeon_dynpm_action { 1204 DYNPM_ACTION_NONE, 1205 DYNPM_ACTION_MINIMUM, 1206 DYNPM_ACTION_DOWNCLOCK, 1207 DYNPM_ACTION_UPCLOCK, 1208 DYNPM_ACTION_DEFAULT 1209 }; 1210 1211 enum radeon_voltage_type { 1212 VOLTAGE_NONE = 0, 1213 VOLTAGE_GPIO, 1214 VOLTAGE_VDDC, 1215 VOLTAGE_SW 1216 }; 1217 1218 enum radeon_pm_state_type { 1219 /* not used for dpm */ 1220 POWER_STATE_TYPE_DEFAULT, 1221 POWER_STATE_TYPE_POWERSAVE, 1222 /* user selectable states */ 1223 POWER_STATE_TYPE_BATTERY, 1224 POWER_STATE_TYPE_BALANCED, 1225 POWER_STATE_TYPE_PERFORMANCE, 1226 /* internal states */ 1227 POWER_STATE_TYPE_INTERNAL_UVD, 1228 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1229 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1230 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1231 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1232 POWER_STATE_TYPE_INTERNAL_BOOT, 1233 POWER_STATE_TYPE_INTERNAL_THERMAL, 1234 POWER_STATE_TYPE_INTERNAL_ACPI, 1235 POWER_STATE_TYPE_INTERNAL_ULV, 1236 POWER_STATE_TYPE_INTERNAL_3DPERF, 1237 }; 1238 1239 enum radeon_pm_profile_type { 1240 PM_PROFILE_DEFAULT, 1241 PM_PROFILE_AUTO, 1242 PM_PROFILE_LOW, 1243 PM_PROFILE_MID, 1244 PM_PROFILE_HIGH, 1245 }; 1246 1247 #define PM_PROFILE_DEFAULT_IDX 0 1248 #define PM_PROFILE_LOW_SH_IDX 1 1249 #define PM_PROFILE_MID_SH_IDX 2 1250 #define PM_PROFILE_HIGH_SH_IDX 3 1251 #define PM_PROFILE_LOW_MH_IDX 4 1252 #define PM_PROFILE_MID_MH_IDX 5 1253 #define PM_PROFILE_HIGH_MH_IDX 6 1254 #define PM_PROFILE_MAX 7 1255 1256 struct radeon_pm_profile { 1257 int dpms_off_ps_idx; 1258 int dpms_on_ps_idx; 1259 int dpms_off_cm_idx; 1260 int dpms_on_cm_idx; 1261 }; 1262 1263 enum radeon_int_thermal_type { 1264 THERMAL_TYPE_NONE, 1265 THERMAL_TYPE_EXTERNAL, 1266 THERMAL_TYPE_EXTERNAL_GPIO, 1267 THERMAL_TYPE_RV6XX, 1268 THERMAL_TYPE_RV770, 1269 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1270 THERMAL_TYPE_EVERGREEN, 1271 THERMAL_TYPE_SUMO, 1272 THERMAL_TYPE_NI, 1273 THERMAL_TYPE_SI, 1274 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1275 THERMAL_TYPE_CI, 1276 THERMAL_TYPE_KV, 1277 }; 1278 1279 struct radeon_voltage { 1280 enum radeon_voltage_type type; 1281 /* gpio voltage */ 1282 struct radeon_gpio_rec gpio; 1283 u32 delay; /* delay in usec from voltage drop to sclk change */ 1284 bool active_high; /* voltage drop is active when bit is high */ 1285 /* VDDC voltage */ 1286 u8 vddc_id; /* index into vddc voltage table */ 1287 u8 vddci_id; /* index into vddci voltage table */ 1288 bool vddci_enabled; 1289 /* r6xx+ sw */ 1290 u16 voltage; 1291 /* evergreen+ vddci */ 1292 u16 vddci; 1293 }; 1294 1295 /* clock mode flags */ 1296 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1297 1298 struct radeon_pm_clock_info { 1299 /* memory clock */ 1300 u32 mclk; 1301 /* engine clock */ 1302 u32 sclk; 1303 /* voltage info */ 1304 struct radeon_voltage voltage; 1305 /* standardized clock flags */ 1306 u32 flags; 1307 }; 1308 1309 /* state flags */ 1310 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1311 1312 struct radeon_power_state { 1313 enum radeon_pm_state_type type; 1314 struct radeon_pm_clock_info *clock_info; 1315 /* number of valid clock modes in this power state */ 1316 int num_clock_modes; 1317 struct radeon_pm_clock_info *default_clock_mode; 1318 /* standardized state flags */ 1319 u32 flags; 1320 u32 misc; /* vbios specific flags */ 1321 u32 misc2; /* vbios specific flags */ 1322 int pcie_lanes; /* pcie lanes */ 1323 }; 1324 1325 /* 1326 * Some modes are overclocked by very low value, accept them 1327 */ 1328 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1329 1330 enum radeon_dpm_auto_throttle_src { 1331 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1332 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1333 }; 1334 1335 enum radeon_dpm_event_src { 1336 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1337 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1338 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1339 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1340 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1341 }; 1342 1343 #define RADEON_MAX_VCE_LEVELS 6 1344 1345 enum radeon_vce_level { 1346 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1347 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1348 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1349 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1350 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1351 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1352 }; 1353 1354 struct radeon_ps { 1355 u32 caps; /* vbios flags */ 1356 u32 class; /* vbios flags */ 1357 u32 class2; /* vbios flags */ 1358 /* UVD clocks */ 1359 u32 vclk; 1360 u32 dclk; 1361 /* VCE clocks */ 1362 u32 evclk; 1363 u32 ecclk; 1364 bool vce_active; 1365 enum radeon_vce_level vce_level; 1366 /* asic priv */ 1367 void *ps_priv; 1368 }; 1369 1370 struct radeon_dpm_thermal { 1371 /* thermal interrupt work */ 1372 struct work_struct work; 1373 /* low temperature threshold */ 1374 int min_temp; 1375 /* high temperature threshold */ 1376 int max_temp; 1377 /* was interrupt low to high or high to low */ 1378 bool high_to_low; 1379 }; 1380 1381 enum radeon_clk_action 1382 { 1383 RADEON_SCLK_UP = 1, 1384 RADEON_SCLK_DOWN 1385 }; 1386 1387 struct radeon_blacklist_clocks 1388 { 1389 u32 sclk; 1390 u32 mclk; 1391 enum radeon_clk_action action; 1392 }; 1393 1394 struct radeon_clock_and_voltage_limits { 1395 u32 sclk; 1396 u32 mclk; 1397 u16 vddc; 1398 u16 vddci; 1399 }; 1400 1401 struct radeon_clock_array { 1402 u32 count; 1403 u32 *values; 1404 }; 1405 1406 struct radeon_clock_voltage_dependency_entry { 1407 u32 clk; 1408 u16 v; 1409 }; 1410 1411 struct radeon_clock_voltage_dependency_table { 1412 u32 count; 1413 struct radeon_clock_voltage_dependency_entry *entries; 1414 }; 1415 1416 union radeon_cac_leakage_entry { 1417 struct { 1418 u16 vddc; 1419 u32 leakage; 1420 }; 1421 struct { 1422 u16 vddc1; 1423 u16 vddc2; 1424 u16 vddc3; 1425 }; 1426 }; 1427 1428 struct radeon_cac_leakage_table { 1429 u32 count; 1430 union radeon_cac_leakage_entry *entries; 1431 }; 1432 1433 struct radeon_phase_shedding_limits_entry { 1434 u16 voltage; 1435 u32 sclk; 1436 u32 mclk; 1437 }; 1438 1439 struct radeon_phase_shedding_limits_table { 1440 u32 count; 1441 struct radeon_phase_shedding_limits_entry *entries; 1442 }; 1443 1444 struct radeon_uvd_clock_voltage_dependency_entry { 1445 u32 vclk; 1446 u32 dclk; 1447 u16 v; 1448 }; 1449 1450 struct radeon_uvd_clock_voltage_dependency_table { 1451 u8 count; 1452 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1453 }; 1454 1455 struct radeon_vce_clock_voltage_dependency_entry { 1456 u32 ecclk; 1457 u32 evclk; 1458 u16 v; 1459 }; 1460 1461 struct radeon_vce_clock_voltage_dependency_table { 1462 u8 count; 1463 struct radeon_vce_clock_voltage_dependency_entry *entries; 1464 }; 1465 1466 struct radeon_ppm_table { 1467 u8 ppm_design; 1468 u16 cpu_core_number; 1469 u32 platform_tdp; 1470 u32 small_ac_platform_tdp; 1471 u32 platform_tdc; 1472 u32 small_ac_platform_tdc; 1473 u32 apu_tdp; 1474 u32 dgpu_tdp; 1475 u32 dgpu_ulv_power; 1476 u32 tj_max; 1477 }; 1478 1479 struct radeon_cac_tdp_table { 1480 u16 tdp; 1481 u16 configurable_tdp; 1482 u16 tdc; 1483 u16 battery_power_limit; 1484 u16 small_power_limit; 1485 u16 low_cac_leakage; 1486 u16 high_cac_leakage; 1487 u16 maximum_power_delivery_limit; 1488 }; 1489 1490 struct radeon_dpm_dynamic_state { 1491 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1492 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1493 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1494 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1495 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1496 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1497 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1498 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1499 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1500 struct radeon_clock_array valid_sclk_values; 1501 struct radeon_clock_array valid_mclk_values; 1502 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1503 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1504 u32 mclk_sclk_ratio; 1505 u32 sclk_mclk_delta; 1506 u16 vddc_vddci_delta; 1507 u16 min_vddc_for_pcie_gen2; 1508 struct radeon_cac_leakage_table cac_leakage_table; 1509 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1510 struct radeon_ppm_table *ppm_table; 1511 struct radeon_cac_tdp_table *cac_tdp_table; 1512 }; 1513 1514 struct radeon_dpm_fan { 1515 u16 t_min; 1516 u16 t_med; 1517 u16 t_high; 1518 u16 pwm_min; 1519 u16 pwm_med; 1520 u16 pwm_high; 1521 u8 t_hyst; 1522 u32 cycle_delay; 1523 u16 t_max; 1524 u8 control_mode; 1525 u16 default_max_fan_pwm; 1526 u16 default_fan_output_sensitivity; 1527 u16 fan_output_sensitivity; 1528 bool ucode_fan_control; 1529 }; 1530 1531 enum radeon_pcie_gen { 1532 RADEON_PCIE_GEN1 = 0, 1533 RADEON_PCIE_GEN2 = 1, 1534 RADEON_PCIE_GEN3 = 2, 1535 RADEON_PCIE_GEN_INVALID = 0xffff 1536 }; 1537 1538 enum radeon_dpm_forced_level { 1539 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1540 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1541 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1542 }; 1543 1544 struct radeon_vce_state { 1545 /* vce clocks */ 1546 u32 evclk; 1547 u32 ecclk; 1548 /* gpu clocks */ 1549 u32 sclk; 1550 u32 mclk; 1551 u8 clk_idx; 1552 u8 pstate; 1553 }; 1554 1555 struct radeon_dpm { 1556 struct radeon_ps *ps; 1557 /* number of valid power states */ 1558 int num_ps; 1559 /* current power state that is active */ 1560 struct radeon_ps *current_ps; 1561 /* requested power state */ 1562 struct radeon_ps *requested_ps; 1563 /* boot up power state */ 1564 struct radeon_ps *boot_ps; 1565 /* default uvd power state */ 1566 struct radeon_ps *uvd_ps; 1567 /* vce requirements */ 1568 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1569 enum radeon_vce_level vce_level; 1570 enum radeon_pm_state_type state; 1571 enum radeon_pm_state_type user_state; 1572 u32 platform_caps; 1573 u32 voltage_response_time; 1574 u32 backbias_response_time; 1575 void *priv; 1576 u32 new_active_crtcs; 1577 int new_active_crtc_count; 1578 u32 current_active_crtcs; 1579 int current_active_crtc_count; 1580 bool single_display; 1581 struct radeon_dpm_dynamic_state dyn_state; 1582 struct radeon_dpm_fan fan; 1583 u32 tdp_limit; 1584 u32 near_tdp_limit; 1585 u32 near_tdp_limit_adjusted; 1586 u32 sq_ramping_threshold; 1587 u32 cac_leakage; 1588 u16 tdp_od_limit; 1589 u32 tdp_adjustment; 1590 u16 load_line_slope; 1591 bool power_control; 1592 bool ac_power; 1593 /* special states active */ 1594 bool thermal_active; 1595 bool uvd_active; 1596 bool vce_active; 1597 /* thermal handling */ 1598 struct radeon_dpm_thermal thermal; 1599 /* forced levels */ 1600 enum radeon_dpm_forced_level forced_level; 1601 /* track UVD streams */ 1602 unsigned sd; 1603 unsigned hd; 1604 }; 1605 1606 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1607 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1608 1609 struct radeon_pm { 1610 struct mutex mutex; 1611 /* write locked while reprogramming mclk */ 1612 struct rw_semaphore mclk_lock; 1613 u32 active_crtcs; 1614 int active_crtc_count; 1615 int req_vblank; 1616 bool vblank_sync; 1617 fixed20_12 max_bandwidth; 1618 fixed20_12 igp_sideport_mclk; 1619 fixed20_12 igp_system_mclk; 1620 fixed20_12 igp_ht_link_clk; 1621 fixed20_12 igp_ht_link_width; 1622 fixed20_12 k8_bandwidth; 1623 fixed20_12 sideport_bandwidth; 1624 fixed20_12 ht_bandwidth; 1625 fixed20_12 core_bandwidth; 1626 fixed20_12 sclk; 1627 fixed20_12 mclk; 1628 fixed20_12 needed_bandwidth; 1629 struct radeon_power_state *power_state; 1630 /* number of valid power states */ 1631 int num_power_states; 1632 int current_power_state_index; 1633 int current_clock_mode_index; 1634 int requested_power_state_index; 1635 int requested_clock_mode_index; 1636 int default_power_state_index; 1637 u32 current_sclk; 1638 u32 current_mclk; 1639 u16 current_vddc; 1640 u16 current_vddci; 1641 u32 default_sclk; 1642 u32 default_mclk; 1643 u16 default_vddc; 1644 u16 default_vddci; 1645 struct radeon_i2c_chan *i2c_bus; 1646 /* selected pm method */ 1647 enum radeon_pm_method pm_method; 1648 /* dynpm power management */ 1649 struct delayed_work dynpm_idle_work; 1650 enum radeon_dynpm_state dynpm_state; 1651 enum radeon_dynpm_action dynpm_planned_action; 1652 unsigned long dynpm_action_timeout; 1653 bool dynpm_can_upclock; 1654 bool dynpm_can_downclock; 1655 /* profile-based power management */ 1656 enum radeon_pm_profile_type profile; 1657 int profile_index; 1658 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1659 /* internal thermal controller on rv6xx+ */ 1660 enum radeon_int_thermal_type int_thermal_type; 1661 struct device *int_hwmon_dev; 1662 /* fan control parameters */ 1663 bool no_fan; 1664 u8 fan_pulses_per_revolution; 1665 u8 fan_min_rpm; 1666 u8 fan_max_rpm; 1667 /* dpm */ 1668 bool dpm_enabled; 1669 bool sysfs_initialized; 1670 struct radeon_dpm dpm; 1671 }; 1672 1673 int radeon_pm_get_type_index(struct radeon_device *rdev, 1674 enum radeon_pm_state_type ps_type, 1675 int instance); 1676 /* 1677 * UVD 1678 */ 1679 #define RADEON_DEFAULT_UVD_HANDLES 10 1680 #define RADEON_MAX_UVD_HANDLES 30 1681 #define RADEON_UVD_STACK_SIZE (200*1024) 1682 #define RADEON_UVD_HEAP_SIZE (256*1024) 1683 #define RADEON_UVD_SESSION_SIZE (50*1024) 1684 1685 struct radeon_uvd { 1686 bool fw_header_present; 1687 struct radeon_bo *vcpu_bo; 1688 void *cpu_addr; 1689 uint64_t gpu_addr; 1690 unsigned max_handles; 1691 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1692 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1693 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1694 struct delayed_work idle_work; 1695 }; 1696 1697 int radeon_uvd_init(struct radeon_device *rdev); 1698 void radeon_uvd_fini(struct radeon_device *rdev); 1699 int radeon_uvd_suspend(struct radeon_device *rdev); 1700 int radeon_uvd_resume(struct radeon_device *rdev); 1701 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1702 uint32_t handle, struct radeon_fence **fence); 1703 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1704 uint32_t handle, struct radeon_fence **fence); 1705 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1706 uint32_t allowed_domains); 1707 void radeon_uvd_free_handles(struct radeon_device *rdev, 1708 struct drm_file *filp); 1709 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1710 void radeon_uvd_note_usage(struct radeon_device *rdev); 1711 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1712 unsigned vclk, unsigned dclk, 1713 unsigned vco_min, unsigned vco_max, 1714 unsigned fb_factor, unsigned fb_mask, 1715 unsigned pd_min, unsigned pd_max, 1716 unsigned pd_even, 1717 unsigned *optimal_fb_div, 1718 unsigned *optimal_vclk_div, 1719 unsigned *optimal_dclk_div); 1720 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1721 unsigned cg_upll_func_cntl); 1722 1723 /* 1724 * VCE 1725 */ 1726 #define RADEON_MAX_VCE_HANDLES 16 1727 1728 struct radeon_vce { 1729 struct radeon_bo *vcpu_bo; 1730 uint64_t gpu_addr; 1731 unsigned fw_version; 1732 unsigned fb_version; 1733 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1734 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1735 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1736 struct delayed_work idle_work; 1737 uint32_t keyselect; 1738 }; 1739 1740 int radeon_vce_init(struct radeon_device *rdev); 1741 void radeon_vce_fini(struct radeon_device *rdev); 1742 int radeon_vce_suspend(struct radeon_device *rdev); 1743 int radeon_vce_resume(struct radeon_device *rdev); 1744 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1745 uint32_t handle, struct radeon_fence **fence); 1746 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1747 uint32_t handle, struct radeon_fence **fence); 1748 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1749 void radeon_vce_note_usage(struct radeon_device *rdev); 1750 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1751 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1752 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1753 struct radeon_ring *ring, 1754 struct radeon_semaphore *semaphore, 1755 bool emit_wait); 1756 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1757 void radeon_vce_fence_emit(struct radeon_device *rdev, 1758 struct radeon_fence *fence); 1759 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1760 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1761 1762 struct r600_audio_pin { 1763 int channels; 1764 int rate; 1765 int bits_per_sample; 1766 u8 status_bits; 1767 u8 category_code; 1768 u32 offset; 1769 bool connected; 1770 u32 id; 1771 }; 1772 1773 struct r600_audio { 1774 bool enabled; 1775 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1776 int num_pins; 1777 struct radeon_audio_funcs *hdmi_funcs; 1778 struct radeon_audio_funcs *dp_funcs; 1779 struct radeon_audio_basic_funcs *funcs; 1780 }; 1781 1782 /* 1783 * Benchmarking 1784 */ 1785 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1786 1787 1788 /* 1789 * Testing 1790 */ 1791 void radeon_test_moves(struct radeon_device *rdev); 1792 void radeon_test_ring_sync(struct radeon_device *rdev, 1793 struct radeon_ring *cpA, 1794 struct radeon_ring *cpB); 1795 void radeon_test_syncing(struct radeon_device *rdev); 1796 1797 /* 1798 * MMU Notifier 1799 */ 1800 #if defined(CONFIG_MMU_NOTIFIER) 1801 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); 1802 void radeon_mn_unregister(struct radeon_bo *bo); 1803 #else 1804 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr) 1805 { 1806 return -ENODEV; 1807 } 1808 static inline void radeon_mn_unregister(struct radeon_bo *bo) {} 1809 #endif 1810 1811 /* 1812 * Debugfs 1813 */ 1814 struct radeon_debugfs { 1815 struct drm_info_list *files; 1816 unsigned num_files; 1817 }; 1818 1819 int radeon_debugfs_add_files(struct radeon_device *rdev, 1820 struct drm_info_list *files, 1821 unsigned nfiles); 1822 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1823 1824 /* 1825 * ASIC ring specific functions. 1826 */ 1827 struct radeon_asic_ring { 1828 /* ring read/write ptr handling */ 1829 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1830 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1831 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1832 1833 /* validating and patching of IBs */ 1834 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1835 int (*cs_parse)(struct radeon_cs_parser *p); 1836 1837 /* command emmit functions */ 1838 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1839 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1840 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1841 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1842 struct radeon_semaphore *semaphore, bool emit_wait); 1843 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring, 1844 unsigned vm_id, uint64_t pd_addr); 1845 1846 /* testing functions */ 1847 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1848 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1849 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1850 1851 /* deprecated */ 1852 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1853 }; 1854 1855 /* 1856 * ASIC specific functions. 1857 */ 1858 struct radeon_asic { 1859 int (*init)(struct radeon_device *rdev); 1860 void (*fini)(struct radeon_device *rdev); 1861 int (*resume)(struct radeon_device *rdev); 1862 int (*suspend)(struct radeon_device *rdev); 1863 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1864 int (*asic_reset)(struct radeon_device *rdev, bool hard); 1865 /* Flush the HDP cache via MMIO */ 1866 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1867 /* check if 3D engine is idle */ 1868 bool (*gui_idle)(struct radeon_device *rdev); 1869 /* wait for mc_idle */ 1870 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1871 /* get the reference clock */ 1872 u32 (*get_xclk)(struct radeon_device *rdev); 1873 /* get the gpu clock counter */ 1874 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1875 /* get register for info ioctl */ 1876 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val); 1877 /* gart */ 1878 struct { 1879 void (*tlb_flush)(struct radeon_device *rdev); 1880 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags); 1881 void (*set_page)(struct radeon_device *rdev, unsigned i, 1882 uint64_t entry); 1883 } gart; 1884 struct { 1885 int (*init)(struct radeon_device *rdev); 1886 void (*fini)(struct radeon_device *rdev); 1887 void (*copy_pages)(struct radeon_device *rdev, 1888 struct radeon_ib *ib, 1889 uint64_t pe, uint64_t src, 1890 unsigned count); 1891 void (*write_pages)(struct radeon_device *rdev, 1892 struct radeon_ib *ib, 1893 uint64_t pe, 1894 uint64_t addr, unsigned count, 1895 uint32_t incr, uint32_t flags); 1896 void (*set_pages)(struct radeon_device *rdev, 1897 struct radeon_ib *ib, 1898 uint64_t pe, 1899 uint64_t addr, unsigned count, 1900 uint32_t incr, uint32_t flags); 1901 void (*pad_ib)(struct radeon_ib *ib); 1902 } vm; 1903 /* ring specific callbacks */ 1904 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1905 /* irqs */ 1906 struct { 1907 int (*set)(struct radeon_device *rdev); 1908 int (*process)(struct radeon_device *rdev); 1909 } irq; 1910 /* displays */ 1911 struct { 1912 /* display watermarks */ 1913 void (*bandwidth_update)(struct radeon_device *rdev); 1914 /* get frame count */ 1915 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1916 /* wait for vblank */ 1917 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1918 /* set backlight level */ 1919 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1920 /* get backlight level */ 1921 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1922 /* audio callbacks */ 1923 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1924 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1925 } display; 1926 /* copy functions for bo handling */ 1927 struct { 1928 struct radeon_fence *(*blit)(struct radeon_device *rdev, 1929 uint64_t src_offset, 1930 uint64_t dst_offset, 1931 unsigned num_gpu_pages, 1932 struct reservation_object *resv); 1933 u32 blit_ring_index; 1934 struct radeon_fence *(*dma)(struct radeon_device *rdev, 1935 uint64_t src_offset, 1936 uint64_t dst_offset, 1937 unsigned num_gpu_pages, 1938 struct reservation_object *resv); 1939 u32 dma_ring_index; 1940 /* method used for bo copy */ 1941 struct radeon_fence *(*copy)(struct radeon_device *rdev, 1942 uint64_t src_offset, 1943 uint64_t dst_offset, 1944 unsigned num_gpu_pages, 1945 struct reservation_object *resv); 1946 /* ring used for bo copies */ 1947 u32 copy_ring_index; 1948 } copy; 1949 /* surfaces */ 1950 struct { 1951 int (*set_reg)(struct radeon_device *rdev, int reg, 1952 uint32_t tiling_flags, uint32_t pitch, 1953 uint32_t offset, uint32_t obj_size); 1954 void (*clear_reg)(struct radeon_device *rdev, int reg); 1955 } surface; 1956 /* hotplug detect */ 1957 struct { 1958 void (*init)(struct radeon_device *rdev); 1959 void (*fini)(struct radeon_device *rdev); 1960 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1961 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1962 } hpd; 1963 /* static power management */ 1964 struct { 1965 void (*misc)(struct radeon_device *rdev); 1966 void (*prepare)(struct radeon_device *rdev); 1967 void (*finish)(struct radeon_device *rdev); 1968 void (*init_profile)(struct radeon_device *rdev); 1969 void (*get_dynpm_state)(struct radeon_device *rdev); 1970 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1971 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1972 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1973 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1974 int (*get_pcie_lanes)(struct radeon_device *rdev); 1975 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1976 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1977 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1978 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1979 int (*get_temperature)(struct radeon_device *rdev); 1980 } pm; 1981 /* dynamic power management */ 1982 struct { 1983 int (*init)(struct radeon_device *rdev); 1984 void (*setup_asic)(struct radeon_device *rdev); 1985 int (*enable)(struct radeon_device *rdev); 1986 int (*late_enable)(struct radeon_device *rdev); 1987 void (*disable)(struct radeon_device *rdev); 1988 int (*pre_set_power_state)(struct radeon_device *rdev); 1989 int (*set_power_state)(struct radeon_device *rdev); 1990 void (*post_set_power_state)(struct radeon_device *rdev); 1991 void (*display_configuration_changed)(struct radeon_device *rdev); 1992 void (*fini)(struct radeon_device *rdev); 1993 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1994 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1995 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1996 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1997 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 1998 bool (*vblank_too_short)(struct radeon_device *rdev); 1999 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 2000 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 2001 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode); 2002 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev); 2003 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed); 2004 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed); 2005 u32 (*get_current_sclk)(struct radeon_device *rdev); 2006 u32 (*get_current_mclk)(struct radeon_device *rdev); 2007 } dpm; 2008 /* pageflipping */ 2009 struct { 2010 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async); 2011 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 2012 } pflip; 2013 }; 2014 2015 /* 2016 * Asic structures 2017 */ 2018 struct r100_asic { 2019 const unsigned *reg_safe_bm; 2020 unsigned reg_safe_bm_size; 2021 u32 hdp_cntl; 2022 }; 2023 2024 struct r300_asic { 2025 const unsigned *reg_safe_bm; 2026 unsigned reg_safe_bm_size; 2027 u32 resync_scratch; 2028 u32 hdp_cntl; 2029 }; 2030 2031 struct r600_asic { 2032 unsigned max_pipes; 2033 unsigned max_tile_pipes; 2034 unsigned max_simds; 2035 unsigned max_backends; 2036 unsigned max_gprs; 2037 unsigned max_threads; 2038 unsigned max_stack_entries; 2039 unsigned max_hw_contexts; 2040 unsigned max_gs_threads; 2041 unsigned sx_max_export_size; 2042 unsigned sx_max_export_pos_size; 2043 unsigned sx_max_export_smx_size; 2044 unsigned sq_num_cf_insts; 2045 unsigned tiling_nbanks; 2046 unsigned tiling_npipes; 2047 unsigned tiling_group_size; 2048 unsigned tile_config; 2049 unsigned backend_map; 2050 unsigned active_simds; 2051 }; 2052 2053 struct rv770_asic { 2054 unsigned max_pipes; 2055 unsigned max_tile_pipes; 2056 unsigned max_simds; 2057 unsigned max_backends; 2058 unsigned max_gprs; 2059 unsigned max_threads; 2060 unsigned max_stack_entries; 2061 unsigned max_hw_contexts; 2062 unsigned max_gs_threads; 2063 unsigned sx_max_export_size; 2064 unsigned sx_max_export_pos_size; 2065 unsigned sx_max_export_smx_size; 2066 unsigned sq_num_cf_insts; 2067 unsigned sx_num_of_sets; 2068 unsigned sc_prim_fifo_size; 2069 unsigned sc_hiz_tile_fifo_size; 2070 unsigned sc_earlyz_tile_fifo_fize; 2071 unsigned tiling_nbanks; 2072 unsigned tiling_npipes; 2073 unsigned tiling_group_size; 2074 unsigned tile_config; 2075 unsigned backend_map; 2076 unsigned active_simds; 2077 }; 2078 2079 struct evergreen_asic { 2080 unsigned num_ses; 2081 unsigned max_pipes; 2082 unsigned max_tile_pipes; 2083 unsigned max_simds; 2084 unsigned max_backends; 2085 unsigned max_gprs; 2086 unsigned max_threads; 2087 unsigned max_stack_entries; 2088 unsigned max_hw_contexts; 2089 unsigned max_gs_threads; 2090 unsigned sx_max_export_size; 2091 unsigned sx_max_export_pos_size; 2092 unsigned sx_max_export_smx_size; 2093 unsigned sq_num_cf_insts; 2094 unsigned sx_num_of_sets; 2095 unsigned sc_prim_fifo_size; 2096 unsigned sc_hiz_tile_fifo_size; 2097 unsigned sc_earlyz_tile_fifo_size; 2098 unsigned tiling_nbanks; 2099 unsigned tiling_npipes; 2100 unsigned tiling_group_size; 2101 unsigned tile_config; 2102 unsigned backend_map; 2103 unsigned active_simds; 2104 }; 2105 2106 struct cayman_asic { 2107 unsigned max_shader_engines; 2108 unsigned max_pipes_per_simd; 2109 unsigned max_tile_pipes; 2110 unsigned max_simds_per_se; 2111 unsigned max_backends_per_se; 2112 unsigned max_texture_channel_caches; 2113 unsigned max_gprs; 2114 unsigned max_threads; 2115 unsigned max_gs_threads; 2116 unsigned max_stack_entries; 2117 unsigned sx_num_of_sets; 2118 unsigned sx_max_export_size; 2119 unsigned sx_max_export_pos_size; 2120 unsigned sx_max_export_smx_size; 2121 unsigned max_hw_contexts; 2122 unsigned sq_num_cf_insts; 2123 unsigned sc_prim_fifo_size; 2124 unsigned sc_hiz_tile_fifo_size; 2125 unsigned sc_earlyz_tile_fifo_size; 2126 2127 unsigned num_shader_engines; 2128 unsigned num_shader_pipes_per_simd; 2129 unsigned num_tile_pipes; 2130 unsigned num_simds_per_se; 2131 unsigned num_backends_per_se; 2132 unsigned backend_disable_mask_per_asic; 2133 unsigned backend_map; 2134 unsigned num_texture_channel_caches; 2135 unsigned mem_max_burst_length_bytes; 2136 unsigned mem_row_size_in_kb; 2137 unsigned shader_engine_tile_size; 2138 unsigned num_gpus; 2139 unsigned multi_gpu_tile_size; 2140 2141 unsigned tile_config; 2142 unsigned active_simds; 2143 }; 2144 2145 struct si_asic { 2146 unsigned max_shader_engines; 2147 unsigned max_tile_pipes; 2148 unsigned max_cu_per_sh; 2149 unsigned max_sh_per_se; 2150 unsigned max_backends_per_se; 2151 unsigned max_texture_channel_caches; 2152 unsigned max_gprs; 2153 unsigned max_gs_threads; 2154 unsigned max_hw_contexts; 2155 unsigned sc_prim_fifo_size_frontend; 2156 unsigned sc_prim_fifo_size_backend; 2157 unsigned sc_hiz_tile_fifo_size; 2158 unsigned sc_earlyz_tile_fifo_size; 2159 2160 unsigned num_tile_pipes; 2161 unsigned backend_enable_mask; 2162 unsigned backend_disable_mask_per_asic; 2163 unsigned backend_map; 2164 unsigned num_texture_channel_caches; 2165 unsigned mem_max_burst_length_bytes; 2166 unsigned mem_row_size_in_kb; 2167 unsigned shader_engine_tile_size; 2168 unsigned num_gpus; 2169 unsigned multi_gpu_tile_size; 2170 2171 unsigned tile_config; 2172 uint32_t tile_mode_array[32]; 2173 uint32_t active_cus; 2174 }; 2175 2176 struct cik_asic { 2177 unsigned max_shader_engines; 2178 unsigned max_tile_pipes; 2179 unsigned max_cu_per_sh; 2180 unsigned max_sh_per_se; 2181 unsigned max_backends_per_se; 2182 unsigned max_texture_channel_caches; 2183 unsigned max_gprs; 2184 unsigned max_gs_threads; 2185 unsigned max_hw_contexts; 2186 unsigned sc_prim_fifo_size_frontend; 2187 unsigned sc_prim_fifo_size_backend; 2188 unsigned sc_hiz_tile_fifo_size; 2189 unsigned sc_earlyz_tile_fifo_size; 2190 2191 unsigned num_tile_pipes; 2192 unsigned backend_enable_mask; 2193 unsigned backend_disable_mask_per_asic; 2194 unsigned backend_map; 2195 unsigned num_texture_channel_caches; 2196 unsigned mem_max_burst_length_bytes; 2197 unsigned mem_row_size_in_kb; 2198 unsigned shader_engine_tile_size; 2199 unsigned num_gpus; 2200 unsigned multi_gpu_tile_size; 2201 2202 unsigned tile_config; 2203 uint32_t tile_mode_array[32]; 2204 uint32_t macrotile_mode_array[16]; 2205 uint32_t active_cus; 2206 }; 2207 2208 union radeon_asic_config { 2209 struct r300_asic r300; 2210 struct r100_asic r100; 2211 struct r600_asic r600; 2212 struct rv770_asic rv770; 2213 struct evergreen_asic evergreen; 2214 struct cayman_asic cayman; 2215 struct si_asic si; 2216 struct cik_asic cik; 2217 }; 2218 2219 /* 2220 * asic initizalization from radeon_asic.c 2221 */ 2222 void radeon_agp_disable(struct radeon_device *rdev); 2223 int radeon_asic_init(struct radeon_device *rdev); 2224 2225 2226 /* 2227 * IOCTL. 2228 */ 2229 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2230 struct drm_file *filp); 2231 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2232 struct drm_file *filp); 2233 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, 2234 struct drm_file *filp); 2235 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2236 struct drm_file *file_priv); 2237 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2238 struct drm_file *file_priv); 2239 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2240 struct drm_file *file_priv); 2241 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2242 struct drm_file *file_priv); 2243 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2244 struct drm_file *filp); 2245 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2246 struct drm_file *filp); 2247 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2248 struct drm_file *filp); 2249 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2250 struct drm_file *filp); 2251 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2252 struct drm_file *filp); 2253 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2254 struct drm_file *filp); 2255 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2256 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2257 struct drm_file *filp); 2258 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2259 struct drm_file *filp); 2260 2261 /* VRAM scratch page for HDP bug, default vram page */ 2262 struct r600_vram_scratch { 2263 struct radeon_bo *robj; 2264 volatile uint32_t *ptr; 2265 u64 gpu_addr; 2266 }; 2267 2268 /* 2269 * ACPI 2270 */ 2271 struct radeon_atif_notification_cfg { 2272 bool enabled; 2273 int command_code; 2274 }; 2275 2276 struct radeon_atif_notifications { 2277 bool display_switch; 2278 bool expansion_mode_change; 2279 bool thermal_state; 2280 bool forced_power_state; 2281 bool system_power_state; 2282 bool display_conf_change; 2283 bool px_gfx_switch; 2284 bool brightness_change; 2285 bool dgpu_display_event; 2286 }; 2287 2288 struct radeon_atif_functions { 2289 bool system_params; 2290 bool sbios_requests; 2291 bool select_active_disp; 2292 bool lid_state; 2293 bool get_tv_standard; 2294 bool set_tv_standard; 2295 bool get_panel_expansion_mode; 2296 bool set_panel_expansion_mode; 2297 bool temperature_change; 2298 bool graphics_device_types; 2299 }; 2300 2301 struct radeon_atif { 2302 struct radeon_atif_notifications notifications; 2303 struct radeon_atif_functions functions; 2304 struct radeon_atif_notification_cfg notification_cfg; 2305 struct radeon_encoder *encoder_for_bl; 2306 }; 2307 2308 struct radeon_atcs_functions { 2309 bool get_ext_state; 2310 bool pcie_perf_req; 2311 bool pcie_dev_rdy; 2312 bool pcie_bus_width; 2313 }; 2314 2315 struct radeon_atcs { 2316 struct radeon_atcs_functions functions; 2317 }; 2318 2319 /* 2320 * Core structure, functions and helpers. 2321 */ 2322 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2323 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2324 2325 struct radeon_device { 2326 struct device *dev; 2327 struct drm_device *ddev; 2328 struct pci_dev *pdev; 2329 struct rw_semaphore exclusive_lock; 2330 /* ASIC */ 2331 union radeon_asic_config config; 2332 enum radeon_family family; 2333 unsigned long flags; 2334 int usec_timeout; 2335 enum radeon_pll_errata pll_errata; 2336 int num_gb_pipes; 2337 int num_z_pipes; 2338 int disp_priority; 2339 /* BIOS */ 2340 uint8_t *bios; 2341 bool is_atom_bios; 2342 uint16_t bios_header_start; 2343 struct radeon_bo *stollen_vga_memory; 2344 /* Register mmio */ 2345 resource_size_t rmmio_base; 2346 resource_size_t rmmio_size; 2347 /* protects concurrent MM_INDEX/DATA based register access */ 2348 spinlock_t mmio_idx_lock; 2349 /* protects concurrent SMC based register access */ 2350 spinlock_t smc_idx_lock; 2351 /* protects concurrent PLL register access */ 2352 spinlock_t pll_idx_lock; 2353 /* protects concurrent MC register access */ 2354 spinlock_t mc_idx_lock; 2355 /* protects concurrent PCIE register access */ 2356 spinlock_t pcie_idx_lock; 2357 /* protects concurrent PCIE_PORT register access */ 2358 spinlock_t pciep_idx_lock; 2359 /* protects concurrent PIF register access */ 2360 spinlock_t pif_idx_lock; 2361 /* protects concurrent CG register access */ 2362 spinlock_t cg_idx_lock; 2363 /* protects concurrent UVD register access */ 2364 spinlock_t uvd_idx_lock; 2365 /* protects concurrent RCU register access */ 2366 spinlock_t rcu_idx_lock; 2367 /* protects concurrent DIDT register access */ 2368 spinlock_t didt_idx_lock; 2369 /* protects concurrent ENDPOINT (audio) register access */ 2370 spinlock_t end_idx_lock; 2371 void __iomem *rmmio; 2372 radeon_rreg_t mc_rreg; 2373 radeon_wreg_t mc_wreg; 2374 radeon_rreg_t pll_rreg; 2375 radeon_wreg_t pll_wreg; 2376 uint32_t pcie_reg_mask; 2377 radeon_rreg_t pciep_rreg; 2378 radeon_wreg_t pciep_wreg; 2379 /* io port */ 2380 void __iomem *rio_mem; 2381 resource_size_t rio_mem_size; 2382 struct radeon_clock clock; 2383 struct radeon_mc mc; 2384 struct radeon_gart gart; 2385 struct radeon_mode_info mode_info; 2386 struct radeon_scratch scratch; 2387 struct radeon_doorbell doorbell; 2388 struct radeon_mman mman; 2389 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2390 wait_queue_head_t fence_queue; 2391 u64 fence_context; 2392 struct mutex ring_lock; 2393 struct radeon_ring ring[RADEON_NUM_RINGS]; 2394 bool ib_pool_ready; 2395 struct radeon_sa_manager ring_tmp_bo; 2396 struct radeon_irq irq; 2397 struct radeon_asic *asic; 2398 struct radeon_gem gem; 2399 struct radeon_pm pm; 2400 struct radeon_uvd uvd; 2401 struct radeon_vce vce; 2402 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2403 struct radeon_wb wb; 2404 struct radeon_dummy_page dummy_page; 2405 bool shutdown; 2406 bool need_dma32; 2407 bool accel_working; 2408 bool fastfb_working; /* IGP feature*/ 2409 bool needs_reset, in_reset; 2410 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2411 const struct firmware *me_fw; /* all family ME firmware */ 2412 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2413 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2414 const struct firmware *mc_fw; /* NI MC firmware */ 2415 const struct firmware *ce_fw; /* SI CE firmware */ 2416 const struct firmware *mec_fw; /* CIK MEC firmware */ 2417 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2418 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2419 const struct firmware *smc_fw; /* SMC firmware */ 2420 const struct firmware *uvd_fw; /* UVD firmware */ 2421 const struct firmware *vce_fw; /* VCE firmware */ 2422 bool new_fw; 2423 struct r600_vram_scratch vram_scratch; 2424 int msi_enabled; /* msi enabled */ 2425 struct r600_ih ih; /* r6/700 interrupt ring */ 2426 struct radeon_rlc rlc; 2427 struct radeon_mec mec; 2428 struct delayed_work hotplug_work; 2429 struct work_struct dp_work; 2430 struct work_struct audio_work; 2431 int num_crtc; /* number of crtcs */ 2432 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2433 bool has_uvd; 2434 bool has_vce; 2435 struct r600_audio audio; /* audio stuff */ 2436 struct notifier_block acpi_nb; 2437 /* only one userspace can use Hyperz features or CMASK at a time */ 2438 struct drm_file *hyperz_filp; 2439 struct drm_file *cmask_filp; 2440 /* i2c buses */ 2441 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2442 /* debugfs */ 2443 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2444 unsigned debugfs_count; 2445 /* virtual memory */ 2446 struct radeon_vm_manager vm_manager; 2447 struct mutex gpu_clock_mutex; 2448 /* memory stats */ 2449 atomic64_t vram_usage; 2450 atomic64_t gtt_usage; 2451 atomic64_t num_bytes_moved; 2452 atomic_t gpu_reset_counter; 2453 /* ACPI interface */ 2454 struct radeon_atif atif; 2455 struct radeon_atcs atcs; 2456 /* srbm instance registers */ 2457 struct mutex srbm_mutex; 2458 /* GRBM index mutex. Protects concurrents access to GRBM index */ 2459 struct mutex grbm_idx_mutex; 2460 /* clock, powergating flags */ 2461 u32 cg_flags; 2462 u32 pg_flags; 2463 2464 struct dev_pm_domain vga_pm_domain; 2465 bool have_disp_power_ref; 2466 u32 px_quirk_flags; 2467 2468 /* tracking pinned memory */ 2469 u64 vram_pin_size; 2470 u64 gart_pin_size; 2471 2472 /* amdkfd interface */ 2473 struct kfd_dev *kfd; 2474 2475 struct mutex mn_lock; 2476 DECLARE_HASHTABLE(mn_hash, 7); 2477 }; 2478 2479 bool radeon_is_px(struct drm_device *dev); 2480 int radeon_device_init(struct radeon_device *rdev, 2481 struct drm_device *ddev, 2482 struct pci_dev *pdev, 2483 uint32_t flags); 2484 void radeon_device_fini(struct radeon_device *rdev); 2485 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2486 2487 #define RADEON_MIN_MMIO_SIZE 0x10000 2488 2489 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg); 2490 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2491 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2492 bool always_indirect) 2493 { 2494 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ 2495 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2496 return readl(((void __iomem *)rdev->rmmio) + reg); 2497 else 2498 return r100_mm_rreg_slow(rdev, reg); 2499 } 2500 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2501 bool always_indirect) 2502 { 2503 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2504 writel(v, ((void __iomem *)rdev->rmmio) + reg); 2505 else 2506 r100_mm_wreg_slow(rdev, reg, v); 2507 } 2508 2509 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2510 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2511 2512 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2513 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2514 2515 /* 2516 * Cast helper 2517 */ 2518 extern const struct dma_fence_ops radeon_fence_ops; 2519 2520 static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f) 2521 { 2522 struct radeon_fence *__f = container_of(f, struct radeon_fence, base); 2523 2524 if (__f->base.ops == &radeon_fence_ops) 2525 return __f; 2526 2527 return NULL; 2528 } 2529 2530 /* 2531 * Registers read & write functions. 2532 */ 2533 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 2534 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 2535 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 2536 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 2537 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2538 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2539 #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \ 2540 r100_mm_rreg(rdev, (reg), false)) 2541 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2542 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2543 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2544 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2545 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2546 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2547 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2548 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2549 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2550 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2551 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2552 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2553 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2554 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2555 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2556 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2557 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2558 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2559 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2560 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2561 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2562 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2563 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2564 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2565 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2566 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2567 #define WREG32_P(reg, val, mask) \ 2568 do { \ 2569 uint32_t tmp_ = RREG32(reg); \ 2570 tmp_ &= (mask); \ 2571 tmp_ |= ((val) & ~(mask)); \ 2572 WREG32(reg, tmp_); \ 2573 } while (0) 2574 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2575 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2576 #define WREG32_PLL_P(reg, val, mask) \ 2577 do { \ 2578 uint32_t tmp_ = RREG32_PLL(reg); \ 2579 tmp_ &= (mask); \ 2580 tmp_ |= ((val) & ~(mask)); \ 2581 WREG32_PLL(reg, tmp_); \ 2582 } while (0) 2583 #define WREG32_SMC_P(reg, val, mask) \ 2584 do { \ 2585 uint32_t tmp_ = RREG32_SMC(reg); \ 2586 tmp_ &= (mask); \ 2587 tmp_ |= ((val) & ~(mask)); \ 2588 WREG32_SMC(reg, tmp_); \ 2589 } while (0) 2590 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2591 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2592 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2593 2594 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2595 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2596 2597 /* 2598 * Indirect registers accessors. 2599 * They used to be inlined, but this increases code size by ~65 kbytes. 2600 * Since each performs a pair of MMIO ops 2601 * within a spin_lock_irqsave/spin_unlock_irqrestore region, 2602 * the cost of call+ret is almost negligible. MMIO and locking 2603 * costs several dozens of cycles each at best, call+ret is ~5 cycles. 2604 */ 2605 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); 2606 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2607 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg); 2608 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2609 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg); 2610 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2611 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg); 2612 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2613 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg); 2614 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2615 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg); 2616 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2617 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg); 2618 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2619 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg); 2620 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2621 2622 void r100_pll_errata_after_index(struct radeon_device *rdev); 2623 2624 2625 /* 2626 * ASICs helpers. 2627 */ 2628 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2629 (rdev->pdev->device == 0x5969)) 2630 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2631 (rdev->family == CHIP_RV200) || \ 2632 (rdev->family == CHIP_RS100) || \ 2633 (rdev->family == CHIP_RS200) || \ 2634 (rdev->family == CHIP_RV250) || \ 2635 (rdev->family == CHIP_RV280) || \ 2636 (rdev->family == CHIP_RS300)) 2637 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2638 (rdev->family == CHIP_RV350) || \ 2639 (rdev->family == CHIP_R350) || \ 2640 (rdev->family == CHIP_RV380) || \ 2641 (rdev->family == CHIP_R420) || \ 2642 (rdev->family == CHIP_R423) || \ 2643 (rdev->family == CHIP_RV410) || \ 2644 (rdev->family == CHIP_RS400) || \ 2645 (rdev->family == CHIP_RS480)) 2646 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2647 (rdev->ddev->pdev->device == 0x9443) || \ 2648 (rdev->ddev->pdev->device == 0x944B) || \ 2649 (rdev->ddev->pdev->device == 0x9506) || \ 2650 (rdev->ddev->pdev->device == 0x9509) || \ 2651 (rdev->ddev->pdev->device == 0x950F) || \ 2652 (rdev->ddev->pdev->device == 0x689C) || \ 2653 (rdev->ddev->pdev->device == 0x689D)) 2654 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2655 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2656 (rdev->family == CHIP_RS690) || \ 2657 (rdev->family == CHIP_RS740) || \ 2658 (rdev->family >= CHIP_R600)) 2659 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2660 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2661 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2662 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2663 (rdev->flags & RADEON_IS_IGP)) 2664 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2665 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2666 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2667 (rdev->flags & RADEON_IS_IGP)) 2668 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2669 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2670 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2671 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2672 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2673 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2674 (rdev->family == CHIP_MULLINS)) 2675 2676 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2677 (rdev->ddev->pdev->device == 0x6850) || \ 2678 (rdev->ddev->pdev->device == 0x6858) || \ 2679 (rdev->ddev->pdev->device == 0x6859) || \ 2680 (rdev->ddev->pdev->device == 0x6840) || \ 2681 (rdev->ddev->pdev->device == 0x6841) || \ 2682 (rdev->ddev->pdev->device == 0x6842) || \ 2683 (rdev->ddev->pdev->device == 0x6843)) 2684 2685 /* 2686 * BIOS helpers. 2687 */ 2688 #define RBIOS8(i) (rdev->bios[i]) 2689 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2690 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2691 2692 int radeon_combios_init(struct radeon_device *rdev); 2693 void radeon_combios_fini(struct radeon_device *rdev); 2694 int radeon_atombios_init(struct radeon_device *rdev); 2695 void radeon_atombios_fini(struct radeon_device *rdev); 2696 2697 2698 /* 2699 * RING helpers. 2700 */ 2701 2702 /** 2703 * radeon_ring_write - write a value to the ring 2704 * 2705 * @ring: radeon_ring structure holding ring information 2706 * @v: dword (dw) value to write 2707 * 2708 * Write a value to the requested ring buffer (all asics). 2709 */ 2710 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2711 { 2712 if (ring->count_dw <= 0) 2713 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2714 2715 ring->ring[ring->wptr++] = v; 2716 ring->wptr &= ring->ptr_mask; 2717 ring->count_dw--; 2718 ring->ring_free_dw--; 2719 } 2720 2721 /* 2722 * ASICs macro. 2723 */ 2724 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2725 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2726 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2727 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2728 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2729 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2730 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false) 2731 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2732 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f)) 2733 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e)) 2734 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2735 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2736 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2737 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2738 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2739 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2740 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2741 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2742 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2743 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2744 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2745 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2746 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr)) 2747 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2748 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2749 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2750 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2751 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2752 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2753 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2754 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2755 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2756 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2757 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2758 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2759 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) 2760 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) 2761 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) 2762 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2763 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2764 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2765 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2766 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2767 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2768 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2769 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2770 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2771 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2772 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2773 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2774 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2775 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2776 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2777 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2778 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2779 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2780 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2781 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2782 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2783 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2784 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2785 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2786 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2787 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2788 #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async)) 2789 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2790 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2791 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2792 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2793 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2794 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v)) 2795 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2796 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2797 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2798 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2799 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2800 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2801 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2802 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2803 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2804 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2805 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2806 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2807 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2808 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2809 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2810 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2811 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2812 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2813 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev)) 2814 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev)) 2815 2816 /* Common functions */ 2817 /* AGP */ 2818 extern int radeon_gpu_reset(struct radeon_device *rdev); 2819 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2820 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2821 extern void radeon_agp_disable(struct radeon_device *rdev); 2822 extern int radeon_modeset_init(struct radeon_device *rdev); 2823 extern void radeon_modeset_fini(struct radeon_device *rdev); 2824 extern bool radeon_card_posted(struct radeon_device *rdev); 2825 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2826 extern void radeon_update_display_priority(struct radeon_device *rdev); 2827 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2828 extern void radeon_scratch_init(struct radeon_device *rdev); 2829 extern void radeon_wb_fini(struct radeon_device *rdev); 2830 extern int radeon_wb_init(struct radeon_device *rdev); 2831 extern void radeon_wb_disable(struct radeon_device *rdev); 2832 extern void radeon_surface_init(struct radeon_device *rdev); 2833 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2834 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 2835 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 2836 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2837 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2838 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2839 uint32_t flags); 2840 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm); 2841 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm); 2842 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2843 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2844 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2845 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, 2846 bool fbcon, bool freeze); 2847 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2848 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2849 const u32 *registers, 2850 const u32 array_size); 2851 2852 /* 2853 * vm 2854 */ 2855 int radeon_vm_manager_init(struct radeon_device *rdev); 2856 void radeon_vm_manager_fini(struct radeon_device *rdev); 2857 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2858 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2859 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, 2860 struct radeon_vm *vm, 2861 struct list_head *head); 2862 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2863 struct radeon_vm *vm, int ring); 2864 void radeon_vm_flush(struct radeon_device *rdev, 2865 struct radeon_vm *vm, 2866 int ring, struct radeon_fence *fence); 2867 void radeon_vm_fence(struct radeon_device *rdev, 2868 struct radeon_vm *vm, 2869 struct radeon_fence *fence); 2870 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2871 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2872 struct radeon_vm *vm); 2873 int radeon_vm_clear_freed(struct radeon_device *rdev, 2874 struct radeon_vm *vm); 2875 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2876 struct radeon_vm *vm); 2877 int radeon_vm_bo_update(struct radeon_device *rdev, 2878 struct radeon_bo_va *bo_va, 2879 struct ttm_mem_reg *mem); 2880 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2881 struct radeon_bo *bo); 2882 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2883 struct radeon_bo *bo); 2884 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2885 struct radeon_vm *vm, 2886 struct radeon_bo *bo); 2887 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2888 struct radeon_bo_va *bo_va, 2889 uint64_t offset, 2890 uint32_t flags); 2891 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2892 struct radeon_bo_va *bo_va); 2893 2894 /* audio */ 2895 void r600_audio_update_hdmi(struct work_struct *work); 2896 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2897 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2898 void r600_audio_enable(struct radeon_device *rdev, 2899 struct r600_audio_pin *pin, 2900 u8 enable_mask); 2901 void dce6_audio_enable(struct radeon_device *rdev, 2902 struct r600_audio_pin *pin, 2903 u8 enable_mask); 2904 2905 /* 2906 * R600 vram scratch functions 2907 */ 2908 int r600_vram_scratch_init(struct radeon_device *rdev); 2909 void r600_vram_scratch_fini(struct radeon_device *rdev); 2910 2911 /* 2912 * r600 cs checking helper 2913 */ 2914 unsigned r600_mip_minify(unsigned size, unsigned level); 2915 bool r600_fmt_is_valid_color(u32 format); 2916 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2917 int r600_fmt_get_blocksize(u32 format); 2918 int r600_fmt_get_nblocksx(u32 format, u32 w); 2919 int r600_fmt_get_nblocksy(u32 format, u32 h); 2920 2921 /* 2922 * r600 functions used by radeon_encoder.c 2923 */ 2924 struct radeon_hdmi_acr { 2925 u32 clock; 2926 2927 int n_32khz; 2928 int cts_32khz; 2929 2930 int n_44_1khz; 2931 int cts_44_1khz; 2932 2933 int n_48khz; 2934 int cts_48khz; 2935 2936 }; 2937 2938 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 2939 2940 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2941 u32 tiling_pipe_num, 2942 u32 max_rb_num, 2943 u32 total_max_rb_num, 2944 u32 enabled_rb_mask); 2945 2946 /* 2947 * evergreen functions used by radeon_encoder.c 2948 */ 2949 2950 extern int ni_init_microcode(struct radeon_device *rdev); 2951 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2952 2953 /* radeon_acpi.c */ 2954 #if defined(CONFIG_ACPI) 2955 extern int radeon_acpi_init(struct radeon_device *rdev); 2956 extern void radeon_acpi_fini(struct radeon_device *rdev); 2957 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 2958 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 2959 u8 perf_req, bool advertise); 2960 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 2961 #else 2962 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 2963 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 2964 #endif 2965 2966 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 2967 struct radeon_cs_packet *pkt, 2968 unsigned idx); 2969 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 2970 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 2971 struct radeon_cs_packet *pkt); 2972 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 2973 struct radeon_bo_list **cs_reloc, 2974 int nomm); 2975 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 2976 uint32_t *vline_start_end, 2977 uint32_t *vline_status); 2978 2979 #include "radeon_object.h" 2980 2981 #endif 2982