1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 /* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45 /* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63 #include <linux/atomic.h> 64 #include <linux/wait.h> 65 #include <linux/list.h> 66 #include <linux/kref.h> 67 #include <linux/interval_tree.h> 68 #include <linux/hashtable.h> 69 #include <linux/dma-fence.h> 70 71 #ifdef CONFIG_MMU_NOTIFIER 72 #include <linux/mmu_notifier.h> 73 #endif 74 75 #include <drm/ttm/ttm_bo_api.h> 76 #include <drm/ttm/ttm_bo_driver.h> 77 #include <drm/ttm/ttm_placement.h> 78 #include <drm/ttm/ttm_execbuf_util.h> 79 80 #include <drm/drm_gem.h> 81 82 #include "radeon_family.h" 83 #include "radeon_mode.h" 84 #include "radeon_reg.h" 85 86 /* 87 * Modules parameters. 88 */ 89 extern int radeon_no_wb; 90 extern int radeon_modeset; 91 extern int radeon_dynclks; 92 extern int radeon_r4xx_atom; 93 extern int radeon_agpmode; 94 extern int radeon_vram_limit; 95 extern int radeon_gart_size; 96 extern int radeon_benchmarking; 97 extern int radeon_testing; 98 extern int radeon_connector_table; 99 extern int radeon_tv; 100 extern int radeon_audio; 101 extern int radeon_disp_priority; 102 extern int radeon_hw_i2c; 103 extern int radeon_pcie_gen2; 104 extern int radeon_msi; 105 extern int radeon_lockup_timeout; 106 extern int radeon_fastfb; 107 extern int radeon_dpm; 108 extern int radeon_aspm; 109 extern int radeon_runtime_pm; 110 extern int radeon_hard_reset; 111 extern int radeon_vm_size; 112 extern int radeon_vm_block_size; 113 extern int radeon_deep_color; 114 extern int radeon_use_pflipirq; 115 extern int radeon_bapm; 116 extern int radeon_backlight; 117 extern int radeon_auxch; 118 extern int radeon_mst; 119 extern int radeon_uvd; 120 extern int radeon_vce; 121 extern int radeon_si_support; 122 extern int radeon_cik_support; 123 124 /* 125 * Copy from radeon_drv.h so we don't have to include both and have conflicting 126 * symbol; 127 */ 128 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 129 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 130 #define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */ 131 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 132 #define RADEON_IB_POOL_SIZE 16 133 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 134 #define RADEONFB_CONN_LIMIT 4 135 #define RADEON_BIOS_NUM_SCRATCH 8 136 137 /* internal ring indices */ 138 /* r1xx+ has gfx CP ring */ 139 #define RADEON_RING_TYPE_GFX_INDEX 0 140 141 /* cayman has 2 compute CP rings */ 142 #define CAYMAN_RING_TYPE_CP1_INDEX 1 143 #define CAYMAN_RING_TYPE_CP2_INDEX 2 144 145 /* R600+ has an async dma ring */ 146 #define R600_RING_TYPE_DMA_INDEX 3 147 /* cayman add a second async dma ring */ 148 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 149 150 /* R600+ */ 151 #define R600_RING_TYPE_UVD_INDEX 5 152 153 /* TN+ */ 154 #define TN_RING_TYPE_VCE1_INDEX 6 155 #define TN_RING_TYPE_VCE2_INDEX 7 156 157 /* max number of rings */ 158 #define RADEON_NUM_RINGS 8 159 160 /* number of hw syncs before falling back on blocking */ 161 #define RADEON_NUM_SYNCS 4 162 163 /* hardcode those limit for now */ 164 #define RADEON_VA_IB_OFFSET (1 << 20) 165 #define RADEON_VA_RESERVED_SIZE (8 << 20) 166 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 167 168 /* hard reset data */ 169 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 170 171 /* reset flags */ 172 #define RADEON_RESET_GFX (1 << 0) 173 #define RADEON_RESET_COMPUTE (1 << 1) 174 #define RADEON_RESET_DMA (1 << 2) 175 #define RADEON_RESET_CP (1 << 3) 176 #define RADEON_RESET_GRBM (1 << 4) 177 #define RADEON_RESET_DMA1 (1 << 5) 178 #define RADEON_RESET_RLC (1 << 6) 179 #define RADEON_RESET_SEM (1 << 7) 180 #define RADEON_RESET_IH (1 << 8) 181 #define RADEON_RESET_VMC (1 << 9) 182 #define RADEON_RESET_MC (1 << 10) 183 #define RADEON_RESET_DISPLAY (1 << 11) 184 185 /* CG block flags */ 186 #define RADEON_CG_BLOCK_GFX (1 << 0) 187 #define RADEON_CG_BLOCK_MC (1 << 1) 188 #define RADEON_CG_BLOCK_SDMA (1 << 2) 189 #define RADEON_CG_BLOCK_UVD (1 << 3) 190 #define RADEON_CG_BLOCK_VCE (1 << 4) 191 #define RADEON_CG_BLOCK_HDP (1 << 5) 192 #define RADEON_CG_BLOCK_BIF (1 << 6) 193 194 /* CG flags */ 195 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 196 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 197 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 198 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 199 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 200 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 201 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 202 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 203 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 204 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 205 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 206 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 207 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 208 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 209 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 210 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 211 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 212 213 /* PG flags */ 214 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 215 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 216 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 217 #define RADEON_PG_SUPPORT_UVD (1 << 3) 218 #define RADEON_PG_SUPPORT_VCE (1 << 4) 219 #define RADEON_PG_SUPPORT_CP (1 << 5) 220 #define RADEON_PG_SUPPORT_GDS (1 << 6) 221 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 222 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 223 #define RADEON_PG_SUPPORT_ACP (1 << 9) 224 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 225 226 /* max cursor sizes (in pixels) */ 227 #define CURSOR_WIDTH 64 228 #define CURSOR_HEIGHT 64 229 230 #define CIK_CURSOR_WIDTH 128 231 #define CIK_CURSOR_HEIGHT 128 232 233 /* 234 * Errata workarounds. 235 */ 236 enum radeon_pll_errata { 237 CHIP_ERRATA_R300_CG = 0x00000001, 238 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 239 CHIP_ERRATA_PLL_DELAY = 0x00000004 240 }; 241 242 243 struct radeon_device; 244 245 246 /* 247 * BIOS. 248 */ 249 bool radeon_get_bios(struct radeon_device *rdev); 250 251 /* 252 * Dummy page 253 */ 254 struct radeon_dummy_page { 255 uint64_t entry; 256 struct page *page; 257 dma_addr_t addr; 258 }; 259 int radeon_dummy_page_init(struct radeon_device *rdev); 260 void radeon_dummy_page_fini(struct radeon_device *rdev); 261 262 263 /* 264 * Clocks 265 */ 266 struct radeon_clock { 267 struct radeon_pll p1pll; 268 struct radeon_pll p2pll; 269 struct radeon_pll dcpll; 270 struct radeon_pll spll; 271 struct radeon_pll mpll; 272 /* 10 Khz units */ 273 uint32_t default_mclk; 274 uint32_t default_sclk; 275 uint32_t default_dispclk; 276 uint32_t current_dispclk; 277 uint32_t dp_extclk; 278 uint32_t max_pixel_clock; 279 uint32_t vco_freq; 280 }; 281 282 /* 283 * Power management 284 */ 285 int radeon_pm_init(struct radeon_device *rdev); 286 int radeon_pm_late_init(struct radeon_device *rdev); 287 void radeon_pm_fini(struct radeon_device *rdev); 288 void radeon_pm_compute_clocks(struct radeon_device *rdev); 289 void radeon_pm_suspend(struct radeon_device *rdev); 290 void radeon_pm_resume(struct radeon_device *rdev); 291 void radeon_combios_get_power_modes(struct radeon_device *rdev); 292 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 293 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 294 u8 clock_type, 295 u32 clock, 296 bool strobe_mode, 297 struct atom_clock_dividers *dividers); 298 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 299 u32 clock, 300 bool strobe_mode, 301 struct atom_mpll_param *mpll_param); 302 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 303 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 304 u16 voltage_level, u8 voltage_type, 305 u32 *gpio_value, u32 *gpio_mask); 306 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 307 u32 eng_clock, u32 mem_clock); 308 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 309 u8 voltage_type, u16 *voltage_step); 310 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 311 u16 voltage_id, u16 *voltage); 312 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 313 u16 *voltage, 314 u16 leakage_idx); 315 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 316 u16 *leakage_id); 317 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 318 u16 *vddc, u16 *vddci, 319 u16 virtual_voltage_id, 320 u16 vbios_voltage_id); 321 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 322 u16 virtual_voltage_id, 323 u16 *voltage); 324 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 325 u8 voltage_type, 326 u16 nominal_voltage, 327 u16 *true_voltage); 328 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 329 u8 voltage_type, u16 *min_voltage); 330 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 331 u8 voltage_type, u16 *max_voltage); 332 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 333 u8 voltage_type, u8 voltage_mode, 334 struct atom_voltage_table *voltage_table); 335 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 336 u8 voltage_type, u8 voltage_mode); 337 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 338 u8 voltage_type, 339 u8 *svd_gpio_id, u8 *svc_gpio_id); 340 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 341 u32 mem_clock); 342 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 343 u32 mem_clock); 344 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 345 u8 module_index, 346 struct atom_mc_reg_table *reg_table); 347 int radeon_atom_get_memory_info(struct radeon_device *rdev, 348 u8 module_index, struct atom_memory_info *mem_info); 349 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 350 bool gddr5, u8 module_index, 351 struct atom_memory_clock_range_table *mclk_range_table); 352 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 353 u16 voltage_id, u16 *voltage); 354 void rs690_pm_info(struct radeon_device *rdev); 355 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 356 unsigned *bankh, unsigned *mtaspect, 357 unsigned *tile_split); 358 359 /* 360 * Fences. 361 */ 362 struct radeon_fence_driver { 363 struct radeon_device *rdev; 364 uint32_t scratch_reg; 365 uint64_t gpu_addr; 366 volatile uint32_t *cpu_addr; 367 /* sync_seq is protected by ring emission lock */ 368 uint64_t sync_seq[RADEON_NUM_RINGS]; 369 atomic64_t last_seq; 370 bool initialized, delayed_irq; 371 struct delayed_work lockup_work; 372 }; 373 374 struct radeon_fence { 375 struct dma_fence base; 376 377 struct radeon_device *rdev; 378 uint64_t seq; 379 /* RB, DMA, etc. */ 380 unsigned ring; 381 bool is_vm_update; 382 383 wait_queue_entry_t fence_wake; 384 }; 385 386 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 387 int radeon_fence_driver_init(struct radeon_device *rdev); 388 void radeon_fence_driver_fini(struct radeon_device *rdev); 389 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 390 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 391 void radeon_fence_process(struct radeon_device *rdev, int ring); 392 bool radeon_fence_signaled(struct radeon_fence *fence); 393 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout); 394 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 395 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 396 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 397 int radeon_fence_wait_any(struct radeon_device *rdev, 398 struct radeon_fence **fences, 399 bool intr); 400 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 401 void radeon_fence_unref(struct radeon_fence **fence); 402 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 403 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 404 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 405 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 406 struct radeon_fence *b) 407 { 408 if (!a) { 409 return b; 410 } 411 412 if (!b) { 413 return a; 414 } 415 416 BUG_ON(a->ring != b->ring); 417 418 if (a->seq > b->seq) { 419 return a; 420 } else { 421 return b; 422 } 423 } 424 425 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 426 struct radeon_fence *b) 427 { 428 if (!a) { 429 return false; 430 } 431 432 if (!b) { 433 return true; 434 } 435 436 BUG_ON(a->ring != b->ring); 437 438 return a->seq < b->seq; 439 } 440 441 /* 442 * Tiling registers 443 */ 444 struct radeon_surface_reg { 445 struct radeon_bo *bo; 446 }; 447 448 #define RADEON_GEM_MAX_SURFACES 8 449 450 /* 451 * TTM. 452 */ 453 struct radeon_mman { 454 struct ttm_bo_device bdev; 455 bool initialized; 456 }; 457 458 struct radeon_bo_list { 459 struct radeon_bo *robj; 460 struct ttm_validate_buffer tv; 461 uint64_t gpu_offset; 462 unsigned preferred_domains; 463 unsigned allowed_domains; 464 uint32_t tiling_flags; 465 }; 466 467 /* bo virtual address in a specific vm */ 468 struct radeon_bo_va { 469 /* protected by bo being reserved */ 470 struct list_head bo_list; 471 uint32_t flags; 472 struct radeon_fence *last_pt_update; 473 unsigned ref_count; 474 475 /* protected by vm mutex */ 476 struct interval_tree_node it; 477 struct list_head vm_status; 478 479 /* constant after initialization */ 480 struct radeon_vm *vm; 481 struct radeon_bo *bo; 482 }; 483 484 struct radeon_bo { 485 /* Protected by gem.mutex */ 486 struct list_head list; 487 /* Protected by tbo.reserved */ 488 u32 initial_domain; 489 struct ttm_place placements[4]; 490 struct ttm_placement placement; 491 struct ttm_buffer_object tbo; 492 struct ttm_bo_kmap_obj kmap; 493 u32 flags; 494 void *kptr; 495 u32 tiling_flags; 496 u32 pitch; 497 int surface_reg; 498 unsigned prime_shared_count; 499 /* list of all virtual address to which this bo 500 * is associated to 501 */ 502 struct list_head va; 503 /* Constant after initialization */ 504 struct radeon_device *rdev; 505 506 pid_t pid; 507 508 #ifdef CONFIG_MMU_NOTIFIER 509 struct mmu_interval_notifier notifier; 510 #endif 511 }; 512 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, tbo.base) 513 514 /* sub-allocation manager, it has to be protected by another lock. 515 * By conception this is an helper for other part of the driver 516 * like the indirect buffer or semaphore, which both have their 517 * locking. 518 * 519 * Principe is simple, we keep a list of sub allocation in offset 520 * order (first entry has offset == 0, last entry has the highest 521 * offset). 522 * 523 * When allocating new object we first check if there is room at 524 * the end total_size - (last_object_offset + last_object_size) >= 525 * alloc_size. If so we allocate new object there. 526 * 527 * When there is not enough room at the end, we start waiting for 528 * each sub object until we reach object_offset+object_size >= 529 * alloc_size, this object then become the sub object we return. 530 * 531 * Alignment can't be bigger than page size. 532 * 533 * Hole are not considered for allocation to keep things simple. 534 * Assumption is that there won't be hole (all object on same 535 * alignment). 536 */ 537 struct radeon_sa_manager { 538 wait_queue_head_t wq; 539 struct radeon_bo *bo; 540 struct list_head *hole; 541 struct list_head flist[RADEON_NUM_RINGS]; 542 struct list_head olist; 543 unsigned size; 544 uint64_t gpu_addr; 545 void *cpu_ptr; 546 uint32_t domain; 547 uint32_t align; 548 }; 549 550 struct radeon_sa_bo; 551 552 /* sub-allocation buffer */ 553 struct radeon_sa_bo { 554 struct list_head olist; 555 struct list_head flist; 556 struct radeon_sa_manager *manager; 557 unsigned soffset; 558 unsigned eoffset; 559 struct radeon_fence *fence; 560 }; 561 562 /* 563 * GEM objects. 564 */ 565 struct radeon_gem { 566 struct mutex mutex; 567 struct list_head objects; 568 }; 569 570 int radeon_gem_init(struct radeon_device *rdev); 571 void radeon_gem_fini(struct radeon_device *rdev); 572 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 573 int alignment, int initial_domain, 574 u32 flags, bool kernel, 575 struct drm_gem_object **obj); 576 577 int radeon_mode_dumb_create(struct drm_file *file_priv, 578 struct drm_device *dev, 579 struct drm_mode_create_dumb *args); 580 int radeon_mode_dumb_mmap(struct drm_file *filp, 581 struct drm_device *dev, 582 uint32_t handle, uint64_t *offset_p); 583 584 /* 585 * Semaphores. 586 */ 587 struct radeon_semaphore { 588 struct radeon_sa_bo *sa_bo; 589 signed waiters; 590 uint64_t gpu_addr; 591 }; 592 593 int radeon_semaphore_create(struct radeon_device *rdev, 594 struct radeon_semaphore **semaphore); 595 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 596 struct radeon_semaphore *semaphore); 597 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 598 struct radeon_semaphore *semaphore); 599 void radeon_semaphore_free(struct radeon_device *rdev, 600 struct radeon_semaphore **semaphore, 601 struct radeon_fence *fence); 602 603 /* 604 * Synchronization 605 */ 606 struct radeon_sync { 607 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS]; 608 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 609 struct radeon_fence *last_vm_update; 610 }; 611 612 void radeon_sync_create(struct radeon_sync *sync); 613 void radeon_sync_fence(struct radeon_sync *sync, 614 struct radeon_fence *fence); 615 int radeon_sync_resv(struct radeon_device *rdev, 616 struct radeon_sync *sync, 617 struct dma_resv *resv, 618 bool shared); 619 int radeon_sync_rings(struct radeon_device *rdev, 620 struct radeon_sync *sync, 621 int waiting_ring); 622 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync, 623 struct radeon_fence *fence); 624 625 /* 626 * GART structures, functions & helpers 627 */ 628 struct radeon_mc; 629 630 #define RADEON_GPU_PAGE_SIZE 4096 631 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 632 #define RADEON_GPU_PAGE_SHIFT 12 633 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 634 635 #define RADEON_GART_PAGE_DUMMY 0 636 #define RADEON_GART_PAGE_VALID (1 << 0) 637 #define RADEON_GART_PAGE_READ (1 << 1) 638 #define RADEON_GART_PAGE_WRITE (1 << 2) 639 #define RADEON_GART_PAGE_SNOOP (1 << 3) 640 641 struct radeon_gart { 642 dma_addr_t table_addr; 643 struct radeon_bo *robj; 644 void *ptr; 645 unsigned num_gpu_pages; 646 unsigned num_cpu_pages; 647 unsigned table_size; 648 struct page **pages; 649 uint64_t *pages_entry; 650 bool ready; 651 }; 652 653 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 654 void radeon_gart_table_ram_free(struct radeon_device *rdev); 655 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 656 void radeon_gart_table_vram_free(struct radeon_device *rdev); 657 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 658 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 659 int radeon_gart_init(struct radeon_device *rdev); 660 void radeon_gart_fini(struct radeon_device *rdev); 661 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 662 int pages); 663 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 664 int pages, struct page **pagelist, 665 dma_addr_t *dma_addr, uint32_t flags); 666 667 668 /* 669 * GPU MC structures, functions & helpers 670 */ 671 struct radeon_mc { 672 resource_size_t aper_size; 673 resource_size_t aper_base; 674 resource_size_t agp_base; 675 /* for some chips with <= 32MB we need to lie 676 * about vram size near mc fb location */ 677 u64 mc_vram_size; 678 u64 visible_vram_size; 679 u64 gtt_size; 680 u64 gtt_start; 681 u64 gtt_end; 682 u64 vram_start; 683 u64 vram_end; 684 unsigned vram_width; 685 u64 real_vram_size; 686 int vram_mtrr; 687 bool vram_is_ddr; 688 bool igp_sideport_enabled; 689 u64 gtt_base_align; 690 u64 mc_mask; 691 }; 692 693 bool radeon_combios_sideport_present(struct radeon_device *rdev); 694 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 695 696 /* 697 * GPU scratch registers structures, functions & helpers 698 */ 699 struct radeon_scratch { 700 unsigned num_reg; 701 uint32_t reg_base; 702 bool free[32]; 703 uint32_t reg[32]; 704 }; 705 706 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 707 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 708 709 /* 710 * GPU doorbell structures, functions & helpers 711 */ 712 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 713 714 struct radeon_doorbell { 715 /* doorbell mmio */ 716 resource_size_t base; 717 resource_size_t size; 718 u32 __iomem *ptr; 719 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 720 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS); 721 }; 722 723 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 724 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 725 726 /* 727 * IRQS. 728 */ 729 730 struct radeon_flip_work { 731 struct work_struct flip_work; 732 struct work_struct unpin_work; 733 struct radeon_device *rdev; 734 int crtc_id; 735 u32 target_vblank; 736 uint64_t base; 737 struct drm_pending_vblank_event *event; 738 struct radeon_bo *old_rbo; 739 struct dma_fence *fence; 740 bool async; 741 }; 742 743 struct r500_irq_stat_regs { 744 u32 disp_int; 745 u32 hdmi0_status; 746 }; 747 748 struct r600_irq_stat_regs { 749 u32 disp_int; 750 u32 disp_int_cont; 751 u32 disp_int_cont2; 752 u32 d1grph_int; 753 u32 d2grph_int; 754 u32 hdmi0_status; 755 u32 hdmi1_status; 756 }; 757 758 struct evergreen_irq_stat_regs { 759 u32 disp_int[6]; 760 u32 grph_int[6]; 761 u32 afmt_status[6]; 762 }; 763 764 struct cik_irq_stat_regs { 765 u32 disp_int; 766 u32 disp_int_cont; 767 u32 disp_int_cont2; 768 u32 disp_int_cont3; 769 u32 disp_int_cont4; 770 u32 disp_int_cont5; 771 u32 disp_int_cont6; 772 u32 d1grph_int; 773 u32 d2grph_int; 774 u32 d3grph_int; 775 u32 d4grph_int; 776 u32 d5grph_int; 777 u32 d6grph_int; 778 }; 779 780 union radeon_irq_stat_regs { 781 struct r500_irq_stat_regs r500; 782 struct r600_irq_stat_regs r600; 783 struct evergreen_irq_stat_regs evergreen; 784 struct cik_irq_stat_regs cik; 785 }; 786 787 struct radeon_irq { 788 bool installed; 789 spinlock_t lock; 790 atomic_t ring_int[RADEON_NUM_RINGS]; 791 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 792 atomic_t pflip[RADEON_MAX_CRTCS]; 793 wait_queue_head_t vblank_queue; 794 bool hpd[RADEON_MAX_HPD_PINS]; 795 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 796 union radeon_irq_stat_regs stat_regs; 797 bool dpm_thermal; 798 }; 799 800 int radeon_irq_kms_init(struct radeon_device *rdev); 801 void radeon_irq_kms_fini(struct radeon_device *rdev); 802 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 803 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); 804 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 805 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 806 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 807 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 808 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 809 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 810 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 811 812 /* 813 * CP & rings. 814 */ 815 816 struct radeon_ib { 817 struct radeon_sa_bo *sa_bo; 818 uint32_t length_dw; 819 uint64_t gpu_addr; 820 uint32_t *ptr; 821 int ring; 822 struct radeon_fence *fence; 823 struct radeon_vm *vm; 824 bool is_const_ib; 825 struct radeon_sync sync; 826 }; 827 828 struct radeon_ring { 829 struct radeon_device *rdev; 830 struct radeon_bo *ring_obj; 831 volatile uint32_t *ring; 832 unsigned rptr_offs; 833 unsigned rptr_save_reg; 834 u64 next_rptr_gpu_addr; 835 volatile u32 *next_rptr_cpu_addr; 836 unsigned wptr; 837 unsigned wptr_old; 838 unsigned ring_size; 839 unsigned ring_free_dw; 840 int count_dw; 841 atomic_t last_rptr; 842 atomic64_t last_activity; 843 uint64_t gpu_addr; 844 uint32_t align_mask; 845 uint32_t ptr_mask; 846 bool ready; 847 u32 nop; 848 u32 idx; 849 u64 last_semaphore_signal_addr; 850 u64 last_semaphore_wait_addr; 851 /* for CIK queues */ 852 u32 me; 853 u32 pipe; 854 u32 queue; 855 struct radeon_bo *mqd_obj; 856 u32 doorbell_index; 857 unsigned wptr_offs; 858 }; 859 860 struct radeon_mec { 861 struct radeon_bo *hpd_eop_obj; 862 u64 hpd_eop_gpu_addr; 863 u32 num_pipe; 864 u32 num_mec; 865 u32 num_queue; 866 }; 867 868 /* 869 * VM 870 */ 871 872 /* maximum number of VMIDs */ 873 #define RADEON_NUM_VM 16 874 875 /* number of entries in page table */ 876 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 877 878 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 879 #define RADEON_VM_PTB_ALIGN_SIZE 32768 880 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 881 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 882 883 #define R600_PTE_VALID (1 << 0) 884 #define R600_PTE_SYSTEM (1 << 1) 885 #define R600_PTE_SNOOPED (1 << 2) 886 #define R600_PTE_READABLE (1 << 5) 887 #define R600_PTE_WRITEABLE (1 << 6) 888 889 /* PTE (Page Table Entry) fragment field for different page sizes */ 890 #define R600_PTE_FRAG_4KB (0 << 7) 891 #define R600_PTE_FRAG_64KB (4 << 7) 892 #define R600_PTE_FRAG_256KB (6 << 7) 893 894 /* flags needed to be set so we can copy directly from the GART table */ 895 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 896 R600_PTE_SYSTEM | R600_PTE_VALID ) 897 898 struct radeon_vm_pt { 899 struct radeon_bo *bo; 900 uint64_t addr; 901 }; 902 903 struct radeon_vm_id { 904 unsigned id; 905 uint64_t pd_gpu_addr; 906 /* last flushed PD/PT update */ 907 struct radeon_fence *flushed_updates; 908 /* last use of vmid */ 909 struct radeon_fence *last_id_use; 910 }; 911 912 struct radeon_vm { 913 struct mutex mutex; 914 915 struct rb_root_cached va; 916 917 /* protecting invalidated and freed */ 918 spinlock_t status_lock; 919 920 /* BOs moved, but not yet updated in the PT */ 921 struct list_head invalidated; 922 923 /* BOs freed, but not yet updated in the PT */ 924 struct list_head freed; 925 926 /* BOs cleared in the PT */ 927 struct list_head cleared; 928 929 /* contains the page directory */ 930 struct radeon_bo *page_directory; 931 unsigned max_pde_used; 932 933 /* array of page tables, one for each page directory entry */ 934 struct radeon_vm_pt *page_tables; 935 936 struct radeon_bo_va *ib_bo_va; 937 938 /* for id and flush management per ring */ 939 struct radeon_vm_id ids[RADEON_NUM_RINGS]; 940 }; 941 942 struct radeon_vm_manager { 943 struct radeon_fence *active[RADEON_NUM_VM]; 944 uint32_t max_pfn; 945 /* number of VMIDs */ 946 unsigned nvm; 947 /* vram base address for page table entry */ 948 u64 vram_base_offset; 949 /* is vm enabled? */ 950 bool enabled; 951 /* for hw to save the PD addr on suspend/resume */ 952 uint32_t saved_table_addr[RADEON_NUM_VM]; 953 }; 954 955 /* 956 * file private structure 957 */ 958 struct radeon_fpriv { 959 struct radeon_vm vm; 960 }; 961 962 /* 963 * R6xx+ IH ring 964 */ 965 struct r600_ih { 966 struct radeon_bo *ring_obj; 967 volatile uint32_t *ring; 968 unsigned rptr; 969 unsigned ring_size; 970 uint64_t gpu_addr; 971 uint32_t ptr_mask; 972 atomic_t lock; 973 bool enabled; 974 }; 975 976 /* 977 * RLC stuff 978 */ 979 #include "clearstate_defs.h" 980 981 struct radeon_rlc { 982 /* for power gating */ 983 struct radeon_bo *save_restore_obj; 984 uint64_t save_restore_gpu_addr; 985 volatile uint32_t *sr_ptr; 986 const u32 *reg_list; 987 u32 reg_list_size; 988 /* for clear state */ 989 struct radeon_bo *clear_state_obj; 990 uint64_t clear_state_gpu_addr; 991 volatile uint32_t *cs_ptr; 992 const struct cs_section_def *cs_data; 993 u32 clear_state_size; 994 /* for cp tables */ 995 struct radeon_bo *cp_table_obj; 996 uint64_t cp_table_gpu_addr; 997 volatile uint32_t *cp_table_ptr; 998 u32 cp_table_size; 999 }; 1000 1001 int radeon_ib_get(struct radeon_device *rdev, int ring, 1002 struct radeon_ib *ib, struct radeon_vm *vm, 1003 unsigned size); 1004 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 1005 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 1006 struct radeon_ib *const_ib, bool hdp_flush); 1007 int radeon_ib_pool_init(struct radeon_device *rdev); 1008 void radeon_ib_pool_fini(struct radeon_device *rdev); 1009 int radeon_ib_ring_tests(struct radeon_device *rdev); 1010 /* Ring access between begin & end cannot sleep */ 1011 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 1012 struct radeon_ring *ring); 1013 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 1014 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1015 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1016 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1017 bool hdp_flush); 1018 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1019 bool hdp_flush); 1020 void radeon_ring_undo(struct radeon_ring *ring); 1021 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 1022 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 1023 void radeon_ring_lockup_update(struct radeon_device *rdev, 1024 struct radeon_ring *ring); 1025 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1026 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1027 uint32_t **data); 1028 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1029 unsigned size, uint32_t *data); 1030 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1031 unsigned rptr_offs, u32 nop); 1032 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1033 1034 1035 /* r600 async dma */ 1036 void r600_dma_stop(struct radeon_device *rdev); 1037 int r600_dma_resume(struct radeon_device *rdev); 1038 void r600_dma_fini(struct radeon_device *rdev); 1039 1040 void cayman_dma_stop(struct radeon_device *rdev); 1041 int cayman_dma_resume(struct radeon_device *rdev); 1042 void cayman_dma_fini(struct radeon_device *rdev); 1043 1044 /* 1045 * CS. 1046 */ 1047 struct radeon_cs_chunk { 1048 uint32_t length_dw; 1049 uint32_t *kdata; 1050 void __user *user_ptr; 1051 }; 1052 1053 struct radeon_cs_parser { 1054 struct device *dev; 1055 struct radeon_device *rdev; 1056 struct drm_file *filp; 1057 /* chunks */ 1058 unsigned nchunks; 1059 struct radeon_cs_chunk *chunks; 1060 uint64_t *chunks_array; 1061 /* IB */ 1062 unsigned idx; 1063 /* relocations */ 1064 unsigned nrelocs; 1065 struct radeon_bo_list *relocs; 1066 struct radeon_bo_list *vm_bos; 1067 struct list_head validated; 1068 unsigned dma_reloc_idx; 1069 /* indices of various chunks */ 1070 struct radeon_cs_chunk *chunk_ib; 1071 struct radeon_cs_chunk *chunk_relocs; 1072 struct radeon_cs_chunk *chunk_flags; 1073 struct radeon_cs_chunk *chunk_const_ib; 1074 struct radeon_ib ib; 1075 struct radeon_ib const_ib; 1076 void *track; 1077 unsigned family; 1078 int parser_error; 1079 u32 cs_flags; 1080 u32 ring; 1081 s32 priority; 1082 struct ww_acquire_ctx ticket; 1083 }; 1084 1085 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1086 { 1087 struct radeon_cs_chunk *ibc = p->chunk_ib; 1088 1089 if (ibc->kdata) 1090 return ibc->kdata[idx]; 1091 return p->ib.ptr[idx]; 1092 } 1093 1094 1095 struct radeon_cs_packet { 1096 unsigned idx; 1097 unsigned type; 1098 unsigned reg; 1099 unsigned opcode; 1100 int count; 1101 unsigned one_reg_wr; 1102 }; 1103 1104 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1105 struct radeon_cs_packet *pkt, 1106 unsigned idx, unsigned reg); 1107 1108 /* 1109 * AGP 1110 */ 1111 int radeon_agp_init(struct radeon_device *rdev); 1112 void radeon_agp_resume(struct radeon_device *rdev); 1113 void radeon_agp_suspend(struct radeon_device *rdev); 1114 void radeon_agp_fini(struct radeon_device *rdev); 1115 1116 1117 /* 1118 * Writeback 1119 */ 1120 struct radeon_wb { 1121 struct radeon_bo *wb_obj; 1122 volatile uint32_t *wb; 1123 uint64_t gpu_addr; 1124 bool enabled; 1125 bool use_event; 1126 }; 1127 1128 #define RADEON_WB_SCRATCH_OFFSET 0 1129 #define RADEON_WB_RING0_NEXT_RPTR 256 1130 #define RADEON_WB_CP_RPTR_OFFSET 1024 1131 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1132 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1133 #define R600_WB_DMA_RPTR_OFFSET 1792 1134 #define R600_WB_IH_WPTR_OFFSET 2048 1135 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1136 #define R600_WB_EVENT_OFFSET 3072 1137 #define CIK_WB_CP1_WPTR_OFFSET 3328 1138 #define CIK_WB_CP2_WPTR_OFFSET 3584 1139 #define R600_WB_DMA_RING_TEST_OFFSET 3588 1140 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 1141 1142 /** 1143 * struct radeon_pm - power management datas 1144 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1145 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1146 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1147 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1148 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1149 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1150 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1151 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1152 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1153 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1154 * @needed_bandwidth: current bandwidth needs 1155 * 1156 * It keeps track of various data needed to take powermanagement decision. 1157 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1158 * Equation between gpu/memory clock and available bandwidth is hw dependent 1159 * (type of memory, bus size, efficiency, ...) 1160 */ 1161 1162 enum radeon_pm_method { 1163 PM_METHOD_PROFILE, 1164 PM_METHOD_DYNPM, 1165 PM_METHOD_DPM, 1166 }; 1167 1168 enum radeon_dynpm_state { 1169 DYNPM_STATE_DISABLED, 1170 DYNPM_STATE_MINIMUM, 1171 DYNPM_STATE_PAUSED, 1172 DYNPM_STATE_ACTIVE, 1173 DYNPM_STATE_SUSPENDED, 1174 }; 1175 enum radeon_dynpm_action { 1176 DYNPM_ACTION_NONE, 1177 DYNPM_ACTION_MINIMUM, 1178 DYNPM_ACTION_DOWNCLOCK, 1179 DYNPM_ACTION_UPCLOCK, 1180 DYNPM_ACTION_DEFAULT 1181 }; 1182 1183 enum radeon_voltage_type { 1184 VOLTAGE_NONE = 0, 1185 VOLTAGE_GPIO, 1186 VOLTAGE_VDDC, 1187 VOLTAGE_SW 1188 }; 1189 1190 enum radeon_pm_state_type { 1191 /* not used for dpm */ 1192 POWER_STATE_TYPE_DEFAULT, 1193 POWER_STATE_TYPE_POWERSAVE, 1194 /* user selectable states */ 1195 POWER_STATE_TYPE_BATTERY, 1196 POWER_STATE_TYPE_BALANCED, 1197 POWER_STATE_TYPE_PERFORMANCE, 1198 /* internal states */ 1199 POWER_STATE_TYPE_INTERNAL_UVD, 1200 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1201 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1202 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1203 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1204 POWER_STATE_TYPE_INTERNAL_BOOT, 1205 POWER_STATE_TYPE_INTERNAL_THERMAL, 1206 POWER_STATE_TYPE_INTERNAL_ACPI, 1207 POWER_STATE_TYPE_INTERNAL_ULV, 1208 POWER_STATE_TYPE_INTERNAL_3DPERF, 1209 }; 1210 1211 enum radeon_pm_profile_type { 1212 PM_PROFILE_DEFAULT, 1213 PM_PROFILE_AUTO, 1214 PM_PROFILE_LOW, 1215 PM_PROFILE_MID, 1216 PM_PROFILE_HIGH, 1217 }; 1218 1219 #define PM_PROFILE_DEFAULT_IDX 0 1220 #define PM_PROFILE_LOW_SH_IDX 1 1221 #define PM_PROFILE_MID_SH_IDX 2 1222 #define PM_PROFILE_HIGH_SH_IDX 3 1223 #define PM_PROFILE_LOW_MH_IDX 4 1224 #define PM_PROFILE_MID_MH_IDX 5 1225 #define PM_PROFILE_HIGH_MH_IDX 6 1226 #define PM_PROFILE_MAX 7 1227 1228 struct radeon_pm_profile { 1229 int dpms_off_ps_idx; 1230 int dpms_on_ps_idx; 1231 int dpms_off_cm_idx; 1232 int dpms_on_cm_idx; 1233 }; 1234 1235 enum radeon_int_thermal_type { 1236 THERMAL_TYPE_NONE, 1237 THERMAL_TYPE_EXTERNAL, 1238 THERMAL_TYPE_EXTERNAL_GPIO, 1239 THERMAL_TYPE_RV6XX, 1240 THERMAL_TYPE_RV770, 1241 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1242 THERMAL_TYPE_EVERGREEN, 1243 THERMAL_TYPE_SUMO, 1244 THERMAL_TYPE_NI, 1245 THERMAL_TYPE_SI, 1246 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1247 THERMAL_TYPE_CI, 1248 THERMAL_TYPE_KV, 1249 }; 1250 1251 struct radeon_voltage { 1252 enum radeon_voltage_type type; 1253 /* gpio voltage */ 1254 struct radeon_gpio_rec gpio; 1255 u32 delay; /* delay in usec from voltage drop to sclk change */ 1256 bool active_high; /* voltage drop is active when bit is high */ 1257 /* VDDC voltage */ 1258 u8 vddc_id; /* index into vddc voltage table */ 1259 u8 vddci_id; /* index into vddci voltage table */ 1260 bool vddci_enabled; 1261 /* r6xx+ sw */ 1262 u16 voltage; 1263 /* evergreen+ vddci */ 1264 u16 vddci; 1265 }; 1266 1267 /* clock mode flags */ 1268 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1269 1270 struct radeon_pm_clock_info { 1271 /* memory clock */ 1272 u32 mclk; 1273 /* engine clock */ 1274 u32 sclk; 1275 /* voltage info */ 1276 struct radeon_voltage voltage; 1277 /* standardized clock flags */ 1278 u32 flags; 1279 }; 1280 1281 /* state flags */ 1282 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1283 1284 struct radeon_power_state { 1285 enum radeon_pm_state_type type; 1286 struct radeon_pm_clock_info *clock_info; 1287 /* number of valid clock modes in this power state */ 1288 int num_clock_modes; 1289 struct radeon_pm_clock_info *default_clock_mode; 1290 /* standardized state flags */ 1291 u32 flags; 1292 u32 misc; /* vbios specific flags */ 1293 u32 misc2; /* vbios specific flags */ 1294 int pcie_lanes; /* pcie lanes */ 1295 }; 1296 1297 /* 1298 * Some modes are overclocked by very low value, accept them 1299 */ 1300 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1301 1302 enum radeon_dpm_auto_throttle_src { 1303 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1304 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1305 }; 1306 1307 enum radeon_dpm_event_src { 1308 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1309 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1310 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1311 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1312 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1313 }; 1314 1315 #define RADEON_MAX_VCE_LEVELS 6 1316 1317 enum radeon_vce_level { 1318 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1319 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1320 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1321 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1322 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1323 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1324 }; 1325 1326 struct radeon_ps { 1327 u32 caps; /* vbios flags */ 1328 u32 class; /* vbios flags */ 1329 u32 class2; /* vbios flags */ 1330 /* UVD clocks */ 1331 u32 vclk; 1332 u32 dclk; 1333 /* VCE clocks */ 1334 u32 evclk; 1335 u32 ecclk; 1336 bool vce_active; 1337 enum radeon_vce_level vce_level; 1338 /* asic priv */ 1339 void *ps_priv; 1340 }; 1341 1342 struct radeon_dpm_thermal { 1343 /* thermal interrupt work */ 1344 struct work_struct work; 1345 /* low temperature threshold */ 1346 int min_temp; 1347 /* high temperature threshold */ 1348 int max_temp; 1349 /* was interrupt low to high or high to low */ 1350 bool high_to_low; 1351 }; 1352 1353 enum radeon_clk_action 1354 { 1355 RADEON_SCLK_UP = 1, 1356 RADEON_SCLK_DOWN 1357 }; 1358 1359 struct radeon_blacklist_clocks 1360 { 1361 u32 sclk; 1362 u32 mclk; 1363 enum radeon_clk_action action; 1364 }; 1365 1366 struct radeon_clock_and_voltage_limits { 1367 u32 sclk; 1368 u32 mclk; 1369 u16 vddc; 1370 u16 vddci; 1371 }; 1372 1373 struct radeon_clock_array { 1374 u32 count; 1375 u32 *values; 1376 }; 1377 1378 struct radeon_clock_voltage_dependency_entry { 1379 u32 clk; 1380 u16 v; 1381 }; 1382 1383 struct radeon_clock_voltage_dependency_table { 1384 u32 count; 1385 struct radeon_clock_voltage_dependency_entry *entries; 1386 }; 1387 1388 union radeon_cac_leakage_entry { 1389 struct { 1390 u16 vddc; 1391 u32 leakage; 1392 }; 1393 struct { 1394 u16 vddc1; 1395 u16 vddc2; 1396 u16 vddc3; 1397 }; 1398 }; 1399 1400 struct radeon_cac_leakage_table { 1401 u32 count; 1402 union radeon_cac_leakage_entry *entries; 1403 }; 1404 1405 struct radeon_phase_shedding_limits_entry { 1406 u16 voltage; 1407 u32 sclk; 1408 u32 mclk; 1409 }; 1410 1411 struct radeon_phase_shedding_limits_table { 1412 u32 count; 1413 struct radeon_phase_shedding_limits_entry *entries; 1414 }; 1415 1416 struct radeon_uvd_clock_voltage_dependency_entry { 1417 u32 vclk; 1418 u32 dclk; 1419 u16 v; 1420 }; 1421 1422 struct radeon_uvd_clock_voltage_dependency_table { 1423 u8 count; 1424 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1425 }; 1426 1427 struct radeon_vce_clock_voltage_dependency_entry { 1428 u32 ecclk; 1429 u32 evclk; 1430 u16 v; 1431 }; 1432 1433 struct radeon_vce_clock_voltage_dependency_table { 1434 u8 count; 1435 struct radeon_vce_clock_voltage_dependency_entry *entries; 1436 }; 1437 1438 struct radeon_ppm_table { 1439 u8 ppm_design; 1440 u16 cpu_core_number; 1441 u32 platform_tdp; 1442 u32 small_ac_platform_tdp; 1443 u32 platform_tdc; 1444 u32 small_ac_platform_tdc; 1445 u32 apu_tdp; 1446 u32 dgpu_tdp; 1447 u32 dgpu_ulv_power; 1448 u32 tj_max; 1449 }; 1450 1451 struct radeon_cac_tdp_table { 1452 u16 tdp; 1453 u16 configurable_tdp; 1454 u16 tdc; 1455 u16 battery_power_limit; 1456 u16 small_power_limit; 1457 u16 low_cac_leakage; 1458 u16 high_cac_leakage; 1459 u16 maximum_power_delivery_limit; 1460 }; 1461 1462 struct radeon_dpm_dynamic_state { 1463 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1464 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1465 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1466 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1467 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1468 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1469 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1470 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1471 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1472 struct radeon_clock_array valid_sclk_values; 1473 struct radeon_clock_array valid_mclk_values; 1474 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1475 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1476 u32 mclk_sclk_ratio; 1477 u32 sclk_mclk_delta; 1478 u16 vddc_vddci_delta; 1479 u16 min_vddc_for_pcie_gen2; 1480 struct radeon_cac_leakage_table cac_leakage_table; 1481 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1482 struct radeon_ppm_table *ppm_table; 1483 struct radeon_cac_tdp_table *cac_tdp_table; 1484 }; 1485 1486 struct radeon_dpm_fan { 1487 u16 t_min; 1488 u16 t_med; 1489 u16 t_high; 1490 u16 pwm_min; 1491 u16 pwm_med; 1492 u16 pwm_high; 1493 u8 t_hyst; 1494 u32 cycle_delay; 1495 u16 t_max; 1496 u8 control_mode; 1497 u16 default_max_fan_pwm; 1498 u16 default_fan_output_sensitivity; 1499 u16 fan_output_sensitivity; 1500 bool ucode_fan_control; 1501 }; 1502 1503 enum radeon_pcie_gen { 1504 RADEON_PCIE_GEN1 = 0, 1505 RADEON_PCIE_GEN2 = 1, 1506 RADEON_PCIE_GEN3 = 2, 1507 RADEON_PCIE_GEN_INVALID = 0xffff 1508 }; 1509 1510 enum radeon_dpm_forced_level { 1511 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1512 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1513 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1514 }; 1515 1516 struct radeon_vce_state { 1517 /* vce clocks */ 1518 u32 evclk; 1519 u32 ecclk; 1520 /* gpu clocks */ 1521 u32 sclk; 1522 u32 mclk; 1523 u8 clk_idx; 1524 u8 pstate; 1525 }; 1526 1527 struct radeon_dpm { 1528 struct radeon_ps *ps; 1529 /* number of valid power states */ 1530 int num_ps; 1531 /* current power state that is active */ 1532 struct radeon_ps *current_ps; 1533 /* requested power state */ 1534 struct radeon_ps *requested_ps; 1535 /* boot up power state */ 1536 struct radeon_ps *boot_ps; 1537 /* default uvd power state */ 1538 struct radeon_ps *uvd_ps; 1539 /* vce requirements */ 1540 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1541 enum radeon_vce_level vce_level; 1542 enum radeon_pm_state_type state; 1543 enum radeon_pm_state_type user_state; 1544 u32 platform_caps; 1545 u32 voltage_response_time; 1546 u32 backbias_response_time; 1547 void *priv; 1548 u32 new_active_crtcs; 1549 int new_active_crtc_count; 1550 u32 current_active_crtcs; 1551 int current_active_crtc_count; 1552 bool single_display; 1553 struct radeon_dpm_dynamic_state dyn_state; 1554 struct radeon_dpm_fan fan; 1555 u32 tdp_limit; 1556 u32 near_tdp_limit; 1557 u32 near_tdp_limit_adjusted; 1558 u32 sq_ramping_threshold; 1559 u32 cac_leakage; 1560 u16 tdp_od_limit; 1561 u32 tdp_adjustment; 1562 u16 load_line_slope; 1563 bool power_control; 1564 bool ac_power; 1565 /* special states active */ 1566 bool thermal_active; 1567 bool uvd_active; 1568 bool vce_active; 1569 /* thermal handling */ 1570 struct radeon_dpm_thermal thermal; 1571 /* forced levels */ 1572 enum radeon_dpm_forced_level forced_level; 1573 /* track UVD streams */ 1574 unsigned sd; 1575 unsigned hd; 1576 }; 1577 1578 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1579 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1580 1581 struct radeon_pm { 1582 struct mutex mutex; 1583 /* write locked while reprogramming mclk */ 1584 struct rw_semaphore mclk_lock; 1585 u32 active_crtcs; 1586 int active_crtc_count; 1587 int req_vblank; 1588 bool vblank_sync; 1589 fixed20_12 max_bandwidth; 1590 fixed20_12 igp_sideport_mclk; 1591 fixed20_12 igp_system_mclk; 1592 fixed20_12 igp_ht_link_clk; 1593 fixed20_12 igp_ht_link_width; 1594 fixed20_12 k8_bandwidth; 1595 fixed20_12 sideport_bandwidth; 1596 fixed20_12 ht_bandwidth; 1597 fixed20_12 core_bandwidth; 1598 fixed20_12 sclk; 1599 fixed20_12 mclk; 1600 fixed20_12 needed_bandwidth; 1601 struct radeon_power_state *power_state; 1602 /* number of valid power states */ 1603 int num_power_states; 1604 int current_power_state_index; 1605 int current_clock_mode_index; 1606 int requested_power_state_index; 1607 int requested_clock_mode_index; 1608 int default_power_state_index; 1609 u32 current_sclk; 1610 u32 current_mclk; 1611 u16 current_vddc; 1612 u16 current_vddci; 1613 u32 default_sclk; 1614 u32 default_mclk; 1615 u16 default_vddc; 1616 u16 default_vddci; 1617 struct radeon_i2c_chan *i2c_bus; 1618 /* selected pm method */ 1619 enum radeon_pm_method pm_method; 1620 /* dynpm power management */ 1621 struct delayed_work dynpm_idle_work; 1622 enum radeon_dynpm_state dynpm_state; 1623 enum radeon_dynpm_action dynpm_planned_action; 1624 unsigned long dynpm_action_timeout; 1625 bool dynpm_can_upclock; 1626 bool dynpm_can_downclock; 1627 /* profile-based power management */ 1628 enum radeon_pm_profile_type profile; 1629 int profile_index; 1630 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1631 /* internal thermal controller on rv6xx+ */ 1632 enum radeon_int_thermal_type int_thermal_type; 1633 struct device *int_hwmon_dev; 1634 /* fan control parameters */ 1635 bool no_fan; 1636 u8 fan_pulses_per_revolution; 1637 u8 fan_min_rpm; 1638 u8 fan_max_rpm; 1639 /* dpm */ 1640 bool dpm_enabled; 1641 bool sysfs_initialized; 1642 struct radeon_dpm dpm; 1643 }; 1644 1645 #define RADEON_PCIE_SPEED_25 1 1646 #define RADEON_PCIE_SPEED_50 2 1647 #define RADEON_PCIE_SPEED_80 4 1648 1649 int radeon_pm_get_type_index(struct radeon_device *rdev, 1650 enum radeon_pm_state_type ps_type, 1651 int instance); 1652 /* 1653 * UVD 1654 */ 1655 #define RADEON_DEFAULT_UVD_HANDLES 10 1656 #define RADEON_MAX_UVD_HANDLES 30 1657 #define RADEON_UVD_STACK_SIZE (200*1024) 1658 #define RADEON_UVD_HEAP_SIZE (256*1024) 1659 #define RADEON_UVD_SESSION_SIZE (50*1024) 1660 1661 struct radeon_uvd { 1662 bool fw_header_present; 1663 struct radeon_bo *vcpu_bo; 1664 void *cpu_addr; 1665 uint64_t gpu_addr; 1666 unsigned max_handles; 1667 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1668 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1669 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1670 struct delayed_work idle_work; 1671 }; 1672 1673 int radeon_uvd_init(struct radeon_device *rdev); 1674 void radeon_uvd_fini(struct radeon_device *rdev); 1675 int radeon_uvd_suspend(struct radeon_device *rdev); 1676 int radeon_uvd_resume(struct radeon_device *rdev); 1677 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1678 uint32_t handle, struct radeon_fence **fence); 1679 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1680 uint32_t handle, struct radeon_fence **fence); 1681 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1682 uint32_t allowed_domains); 1683 void radeon_uvd_free_handles(struct radeon_device *rdev, 1684 struct drm_file *filp); 1685 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1686 void radeon_uvd_note_usage(struct radeon_device *rdev); 1687 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1688 unsigned vclk, unsigned dclk, 1689 unsigned vco_min, unsigned vco_max, 1690 unsigned fb_factor, unsigned fb_mask, 1691 unsigned pd_min, unsigned pd_max, 1692 unsigned pd_even, 1693 unsigned *optimal_fb_div, 1694 unsigned *optimal_vclk_div, 1695 unsigned *optimal_dclk_div); 1696 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1697 unsigned cg_upll_func_cntl); 1698 1699 /* 1700 * VCE 1701 */ 1702 #define RADEON_MAX_VCE_HANDLES 16 1703 1704 struct radeon_vce { 1705 struct radeon_bo *vcpu_bo; 1706 uint64_t gpu_addr; 1707 unsigned fw_version; 1708 unsigned fb_version; 1709 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1710 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1711 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1712 struct delayed_work idle_work; 1713 uint32_t keyselect; 1714 }; 1715 1716 int radeon_vce_init(struct radeon_device *rdev); 1717 void radeon_vce_fini(struct radeon_device *rdev); 1718 int radeon_vce_suspend(struct radeon_device *rdev); 1719 int radeon_vce_resume(struct radeon_device *rdev); 1720 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1721 uint32_t handle, struct radeon_fence **fence); 1722 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1723 uint32_t handle, struct radeon_fence **fence); 1724 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1725 void radeon_vce_note_usage(struct radeon_device *rdev); 1726 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1727 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1728 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1729 struct radeon_ring *ring, 1730 struct radeon_semaphore *semaphore, 1731 bool emit_wait); 1732 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1733 void radeon_vce_fence_emit(struct radeon_device *rdev, 1734 struct radeon_fence *fence); 1735 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1736 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1737 1738 struct r600_audio_pin { 1739 int channels; 1740 int rate; 1741 int bits_per_sample; 1742 u8 status_bits; 1743 u8 category_code; 1744 u32 offset; 1745 bool connected; 1746 u32 id; 1747 }; 1748 1749 struct r600_audio { 1750 bool enabled; 1751 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1752 int num_pins; 1753 struct radeon_audio_funcs *hdmi_funcs; 1754 struct radeon_audio_funcs *dp_funcs; 1755 struct radeon_audio_basic_funcs *funcs; 1756 }; 1757 1758 /* 1759 * Benchmarking 1760 */ 1761 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1762 1763 1764 /* 1765 * Testing 1766 */ 1767 void radeon_test_moves(struct radeon_device *rdev); 1768 void radeon_test_ring_sync(struct radeon_device *rdev, 1769 struct radeon_ring *cpA, 1770 struct radeon_ring *cpB); 1771 void radeon_test_syncing(struct radeon_device *rdev); 1772 1773 /* 1774 * MMU Notifier 1775 */ 1776 #if defined(CONFIG_MMU_NOTIFIER) 1777 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); 1778 void radeon_mn_unregister(struct radeon_bo *bo); 1779 #else 1780 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr) 1781 { 1782 return -ENODEV; 1783 } 1784 static inline void radeon_mn_unregister(struct radeon_bo *bo) {} 1785 #endif 1786 1787 /* 1788 * Debugfs 1789 */ 1790 void radeon_debugfs_fence_init(struct radeon_device *rdev); 1791 void radeon_gem_debugfs_init(struct radeon_device *rdev); 1792 1793 /* 1794 * ASIC ring specific functions. 1795 */ 1796 struct radeon_asic_ring { 1797 /* ring read/write ptr handling */ 1798 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1799 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1800 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1801 1802 /* validating and patching of IBs */ 1803 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1804 int (*cs_parse)(struct radeon_cs_parser *p); 1805 1806 /* command emmit functions */ 1807 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1808 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1809 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1810 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1811 struct radeon_semaphore *semaphore, bool emit_wait); 1812 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring, 1813 unsigned vm_id, uint64_t pd_addr); 1814 1815 /* testing functions */ 1816 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1817 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1818 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1819 1820 /* deprecated */ 1821 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1822 }; 1823 1824 /* 1825 * ASIC specific functions. 1826 */ 1827 struct radeon_asic { 1828 int (*init)(struct radeon_device *rdev); 1829 void (*fini)(struct radeon_device *rdev); 1830 int (*resume)(struct radeon_device *rdev); 1831 int (*suspend)(struct radeon_device *rdev); 1832 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1833 int (*asic_reset)(struct radeon_device *rdev, bool hard); 1834 /* Flush the HDP cache via MMIO */ 1835 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1836 /* check if 3D engine is idle */ 1837 bool (*gui_idle)(struct radeon_device *rdev); 1838 /* wait for mc_idle */ 1839 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1840 /* get the reference clock */ 1841 u32 (*get_xclk)(struct radeon_device *rdev); 1842 /* get the gpu clock counter */ 1843 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1844 /* get register for info ioctl */ 1845 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val); 1846 /* gart */ 1847 struct { 1848 void (*tlb_flush)(struct radeon_device *rdev); 1849 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags); 1850 void (*set_page)(struct radeon_device *rdev, unsigned i, 1851 uint64_t entry); 1852 } gart; 1853 struct { 1854 int (*init)(struct radeon_device *rdev); 1855 void (*fini)(struct radeon_device *rdev); 1856 void (*copy_pages)(struct radeon_device *rdev, 1857 struct radeon_ib *ib, 1858 uint64_t pe, uint64_t src, 1859 unsigned count); 1860 void (*write_pages)(struct radeon_device *rdev, 1861 struct radeon_ib *ib, 1862 uint64_t pe, 1863 uint64_t addr, unsigned count, 1864 uint32_t incr, uint32_t flags); 1865 void (*set_pages)(struct radeon_device *rdev, 1866 struct radeon_ib *ib, 1867 uint64_t pe, 1868 uint64_t addr, unsigned count, 1869 uint32_t incr, uint32_t flags); 1870 void (*pad_ib)(struct radeon_ib *ib); 1871 } vm; 1872 /* ring specific callbacks */ 1873 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1874 /* irqs */ 1875 struct { 1876 int (*set)(struct radeon_device *rdev); 1877 int (*process)(struct radeon_device *rdev); 1878 } irq; 1879 /* displays */ 1880 struct { 1881 /* display watermarks */ 1882 void (*bandwidth_update)(struct radeon_device *rdev); 1883 /* get frame count */ 1884 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1885 /* wait for vblank */ 1886 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1887 /* set backlight level */ 1888 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1889 /* get backlight level */ 1890 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1891 /* audio callbacks */ 1892 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1893 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1894 } display; 1895 /* copy functions for bo handling */ 1896 struct { 1897 struct radeon_fence *(*blit)(struct radeon_device *rdev, 1898 uint64_t src_offset, 1899 uint64_t dst_offset, 1900 unsigned num_gpu_pages, 1901 struct dma_resv *resv); 1902 u32 blit_ring_index; 1903 struct radeon_fence *(*dma)(struct radeon_device *rdev, 1904 uint64_t src_offset, 1905 uint64_t dst_offset, 1906 unsigned num_gpu_pages, 1907 struct dma_resv *resv); 1908 u32 dma_ring_index; 1909 /* method used for bo copy */ 1910 struct radeon_fence *(*copy)(struct radeon_device *rdev, 1911 uint64_t src_offset, 1912 uint64_t dst_offset, 1913 unsigned num_gpu_pages, 1914 struct dma_resv *resv); 1915 /* ring used for bo copies */ 1916 u32 copy_ring_index; 1917 } copy; 1918 /* surfaces */ 1919 struct { 1920 int (*set_reg)(struct radeon_device *rdev, int reg, 1921 uint32_t tiling_flags, uint32_t pitch, 1922 uint32_t offset, uint32_t obj_size); 1923 void (*clear_reg)(struct radeon_device *rdev, int reg); 1924 } surface; 1925 /* hotplug detect */ 1926 struct { 1927 void (*init)(struct radeon_device *rdev); 1928 void (*fini)(struct radeon_device *rdev); 1929 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1930 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1931 } hpd; 1932 /* static power management */ 1933 struct { 1934 void (*misc)(struct radeon_device *rdev); 1935 void (*prepare)(struct radeon_device *rdev); 1936 void (*finish)(struct radeon_device *rdev); 1937 void (*init_profile)(struct radeon_device *rdev); 1938 void (*get_dynpm_state)(struct radeon_device *rdev); 1939 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1940 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1941 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1942 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1943 int (*get_pcie_lanes)(struct radeon_device *rdev); 1944 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1945 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1946 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1947 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1948 int (*get_temperature)(struct radeon_device *rdev); 1949 } pm; 1950 /* dynamic power management */ 1951 struct { 1952 int (*init)(struct radeon_device *rdev); 1953 void (*setup_asic)(struct radeon_device *rdev); 1954 int (*enable)(struct radeon_device *rdev); 1955 int (*late_enable)(struct radeon_device *rdev); 1956 void (*disable)(struct radeon_device *rdev); 1957 int (*pre_set_power_state)(struct radeon_device *rdev); 1958 int (*set_power_state)(struct radeon_device *rdev); 1959 void (*post_set_power_state)(struct radeon_device *rdev); 1960 void (*display_configuration_changed)(struct radeon_device *rdev); 1961 void (*fini)(struct radeon_device *rdev); 1962 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1963 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1964 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1965 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1966 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 1967 bool (*vblank_too_short)(struct radeon_device *rdev); 1968 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 1969 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 1970 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode); 1971 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev); 1972 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed); 1973 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed); 1974 u32 (*get_current_sclk)(struct radeon_device *rdev); 1975 u32 (*get_current_mclk)(struct radeon_device *rdev); 1976 u16 (*get_current_vddc)(struct radeon_device *rdev); 1977 } dpm; 1978 /* pageflipping */ 1979 struct { 1980 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async); 1981 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 1982 } pflip; 1983 }; 1984 1985 /* 1986 * Asic structures 1987 */ 1988 struct r100_asic { 1989 const unsigned *reg_safe_bm; 1990 unsigned reg_safe_bm_size; 1991 u32 hdp_cntl; 1992 }; 1993 1994 struct r300_asic { 1995 const unsigned *reg_safe_bm; 1996 unsigned reg_safe_bm_size; 1997 u32 resync_scratch; 1998 u32 hdp_cntl; 1999 }; 2000 2001 struct r600_asic { 2002 unsigned max_pipes; 2003 unsigned max_tile_pipes; 2004 unsigned max_simds; 2005 unsigned max_backends; 2006 unsigned max_gprs; 2007 unsigned max_threads; 2008 unsigned max_stack_entries; 2009 unsigned max_hw_contexts; 2010 unsigned max_gs_threads; 2011 unsigned sx_max_export_size; 2012 unsigned sx_max_export_pos_size; 2013 unsigned sx_max_export_smx_size; 2014 unsigned sq_num_cf_insts; 2015 unsigned tiling_nbanks; 2016 unsigned tiling_npipes; 2017 unsigned tiling_group_size; 2018 unsigned tile_config; 2019 unsigned backend_map; 2020 unsigned active_simds; 2021 }; 2022 2023 struct rv770_asic { 2024 unsigned max_pipes; 2025 unsigned max_tile_pipes; 2026 unsigned max_simds; 2027 unsigned max_backends; 2028 unsigned max_gprs; 2029 unsigned max_threads; 2030 unsigned max_stack_entries; 2031 unsigned max_hw_contexts; 2032 unsigned max_gs_threads; 2033 unsigned sx_max_export_size; 2034 unsigned sx_max_export_pos_size; 2035 unsigned sx_max_export_smx_size; 2036 unsigned sq_num_cf_insts; 2037 unsigned sx_num_of_sets; 2038 unsigned sc_prim_fifo_size; 2039 unsigned sc_hiz_tile_fifo_size; 2040 unsigned sc_earlyz_tile_fifo_fize; 2041 unsigned tiling_nbanks; 2042 unsigned tiling_npipes; 2043 unsigned tiling_group_size; 2044 unsigned tile_config; 2045 unsigned backend_map; 2046 unsigned active_simds; 2047 }; 2048 2049 struct evergreen_asic { 2050 unsigned num_ses; 2051 unsigned max_pipes; 2052 unsigned max_tile_pipes; 2053 unsigned max_simds; 2054 unsigned max_backends; 2055 unsigned max_gprs; 2056 unsigned max_threads; 2057 unsigned max_stack_entries; 2058 unsigned max_hw_contexts; 2059 unsigned max_gs_threads; 2060 unsigned sx_max_export_size; 2061 unsigned sx_max_export_pos_size; 2062 unsigned sx_max_export_smx_size; 2063 unsigned sq_num_cf_insts; 2064 unsigned sx_num_of_sets; 2065 unsigned sc_prim_fifo_size; 2066 unsigned sc_hiz_tile_fifo_size; 2067 unsigned sc_earlyz_tile_fifo_size; 2068 unsigned tiling_nbanks; 2069 unsigned tiling_npipes; 2070 unsigned tiling_group_size; 2071 unsigned tile_config; 2072 unsigned backend_map; 2073 unsigned active_simds; 2074 }; 2075 2076 struct cayman_asic { 2077 unsigned max_shader_engines; 2078 unsigned max_pipes_per_simd; 2079 unsigned max_tile_pipes; 2080 unsigned max_simds_per_se; 2081 unsigned max_backends_per_se; 2082 unsigned max_texture_channel_caches; 2083 unsigned max_gprs; 2084 unsigned max_threads; 2085 unsigned max_gs_threads; 2086 unsigned max_stack_entries; 2087 unsigned sx_num_of_sets; 2088 unsigned sx_max_export_size; 2089 unsigned sx_max_export_pos_size; 2090 unsigned sx_max_export_smx_size; 2091 unsigned max_hw_contexts; 2092 unsigned sq_num_cf_insts; 2093 unsigned sc_prim_fifo_size; 2094 unsigned sc_hiz_tile_fifo_size; 2095 unsigned sc_earlyz_tile_fifo_size; 2096 2097 unsigned num_shader_engines; 2098 unsigned num_shader_pipes_per_simd; 2099 unsigned num_tile_pipes; 2100 unsigned num_simds_per_se; 2101 unsigned num_backends_per_se; 2102 unsigned backend_disable_mask_per_asic; 2103 unsigned backend_map; 2104 unsigned num_texture_channel_caches; 2105 unsigned mem_max_burst_length_bytes; 2106 unsigned mem_row_size_in_kb; 2107 unsigned shader_engine_tile_size; 2108 unsigned num_gpus; 2109 unsigned multi_gpu_tile_size; 2110 2111 unsigned tile_config; 2112 unsigned active_simds; 2113 }; 2114 2115 struct si_asic { 2116 unsigned max_shader_engines; 2117 unsigned max_tile_pipes; 2118 unsigned max_cu_per_sh; 2119 unsigned max_sh_per_se; 2120 unsigned max_backends_per_se; 2121 unsigned max_texture_channel_caches; 2122 unsigned max_gprs; 2123 unsigned max_gs_threads; 2124 unsigned max_hw_contexts; 2125 unsigned sc_prim_fifo_size_frontend; 2126 unsigned sc_prim_fifo_size_backend; 2127 unsigned sc_hiz_tile_fifo_size; 2128 unsigned sc_earlyz_tile_fifo_size; 2129 2130 unsigned num_tile_pipes; 2131 unsigned backend_enable_mask; 2132 unsigned backend_disable_mask_per_asic; 2133 unsigned backend_map; 2134 unsigned num_texture_channel_caches; 2135 unsigned mem_max_burst_length_bytes; 2136 unsigned mem_row_size_in_kb; 2137 unsigned shader_engine_tile_size; 2138 unsigned num_gpus; 2139 unsigned multi_gpu_tile_size; 2140 2141 unsigned tile_config; 2142 uint32_t tile_mode_array[32]; 2143 uint32_t active_cus; 2144 }; 2145 2146 struct cik_asic { 2147 unsigned max_shader_engines; 2148 unsigned max_tile_pipes; 2149 unsigned max_cu_per_sh; 2150 unsigned max_sh_per_se; 2151 unsigned max_backends_per_se; 2152 unsigned max_texture_channel_caches; 2153 unsigned max_gprs; 2154 unsigned max_gs_threads; 2155 unsigned max_hw_contexts; 2156 unsigned sc_prim_fifo_size_frontend; 2157 unsigned sc_prim_fifo_size_backend; 2158 unsigned sc_hiz_tile_fifo_size; 2159 unsigned sc_earlyz_tile_fifo_size; 2160 2161 unsigned num_tile_pipes; 2162 unsigned backend_enable_mask; 2163 unsigned backend_disable_mask_per_asic; 2164 unsigned backend_map; 2165 unsigned num_texture_channel_caches; 2166 unsigned mem_max_burst_length_bytes; 2167 unsigned mem_row_size_in_kb; 2168 unsigned shader_engine_tile_size; 2169 unsigned num_gpus; 2170 unsigned multi_gpu_tile_size; 2171 2172 unsigned tile_config; 2173 uint32_t tile_mode_array[32]; 2174 uint32_t macrotile_mode_array[16]; 2175 uint32_t active_cus; 2176 }; 2177 2178 union radeon_asic_config { 2179 struct r300_asic r300; 2180 struct r100_asic r100; 2181 struct r600_asic r600; 2182 struct rv770_asic rv770; 2183 struct evergreen_asic evergreen; 2184 struct cayman_asic cayman; 2185 struct si_asic si; 2186 struct cik_asic cik; 2187 }; 2188 2189 /* 2190 * asic initizalization from radeon_asic.c 2191 */ 2192 void radeon_agp_disable(struct radeon_device *rdev); 2193 int radeon_asic_init(struct radeon_device *rdev); 2194 2195 2196 /* 2197 * IOCTL. 2198 */ 2199 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2200 struct drm_file *filp); 2201 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2202 struct drm_file *filp); 2203 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, 2204 struct drm_file *filp); 2205 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2206 struct drm_file *file_priv); 2207 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2208 struct drm_file *file_priv); 2209 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2210 struct drm_file *file_priv); 2211 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2212 struct drm_file *file_priv); 2213 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2214 struct drm_file *filp); 2215 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2216 struct drm_file *filp); 2217 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2218 struct drm_file *filp); 2219 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2220 struct drm_file *filp); 2221 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2222 struct drm_file *filp); 2223 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2224 struct drm_file *filp); 2225 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2226 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2227 struct drm_file *filp); 2228 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2229 struct drm_file *filp); 2230 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2231 2232 /* VRAM scratch page for HDP bug, default vram page */ 2233 struct r600_vram_scratch { 2234 struct radeon_bo *robj; 2235 volatile uint32_t *ptr; 2236 u64 gpu_addr; 2237 }; 2238 2239 /* 2240 * ACPI 2241 */ 2242 struct radeon_atif_notification_cfg { 2243 bool enabled; 2244 int command_code; 2245 }; 2246 2247 struct radeon_atif_notifications { 2248 bool display_switch; 2249 bool expansion_mode_change; 2250 bool thermal_state; 2251 bool forced_power_state; 2252 bool system_power_state; 2253 bool display_conf_change; 2254 bool px_gfx_switch; 2255 bool brightness_change; 2256 bool dgpu_display_event; 2257 }; 2258 2259 struct radeon_atif_functions { 2260 bool system_params; 2261 bool sbios_requests; 2262 bool select_active_disp; 2263 bool lid_state; 2264 bool get_tv_standard; 2265 bool set_tv_standard; 2266 bool get_panel_expansion_mode; 2267 bool set_panel_expansion_mode; 2268 bool temperature_change; 2269 bool graphics_device_types; 2270 }; 2271 2272 struct radeon_atif { 2273 struct radeon_atif_notifications notifications; 2274 struct radeon_atif_functions functions; 2275 struct radeon_atif_notification_cfg notification_cfg; 2276 struct radeon_encoder *encoder_for_bl; 2277 }; 2278 2279 struct radeon_atcs_functions { 2280 bool get_ext_state; 2281 bool pcie_perf_req; 2282 bool pcie_dev_rdy; 2283 bool pcie_bus_width; 2284 }; 2285 2286 struct radeon_atcs { 2287 struct radeon_atcs_functions functions; 2288 }; 2289 2290 /* 2291 * Core structure, functions and helpers. 2292 */ 2293 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2294 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2295 2296 struct radeon_device { 2297 struct device *dev; 2298 struct drm_device *ddev; 2299 struct pci_dev *pdev; 2300 #ifdef __alpha__ 2301 struct pci_controller *hose; 2302 #endif 2303 struct rw_semaphore exclusive_lock; 2304 /* ASIC */ 2305 union radeon_asic_config config; 2306 enum radeon_family family; 2307 unsigned long flags; 2308 int usec_timeout; 2309 enum radeon_pll_errata pll_errata; 2310 int num_gb_pipes; 2311 int num_z_pipes; 2312 int disp_priority; 2313 /* BIOS */ 2314 uint8_t *bios; 2315 bool is_atom_bios; 2316 uint16_t bios_header_start; 2317 struct radeon_bo *stolen_vga_memory; 2318 /* Register mmio */ 2319 resource_size_t rmmio_base; 2320 resource_size_t rmmio_size; 2321 /* protects concurrent MM_INDEX/DATA based register access */ 2322 spinlock_t mmio_idx_lock; 2323 /* protects concurrent SMC based register access */ 2324 spinlock_t smc_idx_lock; 2325 /* protects concurrent PLL register access */ 2326 spinlock_t pll_idx_lock; 2327 /* protects concurrent MC register access */ 2328 spinlock_t mc_idx_lock; 2329 /* protects concurrent PCIE register access */ 2330 spinlock_t pcie_idx_lock; 2331 /* protects concurrent PCIE_PORT register access */ 2332 spinlock_t pciep_idx_lock; 2333 /* protects concurrent PIF register access */ 2334 spinlock_t pif_idx_lock; 2335 /* protects concurrent CG register access */ 2336 spinlock_t cg_idx_lock; 2337 /* protects concurrent UVD register access */ 2338 spinlock_t uvd_idx_lock; 2339 /* protects concurrent RCU register access */ 2340 spinlock_t rcu_idx_lock; 2341 /* protects concurrent DIDT register access */ 2342 spinlock_t didt_idx_lock; 2343 /* protects concurrent ENDPOINT (audio) register access */ 2344 spinlock_t end_idx_lock; 2345 void __iomem *rmmio; 2346 radeon_rreg_t mc_rreg; 2347 radeon_wreg_t mc_wreg; 2348 radeon_rreg_t pll_rreg; 2349 radeon_wreg_t pll_wreg; 2350 uint32_t pcie_reg_mask; 2351 radeon_rreg_t pciep_rreg; 2352 radeon_wreg_t pciep_wreg; 2353 /* io port */ 2354 void __iomem *rio_mem; 2355 resource_size_t rio_mem_size; 2356 struct radeon_clock clock; 2357 struct radeon_mc mc; 2358 struct radeon_gart gart; 2359 struct radeon_mode_info mode_info; 2360 struct radeon_scratch scratch; 2361 struct radeon_doorbell doorbell; 2362 struct radeon_mman mman; 2363 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2364 wait_queue_head_t fence_queue; 2365 u64 fence_context; 2366 struct mutex ring_lock; 2367 struct radeon_ring ring[RADEON_NUM_RINGS]; 2368 bool ib_pool_ready; 2369 struct radeon_sa_manager ring_tmp_bo; 2370 struct radeon_irq irq; 2371 struct radeon_asic *asic; 2372 struct radeon_gem gem; 2373 struct radeon_pm pm; 2374 struct radeon_uvd uvd; 2375 struct radeon_vce vce; 2376 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2377 struct radeon_wb wb; 2378 struct radeon_dummy_page dummy_page; 2379 bool shutdown; 2380 bool need_swiotlb; 2381 bool accel_working; 2382 bool fastfb_working; /* IGP feature*/ 2383 bool needs_reset, in_reset; 2384 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2385 const struct firmware *me_fw; /* all family ME firmware */ 2386 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2387 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2388 const struct firmware *mc_fw; /* NI MC firmware */ 2389 const struct firmware *ce_fw; /* SI CE firmware */ 2390 const struct firmware *mec_fw; /* CIK MEC firmware */ 2391 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2392 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2393 const struct firmware *smc_fw; /* SMC firmware */ 2394 const struct firmware *uvd_fw; /* UVD firmware */ 2395 const struct firmware *vce_fw; /* VCE firmware */ 2396 bool new_fw; 2397 struct r600_vram_scratch vram_scratch; 2398 int msi_enabled; /* msi enabled */ 2399 struct r600_ih ih; /* r6/700 interrupt ring */ 2400 struct radeon_rlc rlc; 2401 struct radeon_mec mec; 2402 struct delayed_work hotplug_work; 2403 struct work_struct dp_work; 2404 struct work_struct audio_work; 2405 int num_crtc; /* number of crtcs */ 2406 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2407 bool has_uvd; 2408 bool has_vce; 2409 struct r600_audio audio; /* audio stuff */ 2410 struct notifier_block acpi_nb; 2411 /* only one userspace can use Hyperz features or CMASK at a time */ 2412 struct drm_file *hyperz_filp; 2413 struct drm_file *cmask_filp; 2414 /* i2c buses */ 2415 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2416 /* virtual memory */ 2417 struct radeon_vm_manager vm_manager; 2418 struct mutex gpu_clock_mutex; 2419 /* memory stats */ 2420 atomic64_t vram_usage; 2421 atomic64_t gtt_usage; 2422 atomic64_t num_bytes_moved; 2423 atomic_t gpu_reset_counter; 2424 /* ACPI interface */ 2425 struct radeon_atif atif; 2426 struct radeon_atcs atcs; 2427 /* srbm instance registers */ 2428 struct mutex srbm_mutex; 2429 /* clock, powergating flags */ 2430 u32 cg_flags; 2431 u32 pg_flags; 2432 2433 struct dev_pm_domain vga_pm_domain; 2434 bool have_disp_power_ref; 2435 u32 px_quirk_flags; 2436 2437 /* tracking pinned memory */ 2438 u64 vram_pin_size; 2439 u64 gart_pin_size; 2440 }; 2441 2442 bool radeon_is_px(struct drm_device *dev); 2443 int radeon_device_init(struct radeon_device *rdev, 2444 struct drm_device *ddev, 2445 struct pci_dev *pdev, 2446 uint32_t flags); 2447 void radeon_device_fini(struct radeon_device *rdev); 2448 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2449 2450 #define RADEON_MIN_MMIO_SIZE 0x10000 2451 2452 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg); 2453 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2454 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2455 bool always_indirect) 2456 { 2457 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ 2458 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2459 return readl(((void __iomem *)rdev->rmmio) + reg); 2460 else 2461 return r100_mm_rreg_slow(rdev, reg); 2462 } 2463 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2464 bool always_indirect) 2465 { 2466 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2467 writel(v, ((void __iomem *)rdev->rmmio) + reg); 2468 else 2469 r100_mm_wreg_slow(rdev, reg, v); 2470 } 2471 2472 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2473 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2474 2475 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2476 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2477 2478 /* 2479 * Cast helper 2480 */ 2481 extern const struct dma_fence_ops radeon_fence_ops; 2482 2483 static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f) 2484 { 2485 struct radeon_fence *__f = container_of(f, struct radeon_fence, base); 2486 2487 if (__f->base.ops == &radeon_fence_ops) 2488 return __f; 2489 2490 return NULL; 2491 } 2492 2493 /* 2494 * Registers read & write functions. 2495 */ 2496 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 2497 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 2498 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 2499 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 2500 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2501 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2502 #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \ 2503 r100_mm_rreg(rdev, (reg), false)) 2504 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2505 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2506 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2507 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2508 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2509 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2510 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2511 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2512 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2513 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2514 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2515 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2516 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2517 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2518 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2519 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2520 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2521 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2522 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2523 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2524 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2525 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2526 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2527 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2528 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2529 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2530 #define WREG32_P(reg, val, mask) \ 2531 do { \ 2532 uint32_t tmp_ = RREG32(reg); \ 2533 tmp_ &= (mask); \ 2534 tmp_ |= ((val) & ~(mask)); \ 2535 WREG32(reg, tmp_); \ 2536 } while (0) 2537 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2538 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2539 #define WREG32_PLL_P(reg, val, mask) \ 2540 do { \ 2541 uint32_t tmp_ = RREG32_PLL(reg); \ 2542 tmp_ &= (mask); \ 2543 tmp_ |= ((val) & ~(mask)); \ 2544 WREG32_PLL(reg, tmp_); \ 2545 } while (0) 2546 #define WREG32_SMC_P(reg, val, mask) \ 2547 do { \ 2548 uint32_t tmp_ = RREG32_SMC(reg); \ 2549 tmp_ &= (mask); \ 2550 tmp_ |= ((val) & ~(mask)); \ 2551 WREG32_SMC(reg, tmp_); \ 2552 } while (0) 2553 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2554 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2555 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2556 2557 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2558 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2559 2560 /* 2561 * Indirect registers accessors. 2562 * They used to be inlined, but this increases code size by ~65 kbytes. 2563 * Since each performs a pair of MMIO ops 2564 * within a spin_lock_irqsave/spin_unlock_irqrestore region, 2565 * the cost of call+ret is almost negligible. MMIO and locking 2566 * costs several dozens of cycles each at best, call+ret is ~5 cycles. 2567 */ 2568 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); 2569 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2570 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg); 2571 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2572 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg); 2573 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2574 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg); 2575 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2576 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg); 2577 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2578 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg); 2579 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2580 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg); 2581 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2582 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg); 2583 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2584 2585 void r100_pll_errata_after_index(struct radeon_device *rdev); 2586 2587 2588 /* 2589 * ASICs helpers. 2590 */ 2591 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2592 (rdev->pdev->device == 0x5969)) 2593 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2594 (rdev->family == CHIP_RV200) || \ 2595 (rdev->family == CHIP_RS100) || \ 2596 (rdev->family == CHIP_RS200) || \ 2597 (rdev->family == CHIP_RV250) || \ 2598 (rdev->family == CHIP_RV280) || \ 2599 (rdev->family == CHIP_RS300)) 2600 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2601 (rdev->family == CHIP_RV350) || \ 2602 (rdev->family == CHIP_R350) || \ 2603 (rdev->family == CHIP_RV380) || \ 2604 (rdev->family == CHIP_R420) || \ 2605 (rdev->family == CHIP_R423) || \ 2606 (rdev->family == CHIP_RV410) || \ 2607 (rdev->family == CHIP_RS400) || \ 2608 (rdev->family == CHIP_RS480)) 2609 #define ASIC_IS_X2(rdev) ((rdev->pdev->device == 0x9441) || \ 2610 (rdev->pdev->device == 0x9443) || \ 2611 (rdev->pdev->device == 0x944B) || \ 2612 (rdev->pdev->device == 0x9506) || \ 2613 (rdev->pdev->device == 0x9509) || \ 2614 (rdev->pdev->device == 0x950F) || \ 2615 (rdev->pdev->device == 0x689C) || \ 2616 (rdev->pdev->device == 0x689D)) 2617 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2618 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2619 (rdev->family == CHIP_RS690) || \ 2620 (rdev->family == CHIP_RS740) || \ 2621 (rdev->family >= CHIP_R600)) 2622 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2623 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2624 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2625 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2626 (rdev->flags & RADEON_IS_IGP)) 2627 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2628 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2629 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2630 (rdev->flags & RADEON_IS_IGP)) 2631 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2632 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2633 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2634 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2635 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2636 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2637 (rdev->family == CHIP_MULLINS)) 2638 2639 #define ASIC_IS_LOMBOK(rdev) ((rdev->pdev->device == 0x6849) || \ 2640 (rdev->pdev->device == 0x6850) || \ 2641 (rdev->pdev->device == 0x6858) || \ 2642 (rdev->pdev->device == 0x6859) || \ 2643 (rdev->pdev->device == 0x6840) || \ 2644 (rdev->pdev->device == 0x6841) || \ 2645 (rdev->pdev->device == 0x6842) || \ 2646 (rdev->pdev->device == 0x6843)) 2647 2648 /* 2649 * BIOS helpers. 2650 */ 2651 #define RBIOS8(i) (rdev->bios[i]) 2652 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2653 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2654 2655 int radeon_combios_init(struct radeon_device *rdev); 2656 void radeon_combios_fini(struct radeon_device *rdev); 2657 int radeon_atombios_init(struct radeon_device *rdev); 2658 void radeon_atombios_fini(struct radeon_device *rdev); 2659 2660 2661 /* 2662 * RING helpers. 2663 */ 2664 2665 /** 2666 * radeon_ring_write - write a value to the ring 2667 * 2668 * @ring: radeon_ring structure holding ring information 2669 * @v: dword (dw) value to write 2670 * 2671 * Write a value to the requested ring buffer (all asics). 2672 */ 2673 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2674 { 2675 if (ring->count_dw <= 0) 2676 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2677 2678 ring->ring[ring->wptr++] = v; 2679 ring->wptr &= ring->ptr_mask; 2680 ring->count_dw--; 2681 ring->ring_free_dw--; 2682 } 2683 2684 /* 2685 * ASICs macro. 2686 */ 2687 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2688 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2689 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2690 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2691 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2692 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2693 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false) 2694 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2695 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f)) 2696 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e)) 2697 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2698 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2699 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2700 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2701 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2702 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2703 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2704 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2705 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2706 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2707 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2708 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2709 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr)) 2710 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2711 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2712 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2713 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2714 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2715 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2716 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2717 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2718 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2719 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2720 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2721 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2722 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) 2723 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) 2724 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) 2725 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2726 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2727 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2728 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2729 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2730 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2731 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2732 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2733 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2734 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2735 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2736 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2737 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2738 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2739 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2740 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2741 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2742 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2743 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2744 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2745 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2746 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2747 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2748 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2749 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2750 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2751 #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async)) 2752 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2753 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2754 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2755 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2756 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2757 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v)) 2758 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2759 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2760 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2761 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2762 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2763 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2764 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2765 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2766 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2767 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2768 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2769 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2770 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2771 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2772 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2773 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2774 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2775 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2776 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev)) 2777 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev)) 2778 2779 /* Common functions */ 2780 /* AGP */ 2781 extern int radeon_gpu_reset(struct radeon_device *rdev); 2782 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2783 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2784 extern void radeon_agp_disable(struct radeon_device *rdev); 2785 extern int radeon_modeset_init(struct radeon_device *rdev); 2786 extern void radeon_modeset_fini(struct radeon_device *rdev); 2787 extern bool radeon_card_posted(struct radeon_device *rdev); 2788 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2789 extern void radeon_update_display_priority(struct radeon_device *rdev); 2790 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2791 extern void radeon_scratch_init(struct radeon_device *rdev); 2792 extern void radeon_wb_fini(struct radeon_device *rdev); 2793 extern int radeon_wb_init(struct radeon_device *rdev); 2794 extern void radeon_wb_disable(struct radeon_device *rdev); 2795 extern void radeon_surface_init(struct radeon_device *rdev); 2796 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2797 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 2798 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 2799 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2800 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2801 extern int radeon_ttm_tt_set_userptr(struct radeon_device *rdev, 2802 struct ttm_tt *ttm, uint64_t addr, 2803 uint32_t flags); 2804 extern bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev, struct ttm_tt *ttm); 2805 extern bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev, struct ttm_tt *ttm); 2806 bool radeon_ttm_tt_is_bound(struct ttm_bo_device *bdev, struct ttm_tt *ttm); 2807 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2808 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2809 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2810 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, 2811 bool fbcon, bool freeze); 2812 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2813 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2814 const u32 *registers, 2815 const u32 array_size); 2816 struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev); 2817 2818 /* KMS */ 2819 2820 u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc); 2821 int radeon_enable_vblank_kms(struct drm_crtc *crtc); 2822 void radeon_disable_vblank_kms(struct drm_crtc *crtc); 2823 2824 /* 2825 * vm 2826 */ 2827 int radeon_vm_manager_init(struct radeon_device *rdev); 2828 void radeon_vm_manager_fini(struct radeon_device *rdev); 2829 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2830 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2831 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, 2832 struct radeon_vm *vm, 2833 struct list_head *head); 2834 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2835 struct radeon_vm *vm, int ring); 2836 void radeon_vm_flush(struct radeon_device *rdev, 2837 struct radeon_vm *vm, 2838 int ring, struct radeon_fence *fence); 2839 void radeon_vm_fence(struct radeon_device *rdev, 2840 struct radeon_vm *vm, 2841 struct radeon_fence *fence); 2842 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2843 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2844 struct radeon_vm *vm); 2845 int radeon_vm_clear_freed(struct radeon_device *rdev, 2846 struct radeon_vm *vm); 2847 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2848 struct radeon_vm *vm); 2849 int radeon_vm_bo_update(struct radeon_device *rdev, 2850 struct radeon_bo_va *bo_va, 2851 struct ttm_resource *mem); 2852 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2853 struct radeon_bo *bo); 2854 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2855 struct radeon_bo *bo); 2856 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2857 struct radeon_vm *vm, 2858 struct radeon_bo *bo); 2859 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2860 struct radeon_bo_va *bo_va, 2861 uint64_t offset, 2862 uint32_t flags); 2863 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2864 struct radeon_bo_va *bo_va); 2865 2866 /* audio */ 2867 void r600_audio_update_hdmi(struct work_struct *work); 2868 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2869 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2870 void r600_audio_enable(struct radeon_device *rdev, 2871 struct r600_audio_pin *pin, 2872 u8 enable_mask); 2873 void dce6_audio_enable(struct radeon_device *rdev, 2874 struct r600_audio_pin *pin, 2875 u8 enable_mask); 2876 2877 /* 2878 * R600 vram scratch functions 2879 */ 2880 int r600_vram_scratch_init(struct radeon_device *rdev); 2881 void r600_vram_scratch_fini(struct radeon_device *rdev); 2882 2883 /* 2884 * r600 cs checking helper 2885 */ 2886 unsigned r600_mip_minify(unsigned size, unsigned level); 2887 bool r600_fmt_is_valid_color(u32 format); 2888 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2889 int r600_fmt_get_blocksize(u32 format); 2890 int r600_fmt_get_nblocksx(u32 format, u32 w); 2891 int r600_fmt_get_nblocksy(u32 format, u32 h); 2892 2893 /* 2894 * r600 functions used by radeon_encoder.c 2895 */ 2896 struct radeon_hdmi_acr { 2897 u32 clock; 2898 2899 int n_32khz; 2900 int cts_32khz; 2901 2902 int n_44_1khz; 2903 int cts_44_1khz; 2904 2905 int n_48khz; 2906 int cts_48khz; 2907 2908 }; 2909 2910 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 2911 2912 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2913 u32 tiling_pipe_num, 2914 u32 max_rb_num, 2915 u32 total_max_rb_num, 2916 u32 enabled_rb_mask); 2917 2918 /* 2919 * evergreen functions used by radeon_encoder.c 2920 */ 2921 2922 extern int ni_init_microcode(struct radeon_device *rdev); 2923 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2924 2925 /* radeon_acpi.c */ 2926 #if defined(CONFIG_ACPI) 2927 extern int radeon_acpi_init(struct radeon_device *rdev); 2928 extern void radeon_acpi_fini(struct radeon_device *rdev); 2929 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 2930 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 2931 u8 perf_req, bool advertise); 2932 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 2933 #else 2934 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 2935 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 2936 #endif 2937 2938 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 2939 struct radeon_cs_packet *pkt, 2940 unsigned idx); 2941 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 2942 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 2943 struct radeon_cs_packet *pkt); 2944 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 2945 struct radeon_bo_list **cs_reloc, 2946 int nomm); 2947 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 2948 uint32_t *vline_start_end, 2949 uint32_t *vline_status); 2950 2951 /* interrupt control register helpers */ 2952 void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev, 2953 u32 reg, u32 mask, 2954 bool enable, const char *name, 2955 unsigned n); 2956 2957 #include "radeon_object.h" 2958 2959 #endif 2960