1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 /* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45 /* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63 #include <asm/atomic.h> 64 #include <linux/wait.h> 65 #include <linux/list.h> 66 #include <linux/kref.h> 67 68 #include <ttm/ttm_bo_api.h> 69 #include <ttm/ttm_bo_driver.h> 70 #include <ttm/ttm_placement.h> 71 #include <ttm/ttm_module.h> 72 73 #include "radeon_family.h" 74 #include "radeon_mode.h" 75 #include "radeon_reg.h" 76 77 /* 78 * Modules parameters. 79 */ 80 extern int radeon_no_wb; 81 extern int radeon_modeset; 82 extern int radeon_dynclks; 83 extern int radeon_r4xx_atom; 84 extern int radeon_agpmode; 85 extern int radeon_vram_limit; 86 extern int radeon_gart_size; 87 extern int radeon_benchmarking; 88 extern int radeon_testing; 89 extern int radeon_connector_table; 90 extern int radeon_tv; 91 extern int radeon_new_pll; 92 extern int radeon_audio; 93 94 /* 95 * Copy from radeon_drv.h so we don't have to include both and have conflicting 96 * symbol; 97 */ 98 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 99 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 100 #define RADEON_IB_POOL_SIZE 16 101 #define RADEON_DEBUGFS_MAX_NUM_FILES 32 102 #define RADEONFB_CONN_LIMIT 4 103 #define RADEON_BIOS_NUM_SCRATCH 8 104 105 /* 106 * Errata workarounds. 107 */ 108 enum radeon_pll_errata { 109 CHIP_ERRATA_R300_CG = 0x00000001, 110 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 111 CHIP_ERRATA_PLL_DELAY = 0x00000004 112 }; 113 114 115 struct radeon_device; 116 117 118 /* 119 * BIOS. 120 */ 121 bool radeon_get_bios(struct radeon_device *rdev); 122 123 124 /* 125 * Dummy page 126 */ 127 struct radeon_dummy_page { 128 struct page *page; 129 dma_addr_t addr; 130 }; 131 int radeon_dummy_page_init(struct radeon_device *rdev); 132 void radeon_dummy_page_fini(struct radeon_device *rdev); 133 134 135 /* 136 * Clocks 137 */ 138 struct radeon_clock { 139 struct radeon_pll p1pll; 140 struct radeon_pll p2pll; 141 struct radeon_pll spll; 142 struct radeon_pll mpll; 143 /* 10 Khz units */ 144 uint32_t default_mclk; 145 uint32_t default_sclk; 146 }; 147 148 /* 149 * Power management 150 */ 151 int radeon_pm_init(struct radeon_device *rdev); 152 153 /* 154 * Fences. 155 */ 156 struct radeon_fence_driver { 157 uint32_t scratch_reg; 158 atomic_t seq; 159 uint32_t last_seq; 160 unsigned long count_timeout; 161 wait_queue_head_t queue; 162 rwlock_t lock; 163 struct list_head created; 164 struct list_head emited; 165 struct list_head signaled; 166 bool initialized; 167 }; 168 169 struct radeon_fence { 170 struct radeon_device *rdev; 171 struct kref kref; 172 struct list_head list; 173 /* protected by radeon_fence.lock */ 174 uint32_t seq; 175 unsigned long timeout; 176 bool emited; 177 bool signaled; 178 }; 179 180 int radeon_fence_driver_init(struct radeon_device *rdev); 181 void radeon_fence_driver_fini(struct radeon_device *rdev); 182 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); 183 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); 184 void radeon_fence_process(struct radeon_device *rdev); 185 bool radeon_fence_signaled(struct radeon_fence *fence); 186 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 187 int radeon_fence_wait_next(struct radeon_device *rdev); 188 int radeon_fence_wait_last(struct radeon_device *rdev); 189 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 190 void radeon_fence_unref(struct radeon_fence **fence); 191 192 /* 193 * Tiling registers 194 */ 195 struct radeon_surface_reg { 196 struct radeon_bo *bo; 197 }; 198 199 #define RADEON_GEM_MAX_SURFACES 8 200 201 /* 202 * TTM. 203 */ 204 struct radeon_mman { 205 struct ttm_bo_global_ref bo_global_ref; 206 struct ttm_global_reference mem_global_ref; 207 struct ttm_bo_device bdev; 208 bool mem_global_referenced; 209 bool initialized; 210 }; 211 212 struct radeon_bo { 213 /* Protected by gem.mutex */ 214 struct list_head list; 215 /* Protected by tbo.reserved */ 216 u32 placements[3]; 217 struct ttm_placement placement; 218 struct ttm_buffer_object tbo; 219 struct ttm_bo_kmap_obj kmap; 220 unsigned pin_count; 221 void *kptr; 222 u32 tiling_flags; 223 u32 pitch; 224 int surface_reg; 225 /* Constant after initialization */ 226 struct radeon_device *rdev; 227 struct drm_gem_object *gobj; 228 }; 229 230 struct radeon_bo_list { 231 struct list_head list; 232 struct radeon_bo *bo; 233 uint64_t gpu_offset; 234 unsigned rdomain; 235 unsigned wdomain; 236 u32 tiling_flags; 237 }; 238 239 /* 240 * GEM objects. 241 */ 242 struct radeon_gem { 243 struct mutex mutex; 244 struct list_head objects; 245 }; 246 247 int radeon_gem_init(struct radeon_device *rdev); 248 void radeon_gem_fini(struct radeon_device *rdev); 249 int radeon_gem_object_create(struct radeon_device *rdev, int size, 250 int alignment, int initial_domain, 251 bool discardable, bool kernel, 252 struct drm_gem_object **obj); 253 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, 254 uint64_t *gpu_addr); 255 void radeon_gem_object_unpin(struct drm_gem_object *obj); 256 257 258 /* 259 * GART structures, functions & helpers 260 */ 261 struct radeon_mc; 262 263 struct radeon_gart_table_ram { 264 volatile uint32_t *ptr; 265 }; 266 267 struct radeon_gart_table_vram { 268 struct radeon_bo *robj; 269 volatile uint32_t *ptr; 270 }; 271 272 union radeon_gart_table { 273 struct radeon_gart_table_ram ram; 274 struct radeon_gart_table_vram vram; 275 }; 276 277 #define RADEON_GPU_PAGE_SIZE 4096 278 279 struct radeon_gart { 280 dma_addr_t table_addr; 281 unsigned num_gpu_pages; 282 unsigned num_cpu_pages; 283 unsigned table_size; 284 union radeon_gart_table table; 285 struct page **pages; 286 dma_addr_t *pages_addr; 287 bool ready; 288 }; 289 290 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 291 void radeon_gart_table_ram_free(struct radeon_device *rdev); 292 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 293 void radeon_gart_table_vram_free(struct radeon_device *rdev); 294 int radeon_gart_init(struct radeon_device *rdev); 295 void radeon_gart_fini(struct radeon_device *rdev); 296 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 297 int pages); 298 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 299 int pages, struct page **pagelist); 300 301 302 /* 303 * GPU MC structures, functions & helpers 304 */ 305 struct radeon_mc { 306 resource_size_t aper_size; 307 resource_size_t aper_base; 308 resource_size_t agp_base; 309 /* for some chips with <= 32MB we need to lie 310 * about vram size near mc fb location */ 311 u64 mc_vram_size; 312 u64 gtt_location; 313 u64 gtt_size; 314 u64 gtt_start; 315 u64 gtt_end; 316 u64 vram_location; 317 u64 vram_start; 318 u64 vram_end; 319 unsigned vram_width; 320 u64 real_vram_size; 321 int vram_mtrr; 322 bool vram_is_ddr; 323 bool igp_sideport_enabled; 324 }; 325 326 int radeon_mc_setup(struct radeon_device *rdev); 327 bool radeon_combios_sideport_present(struct radeon_device *rdev); 328 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 329 330 /* 331 * GPU scratch registers structures, functions & helpers 332 */ 333 struct radeon_scratch { 334 unsigned num_reg; 335 bool free[32]; 336 uint32_t reg[32]; 337 }; 338 339 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 340 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 341 342 343 /* 344 * IRQS. 345 */ 346 struct radeon_irq { 347 bool installed; 348 bool sw_int; 349 /* FIXME: use a define max crtc rather than hardcode it */ 350 bool crtc_vblank_int[2]; 351 /* FIXME: use defines for max hpd/dacs */ 352 bool hpd[6]; 353 spinlock_t sw_lock; 354 int sw_refcount; 355 }; 356 357 int radeon_irq_kms_init(struct radeon_device *rdev); 358 void radeon_irq_kms_fini(struct radeon_device *rdev); 359 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev); 360 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev); 361 362 /* 363 * CP & ring. 364 */ 365 struct radeon_ib { 366 struct list_head list; 367 unsigned idx; 368 uint64_t gpu_addr; 369 struct radeon_fence *fence; 370 uint32_t *ptr; 371 uint32_t length_dw; 372 bool free; 373 }; 374 375 /* 376 * locking - 377 * mutex protects scheduled_ibs, ready, alloc_bm 378 */ 379 struct radeon_ib_pool { 380 struct mutex mutex; 381 struct radeon_bo *robj; 382 struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; 383 bool ready; 384 unsigned head_id; 385 }; 386 387 struct radeon_cp { 388 struct radeon_bo *ring_obj; 389 volatile uint32_t *ring; 390 unsigned rptr; 391 unsigned wptr; 392 unsigned wptr_old; 393 unsigned ring_size; 394 unsigned ring_free_dw; 395 int count_dw; 396 uint64_t gpu_addr; 397 uint32_t align_mask; 398 uint32_t ptr_mask; 399 struct mutex mutex; 400 bool ready; 401 }; 402 403 /* 404 * R6xx+ IH ring 405 */ 406 struct r600_ih { 407 struct radeon_bo *ring_obj; 408 volatile uint32_t *ring; 409 unsigned rptr; 410 unsigned wptr; 411 unsigned wptr_old; 412 unsigned ring_size; 413 uint64_t gpu_addr; 414 uint32_t ptr_mask; 415 spinlock_t lock; 416 bool enabled; 417 }; 418 419 struct r600_blit { 420 struct mutex mutex; 421 struct radeon_bo *shader_obj; 422 u64 shader_gpu_addr; 423 u32 vs_offset, ps_offset; 424 u32 state_offset; 425 u32 state_len; 426 u32 vb_used, vb_total; 427 struct radeon_ib *vb_ib; 428 }; 429 430 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); 431 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); 432 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); 433 int radeon_ib_pool_init(struct radeon_device *rdev); 434 void radeon_ib_pool_fini(struct radeon_device *rdev); 435 int radeon_ib_test(struct radeon_device *rdev); 436 /* Ring access between begin & end cannot sleep */ 437 void radeon_ring_free_size(struct radeon_device *rdev); 438 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); 439 void radeon_ring_unlock_commit(struct radeon_device *rdev); 440 void radeon_ring_unlock_undo(struct radeon_device *rdev); 441 int radeon_ring_test(struct radeon_device *rdev); 442 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); 443 void radeon_ring_fini(struct radeon_device *rdev); 444 445 446 /* 447 * CS. 448 */ 449 struct radeon_cs_reloc { 450 struct drm_gem_object *gobj; 451 struct radeon_bo *robj; 452 struct radeon_bo_list lobj; 453 uint32_t handle; 454 uint32_t flags; 455 }; 456 457 struct radeon_cs_chunk { 458 uint32_t chunk_id; 459 uint32_t length_dw; 460 int kpage_idx[2]; 461 uint32_t *kpage[2]; 462 uint32_t *kdata; 463 void __user *user_ptr; 464 int last_copied_page; 465 int last_page_index; 466 }; 467 468 struct radeon_cs_parser { 469 struct device *dev; 470 struct radeon_device *rdev; 471 struct drm_file *filp; 472 /* chunks */ 473 unsigned nchunks; 474 struct radeon_cs_chunk *chunks; 475 uint64_t *chunks_array; 476 /* IB */ 477 unsigned idx; 478 /* relocations */ 479 unsigned nrelocs; 480 struct radeon_cs_reloc *relocs; 481 struct radeon_cs_reloc **relocs_ptr; 482 struct list_head validated; 483 /* indices of various chunks */ 484 int chunk_ib_idx; 485 int chunk_relocs_idx; 486 struct radeon_ib *ib; 487 void *track; 488 unsigned family; 489 int parser_error; 490 }; 491 492 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); 493 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); 494 495 496 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 497 { 498 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 499 u32 pg_idx, pg_offset; 500 u32 idx_value = 0; 501 int new_page; 502 503 pg_idx = (idx * 4) / PAGE_SIZE; 504 pg_offset = (idx * 4) % PAGE_SIZE; 505 506 if (ibc->kpage_idx[0] == pg_idx) 507 return ibc->kpage[0][pg_offset/4]; 508 if (ibc->kpage_idx[1] == pg_idx) 509 return ibc->kpage[1][pg_offset/4]; 510 511 new_page = radeon_cs_update_pages(p, pg_idx); 512 if (new_page < 0) { 513 p->parser_error = new_page; 514 return 0; 515 } 516 517 idx_value = ibc->kpage[new_page][pg_offset/4]; 518 return idx_value; 519 } 520 521 struct radeon_cs_packet { 522 unsigned idx; 523 unsigned type; 524 unsigned reg; 525 unsigned opcode; 526 int count; 527 unsigned one_reg_wr; 528 }; 529 530 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 531 struct radeon_cs_packet *pkt, 532 unsigned idx, unsigned reg); 533 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 534 struct radeon_cs_packet *pkt); 535 536 537 /* 538 * AGP 539 */ 540 int radeon_agp_init(struct radeon_device *rdev); 541 void radeon_agp_resume(struct radeon_device *rdev); 542 void radeon_agp_fini(struct radeon_device *rdev); 543 544 545 /* 546 * Writeback 547 */ 548 struct radeon_wb { 549 struct radeon_bo *wb_obj; 550 volatile uint32_t *wb; 551 uint64_t gpu_addr; 552 }; 553 554 /** 555 * struct radeon_pm - power management datas 556 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 557 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 558 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 559 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 560 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 561 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 562 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 563 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 564 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 565 * @sclk: GPU clock Mhz (core bandwith depends of this clock) 566 * @needed_bandwidth: current bandwidth needs 567 * 568 * It keeps track of various data needed to take powermanagement decision. 569 * Bandwith need is used to determine minimun clock of the GPU and memory. 570 * Equation between gpu/memory clock and available bandwidth is hw dependent 571 * (type of memory, bus size, efficiency, ...) 572 */ 573 struct radeon_pm { 574 fixed20_12 max_bandwidth; 575 fixed20_12 igp_sideport_mclk; 576 fixed20_12 igp_system_mclk; 577 fixed20_12 igp_ht_link_clk; 578 fixed20_12 igp_ht_link_width; 579 fixed20_12 k8_bandwidth; 580 fixed20_12 sideport_bandwidth; 581 fixed20_12 ht_bandwidth; 582 fixed20_12 core_bandwidth; 583 fixed20_12 sclk; 584 fixed20_12 needed_bandwidth; 585 }; 586 587 588 /* 589 * Benchmarking 590 */ 591 void radeon_benchmark(struct radeon_device *rdev); 592 593 594 /* 595 * Testing 596 */ 597 void radeon_test_moves(struct radeon_device *rdev); 598 599 600 /* 601 * Debugfs 602 */ 603 int radeon_debugfs_add_files(struct radeon_device *rdev, 604 struct drm_info_list *files, 605 unsigned nfiles); 606 int radeon_debugfs_fence_init(struct radeon_device *rdev); 607 int r100_debugfs_rbbm_init(struct radeon_device *rdev); 608 int r100_debugfs_cp_init(struct radeon_device *rdev); 609 610 611 /* 612 * ASIC specific functions. 613 */ 614 struct radeon_asic { 615 int (*init)(struct radeon_device *rdev); 616 void (*fini)(struct radeon_device *rdev); 617 int (*resume)(struct radeon_device *rdev); 618 int (*suspend)(struct radeon_device *rdev); 619 void (*vga_set_state)(struct radeon_device *rdev, bool state); 620 int (*gpu_reset)(struct radeon_device *rdev); 621 void (*gart_tlb_flush)(struct radeon_device *rdev); 622 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); 623 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); 624 void (*cp_fini)(struct radeon_device *rdev); 625 void (*cp_disable)(struct radeon_device *rdev); 626 void (*cp_commit)(struct radeon_device *rdev); 627 void (*ring_start)(struct radeon_device *rdev); 628 int (*ring_test)(struct radeon_device *rdev); 629 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 630 int (*irq_set)(struct radeon_device *rdev); 631 int (*irq_process)(struct radeon_device *rdev); 632 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 633 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); 634 int (*cs_parse)(struct radeon_cs_parser *p); 635 int (*copy_blit)(struct radeon_device *rdev, 636 uint64_t src_offset, 637 uint64_t dst_offset, 638 unsigned num_pages, 639 struct radeon_fence *fence); 640 int (*copy_dma)(struct radeon_device *rdev, 641 uint64_t src_offset, 642 uint64_t dst_offset, 643 unsigned num_pages, 644 struct radeon_fence *fence); 645 int (*copy)(struct radeon_device *rdev, 646 uint64_t src_offset, 647 uint64_t dst_offset, 648 unsigned num_pages, 649 struct radeon_fence *fence); 650 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 651 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 652 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 653 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 654 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 655 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 656 int (*set_surface_reg)(struct radeon_device *rdev, int reg, 657 uint32_t tiling_flags, uint32_t pitch, 658 uint32_t offset, uint32_t obj_size); 659 int (*clear_surface_reg)(struct radeon_device *rdev, int reg); 660 void (*bandwidth_update)(struct radeon_device *rdev); 661 void (*hpd_init)(struct radeon_device *rdev); 662 void (*hpd_fini)(struct radeon_device *rdev); 663 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 664 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 665 /* ioctl hw specific callback. Some hw might want to perform special 666 * operation on specific ioctl. For instance on wait idle some hw 667 * might want to perform and HDP flush through MMIO as it seems that 668 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed 669 * through ring. 670 */ 671 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); 672 }; 673 674 /* 675 * Asic structures 676 */ 677 struct r100_asic { 678 const unsigned *reg_safe_bm; 679 unsigned reg_safe_bm_size; 680 u32 hdp_cntl; 681 }; 682 683 struct r300_asic { 684 const unsigned *reg_safe_bm; 685 unsigned reg_safe_bm_size; 686 u32 resync_scratch; 687 u32 hdp_cntl; 688 }; 689 690 struct r600_asic { 691 unsigned max_pipes; 692 unsigned max_tile_pipes; 693 unsigned max_simds; 694 unsigned max_backends; 695 unsigned max_gprs; 696 unsigned max_threads; 697 unsigned max_stack_entries; 698 unsigned max_hw_contexts; 699 unsigned max_gs_threads; 700 unsigned sx_max_export_size; 701 unsigned sx_max_export_pos_size; 702 unsigned sx_max_export_smx_size; 703 unsigned sq_num_cf_insts; 704 }; 705 706 struct rv770_asic { 707 unsigned max_pipes; 708 unsigned max_tile_pipes; 709 unsigned max_simds; 710 unsigned max_backends; 711 unsigned max_gprs; 712 unsigned max_threads; 713 unsigned max_stack_entries; 714 unsigned max_hw_contexts; 715 unsigned max_gs_threads; 716 unsigned sx_max_export_size; 717 unsigned sx_max_export_pos_size; 718 unsigned sx_max_export_smx_size; 719 unsigned sq_num_cf_insts; 720 unsigned sx_num_of_sets; 721 unsigned sc_prim_fifo_size; 722 unsigned sc_hiz_tile_fifo_size; 723 unsigned sc_earlyz_tile_fifo_fize; 724 }; 725 726 union radeon_asic_config { 727 struct r300_asic r300; 728 struct r100_asic r100; 729 struct r600_asic r600; 730 struct rv770_asic rv770; 731 }; 732 733 734 /* 735 * IOCTL. 736 */ 737 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 738 struct drm_file *filp); 739 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 740 struct drm_file *filp); 741 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 742 struct drm_file *file_priv); 743 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 744 struct drm_file *file_priv); 745 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 746 struct drm_file *file_priv); 747 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 748 struct drm_file *file_priv); 749 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 750 struct drm_file *filp); 751 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 752 struct drm_file *filp); 753 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 754 struct drm_file *filp); 755 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 756 struct drm_file *filp); 757 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 758 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 759 struct drm_file *filp); 760 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 761 struct drm_file *filp); 762 763 764 /* 765 * Core structure, functions and helpers. 766 */ 767 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 768 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 769 770 struct radeon_device { 771 struct device *dev; 772 struct drm_device *ddev; 773 struct pci_dev *pdev; 774 /* ASIC */ 775 union radeon_asic_config config; 776 enum radeon_family family; 777 unsigned long flags; 778 int usec_timeout; 779 enum radeon_pll_errata pll_errata; 780 int num_gb_pipes; 781 int num_z_pipes; 782 int disp_priority; 783 /* BIOS */ 784 uint8_t *bios; 785 bool is_atom_bios; 786 uint16_t bios_header_start; 787 struct radeon_bo *stollen_vga_memory; 788 struct fb_info *fbdev_info; 789 struct radeon_bo *fbdev_rbo; 790 struct radeon_framebuffer *fbdev_rfb; 791 /* Register mmio */ 792 resource_size_t rmmio_base; 793 resource_size_t rmmio_size; 794 void *rmmio; 795 radeon_rreg_t mc_rreg; 796 radeon_wreg_t mc_wreg; 797 radeon_rreg_t pll_rreg; 798 radeon_wreg_t pll_wreg; 799 uint32_t pcie_reg_mask; 800 radeon_rreg_t pciep_rreg; 801 radeon_wreg_t pciep_wreg; 802 struct radeon_clock clock; 803 struct radeon_mc mc; 804 struct radeon_gart gart; 805 struct radeon_mode_info mode_info; 806 struct radeon_scratch scratch; 807 struct radeon_mman mman; 808 struct radeon_fence_driver fence_drv; 809 struct radeon_cp cp; 810 struct radeon_ib_pool ib_pool; 811 struct radeon_irq irq; 812 struct radeon_asic *asic; 813 struct radeon_gem gem; 814 struct radeon_pm pm; 815 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 816 struct mutex cs_mutex; 817 struct radeon_wb wb; 818 struct radeon_dummy_page dummy_page; 819 bool gpu_lockup; 820 bool shutdown; 821 bool suspend; 822 bool need_dma32; 823 bool accel_working; 824 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 825 const struct firmware *me_fw; /* all family ME firmware */ 826 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 827 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 828 struct r600_blit r600_blit; 829 int msi_enabled; /* msi enabled */ 830 struct r600_ih ih; /* r6/700 interrupt ring */ 831 struct workqueue_struct *wq; 832 struct work_struct hotplug_work; 833 834 /* audio stuff */ 835 struct timer_list audio_timer; 836 int audio_channels; 837 int audio_rate; 838 int audio_bits_per_sample; 839 uint8_t audio_status_bits; 840 uint8_t audio_category_code; 841 }; 842 843 int radeon_device_init(struct radeon_device *rdev, 844 struct drm_device *ddev, 845 struct pci_dev *pdev, 846 uint32_t flags); 847 void radeon_device_fini(struct radeon_device *rdev); 848 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 849 850 /* r600 blit */ 851 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); 852 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); 853 void r600_kms_blit_copy(struct radeon_device *rdev, 854 u64 src_gpu_addr, u64 dst_gpu_addr, 855 int size_bytes); 856 857 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) 858 { 859 if (reg < rdev->rmmio_size) 860 return readl(((void __iomem *)rdev->rmmio) + reg); 861 else { 862 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 863 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 864 } 865 } 866 867 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 868 { 869 if (reg < rdev->rmmio_size) 870 writel(v, ((void __iomem *)rdev->rmmio) + reg); 871 else { 872 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 873 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 874 } 875 } 876 877 /* 878 * Cast helper 879 */ 880 #define to_radeon_fence(p) ((struct radeon_fence *)(p)) 881 882 /* 883 * Registers read & write functions. 884 */ 885 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) 886 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) 887 #define RREG32(reg) r100_mm_rreg(rdev, (reg)) 888 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) 889 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) 890 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 891 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 892 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 893 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 894 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 895 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 896 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 897 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 898 #define WREG32_P(reg, val, mask) \ 899 do { \ 900 uint32_t tmp_ = RREG32(reg); \ 901 tmp_ &= (mask); \ 902 tmp_ |= ((val) & ~(mask)); \ 903 WREG32(reg, tmp_); \ 904 } while (0) 905 #define WREG32_PLL_P(reg, val, mask) \ 906 do { \ 907 uint32_t tmp_ = RREG32_PLL(reg); \ 908 tmp_ &= (mask); \ 909 tmp_ |= ((val) & ~(mask)); \ 910 WREG32_PLL(reg, tmp_); \ 911 } while (0) 912 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) 913 914 /* 915 * Indirect registers accessor 916 */ 917 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 918 { 919 uint32_t r; 920 921 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 922 r = RREG32(RADEON_PCIE_DATA); 923 return r; 924 } 925 926 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 927 { 928 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 929 WREG32(RADEON_PCIE_DATA, (v)); 930 } 931 932 void r100_pll_errata_after_index(struct radeon_device *rdev); 933 934 935 /* 936 * ASICs helpers. 937 */ 938 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 939 (rdev->pdev->device == 0x5969)) 940 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 941 (rdev->family == CHIP_RV200) || \ 942 (rdev->family == CHIP_RS100) || \ 943 (rdev->family == CHIP_RS200) || \ 944 (rdev->family == CHIP_RV250) || \ 945 (rdev->family == CHIP_RV280) || \ 946 (rdev->family == CHIP_RS300)) 947 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 948 (rdev->family == CHIP_RV350) || \ 949 (rdev->family == CHIP_R350) || \ 950 (rdev->family == CHIP_RV380) || \ 951 (rdev->family == CHIP_R420) || \ 952 (rdev->family == CHIP_R423) || \ 953 (rdev->family == CHIP_RV410) || \ 954 (rdev->family == CHIP_RS400) || \ 955 (rdev->family == CHIP_RS480)) 956 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 957 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 958 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 959 960 961 /* 962 * BIOS helpers. 963 */ 964 #define RBIOS8(i) (rdev->bios[i]) 965 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 966 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 967 968 int radeon_combios_init(struct radeon_device *rdev); 969 void radeon_combios_fini(struct radeon_device *rdev); 970 int radeon_atombios_init(struct radeon_device *rdev); 971 void radeon_atombios_fini(struct radeon_device *rdev); 972 973 974 /* 975 * RING helpers. 976 */ 977 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) 978 { 979 #if DRM_DEBUG_CODE 980 if (rdev->cp.count_dw <= 0) { 981 DRM_ERROR("radeon: writting more dword to ring than expected !\n"); 982 } 983 #endif 984 rdev->cp.ring[rdev->cp.wptr++] = v; 985 rdev->cp.wptr &= rdev->cp.ptr_mask; 986 rdev->cp.count_dw--; 987 rdev->cp.ring_free_dw--; 988 } 989 990 991 /* 992 * ASICs macro. 993 */ 994 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 995 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 996 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 997 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 998 #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) 999 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 1000 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) 1001 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) 1002 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) 1003 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) 1004 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) 1005 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) 1006 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) 1007 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) 1008 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) 1009 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) 1010 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) 1011 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) 1012 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) 1013 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) 1014 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) 1015 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) 1016 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) 1017 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) 1018 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) 1019 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) 1020 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) 1021 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) 1022 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) 1023 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) 1024 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) 1025 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) 1026 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) 1027 1028 /* Common functions */ 1029 /* AGP */ 1030 extern void radeon_agp_disable(struct radeon_device *rdev); 1031 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); 1032 extern int radeon_modeset_init(struct radeon_device *rdev); 1033 extern void radeon_modeset_fini(struct radeon_device *rdev); 1034 extern bool radeon_card_posted(struct radeon_device *rdev); 1035 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 1036 extern int radeon_clocks_init(struct radeon_device *rdev); 1037 extern void radeon_clocks_fini(struct radeon_device *rdev); 1038 extern void radeon_scratch_init(struct radeon_device *rdev); 1039 extern void radeon_surface_init(struct radeon_device *rdev); 1040 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 1041 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 1042 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 1043 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 1044 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 1045 1046 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ 1047 struct r100_mc_save { 1048 u32 GENMO_WT; 1049 u32 CRTC_EXT_CNTL; 1050 u32 CRTC_GEN_CNTL; 1051 u32 CRTC2_GEN_CNTL; 1052 u32 CUR_OFFSET; 1053 u32 CUR2_OFFSET; 1054 }; 1055 extern void r100_cp_disable(struct radeon_device *rdev); 1056 extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 1057 extern void r100_cp_fini(struct radeon_device *rdev); 1058 extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 1059 extern int r100_pci_gart_init(struct radeon_device *rdev); 1060 extern void r100_pci_gart_fini(struct radeon_device *rdev); 1061 extern int r100_pci_gart_enable(struct radeon_device *rdev); 1062 extern void r100_pci_gart_disable(struct radeon_device *rdev); 1063 extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 1064 extern int r100_debugfs_mc_info_init(struct radeon_device *rdev); 1065 extern int r100_gui_wait_for_idle(struct radeon_device *rdev); 1066 extern void r100_ib_fini(struct radeon_device *rdev); 1067 extern int r100_ib_init(struct radeon_device *rdev); 1068 extern void r100_irq_disable(struct radeon_device *rdev); 1069 extern int r100_irq_set(struct radeon_device *rdev); 1070 extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); 1071 extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); 1072 extern void r100_vram_init_sizes(struct radeon_device *rdev); 1073 extern void r100_wb_disable(struct radeon_device *rdev); 1074 extern void r100_wb_fini(struct radeon_device *rdev); 1075 extern int r100_wb_init(struct radeon_device *rdev); 1076 extern void r100_hdp_reset(struct radeon_device *rdev); 1077 extern int r100_rb2d_reset(struct radeon_device *rdev); 1078 extern int r100_cp_reset(struct radeon_device *rdev); 1079 extern void r100_vga_render_disable(struct radeon_device *rdev); 1080 extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 1081 struct radeon_cs_packet *pkt, 1082 struct radeon_bo *robj); 1083 extern int r100_cs_parse_packet0(struct radeon_cs_parser *p, 1084 struct radeon_cs_packet *pkt, 1085 const unsigned *auth, unsigned n, 1086 radeon_packet0_check_t check); 1087 extern int r100_cs_packet_parse(struct radeon_cs_parser *p, 1088 struct radeon_cs_packet *pkt, 1089 unsigned idx); 1090 extern void r100_enable_bm(struct radeon_device *rdev); 1091 extern void r100_set_common_regs(struct radeon_device *rdev); 1092 1093 /* rv200,rv250,rv280 */ 1094 extern void r200_set_safe_registers(struct radeon_device *rdev); 1095 1096 /* r300,r350,rv350,rv370,rv380 */ 1097 extern void r300_set_reg_safe(struct radeon_device *rdev); 1098 extern void r300_mc_program(struct radeon_device *rdev); 1099 extern void r300_vram_info(struct radeon_device *rdev); 1100 extern void r300_clock_startup(struct radeon_device *rdev); 1101 extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 1102 extern int rv370_pcie_gart_init(struct radeon_device *rdev); 1103 extern void rv370_pcie_gart_fini(struct radeon_device *rdev); 1104 extern int rv370_pcie_gart_enable(struct radeon_device *rdev); 1105 extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 1106 1107 /* r420,r423,rv410 */ 1108 extern int r420_mc_init(struct radeon_device *rdev); 1109 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 1110 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 1111 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 1112 extern void r420_pipes_init(struct radeon_device *rdev); 1113 1114 /* rv515 */ 1115 struct rv515_mc_save { 1116 u32 d1vga_control; 1117 u32 d2vga_control; 1118 u32 vga_render_control; 1119 u32 vga_hdp_control; 1120 u32 d1crtc_control; 1121 u32 d2crtc_control; 1122 }; 1123 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 1124 extern void rv515_vga_render_disable(struct radeon_device *rdev); 1125 extern void rv515_set_safe_registers(struct radeon_device *rdev); 1126 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); 1127 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); 1128 extern void rv515_clock_startup(struct radeon_device *rdev); 1129 extern void rv515_debugfs(struct radeon_device *rdev); 1130 extern int rv515_suspend(struct radeon_device *rdev); 1131 1132 /* rs400 */ 1133 extern int rs400_gart_init(struct radeon_device *rdev); 1134 extern int rs400_gart_enable(struct radeon_device *rdev); 1135 extern void rs400_gart_adjust_size(struct radeon_device *rdev); 1136 extern void rs400_gart_disable(struct radeon_device *rdev); 1137 extern void rs400_gart_fini(struct radeon_device *rdev); 1138 1139 /* rs600 */ 1140 extern void rs600_set_safe_registers(struct radeon_device *rdev); 1141 extern int rs600_irq_set(struct radeon_device *rdev); 1142 extern void rs600_irq_disable(struct radeon_device *rdev); 1143 1144 /* rs690, rs740 */ 1145 extern void rs690_line_buffer_adjust(struct radeon_device *rdev, 1146 struct drm_display_mode *mode1, 1147 struct drm_display_mode *mode2); 1148 1149 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ 1150 extern bool r600_card_posted(struct radeon_device *rdev); 1151 extern void r600_cp_stop(struct radeon_device *rdev); 1152 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); 1153 extern int r600_cp_resume(struct radeon_device *rdev); 1154 extern void r600_cp_fini(struct radeon_device *rdev); 1155 extern int r600_count_pipe_bits(uint32_t val); 1156 extern int r600_gart_clear_page(struct radeon_device *rdev, int i); 1157 extern int r600_mc_wait_for_idle(struct radeon_device *rdev); 1158 extern int r600_pcie_gart_init(struct radeon_device *rdev); 1159 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 1160 extern int r600_ib_test(struct radeon_device *rdev); 1161 extern int r600_ring_test(struct radeon_device *rdev); 1162 extern void r600_wb_fini(struct radeon_device *rdev); 1163 extern int r600_wb_enable(struct radeon_device *rdev); 1164 extern void r600_wb_disable(struct radeon_device *rdev); 1165 extern void r600_scratch_init(struct radeon_device *rdev); 1166 extern int r600_blit_init(struct radeon_device *rdev); 1167 extern void r600_blit_fini(struct radeon_device *rdev); 1168 extern int r600_init_microcode(struct radeon_device *rdev); 1169 extern int r600_gpu_reset(struct radeon_device *rdev); 1170 /* r600 irq */ 1171 extern int r600_irq_init(struct radeon_device *rdev); 1172 extern void r600_irq_fini(struct radeon_device *rdev); 1173 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 1174 extern int r600_irq_set(struct radeon_device *rdev); 1175 extern void r600_irq_suspend(struct radeon_device *rdev); 1176 /* r600 audio */ 1177 extern int r600_audio_init(struct radeon_device *rdev); 1178 extern int r600_audio_tmds_index(struct drm_encoder *encoder); 1179 extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock); 1180 extern void r600_audio_fini(struct radeon_device *rdev); 1181 extern void r600_hdmi_init(struct drm_encoder *encoder); 1182 extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable); 1183 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 1184 extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); 1185 extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder, 1186 int channels, 1187 int rate, 1188 int bps, 1189 uint8_t status_bits, 1190 uint8_t category_code); 1191 1192 #include "radeon_object.h" 1193 1194 #endif 1195