1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 /* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45 /* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63 #include <asm/atomic.h> 64 #include <linux/wait.h> 65 #include <linux/list.h> 66 #include <linux/kref.h> 67 68 #include <ttm/ttm_bo_api.h> 69 #include <ttm/ttm_bo_driver.h> 70 #include <ttm/ttm_placement.h> 71 #include <ttm/ttm_module.h> 72 73 #include "radeon_family.h" 74 #include "radeon_mode.h" 75 #include "radeon_reg.h" 76 77 /* 78 * Modules parameters. 79 */ 80 extern int radeon_no_wb; 81 extern int radeon_modeset; 82 extern int radeon_dynclks; 83 extern int radeon_r4xx_atom; 84 extern int radeon_agpmode; 85 extern int radeon_vram_limit; 86 extern int radeon_gart_size; 87 extern int radeon_benchmarking; 88 extern int radeon_testing; 89 extern int radeon_connector_table; 90 extern int radeon_tv; 91 extern int radeon_new_pll; 92 extern int radeon_audio; 93 94 /* 95 * Copy from radeon_drv.h so we don't have to include both and have conflicting 96 * symbol; 97 */ 98 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 99 #define RADEON_IB_POOL_SIZE 16 100 #define RADEON_DEBUGFS_MAX_NUM_FILES 32 101 #define RADEONFB_CONN_LIMIT 4 102 #define RADEON_BIOS_NUM_SCRATCH 8 103 104 /* 105 * Errata workarounds. 106 */ 107 enum radeon_pll_errata { 108 CHIP_ERRATA_R300_CG = 0x00000001, 109 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 110 CHIP_ERRATA_PLL_DELAY = 0x00000004 111 }; 112 113 114 struct radeon_device; 115 116 117 /* 118 * BIOS. 119 */ 120 bool radeon_get_bios(struct radeon_device *rdev); 121 122 123 /* 124 * Dummy page 125 */ 126 struct radeon_dummy_page { 127 struct page *page; 128 dma_addr_t addr; 129 }; 130 int radeon_dummy_page_init(struct radeon_device *rdev); 131 void radeon_dummy_page_fini(struct radeon_device *rdev); 132 133 134 /* 135 * Clocks 136 */ 137 struct radeon_clock { 138 struct radeon_pll p1pll; 139 struct radeon_pll p2pll; 140 struct radeon_pll spll; 141 struct radeon_pll mpll; 142 /* 10 Khz units */ 143 uint32_t default_mclk; 144 uint32_t default_sclk; 145 }; 146 147 /* 148 * Power management 149 */ 150 int radeon_pm_init(struct radeon_device *rdev); 151 152 /* 153 * Fences. 154 */ 155 struct radeon_fence_driver { 156 uint32_t scratch_reg; 157 atomic_t seq; 158 uint32_t last_seq; 159 unsigned long count_timeout; 160 wait_queue_head_t queue; 161 rwlock_t lock; 162 struct list_head created; 163 struct list_head emited; 164 struct list_head signaled; 165 bool initialized; 166 }; 167 168 struct radeon_fence { 169 struct radeon_device *rdev; 170 struct kref kref; 171 struct list_head list; 172 /* protected by radeon_fence.lock */ 173 uint32_t seq; 174 unsigned long timeout; 175 bool emited; 176 bool signaled; 177 }; 178 179 int radeon_fence_driver_init(struct radeon_device *rdev); 180 void radeon_fence_driver_fini(struct radeon_device *rdev); 181 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); 182 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); 183 void radeon_fence_process(struct radeon_device *rdev); 184 bool radeon_fence_signaled(struct radeon_fence *fence); 185 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 186 int radeon_fence_wait_next(struct radeon_device *rdev); 187 int radeon_fence_wait_last(struct radeon_device *rdev); 188 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 189 void radeon_fence_unref(struct radeon_fence **fence); 190 191 /* 192 * Tiling registers 193 */ 194 struct radeon_surface_reg { 195 struct radeon_bo *bo; 196 }; 197 198 #define RADEON_GEM_MAX_SURFACES 8 199 200 /* 201 * TTM. 202 */ 203 struct radeon_mman { 204 struct ttm_bo_global_ref bo_global_ref; 205 struct ttm_global_reference mem_global_ref; 206 struct ttm_bo_device bdev; 207 bool mem_global_referenced; 208 bool initialized; 209 }; 210 211 struct radeon_bo { 212 /* Protected by gem.mutex */ 213 struct list_head list; 214 /* Protected by tbo.reserved */ 215 u32 placements[3]; 216 struct ttm_placement placement; 217 struct ttm_buffer_object tbo; 218 struct ttm_bo_kmap_obj kmap; 219 unsigned pin_count; 220 void *kptr; 221 u32 tiling_flags; 222 u32 pitch; 223 int surface_reg; 224 /* Constant after initialization */ 225 struct radeon_device *rdev; 226 struct drm_gem_object *gobj; 227 }; 228 229 struct radeon_bo_list { 230 struct list_head list; 231 struct radeon_bo *bo; 232 uint64_t gpu_offset; 233 unsigned rdomain; 234 unsigned wdomain; 235 u32 tiling_flags; 236 }; 237 238 /* 239 * GEM objects. 240 */ 241 struct radeon_gem { 242 struct mutex mutex; 243 struct list_head objects; 244 }; 245 246 int radeon_gem_init(struct radeon_device *rdev); 247 void radeon_gem_fini(struct radeon_device *rdev); 248 int radeon_gem_object_create(struct radeon_device *rdev, int size, 249 int alignment, int initial_domain, 250 bool discardable, bool kernel, 251 struct drm_gem_object **obj); 252 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, 253 uint64_t *gpu_addr); 254 void radeon_gem_object_unpin(struct drm_gem_object *obj); 255 256 257 /* 258 * GART structures, functions & helpers 259 */ 260 struct radeon_mc; 261 262 struct radeon_gart_table_ram { 263 volatile uint32_t *ptr; 264 }; 265 266 struct radeon_gart_table_vram { 267 struct radeon_bo *robj; 268 volatile uint32_t *ptr; 269 }; 270 271 union radeon_gart_table { 272 struct radeon_gart_table_ram ram; 273 struct radeon_gart_table_vram vram; 274 }; 275 276 #define RADEON_GPU_PAGE_SIZE 4096 277 278 struct radeon_gart { 279 dma_addr_t table_addr; 280 unsigned num_gpu_pages; 281 unsigned num_cpu_pages; 282 unsigned table_size; 283 union radeon_gart_table table; 284 struct page **pages; 285 dma_addr_t *pages_addr; 286 bool ready; 287 }; 288 289 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 290 void radeon_gart_table_ram_free(struct radeon_device *rdev); 291 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 292 void radeon_gart_table_vram_free(struct radeon_device *rdev); 293 int radeon_gart_init(struct radeon_device *rdev); 294 void radeon_gart_fini(struct radeon_device *rdev); 295 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 296 int pages); 297 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 298 int pages, struct page **pagelist); 299 300 301 /* 302 * GPU MC structures, functions & helpers 303 */ 304 struct radeon_mc { 305 resource_size_t aper_size; 306 resource_size_t aper_base; 307 resource_size_t agp_base; 308 /* for some chips with <= 32MB we need to lie 309 * about vram size near mc fb location */ 310 u64 mc_vram_size; 311 u64 gtt_location; 312 u64 gtt_size; 313 u64 gtt_start; 314 u64 gtt_end; 315 u64 vram_location; 316 u64 vram_start; 317 u64 vram_end; 318 unsigned vram_width; 319 u64 real_vram_size; 320 int vram_mtrr; 321 bool vram_is_ddr; 322 bool igp_sideport_enabled; 323 }; 324 325 int radeon_mc_setup(struct radeon_device *rdev); 326 bool radeon_combios_sideport_present(struct radeon_device *rdev); 327 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 328 329 /* 330 * GPU scratch registers structures, functions & helpers 331 */ 332 struct radeon_scratch { 333 unsigned num_reg; 334 bool free[32]; 335 uint32_t reg[32]; 336 }; 337 338 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 339 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 340 341 342 /* 343 * IRQS. 344 */ 345 struct radeon_irq { 346 bool installed; 347 bool sw_int; 348 /* FIXME: use a define max crtc rather than hardcode it */ 349 bool crtc_vblank_int[2]; 350 /* FIXME: use defines for max hpd/dacs */ 351 bool hpd[6]; 352 spinlock_t sw_lock; 353 int sw_refcount; 354 }; 355 356 int radeon_irq_kms_init(struct radeon_device *rdev); 357 void radeon_irq_kms_fini(struct radeon_device *rdev); 358 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev); 359 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev); 360 361 /* 362 * CP & ring. 363 */ 364 struct radeon_ib { 365 struct list_head list; 366 unsigned long idx; 367 uint64_t gpu_addr; 368 struct radeon_fence *fence; 369 uint32_t *ptr; 370 uint32_t length_dw; 371 }; 372 373 /* 374 * locking - 375 * mutex protects scheduled_ibs, ready, alloc_bm 376 */ 377 struct radeon_ib_pool { 378 struct mutex mutex; 379 struct radeon_bo *robj; 380 struct list_head scheduled_ibs; 381 struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; 382 bool ready; 383 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE); 384 }; 385 386 struct radeon_cp { 387 struct radeon_bo *ring_obj; 388 volatile uint32_t *ring; 389 unsigned rptr; 390 unsigned wptr; 391 unsigned wptr_old; 392 unsigned ring_size; 393 unsigned ring_free_dw; 394 int count_dw; 395 uint64_t gpu_addr; 396 uint32_t align_mask; 397 uint32_t ptr_mask; 398 struct mutex mutex; 399 bool ready; 400 }; 401 402 /* 403 * R6xx+ IH ring 404 */ 405 struct r600_ih { 406 struct radeon_bo *ring_obj; 407 volatile uint32_t *ring; 408 unsigned rptr; 409 unsigned wptr; 410 unsigned wptr_old; 411 unsigned ring_size; 412 uint64_t gpu_addr; 413 uint32_t align_mask; 414 uint32_t ptr_mask; 415 spinlock_t lock; 416 bool enabled; 417 }; 418 419 struct r600_blit { 420 struct radeon_bo *shader_obj; 421 u64 shader_gpu_addr; 422 u32 vs_offset, ps_offset; 423 u32 state_offset; 424 u32 state_len; 425 u32 vb_used, vb_total; 426 struct radeon_ib *vb_ib; 427 }; 428 429 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); 430 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); 431 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); 432 int radeon_ib_pool_init(struct radeon_device *rdev); 433 void radeon_ib_pool_fini(struct radeon_device *rdev); 434 int radeon_ib_test(struct radeon_device *rdev); 435 /* Ring access between begin & end cannot sleep */ 436 void radeon_ring_free_size(struct radeon_device *rdev); 437 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); 438 void radeon_ring_unlock_commit(struct radeon_device *rdev); 439 void radeon_ring_unlock_undo(struct radeon_device *rdev); 440 int radeon_ring_test(struct radeon_device *rdev); 441 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); 442 void radeon_ring_fini(struct radeon_device *rdev); 443 444 445 /* 446 * CS. 447 */ 448 struct radeon_cs_reloc { 449 struct drm_gem_object *gobj; 450 struct radeon_bo *robj; 451 struct radeon_bo_list lobj; 452 uint32_t handle; 453 uint32_t flags; 454 }; 455 456 struct radeon_cs_chunk { 457 uint32_t chunk_id; 458 uint32_t length_dw; 459 int kpage_idx[2]; 460 uint32_t *kpage[2]; 461 uint32_t *kdata; 462 void __user *user_ptr; 463 int last_copied_page; 464 int last_page_index; 465 }; 466 467 struct radeon_cs_parser { 468 struct radeon_device *rdev; 469 struct drm_file *filp; 470 /* chunks */ 471 unsigned nchunks; 472 struct radeon_cs_chunk *chunks; 473 uint64_t *chunks_array; 474 /* IB */ 475 unsigned idx; 476 /* relocations */ 477 unsigned nrelocs; 478 struct radeon_cs_reloc *relocs; 479 struct radeon_cs_reloc **relocs_ptr; 480 struct list_head validated; 481 /* indices of various chunks */ 482 int chunk_ib_idx; 483 int chunk_relocs_idx; 484 struct radeon_ib *ib; 485 void *track; 486 unsigned family; 487 int parser_error; 488 }; 489 490 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); 491 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); 492 493 494 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 495 { 496 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 497 u32 pg_idx, pg_offset; 498 u32 idx_value = 0; 499 int new_page; 500 501 pg_idx = (idx * 4) / PAGE_SIZE; 502 pg_offset = (idx * 4) % PAGE_SIZE; 503 504 if (ibc->kpage_idx[0] == pg_idx) 505 return ibc->kpage[0][pg_offset/4]; 506 if (ibc->kpage_idx[1] == pg_idx) 507 return ibc->kpage[1][pg_offset/4]; 508 509 new_page = radeon_cs_update_pages(p, pg_idx); 510 if (new_page < 0) { 511 p->parser_error = new_page; 512 return 0; 513 } 514 515 idx_value = ibc->kpage[new_page][pg_offset/4]; 516 return idx_value; 517 } 518 519 struct radeon_cs_packet { 520 unsigned idx; 521 unsigned type; 522 unsigned reg; 523 unsigned opcode; 524 int count; 525 unsigned one_reg_wr; 526 }; 527 528 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 529 struct radeon_cs_packet *pkt, 530 unsigned idx, unsigned reg); 531 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 532 struct radeon_cs_packet *pkt); 533 534 535 /* 536 * AGP 537 */ 538 int radeon_agp_init(struct radeon_device *rdev); 539 void radeon_agp_resume(struct radeon_device *rdev); 540 void radeon_agp_fini(struct radeon_device *rdev); 541 542 543 /* 544 * Writeback 545 */ 546 struct radeon_wb { 547 struct radeon_bo *wb_obj; 548 volatile uint32_t *wb; 549 uint64_t gpu_addr; 550 }; 551 552 /** 553 * struct radeon_pm - power management datas 554 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 555 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 556 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 557 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 558 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 559 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 560 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 561 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 562 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 563 * @sclk: GPU clock Mhz (core bandwith depends of this clock) 564 * @needed_bandwidth: current bandwidth needs 565 * 566 * It keeps track of various data needed to take powermanagement decision. 567 * Bandwith need is used to determine minimun clock of the GPU and memory. 568 * Equation between gpu/memory clock and available bandwidth is hw dependent 569 * (type of memory, bus size, efficiency, ...) 570 */ 571 struct radeon_pm { 572 fixed20_12 max_bandwidth; 573 fixed20_12 igp_sideport_mclk; 574 fixed20_12 igp_system_mclk; 575 fixed20_12 igp_ht_link_clk; 576 fixed20_12 igp_ht_link_width; 577 fixed20_12 k8_bandwidth; 578 fixed20_12 sideport_bandwidth; 579 fixed20_12 ht_bandwidth; 580 fixed20_12 core_bandwidth; 581 fixed20_12 sclk; 582 fixed20_12 needed_bandwidth; 583 }; 584 585 586 /* 587 * Benchmarking 588 */ 589 void radeon_benchmark(struct radeon_device *rdev); 590 591 592 /* 593 * Testing 594 */ 595 void radeon_test_moves(struct radeon_device *rdev); 596 597 598 /* 599 * Debugfs 600 */ 601 int radeon_debugfs_add_files(struct radeon_device *rdev, 602 struct drm_info_list *files, 603 unsigned nfiles); 604 int radeon_debugfs_fence_init(struct radeon_device *rdev); 605 int r100_debugfs_rbbm_init(struct radeon_device *rdev); 606 int r100_debugfs_cp_init(struct radeon_device *rdev); 607 608 609 /* 610 * ASIC specific functions. 611 */ 612 struct radeon_asic { 613 int (*init)(struct radeon_device *rdev); 614 void (*fini)(struct radeon_device *rdev); 615 int (*resume)(struct radeon_device *rdev); 616 int (*suspend)(struct radeon_device *rdev); 617 void (*vga_set_state)(struct radeon_device *rdev, bool state); 618 int (*gpu_reset)(struct radeon_device *rdev); 619 void (*gart_tlb_flush)(struct radeon_device *rdev); 620 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); 621 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); 622 void (*cp_fini)(struct radeon_device *rdev); 623 void (*cp_disable)(struct radeon_device *rdev); 624 void (*cp_commit)(struct radeon_device *rdev); 625 void (*ring_start)(struct radeon_device *rdev); 626 int (*ring_test)(struct radeon_device *rdev); 627 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 628 int (*irq_set)(struct radeon_device *rdev); 629 int (*irq_process)(struct radeon_device *rdev); 630 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 631 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); 632 int (*cs_parse)(struct radeon_cs_parser *p); 633 int (*copy_blit)(struct radeon_device *rdev, 634 uint64_t src_offset, 635 uint64_t dst_offset, 636 unsigned num_pages, 637 struct radeon_fence *fence); 638 int (*copy_dma)(struct radeon_device *rdev, 639 uint64_t src_offset, 640 uint64_t dst_offset, 641 unsigned num_pages, 642 struct radeon_fence *fence); 643 int (*copy)(struct radeon_device *rdev, 644 uint64_t src_offset, 645 uint64_t dst_offset, 646 unsigned num_pages, 647 struct radeon_fence *fence); 648 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 649 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 650 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 651 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 652 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 653 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 654 int (*set_surface_reg)(struct radeon_device *rdev, int reg, 655 uint32_t tiling_flags, uint32_t pitch, 656 uint32_t offset, uint32_t obj_size); 657 int (*clear_surface_reg)(struct radeon_device *rdev, int reg); 658 void (*bandwidth_update)(struct radeon_device *rdev); 659 void (*hpd_init)(struct radeon_device *rdev); 660 void (*hpd_fini)(struct radeon_device *rdev); 661 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 662 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 663 }; 664 665 /* 666 * Asic structures 667 */ 668 struct r100_asic { 669 const unsigned *reg_safe_bm; 670 unsigned reg_safe_bm_size; 671 u32 hdp_cntl; 672 }; 673 674 struct r300_asic { 675 const unsigned *reg_safe_bm; 676 unsigned reg_safe_bm_size; 677 u32 resync_scratch; 678 u32 hdp_cntl; 679 }; 680 681 struct r600_asic { 682 unsigned max_pipes; 683 unsigned max_tile_pipes; 684 unsigned max_simds; 685 unsigned max_backends; 686 unsigned max_gprs; 687 unsigned max_threads; 688 unsigned max_stack_entries; 689 unsigned max_hw_contexts; 690 unsigned max_gs_threads; 691 unsigned sx_max_export_size; 692 unsigned sx_max_export_pos_size; 693 unsigned sx_max_export_smx_size; 694 unsigned sq_num_cf_insts; 695 }; 696 697 struct rv770_asic { 698 unsigned max_pipes; 699 unsigned max_tile_pipes; 700 unsigned max_simds; 701 unsigned max_backends; 702 unsigned max_gprs; 703 unsigned max_threads; 704 unsigned max_stack_entries; 705 unsigned max_hw_contexts; 706 unsigned max_gs_threads; 707 unsigned sx_max_export_size; 708 unsigned sx_max_export_pos_size; 709 unsigned sx_max_export_smx_size; 710 unsigned sq_num_cf_insts; 711 unsigned sx_num_of_sets; 712 unsigned sc_prim_fifo_size; 713 unsigned sc_hiz_tile_fifo_size; 714 unsigned sc_earlyz_tile_fifo_fize; 715 }; 716 717 union radeon_asic_config { 718 struct r300_asic r300; 719 struct r100_asic r100; 720 struct r600_asic r600; 721 struct rv770_asic rv770; 722 }; 723 724 725 /* 726 * IOCTL. 727 */ 728 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 729 struct drm_file *filp); 730 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 731 struct drm_file *filp); 732 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 733 struct drm_file *file_priv); 734 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 735 struct drm_file *file_priv); 736 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 737 struct drm_file *file_priv); 738 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 739 struct drm_file *file_priv); 740 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 741 struct drm_file *filp); 742 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 743 struct drm_file *filp); 744 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 745 struct drm_file *filp); 746 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 747 struct drm_file *filp); 748 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 749 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 750 struct drm_file *filp); 751 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 752 struct drm_file *filp); 753 754 755 /* 756 * Core structure, functions and helpers. 757 */ 758 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 759 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 760 761 struct radeon_device { 762 struct device *dev; 763 struct drm_device *ddev; 764 struct pci_dev *pdev; 765 /* ASIC */ 766 union radeon_asic_config config; 767 enum radeon_family family; 768 unsigned long flags; 769 int usec_timeout; 770 enum radeon_pll_errata pll_errata; 771 int num_gb_pipes; 772 int num_z_pipes; 773 int disp_priority; 774 /* BIOS */ 775 uint8_t *bios; 776 bool is_atom_bios; 777 uint16_t bios_header_start; 778 struct radeon_bo *stollen_vga_memory; 779 struct fb_info *fbdev_info; 780 struct radeon_bo *fbdev_rbo; 781 struct radeon_framebuffer *fbdev_rfb; 782 /* Register mmio */ 783 resource_size_t rmmio_base; 784 resource_size_t rmmio_size; 785 void *rmmio; 786 radeon_rreg_t mc_rreg; 787 radeon_wreg_t mc_wreg; 788 radeon_rreg_t pll_rreg; 789 radeon_wreg_t pll_wreg; 790 uint32_t pcie_reg_mask; 791 radeon_rreg_t pciep_rreg; 792 radeon_wreg_t pciep_wreg; 793 struct radeon_clock clock; 794 struct radeon_mc mc; 795 struct radeon_gart gart; 796 struct radeon_mode_info mode_info; 797 struct radeon_scratch scratch; 798 struct radeon_mman mman; 799 struct radeon_fence_driver fence_drv; 800 struct radeon_cp cp; 801 struct radeon_ib_pool ib_pool; 802 struct radeon_irq irq; 803 struct radeon_asic *asic; 804 struct radeon_gem gem; 805 struct radeon_pm pm; 806 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 807 struct mutex cs_mutex; 808 struct radeon_wb wb; 809 struct radeon_dummy_page dummy_page; 810 bool gpu_lockup; 811 bool shutdown; 812 bool suspend; 813 bool need_dma32; 814 bool accel_working; 815 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 816 const struct firmware *me_fw; /* all family ME firmware */ 817 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 818 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 819 struct r600_blit r600_blit; 820 int msi_enabled; /* msi enabled */ 821 struct r600_ih ih; /* r6/700 interrupt ring */ 822 struct workqueue_struct *wq; 823 struct work_struct hotplug_work; 824 825 /* audio stuff */ 826 struct timer_list audio_timer; 827 int audio_channels; 828 int audio_rate; 829 int audio_bits_per_sample; 830 uint8_t audio_status_bits; 831 uint8_t audio_category_code; 832 }; 833 834 int radeon_device_init(struct radeon_device *rdev, 835 struct drm_device *ddev, 836 struct pci_dev *pdev, 837 uint32_t flags); 838 void radeon_device_fini(struct radeon_device *rdev); 839 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 840 841 /* r600 blit */ 842 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); 843 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); 844 void r600_kms_blit_copy(struct radeon_device *rdev, 845 u64 src_gpu_addr, u64 dst_gpu_addr, 846 int size_bytes); 847 848 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) 849 { 850 if (reg < 0x10000) 851 return readl(((void __iomem *)rdev->rmmio) + reg); 852 else { 853 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 854 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 855 } 856 } 857 858 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 859 { 860 if (reg < 0x10000) 861 writel(v, ((void __iomem *)rdev->rmmio) + reg); 862 else { 863 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 864 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 865 } 866 } 867 868 /* 869 * Cast helper 870 */ 871 #define to_radeon_fence(p) ((struct radeon_fence *)(p)) 872 873 /* 874 * Registers read & write functions. 875 */ 876 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) 877 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) 878 #define RREG32(reg) r100_mm_rreg(rdev, (reg)) 879 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) 880 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) 881 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 882 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 883 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 884 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 885 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 886 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 887 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 888 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 889 #define WREG32_P(reg, val, mask) \ 890 do { \ 891 uint32_t tmp_ = RREG32(reg); \ 892 tmp_ &= (mask); \ 893 tmp_ |= ((val) & ~(mask)); \ 894 WREG32(reg, tmp_); \ 895 } while (0) 896 #define WREG32_PLL_P(reg, val, mask) \ 897 do { \ 898 uint32_t tmp_ = RREG32_PLL(reg); \ 899 tmp_ &= (mask); \ 900 tmp_ |= ((val) & ~(mask)); \ 901 WREG32_PLL(reg, tmp_); \ 902 } while (0) 903 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) 904 905 /* 906 * Indirect registers accessor 907 */ 908 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 909 { 910 uint32_t r; 911 912 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 913 r = RREG32(RADEON_PCIE_DATA); 914 return r; 915 } 916 917 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 918 { 919 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 920 WREG32(RADEON_PCIE_DATA, (v)); 921 } 922 923 void r100_pll_errata_after_index(struct radeon_device *rdev); 924 925 926 /* 927 * ASICs helpers. 928 */ 929 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 930 (rdev->pdev->device == 0x5969)) 931 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 932 (rdev->family == CHIP_RV200) || \ 933 (rdev->family == CHIP_RS100) || \ 934 (rdev->family == CHIP_RS200) || \ 935 (rdev->family == CHIP_RV250) || \ 936 (rdev->family == CHIP_RV280) || \ 937 (rdev->family == CHIP_RS300)) 938 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 939 (rdev->family == CHIP_RV350) || \ 940 (rdev->family == CHIP_R350) || \ 941 (rdev->family == CHIP_RV380) || \ 942 (rdev->family == CHIP_R420) || \ 943 (rdev->family == CHIP_R423) || \ 944 (rdev->family == CHIP_RV410) || \ 945 (rdev->family == CHIP_RS400) || \ 946 (rdev->family == CHIP_RS480)) 947 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 948 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 949 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 950 951 952 /* 953 * BIOS helpers. 954 */ 955 #define RBIOS8(i) (rdev->bios[i]) 956 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 957 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 958 959 int radeon_combios_init(struct radeon_device *rdev); 960 void radeon_combios_fini(struct radeon_device *rdev); 961 int radeon_atombios_init(struct radeon_device *rdev); 962 void radeon_atombios_fini(struct radeon_device *rdev); 963 964 965 /* 966 * RING helpers. 967 */ 968 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) 969 { 970 #if DRM_DEBUG_CODE 971 if (rdev->cp.count_dw <= 0) { 972 DRM_ERROR("radeon: writting more dword to ring than expected !\n"); 973 } 974 #endif 975 rdev->cp.ring[rdev->cp.wptr++] = v; 976 rdev->cp.wptr &= rdev->cp.ptr_mask; 977 rdev->cp.count_dw--; 978 rdev->cp.ring_free_dw--; 979 } 980 981 982 /* 983 * ASICs macro. 984 */ 985 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 986 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 987 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 988 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 989 #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) 990 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 991 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) 992 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) 993 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) 994 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) 995 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) 996 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) 997 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) 998 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) 999 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) 1000 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) 1001 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) 1002 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) 1003 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) 1004 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) 1005 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) 1006 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) 1007 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) 1008 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) 1009 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) 1010 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) 1011 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) 1012 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) 1013 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) 1014 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) 1015 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) 1016 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) 1017 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) 1018 1019 /* Common functions */ 1020 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); 1021 extern int radeon_modeset_init(struct radeon_device *rdev); 1022 extern void radeon_modeset_fini(struct radeon_device *rdev); 1023 extern bool radeon_card_posted(struct radeon_device *rdev); 1024 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 1025 extern int radeon_clocks_init(struct radeon_device *rdev); 1026 extern void radeon_clocks_fini(struct radeon_device *rdev); 1027 extern void radeon_scratch_init(struct radeon_device *rdev); 1028 extern void radeon_surface_init(struct radeon_device *rdev); 1029 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 1030 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 1031 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 1032 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 1033 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 1034 1035 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ 1036 struct r100_mc_save { 1037 u32 GENMO_WT; 1038 u32 CRTC_EXT_CNTL; 1039 u32 CRTC_GEN_CNTL; 1040 u32 CRTC2_GEN_CNTL; 1041 u32 CUR_OFFSET; 1042 u32 CUR2_OFFSET; 1043 }; 1044 extern void r100_cp_disable(struct radeon_device *rdev); 1045 extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 1046 extern void r100_cp_fini(struct radeon_device *rdev); 1047 extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 1048 extern int r100_pci_gart_init(struct radeon_device *rdev); 1049 extern void r100_pci_gart_fini(struct radeon_device *rdev); 1050 extern int r100_pci_gart_enable(struct radeon_device *rdev); 1051 extern void r100_pci_gart_disable(struct radeon_device *rdev); 1052 extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 1053 extern int r100_debugfs_mc_info_init(struct radeon_device *rdev); 1054 extern int r100_gui_wait_for_idle(struct radeon_device *rdev); 1055 extern void r100_ib_fini(struct radeon_device *rdev); 1056 extern int r100_ib_init(struct radeon_device *rdev); 1057 extern void r100_irq_disable(struct radeon_device *rdev); 1058 extern int r100_irq_set(struct radeon_device *rdev); 1059 extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); 1060 extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); 1061 extern void r100_vram_init_sizes(struct radeon_device *rdev); 1062 extern void r100_wb_disable(struct radeon_device *rdev); 1063 extern void r100_wb_fini(struct radeon_device *rdev); 1064 extern int r100_wb_init(struct radeon_device *rdev); 1065 extern void r100_hdp_reset(struct radeon_device *rdev); 1066 extern int r100_rb2d_reset(struct radeon_device *rdev); 1067 extern int r100_cp_reset(struct radeon_device *rdev); 1068 extern void r100_vga_render_disable(struct radeon_device *rdev); 1069 extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 1070 struct radeon_cs_packet *pkt, 1071 struct radeon_bo *robj); 1072 extern int r100_cs_parse_packet0(struct radeon_cs_parser *p, 1073 struct radeon_cs_packet *pkt, 1074 const unsigned *auth, unsigned n, 1075 radeon_packet0_check_t check); 1076 extern int r100_cs_packet_parse(struct radeon_cs_parser *p, 1077 struct radeon_cs_packet *pkt, 1078 unsigned idx); 1079 extern void r100_enable_bm(struct radeon_device *rdev); 1080 extern void r100_set_common_regs(struct radeon_device *rdev); 1081 1082 /* rv200,rv250,rv280 */ 1083 extern void r200_set_safe_registers(struct radeon_device *rdev); 1084 1085 /* r300,r350,rv350,rv370,rv380 */ 1086 extern void r300_set_reg_safe(struct radeon_device *rdev); 1087 extern void r300_mc_program(struct radeon_device *rdev); 1088 extern void r300_vram_info(struct radeon_device *rdev); 1089 extern void r300_clock_startup(struct radeon_device *rdev); 1090 extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 1091 extern int rv370_pcie_gart_init(struct radeon_device *rdev); 1092 extern void rv370_pcie_gart_fini(struct radeon_device *rdev); 1093 extern int rv370_pcie_gart_enable(struct radeon_device *rdev); 1094 extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 1095 1096 /* r420,r423,rv410 */ 1097 extern int r420_mc_init(struct radeon_device *rdev); 1098 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 1099 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 1100 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 1101 extern void r420_pipes_init(struct radeon_device *rdev); 1102 1103 /* rv515 */ 1104 struct rv515_mc_save { 1105 u32 d1vga_control; 1106 u32 d2vga_control; 1107 u32 vga_render_control; 1108 u32 vga_hdp_control; 1109 u32 d1crtc_control; 1110 u32 d2crtc_control; 1111 }; 1112 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 1113 extern void rv515_vga_render_disable(struct radeon_device *rdev); 1114 extern void rv515_set_safe_registers(struct radeon_device *rdev); 1115 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); 1116 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); 1117 extern void rv515_clock_startup(struct radeon_device *rdev); 1118 extern void rv515_debugfs(struct radeon_device *rdev); 1119 extern int rv515_suspend(struct radeon_device *rdev); 1120 1121 /* rs400 */ 1122 extern int rs400_gart_init(struct radeon_device *rdev); 1123 extern int rs400_gart_enable(struct radeon_device *rdev); 1124 extern void rs400_gart_adjust_size(struct radeon_device *rdev); 1125 extern void rs400_gart_disable(struct radeon_device *rdev); 1126 extern void rs400_gart_fini(struct radeon_device *rdev); 1127 1128 /* rs600 */ 1129 extern void rs600_set_safe_registers(struct radeon_device *rdev); 1130 extern int rs600_irq_set(struct radeon_device *rdev); 1131 extern void rs600_irq_disable(struct radeon_device *rdev); 1132 1133 /* rs690, rs740 */ 1134 extern void rs690_line_buffer_adjust(struct radeon_device *rdev, 1135 struct drm_display_mode *mode1, 1136 struct drm_display_mode *mode2); 1137 1138 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ 1139 extern bool r600_card_posted(struct radeon_device *rdev); 1140 extern void r600_cp_stop(struct radeon_device *rdev); 1141 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); 1142 extern int r600_cp_resume(struct radeon_device *rdev); 1143 extern int r600_count_pipe_bits(uint32_t val); 1144 extern int r600_gart_clear_page(struct radeon_device *rdev, int i); 1145 extern int r600_mc_wait_for_idle(struct radeon_device *rdev); 1146 extern int r600_pcie_gart_init(struct radeon_device *rdev); 1147 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 1148 extern int r600_ib_test(struct radeon_device *rdev); 1149 extern int r600_ring_test(struct radeon_device *rdev); 1150 extern void r600_wb_fini(struct radeon_device *rdev); 1151 extern int r600_wb_enable(struct radeon_device *rdev); 1152 extern void r600_wb_disable(struct radeon_device *rdev); 1153 extern void r600_scratch_init(struct radeon_device *rdev); 1154 extern int r600_blit_init(struct radeon_device *rdev); 1155 extern void r600_blit_fini(struct radeon_device *rdev); 1156 extern int r600_init_microcode(struct radeon_device *rdev); 1157 extern int r600_gpu_reset(struct radeon_device *rdev); 1158 /* r600 irq */ 1159 extern int r600_irq_init(struct radeon_device *rdev); 1160 extern void r600_irq_fini(struct radeon_device *rdev); 1161 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 1162 extern int r600_irq_set(struct radeon_device *rdev); 1163 1164 extern int r600_audio_init(struct radeon_device *rdev); 1165 extern int r600_audio_tmds_index(struct drm_encoder *encoder); 1166 extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock); 1167 extern void r600_audio_fini(struct radeon_device *rdev); 1168 extern void r600_hdmi_init(struct drm_encoder *encoder); 1169 extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable); 1170 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 1171 extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); 1172 extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder, 1173 int channels, 1174 int rate, 1175 int bps, 1176 uint8_t status_bits, 1177 uint8_t category_code); 1178 1179 #include "radeon_object.h" 1180 1181 #endif 1182