1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 /* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45 /* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63 #include <linux/atomic.h> 64 #include <linux/wait.h> 65 #include <linux/list.h> 66 #include <linux/kref.h> 67 68 #include <ttm/ttm_bo_api.h> 69 #include <ttm/ttm_bo_driver.h> 70 #include <ttm/ttm_placement.h> 71 #include <ttm/ttm_module.h> 72 #include <ttm/ttm_execbuf_util.h> 73 74 #include "radeon_family.h" 75 #include "radeon_mode.h" 76 #include "radeon_reg.h" 77 78 /* 79 * Modules parameters. 80 */ 81 extern int radeon_no_wb; 82 extern int radeon_modeset; 83 extern int radeon_dynclks; 84 extern int radeon_r4xx_atom; 85 extern int radeon_agpmode; 86 extern int radeon_vram_limit; 87 extern int radeon_gart_size; 88 extern int radeon_benchmarking; 89 extern int radeon_testing; 90 extern int radeon_connector_table; 91 extern int radeon_tv; 92 extern int radeon_audio; 93 extern int radeon_disp_priority; 94 extern int radeon_hw_i2c; 95 extern int radeon_pcie_gen2; 96 extern int radeon_msi; 97 extern int radeon_lockup_timeout; 98 99 /* 100 * Copy from radeon_drv.h so we don't have to include both and have conflicting 101 * symbol; 102 */ 103 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 104 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 105 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 106 #define RADEON_IB_POOL_SIZE 16 107 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 108 #define RADEONFB_CONN_LIMIT 4 109 #define RADEON_BIOS_NUM_SCRATCH 8 110 111 /* max number of rings */ 112 #define RADEON_NUM_RINGS 3 113 114 /* fence seq are set to this number when signaled */ 115 #define RADEON_FENCE_SIGNALED_SEQ 0LL 116 117 /* internal ring indices */ 118 /* r1xx+ has gfx CP ring */ 119 #define RADEON_RING_TYPE_GFX_INDEX 0 120 121 /* cayman has 2 compute CP rings */ 122 #define CAYMAN_RING_TYPE_CP1_INDEX 1 123 #define CAYMAN_RING_TYPE_CP2_INDEX 2 124 125 /* hardcode those limit for now */ 126 #define RADEON_VA_RESERVED_SIZE (8 << 20) 127 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 128 129 /* 130 * Errata workarounds. 131 */ 132 enum radeon_pll_errata { 133 CHIP_ERRATA_R300_CG = 0x00000001, 134 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 135 CHIP_ERRATA_PLL_DELAY = 0x00000004 136 }; 137 138 139 struct radeon_device; 140 141 142 /* 143 * BIOS. 144 */ 145 bool radeon_get_bios(struct radeon_device *rdev); 146 147 /* 148 * Dummy page 149 */ 150 struct radeon_dummy_page { 151 struct page *page; 152 dma_addr_t addr; 153 }; 154 int radeon_dummy_page_init(struct radeon_device *rdev); 155 void radeon_dummy_page_fini(struct radeon_device *rdev); 156 157 158 /* 159 * Clocks 160 */ 161 struct radeon_clock { 162 struct radeon_pll p1pll; 163 struct radeon_pll p2pll; 164 struct radeon_pll dcpll; 165 struct radeon_pll spll; 166 struct radeon_pll mpll; 167 /* 10 Khz units */ 168 uint32_t default_mclk; 169 uint32_t default_sclk; 170 uint32_t default_dispclk; 171 uint32_t dp_extclk; 172 uint32_t max_pixel_clock; 173 }; 174 175 /* 176 * Power management 177 */ 178 int radeon_pm_init(struct radeon_device *rdev); 179 void radeon_pm_fini(struct radeon_device *rdev); 180 void radeon_pm_compute_clocks(struct radeon_device *rdev); 181 void radeon_pm_suspend(struct radeon_device *rdev); 182 void radeon_pm_resume(struct radeon_device *rdev); 183 void radeon_combios_get_power_modes(struct radeon_device *rdev); 184 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 185 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 186 void rs690_pm_info(struct radeon_device *rdev); 187 extern int rv6xx_get_temp(struct radeon_device *rdev); 188 extern int rv770_get_temp(struct radeon_device *rdev); 189 extern int evergreen_get_temp(struct radeon_device *rdev); 190 extern int sumo_get_temp(struct radeon_device *rdev); 191 extern int si_get_temp(struct radeon_device *rdev); 192 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 193 unsigned *bankh, unsigned *mtaspect, 194 unsigned *tile_split); 195 196 /* 197 * Fences. 198 */ 199 struct radeon_fence_driver { 200 uint32_t scratch_reg; 201 uint64_t gpu_addr; 202 volatile uint32_t *cpu_addr; 203 /* sync_seq is protected by ring emission lock */ 204 uint64_t sync_seq[RADEON_NUM_RINGS]; 205 atomic64_t last_seq; 206 unsigned long last_activity; 207 bool initialized; 208 }; 209 210 struct radeon_fence { 211 struct radeon_device *rdev; 212 struct kref kref; 213 /* protected by radeon_fence.lock */ 214 uint64_t seq; 215 /* RB, DMA, etc. */ 216 unsigned ring; 217 }; 218 219 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 220 int radeon_fence_driver_init(struct radeon_device *rdev); 221 void radeon_fence_driver_fini(struct radeon_device *rdev); 222 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 223 void radeon_fence_process(struct radeon_device *rdev, int ring); 224 bool radeon_fence_signaled(struct radeon_fence *fence); 225 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 226 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring); 227 void radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring); 228 int radeon_fence_wait_any(struct radeon_device *rdev, 229 struct radeon_fence **fences, 230 bool intr); 231 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 232 void radeon_fence_unref(struct radeon_fence **fence); 233 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 234 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 235 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 236 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 237 struct radeon_fence *b) 238 { 239 if (!a) { 240 return b; 241 } 242 243 if (!b) { 244 return a; 245 } 246 247 BUG_ON(a->ring != b->ring); 248 249 if (a->seq > b->seq) { 250 return a; 251 } else { 252 return b; 253 } 254 } 255 256 /* 257 * Tiling registers 258 */ 259 struct radeon_surface_reg { 260 struct radeon_bo *bo; 261 }; 262 263 #define RADEON_GEM_MAX_SURFACES 8 264 265 /* 266 * TTM. 267 */ 268 struct radeon_mman { 269 struct ttm_bo_global_ref bo_global_ref; 270 struct drm_global_reference mem_global_ref; 271 struct ttm_bo_device bdev; 272 bool mem_global_referenced; 273 bool initialized; 274 }; 275 276 /* bo virtual address in a specific vm */ 277 struct radeon_bo_va { 278 /* bo list is protected by bo being reserved */ 279 struct list_head bo_list; 280 /* vm list is protected by vm mutex */ 281 struct list_head vm_list; 282 /* constant after initialization */ 283 struct radeon_vm *vm; 284 struct radeon_bo *bo; 285 uint64_t soffset; 286 uint64_t eoffset; 287 uint32_t flags; 288 struct radeon_fence *fence; 289 bool valid; 290 }; 291 292 struct radeon_bo { 293 /* Protected by gem.mutex */ 294 struct list_head list; 295 /* Protected by tbo.reserved */ 296 u32 placements[3]; 297 struct ttm_placement placement; 298 struct ttm_buffer_object tbo; 299 struct ttm_bo_kmap_obj kmap; 300 unsigned pin_count; 301 void *kptr; 302 u32 tiling_flags; 303 u32 pitch; 304 int surface_reg; 305 /* list of all virtual address to which this bo 306 * is associated to 307 */ 308 struct list_head va; 309 /* Constant after initialization */ 310 struct radeon_device *rdev; 311 struct drm_gem_object gem_base; 312 313 struct ttm_bo_kmap_obj dma_buf_vmap; 314 int vmapping_count; 315 }; 316 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 317 318 struct radeon_bo_list { 319 struct ttm_validate_buffer tv; 320 struct radeon_bo *bo; 321 uint64_t gpu_offset; 322 unsigned rdomain; 323 unsigned wdomain; 324 u32 tiling_flags; 325 }; 326 327 /* sub-allocation manager, it has to be protected by another lock. 328 * By conception this is an helper for other part of the driver 329 * like the indirect buffer or semaphore, which both have their 330 * locking. 331 * 332 * Principe is simple, we keep a list of sub allocation in offset 333 * order (first entry has offset == 0, last entry has the highest 334 * offset). 335 * 336 * When allocating new object we first check if there is room at 337 * the end total_size - (last_object_offset + last_object_size) >= 338 * alloc_size. If so we allocate new object there. 339 * 340 * When there is not enough room at the end, we start waiting for 341 * each sub object until we reach object_offset+object_size >= 342 * alloc_size, this object then become the sub object we return. 343 * 344 * Alignment can't be bigger than page size. 345 * 346 * Hole are not considered for allocation to keep things simple. 347 * Assumption is that there won't be hole (all object on same 348 * alignment). 349 */ 350 struct radeon_sa_manager { 351 wait_queue_head_t wq; 352 struct radeon_bo *bo; 353 struct list_head *hole; 354 struct list_head flist[RADEON_NUM_RINGS]; 355 struct list_head olist; 356 unsigned size; 357 uint64_t gpu_addr; 358 void *cpu_ptr; 359 uint32_t domain; 360 }; 361 362 struct radeon_sa_bo; 363 364 /* sub-allocation buffer */ 365 struct radeon_sa_bo { 366 struct list_head olist; 367 struct list_head flist; 368 struct radeon_sa_manager *manager; 369 unsigned soffset; 370 unsigned eoffset; 371 struct radeon_fence *fence; 372 }; 373 374 /* 375 * GEM objects. 376 */ 377 struct radeon_gem { 378 struct mutex mutex; 379 struct list_head objects; 380 }; 381 382 int radeon_gem_init(struct radeon_device *rdev); 383 void radeon_gem_fini(struct radeon_device *rdev); 384 int radeon_gem_object_create(struct radeon_device *rdev, int size, 385 int alignment, int initial_domain, 386 bool discardable, bool kernel, 387 struct drm_gem_object **obj); 388 389 int radeon_mode_dumb_create(struct drm_file *file_priv, 390 struct drm_device *dev, 391 struct drm_mode_create_dumb *args); 392 int radeon_mode_dumb_mmap(struct drm_file *filp, 393 struct drm_device *dev, 394 uint32_t handle, uint64_t *offset_p); 395 int radeon_mode_dumb_destroy(struct drm_file *file_priv, 396 struct drm_device *dev, 397 uint32_t handle); 398 399 /* 400 * Semaphores. 401 */ 402 /* everything here is constant */ 403 struct radeon_semaphore { 404 struct radeon_sa_bo *sa_bo; 405 signed waiters; 406 uint64_t gpu_addr; 407 }; 408 409 int radeon_semaphore_create(struct radeon_device *rdev, 410 struct radeon_semaphore **semaphore); 411 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 412 struct radeon_semaphore *semaphore); 413 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 414 struct radeon_semaphore *semaphore); 415 int radeon_semaphore_sync_rings(struct radeon_device *rdev, 416 struct radeon_semaphore *semaphore, 417 int signaler, int waiter); 418 void radeon_semaphore_free(struct radeon_device *rdev, 419 struct radeon_semaphore **semaphore, 420 struct radeon_fence *fence); 421 422 /* 423 * GART structures, functions & helpers 424 */ 425 struct radeon_mc; 426 427 #define RADEON_GPU_PAGE_SIZE 4096 428 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 429 #define RADEON_GPU_PAGE_SHIFT 12 430 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 431 432 struct radeon_gart { 433 dma_addr_t table_addr; 434 struct radeon_bo *robj; 435 void *ptr; 436 unsigned num_gpu_pages; 437 unsigned num_cpu_pages; 438 unsigned table_size; 439 struct page **pages; 440 dma_addr_t *pages_addr; 441 bool ready; 442 }; 443 444 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 445 void radeon_gart_table_ram_free(struct radeon_device *rdev); 446 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 447 void radeon_gart_table_vram_free(struct radeon_device *rdev); 448 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 449 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 450 int radeon_gart_init(struct radeon_device *rdev); 451 void radeon_gart_fini(struct radeon_device *rdev); 452 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 453 int pages); 454 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 455 int pages, struct page **pagelist, 456 dma_addr_t *dma_addr); 457 void radeon_gart_restore(struct radeon_device *rdev); 458 459 460 /* 461 * GPU MC structures, functions & helpers 462 */ 463 struct radeon_mc { 464 resource_size_t aper_size; 465 resource_size_t aper_base; 466 resource_size_t agp_base; 467 /* for some chips with <= 32MB we need to lie 468 * about vram size near mc fb location */ 469 u64 mc_vram_size; 470 u64 visible_vram_size; 471 u64 gtt_size; 472 u64 gtt_start; 473 u64 gtt_end; 474 u64 vram_start; 475 u64 vram_end; 476 unsigned vram_width; 477 u64 real_vram_size; 478 int vram_mtrr; 479 bool vram_is_ddr; 480 bool igp_sideport_enabled; 481 u64 gtt_base_align; 482 }; 483 484 bool radeon_combios_sideport_present(struct radeon_device *rdev); 485 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 486 487 /* 488 * GPU scratch registers structures, functions & helpers 489 */ 490 struct radeon_scratch { 491 unsigned num_reg; 492 uint32_t reg_base; 493 bool free[32]; 494 uint32_t reg[32]; 495 }; 496 497 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 498 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 499 500 501 /* 502 * IRQS. 503 */ 504 505 struct radeon_unpin_work { 506 struct work_struct work; 507 struct radeon_device *rdev; 508 int crtc_id; 509 struct radeon_fence *fence; 510 struct drm_pending_vblank_event *event; 511 struct radeon_bo *old_rbo; 512 u64 new_crtc_base; 513 }; 514 515 struct r500_irq_stat_regs { 516 u32 disp_int; 517 u32 hdmi0_status; 518 }; 519 520 struct r600_irq_stat_regs { 521 u32 disp_int; 522 u32 disp_int_cont; 523 u32 disp_int_cont2; 524 u32 d1grph_int; 525 u32 d2grph_int; 526 u32 hdmi0_status; 527 u32 hdmi1_status; 528 }; 529 530 struct evergreen_irq_stat_regs { 531 u32 disp_int; 532 u32 disp_int_cont; 533 u32 disp_int_cont2; 534 u32 disp_int_cont3; 535 u32 disp_int_cont4; 536 u32 disp_int_cont5; 537 u32 d1grph_int; 538 u32 d2grph_int; 539 u32 d3grph_int; 540 u32 d4grph_int; 541 u32 d5grph_int; 542 u32 d6grph_int; 543 u32 afmt_status1; 544 u32 afmt_status2; 545 u32 afmt_status3; 546 u32 afmt_status4; 547 u32 afmt_status5; 548 u32 afmt_status6; 549 }; 550 551 union radeon_irq_stat_regs { 552 struct r500_irq_stat_regs r500; 553 struct r600_irq_stat_regs r600; 554 struct evergreen_irq_stat_regs evergreen; 555 }; 556 557 #define RADEON_MAX_HPD_PINS 6 558 #define RADEON_MAX_CRTCS 6 559 #define RADEON_MAX_AFMT_BLOCKS 6 560 561 struct radeon_irq { 562 bool installed; 563 spinlock_t lock; 564 atomic_t ring_int[RADEON_NUM_RINGS]; 565 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 566 atomic_t pflip[RADEON_MAX_CRTCS]; 567 wait_queue_head_t vblank_queue; 568 bool hpd[RADEON_MAX_HPD_PINS]; 569 bool gui_idle; 570 bool gui_idle_acked; 571 wait_queue_head_t idle_queue; 572 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 573 union radeon_irq_stat_regs stat_regs; 574 }; 575 576 int radeon_irq_kms_init(struct radeon_device *rdev); 577 void radeon_irq_kms_fini(struct radeon_device *rdev); 578 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 579 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 580 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 581 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 582 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 583 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 584 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 585 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 586 int radeon_irq_kms_wait_gui_idle(struct radeon_device *rdev); 587 588 /* 589 * CP & rings. 590 */ 591 592 struct radeon_ib { 593 struct radeon_sa_bo *sa_bo; 594 uint32_t length_dw; 595 uint64_t gpu_addr; 596 uint32_t *ptr; 597 int ring; 598 struct radeon_fence *fence; 599 unsigned vm_id; 600 bool is_const_ib; 601 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 602 struct radeon_semaphore *semaphore; 603 }; 604 605 struct radeon_ring { 606 struct radeon_bo *ring_obj; 607 volatile uint32_t *ring; 608 unsigned rptr; 609 unsigned rptr_offs; 610 unsigned rptr_reg; 611 unsigned rptr_save_reg; 612 u64 next_rptr_gpu_addr; 613 volatile u32 *next_rptr_cpu_addr; 614 unsigned wptr; 615 unsigned wptr_old; 616 unsigned wptr_reg; 617 unsigned ring_size; 618 unsigned ring_free_dw; 619 int count_dw; 620 unsigned long last_activity; 621 unsigned last_rptr; 622 uint64_t gpu_addr; 623 uint32_t align_mask; 624 uint32_t ptr_mask; 625 bool ready; 626 u32 ptr_reg_shift; 627 u32 ptr_reg_mask; 628 u32 nop; 629 u32 idx; 630 }; 631 632 /* 633 * VM 634 */ 635 struct radeon_vm { 636 struct list_head list; 637 struct list_head va; 638 int id; 639 unsigned last_pfn; 640 u64 pt_gpu_addr; 641 u64 *pt; 642 struct radeon_sa_bo *sa_bo; 643 struct mutex mutex; 644 /* last fence for cs using this vm */ 645 struct radeon_fence *fence; 646 }; 647 648 struct radeon_vm_funcs { 649 int (*init)(struct radeon_device *rdev); 650 void (*fini)(struct radeon_device *rdev); 651 /* cs mutex must be lock for schedule_ib */ 652 int (*bind)(struct radeon_device *rdev, struct radeon_vm *vm, int id); 653 void (*unbind)(struct radeon_device *rdev, struct radeon_vm *vm); 654 void (*tlb_flush)(struct radeon_device *rdev, struct radeon_vm *vm); 655 uint32_t (*page_flags)(struct radeon_device *rdev, 656 struct radeon_vm *vm, 657 uint32_t flags); 658 void (*set_page)(struct radeon_device *rdev, struct radeon_vm *vm, 659 unsigned pfn, uint64_t addr, uint32_t flags); 660 }; 661 662 struct radeon_vm_manager { 663 struct mutex lock; 664 struct list_head lru_vm; 665 uint32_t use_bitmap; 666 struct radeon_sa_manager sa_manager; 667 uint32_t max_pfn; 668 /* fields constant after init */ 669 const struct radeon_vm_funcs *funcs; 670 /* number of VMIDs */ 671 unsigned nvm; 672 /* vram base address for page table entry */ 673 u64 vram_base_offset; 674 /* is vm enabled? */ 675 bool enabled; 676 }; 677 678 /* 679 * file private structure 680 */ 681 struct radeon_fpriv { 682 struct radeon_vm vm; 683 }; 684 685 /* 686 * R6xx+ IH ring 687 */ 688 struct r600_ih { 689 struct radeon_bo *ring_obj; 690 volatile uint32_t *ring; 691 unsigned rptr; 692 unsigned ring_size; 693 uint64_t gpu_addr; 694 uint32_t ptr_mask; 695 atomic_t lock; 696 bool enabled; 697 }; 698 699 struct r600_blit_cp_primitives { 700 void (*set_render_target)(struct radeon_device *rdev, int format, 701 int w, int h, u64 gpu_addr); 702 void (*cp_set_surface_sync)(struct radeon_device *rdev, 703 u32 sync_type, u32 size, 704 u64 mc_addr); 705 void (*set_shaders)(struct radeon_device *rdev); 706 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr); 707 void (*set_tex_resource)(struct radeon_device *rdev, 708 int format, int w, int h, int pitch, 709 u64 gpu_addr, u32 size); 710 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1, 711 int x2, int y2); 712 void (*draw_auto)(struct radeon_device *rdev); 713 void (*set_default_state)(struct radeon_device *rdev); 714 }; 715 716 struct r600_blit { 717 struct radeon_bo *shader_obj; 718 struct r600_blit_cp_primitives primitives; 719 int max_dim; 720 int ring_size_common; 721 int ring_size_per_loop; 722 u64 shader_gpu_addr; 723 u32 vs_offset, ps_offset; 724 u32 state_offset; 725 u32 state_len; 726 }; 727 728 /* 729 * SI RLC stuff 730 */ 731 struct si_rlc { 732 /* for power gating */ 733 struct radeon_bo *save_restore_obj; 734 uint64_t save_restore_gpu_addr; 735 /* for clear state */ 736 struct radeon_bo *clear_state_obj; 737 uint64_t clear_state_gpu_addr; 738 }; 739 740 int radeon_ib_get(struct radeon_device *rdev, int ring, 741 struct radeon_ib *ib, unsigned size); 742 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 743 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 744 struct radeon_ib *const_ib); 745 int radeon_ib_pool_init(struct radeon_device *rdev); 746 void radeon_ib_pool_fini(struct radeon_device *rdev); 747 int radeon_ib_ring_tests(struct radeon_device *rdev); 748 /* Ring access between begin & end cannot sleep */ 749 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 750 struct radeon_ring *ring); 751 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 752 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 753 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 754 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); 755 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); 756 void radeon_ring_undo(struct radeon_ring *ring); 757 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 758 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 759 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring); 760 void radeon_ring_lockup_update(struct radeon_ring *ring); 761 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 762 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 763 uint32_t **data); 764 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 765 unsigned size, uint32_t *data); 766 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 767 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, 768 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop); 769 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 770 771 772 /* 773 * CS. 774 */ 775 struct radeon_cs_reloc { 776 struct drm_gem_object *gobj; 777 struct radeon_bo *robj; 778 struct radeon_bo_list lobj; 779 uint32_t handle; 780 uint32_t flags; 781 }; 782 783 struct radeon_cs_chunk { 784 uint32_t chunk_id; 785 uint32_t length_dw; 786 int kpage_idx[2]; 787 uint32_t *kpage[2]; 788 uint32_t *kdata; 789 void __user *user_ptr; 790 int last_copied_page; 791 int last_page_index; 792 }; 793 794 struct radeon_cs_parser { 795 struct device *dev; 796 struct radeon_device *rdev; 797 struct drm_file *filp; 798 /* chunks */ 799 unsigned nchunks; 800 struct radeon_cs_chunk *chunks; 801 uint64_t *chunks_array; 802 /* IB */ 803 unsigned idx; 804 /* relocations */ 805 unsigned nrelocs; 806 struct radeon_cs_reloc *relocs; 807 struct radeon_cs_reloc **relocs_ptr; 808 struct list_head validated; 809 /* indices of various chunks */ 810 int chunk_ib_idx; 811 int chunk_relocs_idx; 812 int chunk_flags_idx; 813 int chunk_const_ib_idx; 814 struct radeon_ib ib; 815 struct radeon_ib const_ib; 816 void *track; 817 unsigned family; 818 int parser_error; 819 u32 cs_flags; 820 u32 ring; 821 s32 priority; 822 }; 823 824 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); 825 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); 826 827 struct radeon_cs_packet { 828 unsigned idx; 829 unsigned type; 830 unsigned reg; 831 unsigned opcode; 832 int count; 833 unsigned one_reg_wr; 834 }; 835 836 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 837 struct radeon_cs_packet *pkt, 838 unsigned idx, unsigned reg); 839 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 840 struct radeon_cs_packet *pkt); 841 842 843 /* 844 * AGP 845 */ 846 int radeon_agp_init(struct radeon_device *rdev); 847 void radeon_agp_resume(struct radeon_device *rdev); 848 void radeon_agp_suspend(struct radeon_device *rdev); 849 void radeon_agp_fini(struct radeon_device *rdev); 850 851 852 /* 853 * Writeback 854 */ 855 struct radeon_wb { 856 struct radeon_bo *wb_obj; 857 volatile uint32_t *wb; 858 uint64_t gpu_addr; 859 bool enabled; 860 bool use_event; 861 }; 862 863 #define RADEON_WB_SCRATCH_OFFSET 0 864 #define RADEON_WB_RING0_NEXT_RPTR 256 865 #define RADEON_WB_CP_RPTR_OFFSET 1024 866 #define RADEON_WB_CP1_RPTR_OFFSET 1280 867 #define RADEON_WB_CP2_RPTR_OFFSET 1536 868 #define R600_WB_IH_WPTR_OFFSET 2048 869 #define R600_WB_EVENT_OFFSET 3072 870 871 /** 872 * struct radeon_pm - power management datas 873 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 874 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 875 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 876 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 877 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 878 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 879 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 880 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 881 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 882 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 883 * @needed_bandwidth: current bandwidth needs 884 * 885 * It keeps track of various data needed to take powermanagement decision. 886 * Bandwidth need is used to determine minimun clock of the GPU and memory. 887 * Equation between gpu/memory clock and available bandwidth is hw dependent 888 * (type of memory, bus size, efficiency, ...) 889 */ 890 891 enum radeon_pm_method { 892 PM_METHOD_PROFILE, 893 PM_METHOD_DYNPM, 894 }; 895 896 enum radeon_dynpm_state { 897 DYNPM_STATE_DISABLED, 898 DYNPM_STATE_MINIMUM, 899 DYNPM_STATE_PAUSED, 900 DYNPM_STATE_ACTIVE, 901 DYNPM_STATE_SUSPENDED, 902 }; 903 enum radeon_dynpm_action { 904 DYNPM_ACTION_NONE, 905 DYNPM_ACTION_MINIMUM, 906 DYNPM_ACTION_DOWNCLOCK, 907 DYNPM_ACTION_UPCLOCK, 908 DYNPM_ACTION_DEFAULT 909 }; 910 911 enum radeon_voltage_type { 912 VOLTAGE_NONE = 0, 913 VOLTAGE_GPIO, 914 VOLTAGE_VDDC, 915 VOLTAGE_SW 916 }; 917 918 enum radeon_pm_state_type { 919 POWER_STATE_TYPE_DEFAULT, 920 POWER_STATE_TYPE_POWERSAVE, 921 POWER_STATE_TYPE_BATTERY, 922 POWER_STATE_TYPE_BALANCED, 923 POWER_STATE_TYPE_PERFORMANCE, 924 }; 925 926 enum radeon_pm_profile_type { 927 PM_PROFILE_DEFAULT, 928 PM_PROFILE_AUTO, 929 PM_PROFILE_LOW, 930 PM_PROFILE_MID, 931 PM_PROFILE_HIGH, 932 }; 933 934 #define PM_PROFILE_DEFAULT_IDX 0 935 #define PM_PROFILE_LOW_SH_IDX 1 936 #define PM_PROFILE_MID_SH_IDX 2 937 #define PM_PROFILE_HIGH_SH_IDX 3 938 #define PM_PROFILE_LOW_MH_IDX 4 939 #define PM_PROFILE_MID_MH_IDX 5 940 #define PM_PROFILE_HIGH_MH_IDX 6 941 #define PM_PROFILE_MAX 7 942 943 struct radeon_pm_profile { 944 int dpms_off_ps_idx; 945 int dpms_on_ps_idx; 946 int dpms_off_cm_idx; 947 int dpms_on_cm_idx; 948 }; 949 950 enum radeon_int_thermal_type { 951 THERMAL_TYPE_NONE, 952 THERMAL_TYPE_RV6XX, 953 THERMAL_TYPE_RV770, 954 THERMAL_TYPE_EVERGREEN, 955 THERMAL_TYPE_SUMO, 956 THERMAL_TYPE_NI, 957 THERMAL_TYPE_SI, 958 }; 959 960 struct radeon_voltage { 961 enum radeon_voltage_type type; 962 /* gpio voltage */ 963 struct radeon_gpio_rec gpio; 964 u32 delay; /* delay in usec from voltage drop to sclk change */ 965 bool active_high; /* voltage drop is active when bit is high */ 966 /* VDDC voltage */ 967 u8 vddc_id; /* index into vddc voltage table */ 968 u8 vddci_id; /* index into vddci voltage table */ 969 bool vddci_enabled; 970 /* r6xx+ sw */ 971 u16 voltage; 972 /* evergreen+ vddci */ 973 u16 vddci; 974 }; 975 976 /* clock mode flags */ 977 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 978 979 struct radeon_pm_clock_info { 980 /* memory clock */ 981 u32 mclk; 982 /* engine clock */ 983 u32 sclk; 984 /* voltage info */ 985 struct radeon_voltage voltage; 986 /* standardized clock flags */ 987 u32 flags; 988 }; 989 990 /* state flags */ 991 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 992 993 struct radeon_power_state { 994 enum radeon_pm_state_type type; 995 struct radeon_pm_clock_info *clock_info; 996 /* number of valid clock modes in this power state */ 997 int num_clock_modes; 998 struct radeon_pm_clock_info *default_clock_mode; 999 /* standardized state flags */ 1000 u32 flags; 1001 u32 misc; /* vbios specific flags */ 1002 u32 misc2; /* vbios specific flags */ 1003 int pcie_lanes; /* pcie lanes */ 1004 }; 1005 1006 /* 1007 * Some modes are overclocked by very low value, accept them 1008 */ 1009 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1010 1011 struct radeon_pm { 1012 struct mutex mutex; 1013 /* write locked while reprogramming mclk */ 1014 struct rw_semaphore mclk_lock; 1015 u32 active_crtcs; 1016 int active_crtc_count; 1017 int req_vblank; 1018 bool vblank_sync; 1019 fixed20_12 max_bandwidth; 1020 fixed20_12 igp_sideport_mclk; 1021 fixed20_12 igp_system_mclk; 1022 fixed20_12 igp_ht_link_clk; 1023 fixed20_12 igp_ht_link_width; 1024 fixed20_12 k8_bandwidth; 1025 fixed20_12 sideport_bandwidth; 1026 fixed20_12 ht_bandwidth; 1027 fixed20_12 core_bandwidth; 1028 fixed20_12 sclk; 1029 fixed20_12 mclk; 1030 fixed20_12 needed_bandwidth; 1031 struct radeon_power_state *power_state; 1032 /* number of valid power states */ 1033 int num_power_states; 1034 int current_power_state_index; 1035 int current_clock_mode_index; 1036 int requested_power_state_index; 1037 int requested_clock_mode_index; 1038 int default_power_state_index; 1039 u32 current_sclk; 1040 u32 current_mclk; 1041 u16 current_vddc; 1042 u16 current_vddci; 1043 u32 default_sclk; 1044 u32 default_mclk; 1045 u16 default_vddc; 1046 u16 default_vddci; 1047 struct radeon_i2c_chan *i2c_bus; 1048 /* selected pm method */ 1049 enum radeon_pm_method pm_method; 1050 /* dynpm power management */ 1051 struct delayed_work dynpm_idle_work; 1052 enum radeon_dynpm_state dynpm_state; 1053 enum radeon_dynpm_action dynpm_planned_action; 1054 unsigned long dynpm_action_timeout; 1055 bool dynpm_can_upclock; 1056 bool dynpm_can_downclock; 1057 /* profile-based power management */ 1058 enum radeon_pm_profile_type profile; 1059 int profile_index; 1060 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1061 /* internal thermal controller on rv6xx+ */ 1062 enum radeon_int_thermal_type int_thermal_type; 1063 struct device *int_hwmon_dev; 1064 }; 1065 1066 int radeon_pm_get_type_index(struct radeon_device *rdev, 1067 enum radeon_pm_state_type ps_type, 1068 int instance); 1069 1070 struct r600_audio { 1071 int channels; 1072 int rate; 1073 int bits_per_sample; 1074 u8 status_bits; 1075 u8 category_code; 1076 }; 1077 1078 /* 1079 * Benchmarking 1080 */ 1081 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1082 1083 1084 /* 1085 * Testing 1086 */ 1087 void radeon_test_moves(struct radeon_device *rdev); 1088 void radeon_test_ring_sync(struct radeon_device *rdev, 1089 struct radeon_ring *cpA, 1090 struct radeon_ring *cpB); 1091 void radeon_test_syncing(struct radeon_device *rdev); 1092 1093 1094 /* 1095 * Debugfs 1096 */ 1097 struct radeon_debugfs { 1098 struct drm_info_list *files; 1099 unsigned num_files; 1100 }; 1101 1102 int radeon_debugfs_add_files(struct radeon_device *rdev, 1103 struct drm_info_list *files, 1104 unsigned nfiles); 1105 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1106 1107 1108 /* 1109 * ASIC specific functions. 1110 */ 1111 struct radeon_asic { 1112 int (*init)(struct radeon_device *rdev); 1113 void (*fini)(struct radeon_device *rdev); 1114 int (*resume)(struct radeon_device *rdev); 1115 int (*suspend)(struct radeon_device *rdev); 1116 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1117 int (*asic_reset)(struct radeon_device *rdev); 1118 /* ioctl hw specific callback. Some hw might want to perform special 1119 * operation on specific ioctl. For instance on wait idle some hw 1120 * might want to perform and HDP flush through MMIO as it seems that 1121 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed 1122 * through ring. 1123 */ 1124 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); 1125 /* check if 3D engine is idle */ 1126 bool (*gui_idle)(struct radeon_device *rdev); 1127 /* wait for mc_idle */ 1128 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1129 /* gart */ 1130 struct { 1131 void (*tlb_flush)(struct radeon_device *rdev); 1132 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); 1133 } gart; 1134 /* ring specific callbacks */ 1135 struct { 1136 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1137 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1138 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1139 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1140 struct radeon_semaphore *semaphore, bool emit_wait); 1141 int (*cs_parse)(struct radeon_cs_parser *p); 1142 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1143 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1144 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1145 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1146 } ring[RADEON_NUM_RINGS]; 1147 /* irqs */ 1148 struct { 1149 int (*set)(struct radeon_device *rdev); 1150 int (*process)(struct radeon_device *rdev); 1151 } irq; 1152 /* displays */ 1153 struct { 1154 /* display watermarks */ 1155 void (*bandwidth_update)(struct radeon_device *rdev); 1156 /* get frame count */ 1157 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1158 /* wait for vblank */ 1159 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1160 } display; 1161 /* copy functions for bo handling */ 1162 struct { 1163 int (*blit)(struct radeon_device *rdev, 1164 uint64_t src_offset, 1165 uint64_t dst_offset, 1166 unsigned num_gpu_pages, 1167 struct radeon_fence **fence); 1168 u32 blit_ring_index; 1169 int (*dma)(struct radeon_device *rdev, 1170 uint64_t src_offset, 1171 uint64_t dst_offset, 1172 unsigned num_gpu_pages, 1173 struct radeon_fence **fence); 1174 u32 dma_ring_index; 1175 /* method used for bo copy */ 1176 int (*copy)(struct radeon_device *rdev, 1177 uint64_t src_offset, 1178 uint64_t dst_offset, 1179 unsigned num_gpu_pages, 1180 struct radeon_fence **fence); 1181 /* ring used for bo copies */ 1182 u32 copy_ring_index; 1183 } copy; 1184 /* surfaces */ 1185 struct { 1186 int (*set_reg)(struct radeon_device *rdev, int reg, 1187 uint32_t tiling_flags, uint32_t pitch, 1188 uint32_t offset, uint32_t obj_size); 1189 void (*clear_reg)(struct radeon_device *rdev, int reg); 1190 } surface; 1191 /* hotplug detect */ 1192 struct { 1193 void (*init)(struct radeon_device *rdev); 1194 void (*fini)(struct radeon_device *rdev); 1195 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1196 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1197 } hpd; 1198 /* power management */ 1199 struct { 1200 void (*misc)(struct radeon_device *rdev); 1201 void (*prepare)(struct radeon_device *rdev); 1202 void (*finish)(struct radeon_device *rdev); 1203 void (*init_profile)(struct radeon_device *rdev); 1204 void (*get_dynpm_state)(struct radeon_device *rdev); 1205 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1206 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1207 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1208 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1209 int (*get_pcie_lanes)(struct radeon_device *rdev); 1210 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1211 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1212 } pm; 1213 /* pageflipping */ 1214 struct { 1215 void (*pre_page_flip)(struct radeon_device *rdev, int crtc); 1216 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1217 void (*post_page_flip)(struct radeon_device *rdev, int crtc); 1218 } pflip; 1219 }; 1220 1221 /* 1222 * Asic structures 1223 */ 1224 struct r100_asic { 1225 const unsigned *reg_safe_bm; 1226 unsigned reg_safe_bm_size; 1227 u32 hdp_cntl; 1228 }; 1229 1230 struct r300_asic { 1231 const unsigned *reg_safe_bm; 1232 unsigned reg_safe_bm_size; 1233 u32 resync_scratch; 1234 u32 hdp_cntl; 1235 }; 1236 1237 struct r600_asic { 1238 unsigned max_pipes; 1239 unsigned max_tile_pipes; 1240 unsigned max_simds; 1241 unsigned max_backends; 1242 unsigned max_gprs; 1243 unsigned max_threads; 1244 unsigned max_stack_entries; 1245 unsigned max_hw_contexts; 1246 unsigned max_gs_threads; 1247 unsigned sx_max_export_size; 1248 unsigned sx_max_export_pos_size; 1249 unsigned sx_max_export_smx_size; 1250 unsigned sq_num_cf_insts; 1251 unsigned tiling_nbanks; 1252 unsigned tiling_npipes; 1253 unsigned tiling_group_size; 1254 unsigned tile_config; 1255 unsigned backend_map; 1256 }; 1257 1258 struct rv770_asic { 1259 unsigned max_pipes; 1260 unsigned max_tile_pipes; 1261 unsigned max_simds; 1262 unsigned max_backends; 1263 unsigned max_gprs; 1264 unsigned max_threads; 1265 unsigned max_stack_entries; 1266 unsigned max_hw_contexts; 1267 unsigned max_gs_threads; 1268 unsigned sx_max_export_size; 1269 unsigned sx_max_export_pos_size; 1270 unsigned sx_max_export_smx_size; 1271 unsigned sq_num_cf_insts; 1272 unsigned sx_num_of_sets; 1273 unsigned sc_prim_fifo_size; 1274 unsigned sc_hiz_tile_fifo_size; 1275 unsigned sc_earlyz_tile_fifo_fize; 1276 unsigned tiling_nbanks; 1277 unsigned tiling_npipes; 1278 unsigned tiling_group_size; 1279 unsigned tile_config; 1280 unsigned backend_map; 1281 }; 1282 1283 struct evergreen_asic { 1284 unsigned num_ses; 1285 unsigned max_pipes; 1286 unsigned max_tile_pipes; 1287 unsigned max_simds; 1288 unsigned max_backends; 1289 unsigned max_gprs; 1290 unsigned max_threads; 1291 unsigned max_stack_entries; 1292 unsigned max_hw_contexts; 1293 unsigned max_gs_threads; 1294 unsigned sx_max_export_size; 1295 unsigned sx_max_export_pos_size; 1296 unsigned sx_max_export_smx_size; 1297 unsigned sq_num_cf_insts; 1298 unsigned sx_num_of_sets; 1299 unsigned sc_prim_fifo_size; 1300 unsigned sc_hiz_tile_fifo_size; 1301 unsigned sc_earlyz_tile_fifo_size; 1302 unsigned tiling_nbanks; 1303 unsigned tiling_npipes; 1304 unsigned tiling_group_size; 1305 unsigned tile_config; 1306 unsigned backend_map; 1307 }; 1308 1309 struct cayman_asic { 1310 unsigned max_shader_engines; 1311 unsigned max_pipes_per_simd; 1312 unsigned max_tile_pipes; 1313 unsigned max_simds_per_se; 1314 unsigned max_backends_per_se; 1315 unsigned max_texture_channel_caches; 1316 unsigned max_gprs; 1317 unsigned max_threads; 1318 unsigned max_gs_threads; 1319 unsigned max_stack_entries; 1320 unsigned sx_num_of_sets; 1321 unsigned sx_max_export_size; 1322 unsigned sx_max_export_pos_size; 1323 unsigned sx_max_export_smx_size; 1324 unsigned max_hw_contexts; 1325 unsigned sq_num_cf_insts; 1326 unsigned sc_prim_fifo_size; 1327 unsigned sc_hiz_tile_fifo_size; 1328 unsigned sc_earlyz_tile_fifo_size; 1329 1330 unsigned num_shader_engines; 1331 unsigned num_shader_pipes_per_simd; 1332 unsigned num_tile_pipes; 1333 unsigned num_simds_per_se; 1334 unsigned num_backends_per_se; 1335 unsigned backend_disable_mask_per_asic; 1336 unsigned backend_map; 1337 unsigned num_texture_channel_caches; 1338 unsigned mem_max_burst_length_bytes; 1339 unsigned mem_row_size_in_kb; 1340 unsigned shader_engine_tile_size; 1341 unsigned num_gpus; 1342 unsigned multi_gpu_tile_size; 1343 1344 unsigned tile_config; 1345 }; 1346 1347 struct si_asic { 1348 unsigned max_shader_engines; 1349 unsigned max_tile_pipes; 1350 unsigned max_cu_per_sh; 1351 unsigned max_sh_per_se; 1352 unsigned max_backends_per_se; 1353 unsigned max_texture_channel_caches; 1354 unsigned max_gprs; 1355 unsigned max_gs_threads; 1356 unsigned max_hw_contexts; 1357 unsigned sc_prim_fifo_size_frontend; 1358 unsigned sc_prim_fifo_size_backend; 1359 unsigned sc_hiz_tile_fifo_size; 1360 unsigned sc_earlyz_tile_fifo_size; 1361 1362 unsigned num_tile_pipes; 1363 unsigned num_backends_per_se; 1364 unsigned backend_disable_mask_per_asic; 1365 unsigned backend_map; 1366 unsigned num_texture_channel_caches; 1367 unsigned mem_max_burst_length_bytes; 1368 unsigned mem_row_size_in_kb; 1369 unsigned shader_engine_tile_size; 1370 unsigned num_gpus; 1371 unsigned multi_gpu_tile_size; 1372 1373 unsigned tile_config; 1374 }; 1375 1376 union radeon_asic_config { 1377 struct r300_asic r300; 1378 struct r100_asic r100; 1379 struct r600_asic r600; 1380 struct rv770_asic rv770; 1381 struct evergreen_asic evergreen; 1382 struct cayman_asic cayman; 1383 struct si_asic si; 1384 }; 1385 1386 /* 1387 * asic initizalization from radeon_asic.c 1388 */ 1389 void radeon_agp_disable(struct radeon_device *rdev); 1390 int radeon_asic_init(struct radeon_device *rdev); 1391 1392 1393 /* 1394 * IOCTL. 1395 */ 1396 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 1397 struct drm_file *filp); 1398 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 1399 struct drm_file *filp); 1400 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 1401 struct drm_file *file_priv); 1402 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 1403 struct drm_file *file_priv); 1404 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1405 struct drm_file *file_priv); 1406 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 1407 struct drm_file *file_priv); 1408 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1409 struct drm_file *filp); 1410 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 1411 struct drm_file *filp); 1412 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 1413 struct drm_file *filp); 1414 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1415 struct drm_file *filp); 1416 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 1417 struct drm_file *filp); 1418 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1419 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 1420 struct drm_file *filp); 1421 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 1422 struct drm_file *filp); 1423 1424 /* VRAM scratch page for HDP bug, default vram page */ 1425 struct r600_vram_scratch { 1426 struct radeon_bo *robj; 1427 volatile uint32_t *ptr; 1428 u64 gpu_addr; 1429 }; 1430 1431 1432 /* 1433 * Core structure, functions and helpers. 1434 */ 1435 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 1436 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 1437 1438 struct radeon_device { 1439 struct device *dev; 1440 struct drm_device *ddev; 1441 struct pci_dev *pdev; 1442 struct rw_semaphore exclusive_lock; 1443 /* ASIC */ 1444 union radeon_asic_config config; 1445 enum radeon_family family; 1446 unsigned long flags; 1447 int usec_timeout; 1448 enum radeon_pll_errata pll_errata; 1449 int num_gb_pipes; 1450 int num_z_pipes; 1451 int disp_priority; 1452 /* BIOS */ 1453 uint8_t *bios; 1454 bool is_atom_bios; 1455 uint16_t bios_header_start; 1456 struct radeon_bo *stollen_vga_memory; 1457 /* Register mmio */ 1458 resource_size_t rmmio_base; 1459 resource_size_t rmmio_size; 1460 void __iomem *rmmio; 1461 radeon_rreg_t mc_rreg; 1462 radeon_wreg_t mc_wreg; 1463 radeon_rreg_t pll_rreg; 1464 radeon_wreg_t pll_wreg; 1465 uint32_t pcie_reg_mask; 1466 radeon_rreg_t pciep_rreg; 1467 radeon_wreg_t pciep_wreg; 1468 /* io port */ 1469 void __iomem *rio_mem; 1470 resource_size_t rio_mem_size; 1471 struct radeon_clock clock; 1472 struct radeon_mc mc; 1473 struct radeon_gart gart; 1474 struct radeon_mode_info mode_info; 1475 struct radeon_scratch scratch; 1476 struct radeon_mman mman; 1477 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 1478 wait_queue_head_t fence_queue; 1479 struct mutex ring_lock; 1480 struct radeon_ring ring[RADEON_NUM_RINGS]; 1481 bool ib_pool_ready; 1482 struct radeon_sa_manager ring_tmp_bo; 1483 struct radeon_irq irq; 1484 struct radeon_asic *asic; 1485 struct radeon_gem gem; 1486 struct radeon_pm pm; 1487 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 1488 struct radeon_wb wb; 1489 struct radeon_dummy_page dummy_page; 1490 bool shutdown; 1491 bool suspend; 1492 bool need_dma32; 1493 bool accel_working; 1494 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 1495 const struct firmware *me_fw; /* all family ME firmware */ 1496 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 1497 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 1498 const struct firmware *mc_fw; /* NI MC firmware */ 1499 const struct firmware *ce_fw; /* SI CE firmware */ 1500 struct r600_blit r600_blit; 1501 struct r600_vram_scratch vram_scratch; 1502 int msi_enabled; /* msi enabled */ 1503 struct r600_ih ih; /* r6/700 interrupt ring */ 1504 struct si_rlc rlc; 1505 struct work_struct hotplug_work; 1506 struct work_struct audio_work; 1507 int num_crtc; /* number of crtcs */ 1508 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 1509 bool audio_enabled; 1510 struct r600_audio audio_status; /* audio stuff */ 1511 struct notifier_block acpi_nb; 1512 /* only one userspace can use Hyperz features or CMASK at a time */ 1513 struct drm_file *hyperz_filp; 1514 struct drm_file *cmask_filp; 1515 /* i2c buses */ 1516 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 1517 /* debugfs */ 1518 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 1519 unsigned debugfs_count; 1520 /* virtual memory */ 1521 struct radeon_vm_manager vm_manager; 1522 struct mutex gpu_clock_mutex; 1523 }; 1524 1525 int radeon_device_init(struct radeon_device *rdev, 1526 struct drm_device *ddev, 1527 struct pci_dev *pdev, 1528 uint32_t flags); 1529 void radeon_device_fini(struct radeon_device *rdev); 1530 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 1531 1532 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); 1533 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 1534 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 1535 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 1536 1537 /* 1538 * Cast helper 1539 */ 1540 #define to_radeon_fence(p) ((struct radeon_fence *)(p)) 1541 1542 /* 1543 * Registers read & write functions. 1544 */ 1545 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 1546 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 1547 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 1548 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 1549 #define RREG32(reg) r100_mm_rreg(rdev, (reg)) 1550 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) 1551 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) 1552 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1553 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1554 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 1555 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 1556 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 1557 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 1558 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 1559 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 1560 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) 1561 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 1562 #define WREG32_P(reg, val, mask) \ 1563 do { \ 1564 uint32_t tmp_ = RREG32(reg); \ 1565 tmp_ &= (mask); \ 1566 tmp_ |= ((val) & ~(mask)); \ 1567 WREG32(reg, tmp_); \ 1568 } while (0) 1569 #define WREG32_PLL_P(reg, val, mask) \ 1570 do { \ 1571 uint32_t tmp_ = RREG32_PLL(reg); \ 1572 tmp_ &= (mask); \ 1573 tmp_ |= ((val) & ~(mask)); \ 1574 WREG32_PLL(reg, tmp_); \ 1575 } while (0) 1576 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) 1577 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 1578 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 1579 1580 /* 1581 * Indirect registers accessor 1582 */ 1583 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 1584 { 1585 uint32_t r; 1586 1587 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 1588 r = RREG32(RADEON_PCIE_DATA); 1589 return r; 1590 } 1591 1592 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1593 { 1594 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 1595 WREG32(RADEON_PCIE_DATA, (v)); 1596 } 1597 1598 void r100_pll_errata_after_index(struct radeon_device *rdev); 1599 1600 1601 /* 1602 * ASICs helpers. 1603 */ 1604 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 1605 (rdev->pdev->device == 0x5969)) 1606 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 1607 (rdev->family == CHIP_RV200) || \ 1608 (rdev->family == CHIP_RS100) || \ 1609 (rdev->family == CHIP_RS200) || \ 1610 (rdev->family == CHIP_RV250) || \ 1611 (rdev->family == CHIP_RV280) || \ 1612 (rdev->family == CHIP_RS300)) 1613 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 1614 (rdev->family == CHIP_RV350) || \ 1615 (rdev->family == CHIP_R350) || \ 1616 (rdev->family == CHIP_RV380) || \ 1617 (rdev->family == CHIP_R420) || \ 1618 (rdev->family == CHIP_R423) || \ 1619 (rdev->family == CHIP_RV410) || \ 1620 (rdev->family == CHIP_RS400) || \ 1621 (rdev->family == CHIP_RS480)) 1622 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 1623 (rdev->ddev->pdev->device == 0x9443) || \ 1624 (rdev->ddev->pdev->device == 0x944B) || \ 1625 (rdev->ddev->pdev->device == 0x9506) || \ 1626 (rdev->ddev->pdev->device == 0x9509) || \ 1627 (rdev->ddev->pdev->device == 0x950F) || \ 1628 (rdev->ddev->pdev->device == 0x689C) || \ 1629 (rdev->ddev->pdev->device == 0x689D)) 1630 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 1631 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 1632 (rdev->family == CHIP_RS690) || \ 1633 (rdev->family == CHIP_RS740) || \ 1634 (rdev->family >= CHIP_R600)) 1635 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 1636 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 1637 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 1638 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 1639 (rdev->flags & RADEON_IS_IGP)) 1640 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 1641 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 1642 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 1643 (rdev->flags & RADEON_IS_IGP)) 1644 1645 /* 1646 * BIOS helpers. 1647 */ 1648 #define RBIOS8(i) (rdev->bios[i]) 1649 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1650 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1651 1652 int radeon_combios_init(struct radeon_device *rdev); 1653 void radeon_combios_fini(struct radeon_device *rdev); 1654 int radeon_atombios_init(struct radeon_device *rdev); 1655 void radeon_atombios_fini(struct radeon_device *rdev); 1656 1657 1658 /* 1659 * RING helpers. 1660 */ 1661 #if DRM_DEBUG_CODE == 0 1662 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 1663 { 1664 ring->ring[ring->wptr++] = v; 1665 ring->wptr &= ring->ptr_mask; 1666 ring->count_dw--; 1667 ring->ring_free_dw--; 1668 } 1669 #else 1670 /* With debugging this is just too big to inline */ 1671 void radeon_ring_write(struct radeon_ring *ring, uint32_t v); 1672 #endif 1673 1674 /* 1675 * ASICs macro. 1676 */ 1677 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 1678 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 1679 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 1680 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 1681 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p)) 1682 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 1683 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 1684 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 1685 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) 1686 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) 1687 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) 1688 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) 1689 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) 1690 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) 1691 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) 1692 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 1693 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 1694 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 1695 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) 1696 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 1697 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 1698 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) 1699 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) 1700 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 1701 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 1702 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 1703 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 1704 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 1705 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 1706 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 1707 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 1708 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 1709 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 1710 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 1711 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 1712 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 1713 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 1714 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 1715 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 1716 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 1717 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 1718 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 1719 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 1720 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 1721 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 1722 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 1723 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc)) 1724 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 1725 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) 1726 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 1727 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 1728 1729 /* Common functions */ 1730 /* AGP */ 1731 extern int radeon_gpu_reset(struct radeon_device *rdev); 1732 extern void radeon_agp_disable(struct radeon_device *rdev); 1733 extern int radeon_modeset_init(struct radeon_device *rdev); 1734 extern void radeon_modeset_fini(struct radeon_device *rdev); 1735 extern bool radeon_card_posted(struct radeon_device *rdev); 1736 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 1737 extern void radeon_update_display_priority(struct radeon_device *rdev); 1738 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 1739 extern void radeon_scratch_init(struct radeon_device *rdev); 1740 extern void radeon_wb_fini(struct radeon_device *rdev); 1741 extern int radeon_wb_init(struct radeon_device *rdev); 1742 extern void radeon_wb_disable(struct radeon_device *rdev); 1743 extern void radeon_surface_init(struct radeon_device *rdev); 1744 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 1745 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 1746 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 1747 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 1748 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 1749 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 1750 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 1751 extern int radeon_resume_kms(struct drm_device *dev); 1752 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); 1753 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 1754 1755 /* 1756 * vm 1757 */ 1758 int radeon_vm_manager_init(struct radeon_device *rdev); 1759 void radeon_vm_manager_fini(struct radeon_device *rdev); 1760 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 1761 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 1762 int radeon_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm); 1763 void radeon_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm); 1764 int radeon_vm_bo_update_pte(struct radeon_device *rdev, 1765 struct radeon_vm *vm, 1766 struct radeon_bo *bo, 1767 struct ttm_mem_reg *mem); 1768 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 1769 struct radeon_bo *bo); 1770 int radeon_vm_bo_add(struct radeon_device *rdev, 1771 struct radeon_vm *vm, 1772 struct radeon_bo *bo, 1773 uint64_t offset, 1774 uint32_t flags); 1775 int radeon_vm_bo_rmv(struct radeon_device *rdev, 1776 struct radeon_vm *vm, 1777 struct radeon_bo *bo); 1778 1779 /* audio */ 1780 void r600_audio_update_hdmi(struct work_struct *work); 1781 1782 /* 1783 * R600 vram scratch functions 1784 */ 1785 int r600_vram_scratch_init(struct radeon_device *rdev); 1786 void r600_vram_scratch_fini(struct radeon_device *rdev); 1787 1788 /* 1789 * r600 cs checking helper 1790 */ 1791 unsigned r600_mip_minify(unsigned size, unsigned level); 1792 bool r600_fmt_is_valid_color(u32 format); 1793 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 1794 int r600_fmt_get_blocksize(u32 format); 1795 int r600_fmt_get_nblocksx(u32 format, u32 w); 1796 int r600_fmt_get_nblocksy(u32 format, u32 h); 1797 1798 /* 1799 * r600 functions used by radeon_encoder.c 1800 */ 1801 struct radeon_hdmi_acr { 1802 u32 clock; 1803 1804 int n_32khz; 1805 int cts_32khz; 1806 1807 int n_44_1khz; 1808 int cts_44_1khz; 1809 1810 int n_48khz; 1811 int cts_48khz; 1812 1813 }; 1814 1815 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 1816 1817 extern void r600_hdmi_enable(struct drm_encoder *encoder); 1818 extern void r600_hdmi_disable(struct drm_encoder *encoder); 1819 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 1820 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1821 u32 tiling_pipe_num, 1822 u32 max_rb_num, 1823 u32 total_max_rb_num, 1824 u32 enabled_rb_mask); 1825 1826 /* 1827 * evergreen functions used by radeon_encoder.c 1828 */ 1829 1830 extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 1831 1832 extern int ni_init_microcode(struct radeon_device *rdev); 1833 extern int ni_mc_load_microcode(struct radeon_device *rdev); 1834 1835 /* radeon_acpi.c */ 1836 #if defined(CONFIG_ACPI) 1837 extern int radeon_acpi_init(struct radeon_device *rdev); 1838 #else 1839 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 1840 #endif 1841 1842 #include "radeon_object.h" 1843 1844 #endif 1845