1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 /* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45 /* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63 #include <linux/atomic.h> 64 #include <linux/wait.h> 65 #include <linux/list.h> 66 #include <linux/kref.h> 67 #include <linux/interval_tree.h> 68 69 #include <ttm/ttm_bo_api.h> 70 #include <ttm/ttm_bo_driver.h> 71 #include <ttm/ttm_placement.h> 72 #include <ttm/ttm_module.h> 73 #include <ttm/ttm_execbuf_util.h> 74 75 #include "radeon_family.h" 76 #include "radeon_mode.h" 77 #include "radeon_reg.h" 78 79 /* 80 * Modules parameters. 81 */ 82 extern int radeon_no_wb; 83 extern int radeon_modeset; 84 extern int radeon_dynclks; 85 extern int radeon_r4xx_atom; 86 extern int radeon_agpmode; 87 extern int radeon_vram_limit; 88 extern int radeon_gart_size; 89 extern int radeon_benchmarking; 90 extern int radeon_testing; 91 extern int radeon_connector_table; 92 extern int radeon_tv; 93 extern int radeon_audio; 94 extern int radeon_disp_priority; 95 extern int radeon_hw_i2c; 96 extern int radeon_pcie_gen2; 97 extern int radeon_msi; 98 extern int radeon_lockup_timeout; 99 extern int radeon_fastfb; 100 extern int radeon_dpm; 101 extern int radeon_aspm; 102 extern int radeon_runtime_pm; 103 extern int radeon_hard_reset; 104 extern int radeon_vm_size; 105 extern int radeon_vm_block_size; 106 extern int radeon_deep_color; 107 extern int radeon_use_pflipirq; 108 extern int radeon_bapm; 109 110 /* 111 * Copy from radeon_drv.h so we don't have to include both and have conflicting 112 * symbol; 113 */ 114 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 115 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 116 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 117 #define RADEON_IB_POOL_SIZE 16 118 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 119 #define RADEONFB_CONN_LIMIT 4 120 #define RADEON_BIOS_NUM_SCRATCH 8 121 122 /* fence seq are set to this number when signaled */ 123 #define RADEON_FENCE_SIGNALED_SEQ 0LL 124 125 /* internal ring indices */ 126 /* r1xx+ has gfx CP ring */ 127 #define RADEON_RING_TYPE_GFX_INDEX 0 128 129 /* cayman has 2 compute CP rings */ 130 #define CAYMAN_RING_TYPE_CP1_INDEX 1 131 #define CAYMAN_RING_TYPE_CP2_INDEX 2 132 133 /* R600+ has an async dma ring */ 134 #define R600_RING_TYPE_DMA_INDEX 3 135 /* cayman add a second async dma ring */ 136 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 137 138 /* R600+ */ 139 #define R600_RING_TYPE_UVD_INDEX 5 140 141 /* TN+ */ 142 #define TN_RING_TYPE_VCE1_INDEX 6 143 #define TN_RING_TYPE_VCE2_INDEX 7 144 145 /* max number of rings */ 146 #define RADEON_NUM_RINGS 8 147 148 /* number of hw syncs before falling back on blocking */ 149 #define RADEON_NUM_SYNCS 4 150 151 /* number of hw syncs before falling back on blocking */ 152 #define RADEON_NUM_SYNCS 4 153 154 /* hardcode those limit for now */ 155 #define RADEON_VA_IB_OFFSET (1 << 20) 156 #define RADEON_VA_RESERVED_SIZE (8 << 20) 157 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 158 159 /* hard reset data */ 160 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 161 162 /* reset flags */ 163 #define RADEON_RESET_GFX (1 << 0) 164 #define RADEON_RESET_COMPUTE (1 << 1) 165 #define RADEON_RESET_DMA (1 << 2) 166 #define RADEON_RESET_CP (1 << 3) 167 #define RADEON_RESET_GRBM (1 << 4) 168 #define RADEON_RESET_DMA1 (1 << 5) 169 #define RADEON_RESET_RLC (1 << 6) 170 #define RADEON_RESET_SEM (1 << 7) 171 #define RADEON_RESET_IH (1 << 8) 172 #define RADEON_RESET_VMC (1 << 9) 173 #define RADEON_RESET_MC (1 << 10) 174 #define RADEON_RESET_DISPLAY (1 << 11) 175 176 /* CG block flags */ 177 #define RADEON_CG_BLOCK_GFX (1 << 0) 178 #define RADEON_CG_BLOCK_MC (1 << 1) 179 #define RADEON_CG_BLOCK_SDMA (1 << 2) 180 #define RADEON_CG_BLOCK_UVD (1 << 3) 181 #define RADEON_CG_BLOCK_VCE (1 << 4) 182 #define RADEON_CG_BLOCK_HDP (1 << 5) 183 #define RADEON_CG_BLOCK_BIF (1 << 6) 184 185 /* CG flags */ 186 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 187 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 188 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 189 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 190 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 191 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 192 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 193 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 194 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 195 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 196 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 197 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 198 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 199 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 200 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 201 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 202 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 203 204 /* PG flags */ 205 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 206 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 207 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 208 #define RADEON_PG_SUPPORT_UVD (1 << 3) 209 #define RADEON_PG_SUPPORT_VCE (1 << 4) 210 #define RADEON_PG_SUPPORT_CP (1 << 5) 211 #define RADEON_PG_SUPPORT_GDS (1 << 6) 212 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 213 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 214 #define RADEON_PG_SUPPORT_ACP (1 << 9) 215 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 216 217 /* max cursor sizes (in pixels) */ 218 #define CURSOR_WIDTH 64 219 #define CURSOR_HEIGHT 64 220 221 #define CIK_CURSOR_WIDTH 128 222 #define CIK_CURSOR_HEIGHT 128 223 224 /* 225 * Errata workarounds. 226 */ 227 enum radeon_pll_errata { 228 CHIP_ERRATA_R300_CG = 0x00000001, 229 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 230 CHIP_ERRATA_PLL_DELAY = 0x00000004 231 }; 232 233 234 struct radeon_device; 235 236 237 /* 238 * BIOS. 239 */ 240 bool radeon_get_bios(struct radeon_device *rdev); 241 242 /* 243 * Dummy page 244 */ 245 struct radeon_dummy_page { 246 struct page *page; 247 dma_addr_t addr; 248 }; 249 int radeon_dummy_page_init(struct radeon_device *rdev); 250 void radeon_dummy_page_fini(struct radeon_device *rdev); 251 252 253 /* 254 * Clocks 255 */ 256 struct radeon_clock { 257 struct radeon_pll p1pll; 258 struct radeon_pll p2pll; 259 struct radeon_pll dcpll; 260 struct radeon_pll spll; 261 struct radeon_pll mpll; 262 /* 10 Khz units */ 263 uint32_t default_mclk; 264 uint32_t default_sclk; 265 uint32_t default_dispclk; 266 uint32_t current_dispclk; 267 uint32_t dp_extclk; 268 uint32_t max_pixel_clock; 269 }; 270 271 /* 272 * Power management 273 */ 274 int radeon_pm_init(struct radeon_device *rdev); 275 int radeon_pm_late_init(struct radeon_device *rdev); 276 void radeon_pm_fini(struct radeon_device *rdev); 277 void radeon_pm_compute_clocks(struct radeon_device *rdev); 278 void radeon_pm_suspend(struct radeon_device *rdev); 279 void radeon_pm_resume(struct radeon_device *rdev); 280 void radeon_combios_get_power_modes(struct radeon_device *rdev); 281 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 282 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 283 u8 clock_type, 284 u32 clock, 285 bool strobe_mode, 286 struct atom_clock_dividers *dividers); 287 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 288 u32 clock, 289 bool strobe_mode, 290 struct atom_mpll_param *mpll_param); 291 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 292 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 293 u16 voltage_level, u8 voltage_type, 294 u32 *gpio_value, u32 *gpio_mask); 295 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 296 u32 eng_clock, u32 mem_clock); 297 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 298 u8 voltage_type, u16 *voltage_step); 299 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 300 u16 voltage_id, u16 *voltage); 301 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 302 u16 *voltage, 303 u16 leakage_idx); 304 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 305 u16 *leakage_id); 306 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 307 u16 *vddc, u16 *vddci, 308 u16 virtual_voltage_id, 309 u16 vbios_voltage_id); 310 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 311 u16 virtual_voltage_id, 312 u16 *voltage); 313 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 314 u8 voltage_type, 315 u16 nominal_voltage, 316 u16 *true_voltage); 317 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 318 u8 voltage_type, u16 *min_voltage); 319 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 320 u8 voltage_type, u16 *max_voltage); 321 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 322 u8 voltage_type, u8 voltage_mode, 323 struct atom_voltage_table *voltage_table); 324 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 325 u8 voltage_type, u8 voltage_mode); 326 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 327 u8 voltage_type, 328 u8 *svd_gpio_id, u8 *svc_gpio_id); 329 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 330 u32 mem_clock); 331 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 332 u32 mem_clock); 333 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 334 u8 module_index, 335 struct atom_mc_reg_table *reg_table); 336 int radeon_atom_get_memory_info(struct radeon_device *rdev, 337 u8 module_index, struct atom_memory_info *mem_info); 338 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 339 bool gddr5, u8 module_index, 340 struct atom_memory_clock_range_table *mclk_range_table); 341 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 342 u16 voltage_id, u16 *voltage); 343 void rs690_pm_info(struct radeon_device *rdev); 344 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 345 unsigned *bankh, unsigned *mtaspect, 346 unsigned *tile_split); 347 348 /* 349 * Fences. 350 */ 351 struct radeon_fence_driver { 352 uint32_t scratch_reg; 353 uint64_t gpu_addr; 354 volatile uint32_t *cpu_addr; 355 /* sync_seq is protected by ring emission lock */ 356 uint64_t sync_seq[RADEON_NUM_RINGS]; 357 atomic64_t last_seq; 358 bool initialized; 359 }; 360 361 struct radeon_fence { 362 struct radeon_device *rdev; 363 struct kref kref; 364 /* protected by radeon_fence.lock */ 365 uint64_t seq; 366 /* RB, DMA, etc. */ 367 unsigned ring; 368 }; 369 370 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 371 int radeon_fence_driver_init(struct radeon_device *rdev); 372 void radeon_fence_driver_fini(struct radeon_device *rdev); 373 void radeon_fence_driver_force_completion(struct radeon_device *rdev); 374 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 375 void radeon_fence_process(struct radeon_device *rdev, int ring); 376 bool radeon_fence_signaled(struct radeon_fence *fence); 377 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 378 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 379 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 380 int radeon_fence_wait_any(struct radeon_device *rdev, 381 struct radeon_fence **fences, 382 bool intr); 383 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 384 void radeon_fence_unref(struct radeon_fence **fence); 385 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 386 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 387 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 388 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 389 struct radeon_fence *b) 390 { 391 if (!a) { 392 return b; 393 } 394 395 if (!b) { 396 return a; 397 } 398 399 BUG_ON(a->ring != b->ring); 400 401 if (a->seq > b->seq) { 402 return a; 403 } else { 404 return b; 405 } 406 } 407 408 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 409 struct radeon_fence *b) 410 { 411 if (!a) { 412 return false; 413 } 414 415 if (!b) { 416 return true; 417 } 418 419 BUG_ON(a->ring != b->ring); 420 421 return a->seq < b->seq; 422 } 423 424 /* 425 * Tiling registers 426 */ 427 struct radeon_surface_reg { 428 struct radeon_bo *bo; 429 }; 430 431 #define RADEON_GEM_MAX_SURFACES 8 432 433 /* 434 * TTM. 435 */ 436 struct radeon_mman { 437 struct ttm_bo_global_ref bo_global_ref; 438 struct drm_global_reference mem_global_ref; 439 struct ttm_bo_device bdev; 440 bool mem_global_referenced; 441 bool initialized; 442 443 #if defined(CONFIG_DEBUG_FS) 444 struct dentry *vram; 445 struct dentry *gtt; 446 #endif 447 }; 448 449 /* bo virtual address in a specific vm */ 450 struct radeon_bo_va { 451 /* protected by bo being reserved */ 452 struct list_head bo_list; 453 uint32_t flags; 454 uint64_t addr; 455 unsigned ref_count; 456 457 /* protected by vm mutex */ 458 struct interval_tree_node it; 459 struct list_head vm_status; 460 461 /* constant after initialization */ 462 struct radeon_vm *vm; 463 struct radeon_bo *bo; 464 }; 465 466 struct radeon_bo { 467 /* Protected by gem.mutex */ 468 struct list_head list; 469 /* Protected by tbo.reserved */ 470 u32 initial_domain; 471 u32 placements[3]; 472 struct ttm_placement placement; 473 struct ttm_buffer_object tbo; 474 struct ttm_bo_kmap_obj kmap; 475 u32 flags; 476 unsigned pin_count; 477 void *kptr; 478 u32 tiling_flags; 479 u32 pitch; 480 int surface_reg; 481 /* list of all virtual address to which this bo 482 * is associated to 483 */ 484 struct list_head va; 485 /* Constant after initialization */ 486 struct radeon_device *rdev; 487 struct drm_gem_object gem_base; 488 489 struct ttm_bo_kmap_obj dma_buf_vmap; 490 pid_t pid; 491 }; 492 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 493 494 int radeon_gem_debugfs_init(struct radeon_device *rdev); 495 496 /* sub-allocation manager, it has to be protected by another lock. 497 * By conception this is an helper for other part of the driver 498 * like the indirect buffer or semaphore, which both have their 499 * locking. 500 * 501 * Principe is simple, we keep a list of sub allocation in offset 502 * order (first entry has offset == 0, last entry has the highest 503 * offset). 504 * 505 * When allocating new object we first check if there is room at 506 * the end total_size - (last_object_offset + last_object_size) >= 507 * alloc_size. If so we allocate new object there. 508 * 509 * When there is not enough room at the end, we start waiting for 510 * each sub object until we reach object_offset+object_size >= 511 * alloc_size, this object then become the sub object we return. 512 * 513 * Alignment can't be bigger than page size. 514 * 515 * Hole are not considered for allocation to keep things simple. 516 * Assumption is that there won't be hole (all object on same 517 * alignment). 518 */ 519 struct radeon_sa_manager { 520 wait_queue_head_t wq; 521 struct radeon_bo *bo; 522 struct list_head *hole; 523 struct list_head flist[RADEON_NUM_RINGS]; 524 struct list_head olist; 525 unsigned size; 526 uint64_t gpu_addr; 527 void *cpu_ptr; 528 uint32_t domain; 529 uint32_t align; 530 }; 531 532 struct radeon_sa_bo; 533 534 /* sub-allocation buffer */ 535 struct radeon_sa_bo { 536 struct list_head olist; 537 struct list_head flist; 538 struct radeon_sa_manager *manager; 539 unsigned soffset; 540 unsigned eoffset; 541 struct radeon_fence *fence; 542 }; 543 544 /* 545 * GEM objects. 546 */ 547 struct radeon_gem { 548 struct mutex mutex; 549 struct list_head objects; 550 }; 551 552 int radeon_gem_init(struct radeon_device *rdev); 553 void radeon_gem_fini(struct radeon_device *rdev); 554 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 555 int alignment, int initial_domain, 556 u32 flags, bool kernel, 557 struct drm_gem_object **obj); 558 559 int radeon_mode_dumb_create(struct drm_file *file_priv, 560 struct drm_device *dev, 561 struct drm_mode_create_dumb *args); 562 int radeon_mode_dumb_mmap(struct drm_file *filp, 563 struct drm_device *dev, 564 uint32_t handle, uint64_t *offset_p); 565 566 /* 567 * Semaphores. 568 */ 569 struct radeon_semaphore { 570 struct radeon_sa_bo *sa_bo; 571 signed waiters; 572 uint64_t gpu_addr; 573 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 574 }; 575 576 int radeon_semaphore_create(struct radeon_device *rdev, 577 struct radeon_semaphore **semaphore); 578 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 579 struct radeon_semaphore *semaphore); 580 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 581 struct radeon_semaphore *semaphore); 582 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore, 583 struct radeon_fence *fence); 584 int radeon_semaphore_sync_rings(struct radeon_device *rdev, 585 struct radeon_semaphore *semaphore, 586 int waiting_ring); 587 void radeon_semaphore_free(struct radeon_device *rdev, 588 struct radeon_semaphore **semaphore, 589 struct radeon_fence *fence); 590 591 /* 592 * GART structures, functions & helpers 593 */ 594 struct radeon_mc; 595 596 #define RADEON_GPU_PAGE_SIZE 4096 597 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 598 #define RADEON_GPU_PAGE_SHIFT 12 599 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 600 601 #define RADEON_GART_PAGE_DUMMY 0 602 #define RADEON_GART_PAGE_VALID (1 << 0) 603 #define RADEON_GART_PAGE_READ (1 << 1) 604 #define RADEON_GART_PAGE_WRITE (1 << 2) 605 #define RADEON_GART_PAGE_SNOOP (1 << 3) 606 607 struct radeon_gart { 608 dma_addr_t table_addr; 609 struct radeon_bo *robj; 610 void *ptr; 611 unsigned num_gpu_pages; 612 unsigned num_cpu_pages; 613 unsigned table_size; 614 struct page **pages; 615 dma_addr_t *pages_addr; 616 bool ready; 617 }; 618 619 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 620 void radeon_gart_table_ram_free(struct radeon_device *rdev); 621 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 622 void radeon_gart_table_vram_free(struct radeon_device *rdev); 623 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 624 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 625 int radeon_gart_init(struct radeon_device *rdev); 626 void radeon_gart_fini(struct radeon_device *rdev); 627 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 628 int pages); 629 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 630 int pages, struct page **pagelist, 631 dma_addr_t *dma_addr, uint32_t flags); 632 633 634 /* 635 * GPU MC structures, functions & helpers 636 */ 637 struct radeon_mc { 638 resource_size_t aper_size; 639 resource_size_t aper_base; 640 resource_size_t agp_base; 641 /* for some chips with <= 32MB we need to lie 642 * about vram size near mc fb location */ 643 u64 mc_vram_size; 644 u64 visible_vram_size; 645 u64 gtt_size; 646 u64 gtt_start; 647 u64 gtt_end; 648 u64 vram_start; 649 u64 vram_end; 650 unsigned vram_width; 651 u64 real_vram_size; 652 int vram_mtrr; 653 bool vram_is_ddr; 654 bool igp_sideport_enabled; 655 u64 gtt_base_align; 656 u64 mc_mask; 657 }; 658 659 bool radeon_combios_sideport_present(struct radeon_device *rdev); 660 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 661 662 /* 663 * GPU scratch registers structures, functions & helpers 664 */ 665 struct radeon_scratch { 666 unsigned num_reg; 667 uint32_t reg_base; 668 bool free[32]; 669 uint32_t reg[32]; 670 }; 671 672 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 673 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 674 675 /* 676 * GPU doorbell structures, functions & helpers 677 */ 678 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 679 680 struct radeon_doorbell { 681 /* doorbell mmio */ 682 resource_size_t base; 683 resource_size_t size; 684 u32 __iomem *ptr; 685 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 686 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)]; 687 }; 688 689 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 690 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 691 692 /* 693 * IRQS. 694 */ 695 696 struct radeon_flip_work { 697 struct work_struct flip_work; 698 struct work_struct unpin_work; 699 struct radeon_device *rdev; 700 int crtc_id; 701 uint64_t base; 702 struct drm_pending_vblank_event *event; 703 struct radeon_bo *old_rbo; 704 struct radeon_fence *fence; 705 }; 706 707 struct r500_irq_stat_regs { 708 u32 disp_int; 709 u32 hdmi0_status; 710 }; 711 712 struct r600_irq_stat_regs { 713 u32 disp_int; 714 u32 disp_int_cont; 715 u32 disp_int_cont2; 716 u32 d1grph_int; 717 u32 d2grph_int; 718 u32 hdmi0_status; 719 u32 hdmi1_status; 720 }; 721 722 struct evergreen_irq_stat_regs { 723 u32 disp_int; 724 u32 disp_int_cont; 725 u32 disp_int_cont2; 726 u32 disp_int_cont3; 727 u32 disp_int_cont4; 728 u32 disp_int_cont5; 729 u32 d1grph_int; 730 u32 d2grph_int; 731 u32 d3grph_int; 732 u32 d4grph_int; 733 u32 d5grph_int; 734 u32 d6grph_int; 735 u32 afmt_status1; 736 u32 afmt_status2; 737 u32 afmt_status3; 738 u32 afmt_status4; 739 u32 afmt_status5; 740 u32 afmt_status6; 741 }; 742 743 struct cik_irq_stat_regs { 744 u32 disp_int; 745 u32 disp_int_cont; 746 u32 disp_int_cont2; 747 u32 disp_int_cont3; 748 u32 disp_int_cont4; 749 u32 disp_int_cont5; 750 u32 disp_int_cont6; 751 u32 d1grph_int; 752 u32 d2grph_int; 753 u32 d3grph_int; 754 u32 d4grph_int; 755 u32 d5grph_int; 756 u32 d6grph_int; 757 }; 758 759 union radeon_irq_stat_regs { 760 struct r500_irq_stat_regs r500; 761 struct r600_irq_stat_regs r600; 762 struct evergreen_irq_stat_regs evergreen; 763 struct cik_irq_stat_regs cik; 764 }; 765 766 struct radeon_irq { 767 bool installed; 768 spinlock_t lock; 769 atomic_t ring_int[RADEON_NUM_RINGS]; 770 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 771 atomic_t pflip[RADEON_MAX_CRTCS]; 772 wait_queue_head_t vblank_queue; 773 bool hpd[RADEON_MAX_HPD_PINS]; 774 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 775 union radeon_irq_stat_regs stat_regs; 776 bool dpm_thermal; 777 }; 778 779 int radeon_irq_kms_init(struct radeon_device *rdev); 780 void radeon_irq_kms_fini(struct radeon_device *rdev); 781 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 782 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 783 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 784 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 785 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 786 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 787 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 788 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 789 790 /* 791 * CP & rings. 792 */ 793 794 struct radeon_ib { 795 struct radeon_sa_bo *sa_bo; 796 uint32_t length_dw; 797 uint64_t gpu_addr; 798 uint32_t *ptr; 799 int ring; 800 struct radeon_fence *fence; 801 struct radeon_vm *vm; 802 bool is_const_ib; 803 struct radeon_semaphore *semaphore; 804 }; 805 806 struct radeon_ring { 807 struct radeon_bo *ring_obj; 808 volatile uint32_t *ring; 809 unsigned rptr_offs; 810 unsigned rptr_save_reg; 811 u64 next_rptr_gpu_addr; 812 volatile u32 *next_rptr_cpu_addr; 813 unsigned wptr; 814 unsigned wptr_old; 815 unsigned ring_size; 816 unsigned ring_free_dw; 817 int count_dw; 818 atomic_t last_rptr; 819 atomic64_t last_activity; 820 uint64_t gpu_addr; 821 uint32_t align_mask; 822 uint32_t ptr_mask; 823 bool ready; 824 u32 nop; 825 u32 idx; 826 u64 last_semaphore_signal_addr; 827 u64 last_semaphore_wait_addr; 828 /* for CIK queues */ 829 u32 me; 830 u32 pipe; 831 u32 queue; 832 struct radeon_bo *mqd_obj; 833 u32 doorbell_index; 834 unsigned wptr_offs; 835 }; 836 837 struct radeon_mec { 838 struct radeon_bo *hpd_eop_obj; 839 u64 hpd_eop_gpu_addr; 840 u32 num_pipe; 841 u32 num_mec; 842 u32 num_queue; 843 }; 844 845 /* 846 * VM 847 */ 848 849 /* maximum number of VMIDs */ 850 #define RADEON_NUM_VM 16 851 852 /* number of entries in page table */ 853 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 854 855 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 856 #define RADEON_VM_PTB_ALIGN_SIZE 32768 857 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 858 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 859 860 #define R600_PTE_VALID (1 << 0) 861 #define R600_PTE_SYSTEM (1 << 1) 862 #define R600_PTE_SNOOPED (1 << 2) 863 #define R600_PTE_READABLE (1 << 5) 864 #define R600_PTE_WRITEABLE (1 << 6) 865 866 /* PTE (Page Table Entry) fragment field for different page sizes */ 867 #define R600_PTE_FRAG_4KB (0 << 7) 868 #define R600_PTE_FRAG_64KB (4 << 7) 869 #define R600_PTE_FRAG_256KB (6 << 7) 870 871 /* flags needed to be set so we can copy directly from the GART table */ 872 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 873 R600_PTE_SYSTEM | R600_PTE_VALID ) 874 875 struct radeon_vm_pt { 876 struct radeon_bo *bo; 877 uint64_t addr; 878 }; 879 880 struct radeon_vm { 881 struct rb_root va; 882 unsigned id; 883 884 /* BOs moved, but not yet updated in the PT */ 885 struct list_head invalidated; 886 887 /* BOs freed, but not yet updated in the PT */ 888 struct list_head freed; 889 890 /* contains the page directory */ 891 struct radeon_bo *page_directory; 892 uint64_t pd_gpu_addr; 893 unsigned max_pde_used; 894 895 /* array of page tables, one for each page directory entry */ 896 struct radeon_vm_pt *page_tables; 897 898 struct radeon_bo_va *ib_bo_va; 899 900 struct mutex mutex; 901 /* last fence for cs using this vm */ 902 struct radeon_fence *fence; 903 /* last flush or NULL if we still need to flush */ 904 struct radeon_fence *last_flush; 905 /* last use of vmid */ 906 struct radeon_fence *last_id_use; 907 }; 908 909 struct radeon_vm_manager { 910 struct radeon_fence *active[RADEON_NUM_VM]; 911 uint32_t max_pfn; 912 /* number of VMIDs */ 913 unsigned nvm; 914 /* vram base address for page table entry */ 915 u64 vram_base_offset; 916 /* is vm enabled? */ 917 bool enabled; 918 }; 919 920 /* 921 * file private structure 922 */ 923 struct radeon_fpriv { 924 struct radeon_vm vm; 925 }; 926 927 /* 928 * R6xx+ IH ring 929 */ 930 struct r600_ih { 931 struct radeon_bo *ring_obj; 932 volatile uint32_t *ring; 933 unsigned rptr; 934 unsigned ring_size; 935 uint64_t gpu_addr; 936 uint32_t ptr_mask; 937 atomic_t lock; 938 bool enabled; 939 }; 940 941 /* 942 * RLC stuff 943 */ 944 #include "clearstate_defs.h" 945 946 struct radeon_rlc { 947 /* for power gating */ 948 struct radeon_bo *save_restore_obj; 949 uint64_t save_restore_gpu_addr; 950 volatile uint32_t *sr_ptr; 951 const u32 *reg_list; 952 u32 reg_list_size; 953 /* for clear state */ 954 struct radeon_bo *clear_state_obj; 955 uint64_t clear_state_gpu_addr; 956 volatile uint32_t *cs_ptr; 957 const struct cs_section_def *cs_data; 958 u32 clear_state_size; 959 /* for cp tables */ 960 struct radeon_bo *cp_table_obj; 961 uint64_t cp_table_gpu_addr; 962 volatile uint32_t *cp_table_ptr; 963 u32 cp_table_size; 964 }; 965 966 int radeon_ib_get(struct radeon_device *rdev, int ring, 967 struct radeon_ib *ib, struct radeon_vm *vm, 968 unsigned size); 969 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 970 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 971 struct radeon_ib *const_ib, bool hdp_flush); 972 int radeon_ib_pool_init(struct radeon_device *rdev); 973 void radeon_ib_pool_fini(struct radeon_device *rdev); 974 int radeon_ib_ring_tests(struct radeon_device *rdev); 975 /* Ring access between begin & end cannot sleep */ 976 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 977 struct radeon_ring *ring); 978 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 979 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 980 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 981 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 982 bool hdp_flush); 983 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 984 bool hdp_flush); 985 void radeon_ring_undo(struct radeon_ring *ring); 986 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 987 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 988 void radeon_ring_lockup_update(struct radeon_device *rdev, 989 struct radeon_ring *ring); 990 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 991 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 992 uint32_t **data); 993 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 994 unsigned size, uint32_t *data); 995 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 996 unsigned rptr_offs, u32 nop); 997 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 998 999 1000 /* r600 async dma */ 1001 void r600_dma_stop(struct radeon_device *rdev); 1002 int r600_dma_resume(struct radeon_device *rdev); 1003 void r600_dma_fini(struct radeon_device *rdev); 1004 1005 void cayman_dma_stop(struct radeon_device *rdev); 1006 int cayman_dma_resume(struct radeon_device *rdev); 1007 void cayman_dma_fini(struct radeon_device *rdev); 1008 1009 /* 1010 * CS. 1011 */ 1012 struct radeon_cs_reloc { 1013 struct drm_gem_object *gobj; 1014 struct radeon_bo *robj; 1015 struct ttm_validate_buffer tv; 1016 uint64_t gpu_offset; 1017 unsigned prefered_domains; 1018 unsigned allowed_domains; 1019 uint32_t tiling_flags; 1020 uint32_t handle; 1021 }; 1022 1023 struct radeon_cs_chunk { 1024 uint32_t chunk_id; 1025 uint32_t length_dw; 1026 uint32_t *kdata; 1027 void __user *user_ptr; 1028 }; 1029 1030 struct radeon_cs_parser { 1031 struct device *dev; 1032 struct radeon_device *rdev; 1033 struct drm_file *filp; 1034 /* chunks */ 1035 unsigned nchunks; 1036 struct radeon_cs_chunk *chunks; 1037 uint64_t *chunks_array; 1038 /* IB */ 1039 unsigned idx; 1040 /* relocations */ 1041 unsigned nrelocs; 1042 struct radeon_cs_reloc *relocs; 1043 struct radeon_cs_reloc **relocs_ptr; 1044 struct radeon_cs_reloc *vm_bos; 1045 struct list_head validated; 1046 unsigned dma_reloc_idx; 1047 /* indices of various chunks */ 1048 int chunk_ib_idx; 1049 int chunk_relocs_idx; 1050 int chunk_flags_idx; 1051 int chunk_const_ib_idx; 1052 struct radeon_ib ib; 1053 struct radeon_ib const_ib; 1054 void *track; 1055 unsigned family; 1056 int parser_error; 1057 u32 cs_flags; 1058 u32 ring; 1059 s32 priority; 1060 struct ww_acquire_ctx ticket; 1061 }; 1062 1063 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1064 { 1065 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 1066 1067 if (ibc->kdata) 1068 return ibc->kdata[idx]; 1069 return p->ib.ptr[idx]; 1070 } 1071 1072 1073 struct radeon_cs_packet { 1074 unsigned idx; 1075 unsigned type; 1076 unsigned reg; 1077 unsigned opcode; 1078 int count; 1079 unsigned one_reg_wr; 1080 }; 1081 1082 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1083 struct radeon_cs_packet *pkt, 1084 unsigned idx, unsigned reg); 1085 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1086 struct radeon_cs_packet *pkt); 1087 1088 1089 /* 1090 * AGP 1091 */ 1092 int radeon_agp_init(struct radeon_device *rdev); 1093 void radeon_agp_resume(struct radeon_device *rdev); 1094 void radeon_agp_suspend(struct radeon_device *rdev); 1095 void radeon_agp_fini(struct radeon_device *rdev); 1096 1097 1098 /* 1099 * Writeback 1100 */ 1101 struct radeon_wb { 1102 struct radeon_bo *wb_obj; 1103 volatile uint32_t *wb; 1104 uint64_t gpu_addr; 1105 bool enabled; 1106 bool use_event; 1107 }; 1108 1109 #define RADEON_WB_SCRATCH_OFFSET 0 1110 #define RADEON_WB_RING0_NEXT_RPTR 256 1111 #define RADEON_WB_CP_RPTR_OFFSET 1024 1112 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1113 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1114 #define R600_WB_DMA_RPTR_OFFSET 1792 1115 #define R600_WB_IH_WPTR_OFFSET 2048 1116 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1117 #define R600_WB_EVENT_OFFSET 3072 1118 #define CIK_WB_CP1_WPTR_OFFSET 3328 1119 #define CIK_WB_CP2_WPTR_OFFSET 3584 1120 1121 /** 1122 * struct radeon_pm - power management datas 1123 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1124 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1125 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1126 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1127 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1128 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1129 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1130 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1131 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1132 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1133 * @needed_bandwidth: current bandwidth needs 1134 * 1135 * It keeps track of various data needed to take powermanagement decision. 1136 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1137 * Equation between gpu/memory clock and available bandwidth is hw dependent 1138 * (type of memory, bus size, efficiency, ...) 1139 */ 1140 1141 enum radeon_pm_method { 1142 PM_METHOD_PROFILE, 1143 PM_METHOD_DYNPM, 1144 PM_METHOD_DPM, 1145 }; 1146 1147 enum radeon_dynpm_state { 1148 DYNPM_STATE_DISABLED, 1149 DYNPM_STATE_MINIMUM, 1150 DYNPM_STATE_PAUSED, 1151 DYNPM_STATE_ACTIVE, 1152 DYNPM_STATE_SUSPENDED, 1153 }; 1154 enum radeon_dynpm_action { 1155 DYNPM_ACTION_NONE, 1156 DYNPM_ACTION_MINIMUM, 1157 DYNPM_ACTION_DOWNCLOCK, 1158 DYNPM_ACTION_UPCLOCK, 1159 DYNPM_ACTION_DEFAULT 1160 }; 1161 1162 enum radeon_voltage_type { 1163 VOLTAGE_NONE = 0, 1164 VOLTAGE_GPIO, 1165 VOLTAGE_VDDC, 1166 VOLTAGE_SW 1167 }; 1168 1169 enum radeon_pm_state_type { 1170 /* not used for dpm */ 1171 POWER_STATE_TYPE_DEFAULT, 1172 POWER_STATE_TYPE_POWERSAVE, 1173 /* user selectable states */ 1174 POWER_STATE_TYPE_BATTERY, 1175 POWER_STATE_TYPE_BALANCED, 1176 POWER_STATE_TYPE_PERFORMANCE, 1177 /* internal states */ 1178 POWER_STATE_TYPE_INTERNAL_UVD, 1179 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1180 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1181 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1182 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1183 POWER_STATE_TYPE_INTERNAL_BOOT, 1184 POWER_STATE_TYPE_INTERNAL_THERMAL, 1185 POWER_STATE_TYPE_INTERNAL_ACPI, 1186 POWER_STATE_TYPE_INTERNAL_ULV, 1187 POWER_STATE_TYPE_INTERNAL_3DPERF, 1188 }; 1189 1190 enum radeon_pm_profile_type { 1191 PM_PROFILE_DEFAULT, 1192 PM_PROFILE_AUTO, 1193 PM_PROFILE_LOW, 1194 PM_PROFILE_MID, 1195 PM_PROFILE_HIGH, 1196 }; 1197 1198 #define PM_PROFILE_DEFAULT_IDX 0 1199 #define PM_PROFILE_LOW_SH_IDX 1 1200 #define PM_PROFILE_MID_SH_IDX 2 1201 #define PM_PROFILE_HIGH_SH_IDX 3 1202 #define PM_PROFILE_LOW_MH_IDX 4 1203 #define PM_PROFILE_MID_MH_IDX 5 1204 #define PM_PROFILE_HIGH_MH_IDX 6 1205 #define PM_PROFILE_MAX 7 1206 1207 struct radeon_pm_profile { 1208 int dpms_off_ps_idx; 1209 int dpms_on_ps_idx; 1210 int dpms_off_cm_idx; 1211 int dpms_on_cm_idx; 1212 }; 1213 1214 enum radeon_int_thermal_type { 1215 THERMAL_TYPE_NONE, 1216 THERMAL_TYPE_EXTERNAL, 1217 THERMAL_TYPE_EXTERNAL_GPIO, 1218 THERMAL_TYPE_RV6XX, 1219 THERMAL_TYPE_RV770, 1220 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1221 THERMAL_TYPE_EVERGREEN, 1222 THERMAL_TYPE_SUMO, 1223 THERMAL_TYPE_NI, 1224 THERMAL_TYPE_SI, 1225 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1226 THERMAL_TYPE_CI, 1227 THERMAL_TYPE_KV, 1228 }; 1229 1230 struct radeon_voltage { 1231 enum radeon_voltage_type type; 1232 /* gpio voltage */ 1233 struct radeon_gpio_rec gpio; 1234 u32 delay; /* delay in usec from voltage drop to sclk change */ 1235 bool active_high; /* voltage drop is active when bit is high */ 1236 /* VDDC voltage */ 1237 u8 vddc_id; /* index into vddc voltage table */ 1238 u8 vddci_id; /* index into vddci voltage table */ 1239 bool vddci_enabled; 1240 /* r6xx+ sw */ 1241 u16 voltage; 1242 /* evergreen+ vddci */ 1243 u16 vddci; 1244 }; 1245 1246 /* clock mode flags */ 1247 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1248 1249 struct radeon_pm_clock_info { 1250 /* memory clock */ 1251 u32 mclk; 1252 /* engine clock */ 1253 u32 sclk; 1254 /* voltage info */ 1255 struct radeon_voltage voltage; 1256 /* standardized clock flags */ 1257 u32 flags; 1258 }; 1259 1260 /* state flags */ 1261 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1262 1263 struct radeon_power_state { 1264 enum radeon_pm_state_type type; 1265 struct radeon_pm_clock_info *clock_info; 1266 /* number of valid clock modes in this power state */ 1267 int num_clock_modes; 1268 struct radeon_pm_clock_info *default_clock_mode; 1269 /* standardized state flags */ 1270 u32 flags; 1271 u32 misc; /* vbios specific flags */ 1272 u32 misc2; /* vbios specific flags */ 1273 int pcie_lanes; /* pcie lanes */ 1274 }; 1275 1276 /* 1277 * Some modes are overclocked by very low value, accept them 1278 */ 1279 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1280 1281 enum radeon_dpm_auto_throttle_src { 1282 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1283 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1284 }; 1285 1286 enum radeon_dpm_event_src { 1287 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1288 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1289 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1290 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1291 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1292 }; 1293 1294 #define RADEON_MAX_VCE_LEVELS 6 1295 1296 enum radeon_vce_level { 1297 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1298 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1299 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1300 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1301 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1302 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1303 }; 1304 1305 struct radeon_ps { 1306 u32 caps; /* vbios flags */ 1307 u32 class; /* vbios flags */ 1308 u32 class2; /* vbios flags */ 1309 /* UVD clocks */ 1310 u32 vclk; 1311 u32 dclk; 1312 /* VCE clocks */ 1313 u32 evclk; 1314 u32 ecclk; 1315 bool vce_active; 1316 enum radeon_vce_level vce_level; 1317 /* asic priv */ 1318 void *ps_priv; 1319 }; 1320 1321 struct radeon_dpm_thermal { 1322 /* thermal interrupt work */ 1323 struct work_struct work; 1324 /* low temperature threshold */ 1325 int min_temp; 1326 /* high temperature threshold */ 1327 int max_temp; 1328 /* was interrupt low to high or high to low */ 1329 bool high_to_low; 1330 }; 1331 1332 enum radeon_clk_action 1333 { 1334 RADEON_SCLK_UP = 1, 1335 RADEON_SCLK_DOWN 1336 }; 1337 1338 struct radeon_blacklist_clocks 1339 { 1340 u32 sclk; 1341 u32 mclk; 1342 enum radeon_clk_action action; 1343 }; 1344 1345 struct radeon_clock_and_voltage_limits { 1346 u32 sclk; 1347 u32 mclk; 1348 u16 vddc; 1349 u16 vddci; 1350 }; 1351 1352 struct radeon_clock_array { 1353 u32 count; 1354 u32 *values; 1355 }; 1356 1357 struct radeon_clock_voltage_dependency_entry { 1358 u32 clk; 1359 u16 v; 1360 }; 1361 1362 struct radeon_clock_voltage_dependency_table { 1363 u32 count; 1364 struct radeon_clock_voltage_dependency_entry *entries; 1365 }; 1366 1367 union radeon_cac_leakage_entry { 1368 struct { 1369 u16 vddc; 1370 u32 leakage; 1371 }; 1372 struct { 1373 u16 vddc1; 1374 u16 vddc2; 1375 u16 vddc3; 1376 }; 1377 }; 1378 1379 struct radeon_cac_leakage_table { 1380 u32 count; 1381 union radeon_cac_leakage_entry *entries; 1382 }; 1383 1384 struct radeon_phase_shedding_limits_entry { 1385 u16 voltage; 1386 u32 sclk; 1387 u32 mclk; 1388 }; 1389 1390 struct radeon_phase_shedding_limits_table { 1391 u32 count; 1392 struct radeon_phase_shedding_limits_entry *entries; 1393 }; 1394 1395 struct radeon_uvd_clock_voltage_dependency_entry { 1396 u32 vclk; 1397 u32 dclk; 1398 u16 v; 1399 }; 1400 1401 struct radeon_uvd_clock_voltage_dependency_table { 1402 u8 count; 1403 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1404 }; 1405 1406 struct radeon_vce_clock_voltage_dependency_entry { 1407 u32 ecclk; 1408 u32 evclk; 1409 u16 v; 1410 }; 1411 1412 struct radeon_vce_clock_voltage_dependency_table { 1413 u8 count; 1414 struct radeon_vce_clock_voltage_dependency_entry *entries; 1415 }; 1416 1417 struct radeon_ppm_table { 1418 u8 ppm_design; 1419 u16 cpu_core_number; 1420 u32 platform_tdp; 1421 u32 small_ac_platform_tdp; 1422 u32 platform_tdc; 1423 u32 small_ac_platform_tdc; 1424 u32 apu_tdp; 1425 u32 dgpu_tdp; 1426 u32 dgpu_ulv_power; 1427 u32 tj_max; 1428 }; 1429 1430 struct radeon_cac_tdp_table { 1431 u16 tdp; 1432 u16 configurable_tdp; 1433 u16 tdc; 1434 u16 battery_power_limit; 1435 u16 small_power_limit; 1436 u16 low_cac_leakage; 1437 u16 high_cac_leakage; 1438 u16 maximum_power_delivery_limit; 1439 }; 1440 1441 struct radeon_dpm_dynamic_state { 1442 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1443 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1444 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1445 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1446 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1447 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1448 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1449 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1450 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1451 struct radeon_clock_array valid_sclk_values; 1452 struct radeon_clock_array valid_mclk_values; 1453 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1454 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1455 u32 mclk_sclk_ratio; 1456 u32 sclk_mclk_delta; 1457 u16 vddc_vddci_delta; 1458 u16 min_vddc_for_pcie_gen2; 1459 struct radeon_cac_leakage_table cac_leakage_table; 1460 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1461 struct radeon_ppm_table *ppm_table; 1462 struct radeon_cac_tdp_table *cac_tdp_table; 1463 }; 1464 1465 struct radeon_dpm_fan { 1466 u16 t_min; 1467 u16 t_med; 1468 u16 t_high; 1469 u16 pwm_min; 1470 u16 pwm_med; 1471 u16 pwm_high; 1472 u8 t_hyst; 1473 u32 cycle_delay; 1474 u16 t_max; 1475 bool ucode_fan_control; 1476 }; 1477 1478 enum radeon_pcie_gen { 1479 RADEON_PCIE_GEN1 = 0, 1480 RADEON_PCIE_GEN2 = 1, 1481 RADEON_PCIE_GEN3 = 2, 1482 RADEON_PCIE_GEN_INVALID = 0xffff 1483 }; 1484 1485 enum radeon_dpm_forced_level { 1486 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1487 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1488 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1489 }; 1490 1491 struct radeon_vce_state { 1492 /* vce clocks */ 1493 u32 evclk; 1494 u32 ecclk; 1495 /* gpu clocks */ 1496 u32 sclk; 1497 u32 mclk; 1498 u8 clk_idx; 1499 u8 pstate; 1500 }; 1501 1502 struct radeon_dpm { 1503 struct radeon_ps *ps; 1504 /* number of valid power states */ 1505 int num_ps; 1506 /* current power state that is active */ 1507 struct radeon_ps *current_ps; 1508 /* requested power state */ 1509 struct radeon_ps *requested_ps; 1510 /* boot up power state */ 1511 struct radeon_ps *boot_ps; 1512 /* default uvd power state */ 1513 struct radeon_ps *uvd_ps; 1514 /* vce requirements */ 1515 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1516 enum radeon_vce_level vce_level; 1517 enum radeon_pm_state_type state; 1518 enum radeon_pm_state_type user_state; 1519 u32 platform_caps; 1520 u32 voltage_response_time; 1521 u32 backbias_response_time; 1522 void *priv; 1523 u32 new_active_crtcs; 1524 int new_active_crtc_count; 1525 u32 current_active_crtcs; 1526 int current_active_crtc_count; 1527 struct radeon_dpm_dynamic_state dyn_state; 1528 struct radeon_dpm_fan fan; 1529 u32 tdp_limit; 1530 u32 near_tdp_limit; 1531 u32 near_tdp_limit_adjusted; 1532 u32 sq_ramping_threshold; 1533 u32 cac_leakage; 1534 u16 tdp_od_limit; 1535 u32 tdp_adjustment; 1536 u16 load_line_slope; 1537 bool power_control; 1538 bool ac_power; 1539 /* special states active */ 1540 bool thermal_active; 1541 bool uvd_active; 1542 bool vce_active; 1543 /* thermal handling */ 1544 struct radeon_dpm_thermal thermal; 1545 /* forced levels */ 1546 enum radeon_dpm_forced_level forced_level; 1547 /* track UVD streams */ 1548 unsigned sd; 1549 unsigned hd; 1550 }; 1551 1552 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1553 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1554 1555 struct radeon_pm { 1556 struct mutex mutex; 1557 /* write locked while reprogramming mclk */ 1558 struct rw_semaphore mclk_lock; 1559 u32 active_crtcs; 1560 int active_crtc_count; 1561 int req_vblank; 1562 bool vblank_sync; 1563 fixed20_12 max_bandwidth; 1564 fixed20_12 igp_sideport_mclk; 1565 fixed20_12 igp_system_mclk; 1566 fixed20_12 igp_ht_link_clk; 1567 fixed20_12 igp_ht_link_width; 1568 fixed20_12 k8_bandwidth; 1569 fixed20_12 sideport_bandwidth; 1570 fixed20_12 ht_bandwidth; 1571 fixed20_12 core_bandwidth; 1572 fixed20_12 sclk; 1573 fixed20_12 mclk; 1574 fixed20_12 needed_bandwidth; 1575 struct radeon_power_state *power_state; 1576 /* number of valid power states */ 1577 int num_power_states; 1578 int current_power_state_index; 1579 int current_clock_mode_index; 1580 int requested_power_state_index; 1581 int requested_clock_mode_index; 1582 int default_power_state_index; 1583 u32 current_sclk; 1584 u32 current_mclk; 1585 u16 current_vddc; 1586 u16 current_vddci; 1587 u32 default_sclk; 1588 u32 default_mclk; 1589 u16 default_vddc; 1590 u16 default_vddci; 1591 struct radeon_i2c_chan *i2c_bus; 1592 /* selected pm method */ 1593 enum radeon_pm_method pm_method; 1594 /* dynpm power management */ 1595 struct delayed_work dynpm_idle_work; 1596 enum radeon_dynpm_state dynpm_state; 1597 enum radeon_dynpm_action dynpm_planned_action; 1598 unsigned long dynpm_action_timeout; 1599 bool dynpm_can_upclock; 1600 bool dynpm_can_downclock; 1601 /* profile-based power management */ 1602 enum radeon_pm_profile_type profile; 1603 int profile_index; 1604 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1605 /* internal thermal controller on rv6xx+ */ 1606 enum radeon_int_thermal_type int_thermal_type; 1607 struct device *int_hwmon_dev; 1608 /* dpm */ 1609 bool dpm_enabled; 1610 struct radeon_dpm dpm; 1611 }; 1612 1613 int radeon_pm_get_type_index(struct radeon_device *rdev, 1614 enum radeon_pm_state_type ps_type, 1615 int instance); 1616 /* 1617 * UVD 1618 */ 1619 #define RADEON_MAX_UVD_HANDLES 10 1620 #define RADEON_UVD_STACK_SIZE (1024*1024) 1621 #define RADEON_UVD_HEAP_SIZE (1024*1024) 1622 1623 struct radeon_uvd { 1624 struct radeon_bo *vcpu_bo; 1625 void *cpu_addr; 1626 uint64_t gpu_addr; 1627 void *saved_bo; 1628 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1629 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1630 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1631 struct delayed_work idle_work; 1632 }; 1633 1634 int radeon_uvd_init(struct radeon_device *rdev); 1635 void radeon_uvd_fini(struct radeon_device *rdev); 1636 int radeon_uvd_suspend(struct radeon_device *rdev); 1637 int radeon_uvd_resume(struct radeon_device *rdev); 1638 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1639 uint32_t handle, struct radeon_fence **fence); 1640 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1641 uint32_t handle, struct radeon_fence **fence); 1642 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo); 1643 void radeon_uvd_free_handles(struct radeon_device *rdev, 1644 struct drm_file *filp); 1645 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1646 void radeon_uvd_note_usage(struct radeon_device *rdev); 1647 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1648 unsigned vclk, unsigned dclk, 1649 unsigned vco_min, unsigned vco_max, 1650 unsigned fb_factor, unsigned fb_mask, 1651 unsigned pd_min, unsigned pd_max, 1652 unsigned pd_even, 1653 unsigned *optimal_fb_div, 1654 unsigned *optimal_vclk_div, 1655 unsigned *optimal_dclk_div); 1656 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1657 unsigned cg_upll_func_cntl); 1658 1659 /* 1660 * VCE 1661 */ 1662 #define RADEON_MAX_VCE_HANDLES 16 1663 #define RADEON_VCE_STACK_SIZE (1024*1024) 1664 #define RADEON_VCE_HEAP_SIZE (4*1024*1024) 1665 1666 struct radeon_vce { 1667 struct radeon_bo *vcpu_bo; 1668 uint64_t gpu_addr; 1669 unsigned fw_version; 1670 unsigned fb_version; 1671 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1672 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1673 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1674 struct delayed_work idle_work; 1675 }; 1676 1677 int radeon_vce_init(struct radeon_device *rdev); 1678 void radeon_vce_fini(struct radeon_device *rdev); 1679 int radeon_vce_suspend(struct radeon_device *rdev); 1680 int radeon_vce_resume(struct radeon_device *rdev); 1681 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1682 uint32_t handle, struct radeon_fence **fence); 1683 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1684 uint32_t handle, struct radeon_fence **fence); 1685 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1686 void radeon_vce_note_usage(struct radeon_device *rdev); 1687 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1688 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1689 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1690 struct radeon_ring *ring, 1691 struct radeon_semaphore *semaphore, 1692 bool emit_wait); 1693 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1694 void radeon_vce_fence_emit(struct radeon_device *rdev, 1695 struct radeon_fence *fence); 1696 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1697 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1698 1699 struct r600_audio_pin { 1700 int channels; 1701 int rate; 1702 int bits_per_sample; 1703 u8 status_bits; 1704 u8 category_code; 1705 u32 offset; 1706 bool connected; 1707 u32 id; 1708 }; 1709 1710 struct r600_audio { 1711 bool enabled; 1712 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1713 int num_pins; 1714 }; 1715 1716 /* 1717 * Benchmarking 1718 */ 1719 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1720 1721 1722 /* 1723 * Testing 1724 */ 1725 void radeon_test_moves(struct radeon_device *rdev); 1726 void radeon_test_ring_sync(struct radeon_device *rdev, 1727 struct radeon_ring *cpA, 1728 struct radeon_ring *cpB); 1729 void radeon_test_syncing(struct radeon_device *rdev); 1730 1731 1732 /* 1733 * Debugfs 1734 */ 1735 struct radeon_debugfs { 1736 struct drm_info_list *files; 1737 unsigned num_files; 1738 }; 1739 1740 int radeon_debugfs_add_files(struct radeon_device *rdev, 1741 struct drm_info_list *files, 1742 unsigned nfiles); 1743 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1744 1745 /* 1746 * ASIC ring specific functions. 1747 */ 1748 struct radeon_asic_ring { 1749 /* ring read/write ptr handling */ 1750 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1751 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1752 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1753 1754 /* validating and patching of IBs */ 1755 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1756 int (*cs_parse)(struct radeon_cs_parser *p); 1757 1758 /* command emmit functions */ 1759 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1760 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1761 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1762 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1763 struct radeon_semaphore *semaphore, bool emit_wait); 1764 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 1765 1766 /* testing functions */ 1767 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1768 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1769 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1770 1771 /* deprecated */ 1772 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1773 }; 1774 1775 /* 1776 * ASIC specific functions. 1777 */ 1778 struct radeon_asic { 1779 int (*init)(struct radeon_device *rdev); 1780 void (*fini)(struct radeon_device *rdev); 1781 int (*resume)(struct radeon_device *rdev); 1782 int (*suspend)(struct radeon_device *rdev); 1783 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1784 int (*asic_reset)(struct radeon_device *rdev); 1785 /* Flush the HDP cache via MMIO */ 1786 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1787 /* check if 3D engine is idle */ 1788 bool (*gui_idle)(struct radeon_device *rdev); 1789 /* wait for mc_idle */ 1790 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1791 /* get the reference clock */ 1792 u32 (*get_xclk)(struct radeon_device *rdev); 1793 /* get the gpu clock counter */ 1794 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1795 /* gart */ 1796 struct { 1797 void (*tlb_flush)(struct radeon_device *rdev); 1798 void (*set_page)(struct radeon_device *rdev, unsigned i, 1799 uint64_t addr, uint32_t flags); 1800 } gart; 1801 struct { 1802 int (*init)(struct radeon_device *rdev); 1803 void (*fini)(struct radeon_device *rdev); 1804 void (*copy_pages)(struct radeon_device *rdev, 1805 struct radeon_ib *ib, 1806 uint64_t pe, uint64_t src, 1807 unsigned count); 1808 void (*write_pages)(struct radeon_device *rdev, 1809 struct radeon_ib *ib, 1810 uint64_t pe, 1811 uint64_t addr, unsigned count, 1812 uint32_t incr, uint32_t flags); 1813 void (*set_pages)(struct radeon_device *rdev, 1814 struct radeon_ib *ib, 1815 uint64_t pe, 1816 uint64_t addr, unsigned count, 1817 uint32_t incr, uint32_t flags); 1818 void (*pad_ib)(struct radeon_ib *ib); 1819 } vm; 1820 /* ring specific callbacks */ 1821 struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1822 /* irqs */ 1823 struct { 1824 int (*set)(struct radeon_device *rdev); 1825 int (*process)(struct radeon_device *rdev); 1826 } irq; 1827 /* displays */ 1828 struct { 1829 /* display watermarks */ 1830 void (*bandwidth_update)(struct radeon_device *rdev); 1831 /* get frame count */ 1832 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1833 /* wait for vblank */ 1834 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1835 /* set backlight level */ 1836 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1837 /* get backlight level */ 1838 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1839 /* audio callbacks */ 1840 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1841 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1842 } display; 1843 /* copy functions for bo handling */ 1844 struct { 1845 int (*blit)(struct radeon_device *rdev, 1846 uint64_t src_offset, 1847 uint64_t dst_offset, 1848 unsigned num_gpu_pages, 1849 struct radeon_fence **fence); 1850 u32 blit_ring_index; 1851 int (*dma)(struct radeon_device *rdev, 1852 uint64_t src_offset, 1853 uint64_t dst_offset, 1854 unsigned num_gpu_pages, 1855 struct radeon_fence **fence); 1856 u32 dma_ring_index; 1857 /* method used for bo copy */ 1858 int (*copy)(struct radeon_device *rdev, 1859 uint64_t src_offset, 1860 uint64_t dst_offset, 1861 unsigned num_gpu_pages, 1862 struct radeon_fence **fence); 1863 /* ring used for bo copies */ 1864 u32 copy_ring_index; 1865 } copy; 1866 /* surfaces */ 1867 struct { 1868 int (*set_reg)(struct radeon_device *rdev, int reg, 1869 uint32_t tiling_flags, uint32_t pitch, 1870 uint32_t offset, uint32_t obj_size); 1871 void (*clear_reg)(struct radeon_device *rdev, int reg); 1872 } surface; 1873 /* hotplug detect */ 1874 struct { 1875 void (*init)(struct radeon_device *rdev); 1876 void (*fini)(struct radeon_device *rdev); 1877 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1878 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1879 } hpd; 1880 /* static power management */ 1881 struct { 1882 void (*misc)(struct radeon_device *rdev); 1883 void (*prepare)(struct radeon_device *rdev); 1884 void (*finish)(struct radeon_device *rdev); 1885 void (*init_profile)(struct radeon_device *rdev); 1886 void (*get_dynpm_state)(struct radeon_device *rdev); 1887 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1888 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1889 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1890 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1891 int (*get_pcie_lanes)(struct radeon_device *rdev); 1892 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1893 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1894 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1895 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1896 int (*get_temperature)(struct radeon_device *rdev); 1897 } pm; 1898 /* dynamic power management */ 1899 struct { 1900 int (*init)(struct radeon_device *rdev); 1901 void (*setup_asic)(struct radeon_device *rdev); 1902 int (*enable)(struct radeon_device *rdev); 1903 int (*late_enable)(struct radeon_device *rdev); 1904 void (*disable)(struct radeon_device *rdev); 1905 int (*pre_set_power_state)(struct radeon_device *rdev); 1906 int (*set_power_state)(struct radeon_device *rdev); 1907 void (*post_set_power_state)(struct radeon_device *rdev); 1908 void (*display_configuration_changed)(struct radeon_device *rdev); 1909 void (*fini)(struct radeon_device *rdev); 1910 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1911 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1912 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1913 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1914 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 1915 bool (*vblank_too_short)(struct radeon_device *rdev); 1916 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 1917 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 1918 } dpm; 1919 /* pageflipping */ 1920 struct { 1921 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1922 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 1923 } pflip; 1924 }; 1925 1926 /* 1927 * Asic structures 1928 */ 1929 struct r100_asic { 1930 const unsigned *reg_safe_bm; 1931 unsigned reg_safe_bm_size; 1932 u32 hdp_cntl; 1933 }; 1934 1935 struct r300_asic { 1936 const unsigned *reg_safe_bm; 1937 unsigned reg_safe_bm_size; 1938 u32 resync_scratch; 1939 u32 hdp_cntl; 1940 }; 1941 1942 struct r600_asic { 1943 unsigned max_pipes; 1944 unsigned max_tile_pipes; 1945 unsigned max_simds; 1946 unsigned max_backends; 1947 unsigned max_gprs; 1948 unsigned max_threads; 1949 unsigned max_stack_entries; 1950 unsigned max_hw_contexts; 1951 unsigned max_gs_threads; 1952 unsigned sx_max_export_size; 1953 unsigned sx_max_export_pos_size; 1954 unsigned sx_max_export_smx_size; 1955 unsigned sq_num_cf_insts; 1956 unsigned tiling_nbanks; 1957 unsigned tiling_npipes; 1958 unsigned tiling_group_size; 1959 unsigned tile_config; 1960 unsigned backend_map; 1961 unsigned active_simds; 1962 }; 1963 1964 struct rv770_asic { 1965 unsigned max_pipes; 1966 unsigned max_tile_pipes; 1967 unsigned max_simds; 1968 unsigned max_backends; 1969 unsigned max_gprs; 1970 unsigned max_threads; 1971 unsigned max_stack_entries; 1972 unsigned max_hw_contexts; 1973 unsigned max_gs_threads; 1974 unsigned sx_max_export_size; 1975 unsigned sx_max_export_pos_size; 1976 unsigned sx_max_export_smx_size; 1977 unsigned sq_num_cf_insts; 1978 unsigned sx_num_of_sets; 1979 unsigned sc_prim_fifo_size; 1980 unsigned sc_hiz_tile_fifo_size; 1981 unsigned sc_earlyz_tile_fifo_fize; 1982 unsigned tiling_nbanks; 1983 unsigned tiling_npipes; 1984 unsigned tiling_group_size; 1985 unsigned tile_config; 1986 unsigned backend_map; 1987 unsigned active_simds; 1988 }; 1989 1990 struct evergreen_asic { 1991 unsigned num_ses; 1992 unsigned max_pipes; 1993 unsigned max_tile_pipes; 1994 unsigned max_simds; 1995 unsigned max_backends; 1996 unsigned max_gprs; 1997 unsigned max_threads; 1998 unsigned max_stack_entries; 1999 unsigned max_hw_contexts; 2000 unsigned max_gs_threads; 2001 unsigned sx_max_export_size; 2002 unsigned sx_max_export_pos_size; 2003 unsigned sx_max_export_smx_size; 2004 unsigned sq_num_cf_insts; 2005 unsigned sx_num_of_sets; 2006 unsigned sc_prim_fifo_size; 2007 unsigned sc_hiz_tile_fifo_size; 2008 unsigned sc_earlyz_tile_fifo_size; 2009 unsigned tiling_nbanks; 2010 unsigned tiling_npipes; 2011 unsigned tiling_group_size; 2012 unsigned tile_config; 2013 unsigned backend_map; 2014 unsigned active_simds; 2015 }; 2016 2017 struct cayman_asic { 2018 unsigned max_shader_engines; 2019 unsigned max_pipes_per_simd; 2020 unsigned max_tile_pipes; 2021 unsigned max_simds_per_se; 2022 unsigned max_backends_per_se; 2023 unsigned max_texture_channel_caches; 2024 unsigned max_gprs; 2025 unsigned max_threads; 2026 unsigned max_gs_threads; 2027 unsigned max_stack_entries; 2028 unsigned sx_num_of_sets; 2029 unsigned sx_max_export_size; 2030 unsigned sx_max_export_pos_size; 2031 unsigned sx_max_export_smx_size; 2032 unsigned max_hw_contexts; 2033 unsigned sq_num_cf_insts; 2034 unsigned sc_prim_fifo_size; 2035 unsigned sc_hiz_tile_fifo_size; 2036 unsigned sc_earlyz_tile_fifo_size; 2037 2038 unsigned num_shader_engines; 2039 unsigned num_shader_pipes_per_simd; 2040 unsigned num_tile_pipes; 2041 unsigned num_simds_per_se; 2042 unsigned num_backends_per_se; 2043 unsigned backend_disable_mask_per_asic; 2044 unsigned backend_map; 2045 unsigned num_texture_channel_caches; 2046 unsigned mem_max_burst_length_bytes; 2047 unsigned mem_row_size_in_kb; 2048 unsigned shader_engine_tile_size; 2049 unsigned num_gpus; 2050 unsigned multi_gpu_tile_size; 2051 2052 unsigned tile_config; 2053 unsigned active_simds; 2054 }; 2055 2056 struct si_asic { 2057 unsigned max_shader_engines; 2058 unsigned max_tile_pipes; 2059 unsigned max_cu_per_sh; 2060 unsigned max_sh_per_se; 2061 unsigned max_backends_per_se; 2062 unsigned max_texture_channel_caches; 2063 unsigned max_gprs; 2064 unsigned max_gs_threads; 2065 unsigned max_hw_contexts; 2066 unsigned sc_prim_fifo_size_frontend; 2067 unsigned sc_prim_fifo_size_backend; 2068 unsigned sc_hiz_tile_fifo_size; 2069 unsigned sc_earlyz_tile_fifo_size; 2070 2071 unsigned num_tile_pipes; 2072 unsigned backend_enable_mask; 2073 unsigned backend_disable_mask_per_asic; 2074 unsigned backend_map; 2075 unsigned num_texture_channel_caches; 2076 unsigned mem_max_burst_length_bytes; 2077 unsigned mem_row_size_in_kb; 2078 unsigned shader_engine_tile_size; 2079 unsigned num_gpus; 2080 unsigned multi_gpu_tile_size; 2081 2082 unsigned tile_config; 2083 uint32_t tile_mode_array[32]; 2084 uint32_t active_cus; 2085 }; 2086 2087 struct cik_asic { 2088 unsigned max_shader_engines; 2089 unsigned max_tile_pipes; 2090 unsigned max_cu_per_sh; 2091 unsigned max_sh_per_se; 2092 unsigned max_backends_per_se; 2093 unsigned max_texture_channel_caches; 2094 unsigned max_gprs; 2095 unsigned max_gs_threads; 2096 unsigned max_hw_contexts; 2097 unsigned sc_prim_fifo_size_frontend; 2098 unsigned sc_prim_fifo_size_backend; 2099 unsigned sc_hiz_tile_fifo_size; 2100 unsigned sc_earlyz_tile_fifo_size; 2101 2102 unsigned num_tile_pipes; 2103 unsigned backend_enable_mask; 2104 unsigned backend_disable_mask_per_asic; 2105 unsigned backend_map; 2106 unsigned num_texture_channel_caches; 2107 unsigned mem_max_burst_length_bytes; 2108 unsigned mem_row_size_in_kb; 2109 unsigned shader_engine_tile_size; 2110 unsigned num_gpus; 2111 unsigned multi_gpu_tile_size; 2112 2113 unsigned tile_config; 2114 uint32_t tile_mode_array[32]; 2115 uint32_t macrotile_mode_array[16]; 2116 uint32_t active_cus; 2117 }; 2118 2119 union radeon_asic_config { 2120 struct r300_asic r300; 2121 struct r100_asic r100; 2122 struct r600_asic r600; 2123 struct rv770_asic rv770; 2124 struct evergreen_asic evergreen; 2125 struct cayman_asic cayman; 2126 struct si_asic si; 2127 struct cik_asic cik; 2128 }; 2129 2130 /* 2131 * asic initizalization from radeon_asic.c 2132 */ 2133 void radeon_agp_disable(struct radeon_device *rdev); 2134 int radeon_asic_init(struct radeon_device *rdev); 2135 2136 2137 /* 2138 * IOCTL. 2139 */ 2140 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2141 struct drm_file *filp); 2142 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2143 struct drm_file *filp); 2144 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2145 struct drm_file *file_priv); 2146 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2147 struct drm_file *file_priv); 2148 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2149 struct drm_file *file_priv); 2150 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2151 struct drm_file *file_priv); 2152 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2153 struct drm_file *filp); 2154 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2155 struct drm_file *filp); 2156 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2157 struct drm_file *filp); 2158 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2159 struct drm_file *filp); 2160 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2161 struct drm_file *filp); 2162 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2163 struct drm_file *filp); 2164 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2165 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2166 struct drm_file *filp); 2167 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2168 struct drm_file *filp); 2169 2170 /* VRAM scratch page for HDP bug, default vram page */ 2171 struct r600_vram_scratch { 2172 struct radeon_bo *robj; 2173 volatile uint32_t *ptr; 2174 u64 gpu_addr; 2175 }; 2176 2177 /* 2178 * ACPI 2179 */ 2180 struct radeon_atif_notification_cfg { 2181 bool enabled; 2182 int command_code; 2183 }; 2184 2185 struct radeon_atif_notifications { 2186 bool display_switch; 2187 bool expansion_mode_change; 2188 bool thermal_state; 2189 bool forced_power_state; 2190 bool system_power_state; 2191 bool display_conf_change; 2192 bool px_gfx_switch; 2193 bool brightness_change; 2194 bool dgpu_display_event; 2195 }; 2196 2197 struct radeon_atif_functions { 2198 bool system_params; 2199 bool sbios_requests; 2200 bool select_active_disp; 2201 bool lid_state; 2202 bool get_tv_standard; 2203 bool set_tv_standard; 2204 bool get_panel_expansion_mode; 2205 bool set_panel_expansion_mode; 2206 bool temperature_change; 2207 bool graphics_device_types; 2208 }; 2209 2210 struct radeon_atif { 2211 struct radeon_atif_notifications notifications; 2212 struct radeon_atif_functions functions; 2213 struct radeon_atif_notification_cfg notification_cfg; 2214 struct radeon_encoder *encoder_for_bl; 2215 }; 2216 2217 struct radeon_atcs_functions { 2218 bool get_ext_state; 2219 bool pcie_perf_req; 2220 bool pcie_dev_rdy; 2221 bool pcie_bus_width; 2222 }; 2223 2224 struct radeon_atcs { 2225 struct radeon_atcs_functions functions; 2226 }; 2227 2228 /* 2229 * Core structure, functions and helpers. 2230 */ 2231 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2232 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2233 2234 struct radeon_device { 2235 struct device *dev; 2236 struct drm_device *ddev; 2237 struct pci_dev *pdev; 2238 struct rw_semaphore exclusive_lock; 2239 /* ASIC */ 2240 union radeon_asic_config config; 2241 enum radeon_family family; 2242 unsigned long flags; 2243 int usec_timeout; 2244 enum radeon_pll_errata pll_errata; 2245 int num_gb_pipes; 2246 int num_z_pipes; 2247 int disp_priority; 2248 /* BIOS */ 2249 uint8_t *bios; 2250 bool is_atom_bios; 2251 uint16_t bios_header_start; 2252 struct radeon_bo *stollen_vga_memory; 2253 /* Register mmio */ 2254 resource_size_t rmmio_base; 2255 resource_size_t rmmio_size; 2256 /* protects concurrent MM_INDEX/DATA based register access */ 2257 spinlock_t mmio_idx_lock; 2258 /* protects concurrent SMC based register access */ 2259 spinlock_t smc_idx_lock; 2260 /* protects concurrent PLL register access */ 2261 spinlock_t pll_idx_lock; 2262 /* protects concurrent MC register access */ 2263 spinlock_t mc_idx_lock; 2264 /* protects concurrent PCIE register access */ 2265 spinlock_t pcie_idx_lock; 2266 /* protects concurrent PCIE_PORT register access */ 2267 spinlock_t pciep_idx_lock; 2268 /* protects concurrent PIF register access */ 2269 spinlock_t pif_idx_lock; 2270 /* protects concurrent CG register access */ 2271 spinlock_t cg_idx_lock; 2272 /* protects concurrent UVD register access */ 2273 spinlock_t uvd_idx_lock; 2274 /* protects concurrent RCU register access */ 2275 spinlock_t rcu_idx_lock; 2276 /* protects concurrent DIDT register access */ 2277 spinlock_t didt_idx_lock; 2278 /* protects concurrent ENDPOINT (audio) register access */ 2279 spinlock_t end_idx_lock; 2280 void __iomem *rmmio; 2281 radeon_rreg_t mc_rreg; 2282 radeon_wreg_t mc_wreg; 2283 radeon_rreg_t pll_rreg; 2284 radeon_wreg_t pll_wreg; 2285 uint32_t pcie_reg_mask; 2286 radeon_rreg_t pciep_rreg; 2287 radeon_wreg_t pciep_wreg; 2288 /* io port */ 2289 void __iomem *rio_mem; 2290 resource_size_t rio_mem_size; 2291 struct radeon_clock clock; 2292 struct radeon_mc mc; 2293 struct radeon_gart gart; 2294 struct radeon_mode_info mode_info; 2295 struct radeon_scratch scratch; 2296 struct radeon_doorbell doorbell; 2297 struct radeon_mman mman; 2298 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2299 wait_queue_head_t fence_queue; 2300 struct mutex ring_lock; 2301 struct radeon_ring ring[RADEON_NUM_RINGS]; 2302 bool ib_pool_ready; 2303 struct radeon_sa_manager ring_tmp_bo; 2304 struct radeon_irq irq; 2305 struct radeon_asic *asic; 2306 struct radeon_gem gem; 2307 struct radeon_pm pm; 2308 struct radeon_uvd uvd; 2309 struct radeon_vce vce; 2310 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2311 struct radeon_wb wb; 2312 struct radeon_dummy_page dummy_page; 2313 bool shutdown; 2314 bool suspend; 2315 bool need_dma32; 2316 bool accel_working; 2317 bool fastfb_working; /* IGP feature*/ 2318 bool needs_reset; 2319 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2320 const struct firmware *me_fw; /* all family ME firmware */ 2321 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2322 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2323 const struct firmware *mc_fw; /* NI MC firmware */ 2324 const struct firmware *ce_fw; /* SI CE firmware */ 2325 const struct firmware *mec_fw; /* CIK MEC firmware */ 2326 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2327 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2328 const struct firmware *smc_fw; /* SMC firmware */ 2329 const struct firmware *uvd_fw; /* UVD firmware */ 2330 const struct firmware *vce_fw; /* VCE firmware */ 2331 bool new_fw; 2332 struct r600_vram_scratch vram_scratch; 2333 int msi_enabled; /* msi enabled */ 2334 struct r600_ih ih; /* r6/700 interrupt ring */ 2335 struct radeon_rlc rlc; 2336 struct radeon_mec mec; 2337 struct work_struct hotplug_work; 2338 struct work_struct audio_work; 2339 struct work_struct reset_work; 2340 int num_crtc; /* number of crtcs */ 2341 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2342 bool has_uvd; 2343 struct r600_audio audio; /* audio stuff */ 2344 struct notifier_block acpi_nb; 2345 /* only one userspace can use Hyperz features or CMASK at a time */ 2346 struct drm_file *hyperz_filp; 2347 struct drm_file *cmask_filp; 2348 /* i2c buses */ 2349 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2350 /* debugfs */ 2351 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2352 unsigned debugfs_count; 2353 /* virtual memory */ 2354 struct radeon_vm_manager vm_manager; 2355 struct mutex gpu_clock_mutex; 2356 /* memory stats */ 2357 atomic64_t vram_usage; 2358 atomic64_t gtt_usage; 2359 atomic64_t num_bytes_moved; 2360 /* ACPI interface */ 2361 struct radeon_atif atif; 2362 struct radeon_atcs atcs; 2363 /* srbm instance registers */ 2364 struct mutex srbm_mutex; 2365 /* clock, powergating flags */ 2366 u32 cg_flags; 2367 u32 pg_flags; 2368 2369 struct dev_pm_domain vga_pm_domain; 2370 bool have_disp_power_ref; 2371 u32 px_quirk_flags; 2372 2373 /* tracking pinned memory */ 2374 u64 vram_pin_size; 2375 u64 gart_pin_size; 2376 }; 2377 2378 bool radeon_is_px(struct drm_device *dev); 2379 int radeon_device_init(struct radeon_device *rdev, 2380 struct drm_device *ddev, 2381 struct pci_dev *pdev, 2382 uint32_t flags); 2383 void radeon_device_fini(struct radeon_device *rdev); 2384 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2385 2386 #define RADEON_MIN_MMIO_SIZE 0x10000 2387 2388 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2389 bool always_indirect) 2390 { 2391 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ 2392 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2393 return readl(((void __iomem *)rdev->rmmio) + reg); 2394 else { 2395 unsigned long flags; 2396 uint32_t ret; 2397 2398 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 2399 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 2400 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 2401 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 2402 2403 return ret; 2404 } 2405 } 2406 2407 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2408 bool always_indirect) 2409 { 2410 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2411 writel(v, ((void __iomem *)rdev->rmmio) + reg); 2412 else { 2413 unsigned long flags; 2414 2415 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 2416 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 2417 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 2418 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 2419 } 2420 } 2421 2422 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2423 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2424 2425 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2426 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2427 2428 /* 2429 * Cast helper 2430 */ 2431 #define to_radeon_fence(p) ((struct radeon_fence *)(p)) 2432 2433 /* 2434 * Registers read & write functions. 2435 */ 2436 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 2437 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 2438 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 2439 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 2440 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2441 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2442 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) 2443 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2444 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2445 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2446 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2447 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2448 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2449 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2450 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2451 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2452 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2453 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2454 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2455 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2456 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2457 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2458 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2459 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2460 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2461 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2462 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2463 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2464 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2465 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2466 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2467 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2468 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2469 #define WREG32_P(reg, val, mask) \ 2470 do { \ 2471 uint32_t tmp_ = RREG32(reg); \ 2472 tmp_ &= (mask); \ 2473 tmp_ |= ((val) & ~(mask)); \ 2474 WREG32(reg, tmp_); \ 2475 } while (0) 2476 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2477 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2478 #define WREG32_PLL_P(reg, val, mask) \ 2479 do { \ 2480 uint32_t tmp_ = RREG32_PLL(reg); \ 2481 tmp_ &= (mask); \ 2482 tmp_ |= ((val) & ~(mask)); \ 2483 WREG32_PLL(reg, tmp_); \ 2484 } while (0) 2485 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2486 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2487 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2488 2489 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2490 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2491 2492 /* 2493 * Indirect registers accessor 2494 */ 2495 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 2496 { 2497 unsigned long flags; 2498 uint32_t r; 2499 2500 spin_lock_irqsave(&rdev->pcie_idx_lock, flags); 2501 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2502 r = RREG32(RADEON_PCIE_DATA); 2503 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); 2504 return r; 2505 } 2506 2507 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2508 { 2509 unsigned long flags; 2510 2511 spin_lock_irqsave(&rdev->pcie_idx_lock, flags); 2512 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2513 WREG32(RADEON_PCIE_DATA, (v)); 2514 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); 2515 } 2516 2517 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) 2518 { 2519 unsigned long flags; 2520 u32 r; 2521 2522 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 2523 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2524 r = RREG32(TN_SMC_IND_DATA_0); 2525 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 2526 return r; 2527 } 2528 2529 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2530 { 2531 unsigned long flags; 2532 2533 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 2534 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2535 WREG32(TN_SMC_IND_DATA_0, (v)); 2536 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 2537 } 2538 2539 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) 2540 { 2541 unsigned long flags; 2542 u32 r; 2543 2544 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); 2545 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2546 r = RREG32(R600_RCU_DATA); 2547 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); 2548 return r; 2549 } 2550 2551 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2552 { 2553 unsigned long flags; 2554 2555 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); 2556 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2557 WREG32(R600_RCU_DATA, (v)); 2558 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); 2559 } 2560 2561 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) 2562 { 2563 unsigned long flags; 2564 u32 r; 2565 2566 spin_lock_irqsave(&rdev->cg_idx_lock, flags); 2567 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2568 r = RREG32(EVERGREEN_CG_IND_DATA); 2569 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); 2570 return r; 2571 } 2572 2573 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2574 { 2575 unsigned long flags; 2576 2577 spin_lock_irqsave(&rdev->cg_idx_lock, flags); 2578 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2579 WREG32(EVERGREEN_CG_IND_DATA, (v)); 2580 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); 2581 } 2582 2583 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) 2584 { 2585 unsigned long flags; 2586 u32 r; 2587 2588 spin_lock_irqsave(&rdev->pif_idx_lock, flags); 2589 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2590 r = RREG32(EVERGREEN_PIF_PHY0_DATA); 2591 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); 2592 return r; 2593 } 2594 2595 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2596 { 2597 unsigned long flags; 2598 2599 spin_lock_irqsave(&rdev->pif_idx_lock, flags); 2600 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2601 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); 2602 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); 2603 } 2604 2605 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) 2606 { 2607 unsigned long flags; 2608 u32 r; 2609 2610 spin_lock_irqsave(&rdev->pif_idx_lock, flags); 2611 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2612 r = RREG32(EVERGREEN_PIF_PHY1_DATA); 2613 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); 2614 return r; 2615 } 2616 2617 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2618 { 2619 unsigned long flags; 2620 2621 spin_lock_irqsave(&rdev->pif_idx_lock, flags); 2622 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2623 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); 2624 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); 2625 } 2626 2627 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) 2628 { 2629 unsigned long flags; 2630 u32 r; 2631 2632 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); 2633 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2634 r = RREG32(R600_UVD_CTX_DATA); 2635 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); 2636 return r; 2637 } 2638 2639 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2640 { 2641 unsigned long flags; 2642 2643 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); 2644 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2645 WREG32(R600_UVD_CTX_DATA, (v)); 2646 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); 2647 } 2648 2649 2650 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) 2651 { 2652 unsigned long flags; 2653 u32 r; 2654 2655 spin_lock_irqsave(&rdev->didt_idx_lock, flags); 2656 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2657 r = RREG32(CIK_DIDT_IND_DATA); 2658 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); 2659 return r; 2660 } 2661 2662 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2663 { 2664 unsigned long flags; 2665 2666 spin_lock_irqsave(&rdev->didt_idx_lock, flags); 2667 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2668 WREG32(CIK_DIDT_IND_DATA, (v)); 2669 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); 2670 } 2671 2672 void r100_pll_errata_after_index(struct radeon_device *rdev); 2673 2674 2675 /* 2676 * ASICs helpers. 2677 */ 2678 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2679 (rdev->pdev->device == 0x5969)) 2680 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2681 (rdev->family == CHIP_RV200) || \ 2682 (rdev->family == CHIP_RS100) || \ 2683 (rdev->family == CHIP_RS200) || \ 2684 (rdev->family == CHIP_RV250) || \ 2685 (rdev->family == CHIP_RV280) || \ 2686 (rdev->family == CHIP_RS300)) 2687 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2688 (rdev->family == CHIP_RV350) || \ 2689 (rdev->family == CHIP_R350) || \ 2690 (rdev->family == CHIP_RV380) || \ 2691 (rdev->family == CHIP_R420) || \ 2692 (rdev->family == CHIP_R423) || \ 2693 (rdev->family == CHIP_RV410) || \ 2694 (rdev->family == CHIP_RS400) || \ 2695 (rdev->family == CHIP_RS480)) 2696 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2697 (rdev->ddev->pdev->device == 0x9443) || \ 2698 (rdev->ddev->pdev->device == 0x944B) || \ 2699 (rdev->ddev->pdev->device == 0x9506) || \ 2700 (rdev->ddev->pdev->device == 0x9509) || \ 2701 (rdev->ddev->pdev->device == 0x950F) || \ 2702 (rdev->ddev->pdev->device == 0x689C) || \ 2703 (rdev->ddev->pdev->device == 0x689D)) 2704 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2705 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2706 (rdev->family == CHIP_RS690) || \ 2707 (rdev->family == CHIP_RS740) || \ 2708 (rdev->family >= CHIP_R600)) 2709 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2710 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2711 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2712 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2713 (rdev->flags & RADEON_IS_IGP)) 2714 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2715 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2716 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2717 (rdev->flags & RADEON_IS_IGP)) 2718 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2719 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2720 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2721 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2722 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2723 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2724 (rdev->family == CHIP_MULLINS)) 2725 2726 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2727 (rdev->ddev->pdev->device == 0x6850) || \ 2728 (rdev->ddev->pdev->device == 0x6858) || \ 2729 (rdev->ddev->pdev->device == 0x6859) || \ 2730 (rdev->ddev->pdev->device == 0x6840) || \ 2731 (rdev->ddev->pdev->device == 0x6841) || \ 2732 (rdev->ddev->pdev->device == 0x6842) || \ 2733 (rdev->ddev->pdev->device == 0x6843)) 2734 2735 /* 2736 * BIOS helpers. 2737 */ 2738 #define RBIOS8(i) (rdev->bios[i]) 2739 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2740 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2741 2742 int radeon_combios_init(struct radeon_device *rdev); 2743 void radeon_combios_fini(struct radeon_device *rdev); 2744 int radeon_atombios_init(struct radeon_device *rdev); 2745 void radeon_atombios_fini(struct radeon_device *rdev); 2746 2747 2748 /* 2749 * RING helpers. 2750 */ 2751 #if DRM_DEBUG_CODE == 0 2752 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2753 { 2754 ring->ring[ring->wptr++] = v; 2755 ring->wptr &= ring->ptr_mask; 2756 ring->count_dw--; 2757 ring->ring_free_dw--; 2758 } 2759 #else 2760 /* With debugging this is just too big to inline */ 2761 void radeon_ring_write(struct radeon_ring *ring, uint32_t v); 2762 #endif 2763 2764 /* 2765 * ASICs macro. 2766 */ 2767 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2768 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2769 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2770 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2771 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2772 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2773 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 2774 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2775 #define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f)) 2776 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2777 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2778 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2779 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2780 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2781 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2782 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2783 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2784 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2785 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2786 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2787 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2788 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm)) 2789 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2790 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2791 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2792 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2793 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2794 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2795 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2796 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2797 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2798 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2799 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2800 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2801 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 2802 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) 2803 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) 2804 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2805 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2806 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2807 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2808 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2809 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2810 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2811 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2812 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2813 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2814 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2815 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2816 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2817 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2818 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2819 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2820 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2821 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2822 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2823 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2824 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2825 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2826 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2827 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2828 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2829 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2830 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 2831 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2832 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2833 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2834 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2835 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2836 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2837 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2838 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2839 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2840 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2841 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2842 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2843 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2844 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2845 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2846 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2847 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2848 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2849 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2850 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2851 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2852 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2853 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2854 2855 /* Common functions */ 2856 /* AGP */ 2857 extern int radeon_gpu_reset(struct radeon_device *rdev); 2858 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2859 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2860 extern void radeon_agp_disable(struct radeon_device *rdev); 2861 extern int radeon_modeset_init(struct radeon_device *rdev); 2862 extern void radeon_modeset_fini(struct radeon_device *rdev); 2863 extern bool radeon_card_posted(struct radeon_device *rdev); 2864 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2865 extern void radeon_update_display_priority(struct radeon_device *rdev); 2866 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2867 extern void radeon_scratch_init(struct radeon_device *rdev); 2868 extern void radeon_wb_fini(struct radeon_device *rdev); 2869 extern int radeon_wb_init(struct radeon_device *rdev); 2870 extern void radeon_wb_disable(struct radeon_device *rdev); 2871 extern void radeon_surface_init(struct radeon_device *rdev); 2872 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2873 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 2874 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 2875 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2876 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2877 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2878 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2879 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2880 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2881 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2882 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2883 const u32 *registers, 2884 const u32 array_size); 2885 2886 /* 2887 * vm 2888 */ 2889 int radeon_vm_manager_init(struct radeon_device *rdev); 2890 void radeon_vm_manager_fini(struct radeon_device *rdev); 2891 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2892 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2893 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev, 2894 struct radeon_vm *vm, 2895 struct list_head *head); 2896 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2897 struct radeon_vm *vm, int ring); 2898 void radeon_vm_flush(struct radeon_device *rdev, 2899 struct radeon_vm *vm, 2900 int ring); 2901 void radeon_vm_fence(struct radeon_device *rdev, 2902 struct radeon_vm *vm, 2903 struct radeon_fence *fence); 2904 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2905 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2906 struct radeon_vm *vm); 2907 int radeon_vm_clear_freed(struct radeon_device *rdev, 2908 struct radeon_vm *vm); 2909 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2910 struct radeon_vm *vm); 2911 int radeon_vm_bo_update(struct radeon_device *rdev, 2912 struct radeon_bo_va *bo_va, 2913 struct ttm_mem_reg *mem); 2914 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2915 struct radeon_bo *bo); 2916 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2917 struct radeon_bo *bo); 2918 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2919 struct radeon_vm *vm, 2920 struct radeon_bo *bo); 2921 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2922 struct radeon_bo_va *bo_va, 2923 uint64_t offset, 2924 uint32_t flags); 2925 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2926 struct radeon_bo_va *bo_va); 2927 2928 /* audio */ 2929 void r600_audio_update_hdmi(struct work_struct *work); 2930 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2931 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2932 void r600_audio_enable(struct radeon_device *rdev, 2933 struct r600_audio_pin *pin, 2934 bool enable); 2935 void dce6_audio_enable(struct radeon_device *rdev, 2936 struct r600_audio_pin *pin, 2937 bool enable); 2938 2939 /* 2940 * R600 vram scratch functions 2941 */ 2942 int r600_vram_scratch_init(struct radeon_device *rdev); 2943 void r600_vram_scratch_fini(struct radeon_device *rdev); 2944 2945 /* 2946 * r600 cs checking helper 2947 */ 2948 unsigned r600_mip_minify(unsigned size, unsigned level); 2949 bool r600_fmt_is_valid_color(u32 format); 2950 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2951 int r600_fmt_get_blocksize(u32 format); 2952 int r600_fmt_get_nblocksx(u32 format, u32 w); 2953 int r600_fmt_get_nblocksy(u32 format, u32 h); 2954 2955 /* 2956 * r600 functions used by radeon_encoder.c 2957 */ 2958 struct radeon_hdmi_acr { 2959 u32 clock; 2960 2961 int n_32khz; 2962 int cts_32khz; 2963 2964 int n_44_1khz; 2965 int cts_44_1khz; 2966 2967 int n_48khz; 2968 int cts_48khz; 2969 2970 }; 2971 2972 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 2973 2974 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2975 u32 tiling_pipe_num, 2976 u32 max_rb_num, 2977 u32 total_max_rb_num, 2978 u32 enabled_rb_mask); 2979 2980 /* 2981 * evergreen functions used by radeon_encoder.c 2982 */ 2983 2984 extern int ni_init_microcode(struct radeon_device *rdev); 2985 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2986 2987 /* radeon_acpi.c */ 2988 #if defined(CONFIG_ACPI) 2989 extern int radeon_acpi_init(struct radeon_device *rdev); 2990 extern void radeon_acpi_fini(struct radeon_device *rdev); 2991 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 2992 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 2993 u8 perf_req, bool advertise); 2994 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 2995 #else 2996 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 2997 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 2998 #endif 2999 3000 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 3001 struct radeon_cs_packet *pkt, 3002 unsigned idx); 3003 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 3004 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 3005 struct radeon_cs_packet *pkt); 3006 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 3007 struct radeon_cs_reloc **cs_reloc, 3008 int nomm); 3009 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 3010 uint32_t *vline_start_end, 3011 uint32_t *vline_status); 3012 3013 #include "radeon_object.h" 3014 3015 #endif 3016