1 /* 2 * Copyright 2009 Advanced Micro Devices, Inc. 3 * Copyright 2009 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 */ 27 #ifndef R600D_H 28 #define R600D_H 29 30 #define CP_PACKET2 0x80000000 31 #define PACKET2_PAD_SHIFT 0 32 #define PACKET2_PAD_MASK (0x3fffffff << 0) 33 34 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 35 36 #define R6XX_MAX_SH_GPRS 256 37 #define R6XX_MAX_TEMP_GPRS 16 38 #define R6XX_MAX_SH_THREADS 256 39 #define R6XX_MAX_SH_STACK_ENTRIES 4096 40 #define R6XX_MAX_BACKENDS 8 41 #define R6XX_MAX_BACKENDS_MASK 0xff 42 #define R6XX_MAX_SIMDS 8 43 #define R6XX_MAX_SIMDS_MASK 0xff 44 #define R6XX_MAX_PIPES 8 45 #define R6XX_MAX_PIPES_MASK 0xff 46 47 /* PTE flags */ 48 #define PTE_VALID (1 << 0) 49 #define PTE_SYSTEM (1 << 1) 50 #define PTE_SNOOPED (1 << 2) 51 #define PTE_READABLE (1 << 5) 52 #define PTE_WRITEABLE (1 << 6) 53 54 /* Registers */ 55 #define ARB_POP 0x2418 56 #define ENABLE_TC128 (1 << 30) 57 #define ARB_GDEC_RD_CNTL 0x246C 58 59 #define CC_GC_SHADER_PIPE_CONFIG 0x8950 60 #define CC_RB_BACKEND_DISABLE 0x98F4 61 #define BACKEND_DISABLE(x) ((x) << 16) 62 63 #define CB_COLOR0_BASE 0x28040 64 #define CB_COLOR1_BASE 0x28044 65 #define CB_COLOR2_BASE 0x28048 66 #define CB_COLOR3_BASE 0x2804C 67 #define CB_COLOR4_BASE 0x28050 68 #define CB_COLOR5_BASE 0x28054 69 #define CB_COLOR6_BASE 0x28058 70 #define CB_COLOR7_BASE 0x2805C 71 #define CB_COLOR7_FRAG 0x280FC 72 73 #define CB_COLOR0_SIZE 0x28060 74 #define CB_COLOR0_VIEW 0x28080 75 #define CB_COLOR0_INFO 0x280a0 76 #define CB_COLOR0_TILE 0x280c0 77 #define CB_COLOR0_FRAG 0x280e0 78 #define CB_COLOR0_MASK 0x28100 79 80 #define CONFIG_MEMSIZE 0x5428 81 #define CONFIG_CNTL 0x5424 82 #define CP_STAT 0x8680 83 #define CP_COHER_BASE 0x85F8 84 #define CP_DEBUG 0xC1FC 85 #define R_0086D8_CP_ME_CNTL 0x86D8 86 #define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28) 87 #define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF) 88 #define CP_ME_RAM_DATA 0xC160 89 #define CP_ME_RAM_RADDR 0xC158 90 #define CP_ME_RAM_WADDR 0xC15C 91 #define CP_MEQ_THRESHOLDS 0x8764 92 #define MEQ_END(x) ((x) << 16) 93 #define ROQ_END(x) ((x) << 24) 94 #define CP_PERFMON_CNTL 0x87FC 95 #define CP_PFP_UCODE_ADDR 0xC150 96 #define CP_PFP_UCODE_DATA 0xC154 97 #define CP_QUEUE_THRESHOLDS 0x8760 98 #define ROQ_IB1_START(x) ((x) << 0) 99 #define ROQ_IB2_START(x) ((x) << 8) 100 #define CP_RB_BASE 0xC100 101 #define CP_RB_CNTL 0xC104 102 #define RB_BUFSZ(x) ((x)<<0) 103 #define RB_BLKSZ(x) ((x)<<8) 104 #define RB_NO_UPDATE (1<<27) 105 #define RB_RPTR_WR_ENA (1<<31) 106 #define BUF_SWAP_32BIT (2 << 16) 107 #define CP_RB_RPTR 0x8700 108 #define CP_RB_RPTR_ADDR 0xC10C 109 #define CP_RB_RPTR_ADDR_HI 0xC110 110 #define CP_RB_RPTR_WR 0xC108 111 #define CP_RB_WPTR 0xC114 112 #define CP_RB_WPTR_ADDR 0xC118 113 #define CP_RB_WPTR_ADDR_HI 0xC11C 114 #define CP_RB_WPTR_DELAY 0x8704 115 #define CP_ROQ_IB1_STAT 0x8784 116 #define CP_ROQ_IB2_STAT 0x8788 117 #define CP_SEM_WAIT_TIMER 0x85BC 118 119 #define DB_DEBUG 0x9830 120 #define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) 121 #define DB_DEPTH_BASE 0x2800C 122 #define DB_HTILE_DATA_BASE 0x28014 123 #define DB_WATERMARKS 0x9838 124 #define DEPTH_FREE(x) ((x) << 0) 125 #define DEPTH_FLUSH(x) ((x) << 5) 126 #define DEPTH_PENDING_FREE(x) ((x) << 15) 127 #define DEPTH_CACHELINE_FREE(x) ((x) << 20) 128 129 #define DCP_TILING_CONFIG 0x6CA0 130 #define PIPE_TILING(x) ((x) << 1) 131 #define BANK_TILING(x) ((x) << 4) 132 #define GROUP_SIZE(x) ((x) << 6) 133 #define ROW_TILING(x) ((x) << 8) 134 #define BANK_SWAPS(x) ((x) << 11) 135 #define SAMPLE_SPLIT(x) ((x) << 14) 136 #define BACKEND_MAP(x) ((x) << 16) 137 138 #define GB_TILING_CONFIG 0x98F0 139 140 #define GC_USER_SHADER_PIPE_CONFIG 0x8954 141 #define INACTIVE_QD_PIPES(x) ((x) << 8) 142 #define INACTIVE_QD_PIPES_MASK 0x0000FF00 143 #define INACTIVE_SIMDS(x) ((x) << 16) 144 #define INACTIVE_SIMDS_MASK 0x00FF0000 145 146 #define SQ_CONFIG 0x8c00 147 # define VC_ENABLE (1 << 0) 148 # define EXPORT_SRC_C (1 << 1) 149 # define DX9_CONSTS (1 << 2) 150 # define ALU_INST_PREFER_VECTOR (1 << 3) 151 # define DX10_CLAMP (1 << 4) 152 # define CLAUSE_SEQ_PRIO(x) ((x) << 8) 153 # define PS_PRIO(x) ((x) << 24) 154 # define VS_PRIO(x) ((x) << 26) 155 # define GS_PRIO(x) ((x) << 28) 156 # define ES_PRIO(x) ((x) << 30) 157 #define SQ_GPR_RESOURCE_MGMT_1 0x8c04 158 # define NUM_PS_GPRS(x) ((x) << 0) 159 # define NUM_VS_GPRS(x) ((x) << 16) 160 # define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 161 #define SQ_GPR_RESOURCE_MGMT_2 0x8c08 162 # define NUM_GS_GPRS(x) ((x) << 0) 163 # define NUM_ES_GPRS(x) ((x) << 16) 164 #define SQ_THREAD_RESOURCE_MGMT 0x8c0c 165 # define NUM_PS_THREADS(x) ((x) << 0) 166 # define NUM_VS_THREADS(x) ((x) << 8) 167 # define NUM_GS_THREADS(x) ((x) << 16) 168 # define NUM_ES_THREADS(x) ((x) << 24) 169 #define SQ_STACK_RESOURCE_MGMT_1 0x8c10 170 # define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 171 # define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 172 #define SQ_STACK_RESOURCE_MGMT_2 0x8c14 173 # define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 174 # define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 175 #define SQ_ESGS_RING_BASE 0x8c40 176 #define SQ_GSVS_RING_BASE 0x8c48 177 #define SQ_ESTMP_RING_BASE 0x8c50 178 #define SQ_GSTMP_RING_BASE 0x8c58 179 #define SQ_VSTMP_RING_BASE 0x8c60 180 #define SQ_PSTMP_RING_BASE 0x8c68 181 #define SQ_FBUF_RING_BASE 0x8c70 182 #define SQ_REDUC_RING_BASE 0x8c78 183 184 #define GRBM_CNTL 0x8000 185 # define GRBM_READ_TIMEOUT(x) ((x) << 0) 186 #define GRBM_STATUS 0x8010 187 #define CMDFIFO_AVAIL_MASK 0x0000001F 188 #define GUI_ACTIVE (1<<31) 189 #define GRBM_STATUS2 0x8014 190 #define GRBM_SOFT_RESET 0x8020 191 #define SOFT_RESET_CP (1<<0) 192 193 #define HDP_HOST_PATH_CNTL 0x2C00 194 #define HDP_NONSURFACE_BASE 0x2C04 195 #define HDP_NONSURFACE_INFO 0x2C08 196 #define HDP_NONSURFACE_SIZE 0x2C0C 197 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 198 #define HDP_TILING_CONFIG 0x2F3C 199 200 #define MC_VM_AGP_TOP 0x2184 201 #define MC_VM_AGP_BOT 0x2188 202 #define MC_VM_AGP_BASE 0x218C 203 #define MC_VM_FB_LOCATION 0x2180 204 #define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C 205 #define ENABLE_L1_TLB (1 << 0) 206 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 207 #define ENABLE_L1_STRICT_ORDERING (1 << 2) 208 #define SYSTEM_ACCESS_MODE_MASK 0x000000C0 209 #define SYSTEM_ACCESS_MODE_SHIFT 6 210 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) 211 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) 212 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) 213 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) 214 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) 215 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) 216 #define ENABLE_SEMAPHORE_MODE (1 << 10) 217 #define ENABLE_WAIT_L2_QUERY (1 << 11) 218 #define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12) 219 #define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000 220 #define EFFECTIVE_L1_TLB_SIZE_SHIFT 12 221 #define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15) 222 #define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000 223 #define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15 224 #define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0 225 #define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC 226 #define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204 227 #define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208 228 #define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C 229 #define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200 230 #define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4 231 #define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8 232 #define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210 233 #define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218 234 #define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C 235 #define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220 236 #define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214 237 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 238 #define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF 239 #define LOGICAL_PAGE_NUMBER_SHIFT 0 240 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 241 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 242 243 #define PA_CL_ENHANCE 0x8A14 244 #define CLIP_VTX_REORDER_ENA (1 << 0) 245 #define NUM_CLIP_SEQ(x) ((x) << 1) 246 #define PA_SC_AA_CONFIG 0x28C04 247 #define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40 248 #define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44 249 #define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48 250 #define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C 251 #define S0_X(x) ((x) << 0) 252 #define S0_Y(x) ((x) << 4) 253 #define S1_X(x) ((x) << 8) 254 #define S1_Y(x) ((x) << 12) 255 #define S2_X(x) ((x) << 16) 256 #define S2_Y(x) ((x) << 20) 257 #define S3_X(x) ((x) << 24) 258 #define S3_Y(x) ((x) << 28) 259 #define S4_X(x) ((x) << 0) 260 #define S4_Y(x) ((x) << 4) 261 #define S5_X(x) ((x) << 8) 262 #define S5_Y(x) ((x) << 12) 263 #define S6_X(x) ((x) << 16) 264 #define S6_Y(x) ((x) << 20) 265 #define S7_X(x) ((x) << 24) 266 #define S7_Y(x) ((x) << 28) 267 #define PA_SC_CLIPRECT_RULE 0x2820c 268 #define PA_SC_ENHANCE 0x8BF0 269 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 270 #define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) 271 #define PA_SC_LINE_STIPPLE 0x28A0C 272 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 273 #define PA_SC_MODE_CNTL 0x28A4C 274 #define PA_SC_MULTI_CHIP_CNTL 0x8B20 275 276 #define PA_SC_SCREEN_SCISSOR_TL 0x28030 277 #define PA_SC_GENERIC_SCISSOR_TL 0x28240 278 #define PA_SC_WINDOW_SCISSOR_TL 0x28204 279 280 #define PCIE_PORT_INDEX 0x0038 281 #define PCIE_PORT_DATA 0x003C 282 283 #define CHMAP 0x2004 284 #define NOOFCHAN_SHIFT 12 285 #define NOOFCHAN_MASK 0x00003000 286 287 #define RAMCFG 0x2408 288 #define NOOFBANK_SHIFT 0 289 #define NOOFBANK_MASK 0x00000001 290 #define NOOFRANK_SHIFT 1 291 #define NOOFRANK_MASK 0x00000002 292 #define NOOFROWS_SHIFT 2 293 #define NOOFROWS_MASK 0x0000001C 294 #define NOOFCOLS_SHIFT 5 295 #define NOOFCOLS_MASK 0x00000060 296 #define CHANSIZE_SHIFT 7 297 #define CHANSIZE_MASK 0x00000080 298 #define BURSTLENGTH_SHIFT 8 299 #define BURSTLENGTH_MASK 0x00000100 300 #define CHANSIZE_OVERRIDE (1 << 10) 301 302 #define SCRATCH_REG0 0x8500 303 #define SCRATCH_REG1 0x8504 304 #define SCRATCH_REG2 0x8508 305 #define SCRATCH_REG3 0x850C 306 #define SCRATCH_REG4 0x8510 307 #define SCRATCH_REG5 0x8514 308 #define SCRATCH_REG6 0x8518 309 #define SCRATCH_REG7 0x851C 310 #define SCRATCH_UMSK 0x8540 311 #define SCRATCH_ADDR 0x8544 312 313 #define SPI_CONFIG_CNTL 0x9100 314 #define GPR_WRITE_PRIORITY(x) ((x) << 0) 315 #define DISABLE_INTERP_1 (1 << 5) 316 #define SPI_CONFIG_CNTL_1 0x913C 317 #define VTX_DONE_DELAY(x) ((x) << 0) 318 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 319 #define SPI_INPUT_Z 0x286D8 320 #define SPI_PS_IN_CONTROL_0 0x286CC 321 #define NUM_INTERP(x) ((x)<<0) 322 #define POSITION_ENA (1<<8) 323 #define POSITION_CENTROID (1<<9) 324 #define POSITION_ADDR(x) ((x)<<10) 325 #define PARAM_GEN(x) ((x)<<15) 326 #define PARAM_GEN_ADDR(x) ((x)<<19) 327 #define BARYC_SAMPLE_CNTL(x) ((x)<<26) 328 #define PERSP_GRADIENT_ENA (1<<28) 329 #define LINEAR_GRADIENT_ENA (1<<29) 330 #define POSITION_SAMPLE (1<<30) 331 #define BARYC_AT_SAMPLE_ENA (1<<31) 332 #define SPI_PS_IN_CONTROL_1 0x286D0 333 #define GEN_INDEX_PIX (1<<0) 334 #define GEN_INDEX_PIX_ADDR(x) ((x)<<1) 335 #define FRONT_FACE_ENA (1<<8) 336 #define FRONT_FACE_CHAN(x) ((x)<<9) 337 #define FRONT_FACE_ALL_BITS (1<<11) 338 #define FRONT_FACE_ADDR(x) ((x)<<12) 339 #define FOG_ADDR(x) ((x)<<17) 340 #define FIXED_PT_POSITION_ENA (1<<24) 341 #define FIXED_PT_POSITION_ADDR(x) ((x)<<25) 342 343 #define SQ_MS_FIFO_SIZES 0x8CF0 344 #define CACHE_FIFO_SIZE(x) ((x) << 0) 345 #define FETCH_FIFO_HIWATER(x) ((x) << 8) 346 #define DONE_FIFO_HIWATER(x) ((x) << 16) 347 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 348 #define SQ_PGM_START_ES 0x28880 349 #define SQ_PGM_START_FS 0x28894 350 #define SQ_PGM_START_GS 0x2886C 351 #define SQ_PGM_START_PS 0x28840 352 #define SQ_PGM_RESOURCES_PS 0x28850 353 #define SQ_PGM_EXPORTS_PS 0x28854 354 #define SQ_PGM_CF_OFFSET_PS 0x288cc 355 #define SQ_PGM_START_VS 0x28858 356 #define SQ_PGM_RESOURCES_VS 0x28868 357 #define SQ_PGM_CF_OFFSET_VS 0x288d0 358 #define SQ_VTX_CONSTANT_WORD6_0 0x38018 359 #define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30) 360 #define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3) 361 #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 362 #define SQ_TEX_VTX_INVALID_BUFFER 0x1 363 #define SQ_TEX_VTX_VALID_TEXTURE 0x2 364 #define SQ_TEX_VTX_VALID_BUFFER 0x3 365 366 367 #define SX_MISC 0x28350 368 #define SX_MEMORY_EXPORT_BASE 0x9010 369 #define SX_DEBUG_1 0x9054 370 #define SMX_EVENT_RELEASE (1 << 0) 371 #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 372 373 #define TA_CNTL_AUX 0x9508 374 #define DISABLE_CUBE_WRAP (1 << 0) 375 #define DISABLE_CUBE_ANISO (1 << 1) 376 #define SYNC_GRADIENT (1 << 24) 377 #define SYNC_WALKER (1 << 25) 378 #define SYNC_ALIGNER (1 << 26) 379 #define BILINEAR_PRECISION_6_BIT (0 << 31) 380 #define BILINEAR_PRECISION_8_BIT (1 << 31) 381 382 #define TC_CNTL 0x9608 383 #define TC_L2_SIZE(x) ((x)<<5) 384 #define L2_DISABLE_LATE_HIT (1<<9) 385 386 387 #define VGT_CACHE_INVALIDATION 0x88C4 388 #define CACHE_INVALIDATION(x) ((x)<<0) 389 #define VC_ONLY 0 390 #define TC_ONLY 1 391 #define VC_AND_TC 2 392 #define VGT_DMA_BASE 0x287E8 393 #define VGT_DMA_BASE_HI 0x287E4 394 #define VGT_ES_PER_GS 0x88CC 395 #define VGT_GS_PER_ES 0x88C8 396 #define VGT_GS_PER_VS 0x88E8 397 #define VGT_GS_VERTEX_REUSE 0x88D4 398 #define VGT_PRIMITIVE_TYPE 0x8958 399 #define VGT_NUM_INSTANCES 0x8974 400 #define VGT_OUT_DEALLOC_CNTL 0x28C5C 401 #define DEALLOC_DIST_MASK 0x0000007F 402 #define VGT_STRMOUT_BASE_OFFSET_0 0x28B10 403 #define VGT_STRMOUT_BASE_OFFSET_1 0x28B14 404 #define VGT_STRMOUT_BASE_OFFSET_2 0x28B18 405 #define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c 406 #define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44 407 #define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48 408 #define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c 409 #define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50 410 #define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 411 #define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 412 #define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 413 #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 414 #define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC 415 #define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC 416 #define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC 417 #define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C 418 #define VGT_STRMOUT_EN 0x28AB0 419 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 420 #define VTX_REUSE_DEPTH_MASK 0x000000FF 421 #define VGT_EVENT_INITIATOR 0x28a90 422 # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 423 424 #define VM_CONTEXT0_CNTL 0x1410 425 #define ENABLE_CONTEXT (1 << 0) 426 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 427 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 428 #define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 429 #define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0 430 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 431 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 432 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4 433 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554 434 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 435 #define REQUEST_TYPE(x) (((x) & 0xf) << 0) 436 #define RESPONSE_TYPE_MASK 0x000000F0 437 #define RESPONSE_TYPE_SHIFT 4 438 #define VM_L2_CNTL 0x1400 439 #define ENABLE_L2_CACHE (1 << 0) 440 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 441 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 442 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13) 443 #define VM_L2_CNTL2 0x1404 444 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 445 #define INVALIDATE_L2_CACHE (1 << 1) 446 #define VM_L2_CNTL3 0x1408 447 #define BANK_SELECT_0(x) (((x) & 0x1f) << 0) 448 #define BANK_SELECT_1(x) (((x) & 0x1f) << 5) 449 #define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10) 450 #define VM_L2_STATUS 0x140C 451 #define L2_BUSY (1 << 0) 452 453 #define WAIT_UNTIL 0x8040 454 #define WAIT_2D_IDLE_bit (1 << 14) 455 #define WAIT_3D_IDLE_bit (1 << 15) 456 #define WAIT_2D_IDLECLEAN_bit (1 << 16) 457 #define WAIT_3D_IDLECLEAN_bit (1 << 17) 458 459 #define IH_RB_CNTL 0x3e00 460 # define IH_RB_ENABLE (1 << 0) 461 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 462 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 463 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 464 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 465 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 466 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 467 #define IH_RB_BASE 0x3e04 468 #define IH_RB_RPTR 0x3e08 469 #define IH_RB_WPTR 0x3e0c 470 # define RB_OVERFLOW (1 << 0) 471 # define WPTR_OFFSET_MASK 0x3fffc 472 #define IH_RB_WPTR_ADDR_HI 0x3e10 473 #define IH_RB_WPTR_ADDR_LO 0x3e14 474 #define IH_CNTL 0x3e18 475 # define ENABLE_INTR (1 << 0) 476 # define IH_MC_SWAP(x) ((x) << 2) 477 # define IH_MC_SWAP_NONE 0 478 # define IH_MC_SWAP_16BIT 1 479 # define IH_MC_SWAP_32BIT 2 480 # define IH_MC_SWAP_64BIT 3 481 # define RPTR_REARM (1 << 4) 482 # define MC_WRREQ_CREDIT(x) ((x) << 15) 483 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 484 485 #define RLC_CNTL 0x3f00 486 # define RLC_ENABLE (1 << 0) 487 #define RLC_HB_BASE 0x3f10 488 #define RLC_HB_CNTL 0x3f0c 489 #define RLC_HB_RPTR 0x3f20 490 #define RLC_HB_WPTR 0x3f1c 491 #define RLC_HB_WPTR_LSB_ADDR 0x3f14 492 #define RLC_HB_WPTR_MSB_ADDR 0x3f18 493 #define RLC_MC_CNTL 0x3f44 494 #define RLC_UCODE_CNTL 0x3f48 495 #define RLC_UCODE_ADDR 0x3f2c 496 #define RLC_UCODE_DATA 0x3f30 497 498 #define SRBM_SOFT_RESET 0xe60 499 # define SOFT_RESET_RLC (1 << 13) 500 501 #define CP_INT_CNTL 0xc124 502 # define CNTX_BUSY_INT_ENABLE (1 << 19) 503 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 504 # define SCRATCH_INT_ENABLE (1 << 25) 505 # define TIME_STAMP_INT_ENABLE (1 << 26) 506 # define IB2_INT_ENABLE (1 << 29) 507 # define IB1_INT_ENABLE (1 << 30) 508 # define RB_INT_ENABLE (1 << 31) 509 #define CP_INT_STATUS 0xc128 510 # define SCRATCH_INT_STAT (1 << 25) 511 # define TIME_STAMP_INT_STAT (1 << 26) 512 # define IB2_INT_STAT (1 << 29) 513 # define IB1_INT_STAT (1 << 30) 514 # define RB_INT_STAT (1 << 31) 515 516 #define GRBM_INT_CNTL 0x8060 517 # define RDERR_INT_ENABLE (1 << 0) 518 # define WAIT_COUNT_TIMEOUT_INT_ENABLE (1 << 1) 519 # define GUI_IDLE_INT_ENABLE (1 << 19) 520 521 #define INTERRUPT_CNTL 0x5468 522 # define IH_DUMMY_RD_OVERRIDE (1 << 0) 523 # define IH_DUMMY_RD_EN (1 << 1) 524 # define IH_REQ_NONSNOOP_EN (1 << 3) 525 # define GEN_IH_INT_EN (1 << 8) 526 #define INTERRUPT_CNTL2 0x546c 527 528 #define D1MODE_VBLANK_STATUS 0x6534 529 #define D2MODE_VBLANK_STATUS 0x6d34 530 # define DxMODE_VBLANK_OCCURRED (1 << 0) 531 # define DxMODE_VBLANK_ACK (1 << 4) 532 # define DxMODE_VBLANK_STAT (1 << 12) 533 # define DxMODE_VBLANK_INTERRUPT (1 << 16) 534 # define DxMODE_VBLANK_INTERRUPT_TYPE (1 << 17) 535 #define D1MODE_VLINE_STATUS 0x653c 536 #define D2MODE_VLINE_STATUS 0x6d3c 537 # define DxMODE_VLINE_OCCURRED (1 << 0) 538 # define DxMODE_VLINE_ACK (1 << 4) 539 # define DxMODE_VLINE_STAT (1 << 12) 540 # define DxMODE_VLINE_INTERRUPT (1 << 16) 541 # define DxMODE_VLINE_INTERRUPT_TYPE (1 << 17) 542 #define DxMODE_INT_MASK 0x6540 543 # define D1MODE_VBLANK_INT_MASK (1 << 0) 544 # define D1MODE_VLINE_INT_MASK (1 << 4) 545 # define D2MODE_VBLANK_INT_MASK (1 << 8) 546 # define D2MODE_VLINE_INT_MASK (1 << 12) 547 #define DCE3_DISP_INTERRUPT_STATUS 0x7ddc 548 # define DC_HPD1_INTERRUPT (1 << 18) 549 # define DC_HPD2_INTERRUPT (1 << 19) 550 #define DISP_INTERRUPT_STATUS 0x7edc 551 # define LB_D1_VLINE_INTERRUPT (1 << 2) 552 # define LB_D2_VLINE_INTERRUPT (1 << 3) 553 # define LB_D1_VBLANK_INTERRUPT (1 << 4) 554 # define LB_D2_VBLANK_INTERRUPT (1 << 5) 555 # define DACA_AUTODETECT_INTERRUPT (1 << 16) 556 # define DACB_AUTODETECT_INTERRUPT (1 << 17) 557 # define DC_HOT_PLUG_DETECT1_INTERRUPT (1 << 18) 558 # define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19) 559 # define DC_I2C_SW_DONE_INTERRUPT (1 << 20) 560 # define DC_I2C_HW_DONE_INTERRUPT (1 << 21) 561 #define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8 562 #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8 563 # define DC_HPD4_INTERRUPT (1 << 14) 564 # define DC_HPD4_RX_INTERRUPT (1 << 15) 565 # define DC_HPD3_INTERRUPT (1 << 28) 566 # define DC_HPD1_RX_INTERRUPT (1 << 29) 567 # define DC_HPD2_RX_INTERRUPT (1 << 30) 568 #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE2 0x7dec 569 # define DC_HPD3_RX_INTERRUPT (1 << 0) 570 # define DIGA_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 1) 571 # define DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 2) 572 # define DIGB_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 3) 573 # define DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 4) 574 # define AUX1_SW_DONE_INTERRUPT (1 << 5) 575 # define AUX1_LS_DONE_INTERRUPT (1 << 6) 576 # define AUX2_SW_DONE_INTERRUPT (1 << 7) 577 # define AUX2_LS_DONE_INTERRUPT (1 << 8) 578 # define AUX3_SW_DONE_INTERRUPT (1 << 9) 579 # define AUX3_LS_DONE_INTERRUPT (1 << 10) 580 # define AUX4_SW_DONE_INTERRUPT (1 << 11) 581 # define AUX4_LS_DONE_INTERRUPT (1 << 12) 582 # define DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 13) 583 # define DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 14) 584 /* DCE 3.2 */ 585 # define AUX5_SW_DONE_INTERRUPT (1 << 15) 586 # define AUX5_LS_DONE_INTERRUPT (1 << 16) 587 # define AUX6_SW_DONE_INTERRUPT (1 << 17) 588 # define AUX6_LS_DONE_INTERRUPT (1 << 18) 589 # define DC_HPD5_INTERRUPT (1 << 19) 590 # define DC_HPD5_RX_INTERRUPT (1 << 20) 591 # define DC_HPD6_INTERRUPT (1 << 21) 592 # define DC_HPD6_RX_INTERRUPT (1 << 22) 593 594 #define DACA_AUTO_DETECT_CONTROL 0x7828 595 #define DACB_AUTO_DETECT_CONTROL 0x7a28 596 #define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028 597 #define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128 598 # define DACx_AUTODETECT_MODE(x) ((x) << 0) 599 # define DACx_AUTODETECT_MODE_NONE 0 600 # define DACx_AUTODETECT_MODE_CONNECT 1 601 # define DACx_AUTODETECT_MODE_DISCONNECT 2 602 # define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8) 603 /* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */ 604 # define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16) 605 606 #define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038 607 #define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138 608 #define DACA_AUTODETECT_INT_CONTROL 0x7838 609 #define DACB_AUTODETECT_INT_CONTROL 0x7a38 610 # define DACx_AUTODETECT_ACK (1 << 0) 611 # define DACx_AUTODETECT_INT_ENABLE (1 << 16) 612 613 #define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00 614 #define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10 615 #define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24 616 # define DC_HOT_PLUG_DETECTx_EN (1 << 0) 617 618 #define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04 619 #define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14 620 #define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28 621 # define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0) 622 # define DC_HOT_PLUG_DETECTx_SENSE (1 << 1) 623 624 /* DCE 3.0 */ 625 #define DC_HPD1_INT_STATUS 0x7d00 626 #define DC_HPD2_INT_STATUS 0x7d0c 627 #define DC_HPD3_INT_STATUS 0x7d18 628 #define DC_HPD4_INT_STATUS 0x7d24 629 /* DCE 3.2 */ 630 #define DC_HPD5_INT_STATUS 0x7dc0 631 #define DC_HPD6_INT_STATUS 0x7df4 632 # define DC_HPDx_INT_STATUS (1 << 0) 633 # define DC_HPDx_SENSE (1 << 1) 634 # define DC_HPDx_RX_INT_STATUS (1 << 8) 635 636 #define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08 637 #define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18 638 #define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c 639 # define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0) 640 # define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8) 641 # define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16) 642 /* DCE 3.0 */ 643 #define DC_HPD1_INT_CONTROL 0x7d04 644 #define DC_HPD2_INT_CONTROL 0x7d10 645 #define DC_HPD3_INT_CONTROL 0x7d1c 646 #define DC_HPD4_INT_CONTROL 0x7d28 647 /* DCE 3.2 */ 648 #define DC_HPD5_INT_CONTROL 0x7dc4 649 #define DC_HPD6_INT_CONTROL 0x7df8 650 # define DC_HPDx_INT_ACK (1 << 0) 651 # define DC_HPDx_INT_POLARITY (1 << 8) 652 # define DC_HPDx_INT_EN (1 << 16) 653 # define DC_HPDx_RX_INT_ACK (1 << 20) 654 # define DC_HPDx_RX_INT_EN (1 << 24) 655 656 /* DCE 3.0 */ 657 #define DC_HPD1_CONTROL 0x7d08 658 #define DC_HPD2_CONTROL 0x7d14 659 #define DC_HPD3_CONTROL 0x7d20 660 #define DC_HPD4_CONTROL 0x7d2c 661 /* DCE 3.2 */ 662 #define DC_HPD5_CONTROL 0x7dc8 663 #define DC_HPD6_CONTROL 0x7dfc 664 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 665 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 666 /* DCE 3.2 */ 667 # define DC_HPDx_EN (1 << 28) 668 669 /* 670 * PM4 671 */ 672 #define PACKET_TYPE0 0 673 #define PACKET_TYPE1 1 674 #define PACKET_TYPE2 2 675 #define PACKET_TYPE3 3 676 677 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 678 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 679 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 680 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 681 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 682 (((reg) >> 2) & 0xFFFF) | \ 683 ((n) & 0x3FFF) << 16) 684 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 685 (((op) & 0xFF) << 8) | \ 686 ((n) & 0x3FFF) << 16) 687 688 /* Packet 3 types */ 689 #define PACKET3_NOP 0x10 690 #define PACKET3_INDIRECT_BUFFER_END 0x17 691 #define PACKET3_SET_PREDICATION 0x20 692 #define PACKET3_REG_RMW 0x21 693 #define PACKET3_COND_EXEC 0x22 694 #define PACKET3_PRED_EXEC 0x23 695 #define PACKET3_START_3D_CMDBUF 0x24 696 #define PACKET3_DRAW_INDEX_2 0x27 697 #define PACKET3_CONTEXT_CONTROL 0x28 698 #define PACKET3_DRAW_INDEX_IMMD_BE 0x29 699 #define PACKET3_INDEX_TYPE 0x2A 700 #define PACKET3_DRAW_INDEX 0x2B 701 #define PACKET3_DRAW_INDEX_AUTO 0x2D 702 #define PACKET3_DRAW_INDEX_IMMD 0x2E 703 #define PACKET3_NUM_INSTANCES 0x2F 704 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 705 #define PACKET3_INDIRECT_BUFFER_MP 0x38 706 #define PACKET3_MEM_SEMAPHORE 0x39 707 #define PACKET3_MPEG_INDEX 0x3A 708 #define PACKET3_WAIT_REG_MEM 0x3C 709 #define PACKET3_MEM_WRITE 0x3D 710 #define PACKET3_INDIRECT_BUFFER 0x32 711 #define PACKET3_SURFACE_SYNC 0x43 712 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 713 # define PACKET3_TC_ACTION_ENA (1 << 23) 714 # define PACKET3_VC_ACTION_ENA (1 << 24) 715 # define PACKET3_CB_ACTION_ENA (1 << 25) 716 # define PACKET3_DB_ACTION_ENA (1 << 26) 717 # define PACKET3_SH_ACTION_ENA (1 << 27) 718 # define PACKET3_SMX_ACTION_ENA (1 << 28) 719 #define PACKET3_ME_INITIALIZE 0x44 720 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 721 #define PACKET3_COND_WRITE 0x45 722 #define PACKET3_EVENT_WRITE 0x46 723 #define PACKET3_EVENT_WRITE_EOP 0x47 724 #define PACKET3_ONE_REG_WRITE 0x57 725 #define PACKET3_SET_CONFIG_REG 0x68 726 #define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000 727 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 728 #define PACKET3_SET_CONTEXT_REG 0x69 729 #define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000 730 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 731 #define PACKET3_SET_ALU_CONST 0x6A 732 #define PACKET3_SET_ALU_CONST_OFFSET 0x00030000 733 #define PACKET3_SET_ALU_CONST_END 0x00032000 734 #define PACKET3_SET_BOOL_CONST 0x6B 735 #define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380 736 #define PACKET3_SET_BOOL_CONST_END 0x00040000 737 #define PACKET3_SET_LOOP_CONST 0x6C 738 #define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200 739 #define PACKET3_SET_LOOP_CONST_END 0x0003e380 740 #define PACKET3_SET_RESOURCE 0x6D 741 #define PACKET3_SET_RESOURCE_OFFSET 0x00038000 742 #define PACKET3_SET_RESOURCE_END 0x0003c000 743 #define PACKET3_SET_SAMPLER 0x6E 744 #define PACKET3_SET_SAMPLER_OFFSET 0x0003c000 745 #define PACKET3_SET_SAMPLER_END 0x0003cff0 746 #define PACKET3_SET_CTL_CONST 0x6F 747 #define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0 748 #define PACKET3_SET_CTL_CONST_END 0x0003e200 749 #define PACKET3_SURFACE_BASE_UPDATE 0x73 750 751 752 #define R_008020_GRBM_SOFT_RESET 0x8020 753 #define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0) 754 #define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1) 755 #define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2) 756 #define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3) 757 #define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5) 758 #define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6) 759 #define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7) 760 #define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8) 761 #define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9) 762 #define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10) 763 #define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11) 764 #define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12) 765 #define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13) 766 #define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14) 767 #define R_008010_GRBM_STATUS 0x8010 768 #define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0) 769 #define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6) 770 #define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7) 771 #define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8) 772 #define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10) 773 #define S_008010_VC_BUSY(x) (((x) & 1) << 11) 774 #define S_008010_DB03_CLEAN(x) (((x) & 1) << 12) 775 #define S_008010_CB03_CLEAN(x) (((x) & 1) << 13) 776 #define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16) 777 #define S_008010_VGT_BUSY(x) (((x) & 1) << 17) 778 #define S_008010_TA03_BUSY(x) (((x) & 1) << 18) 779 #define S_008010_TC_BUSY(x) (((x) & 1) << 19) 780 #define S_008010_SX_BUSY(x) (((x) & 1) << 20) 781 #define S_008010_SH_BUSY(x) (((x) & 1) << 21) 782 #define S_008010_SPI03_BUSY(x) (((x) & 1) << 22) 783 #define S_008010_SMX_BUSY(x) (((x) & 1) << 23) 784 #define S_008010_SC_BUSY(x) (((x) & 1) << 24) 785 #define S_008010_PA_BUSY(x) (((x) & 1) << 25) 786 #define S_008010_DB03_BUSY(x) (((x) & 1) << 26) 787 #define S_008010_CR_BUSY(x) (((x) & 1) << 27) 788 #define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28) 789 #define S_008010_CP_BUSY(x) (((x) & 1) << 29) 790 #define S_008010_CB03_BUSY(x) (((x) & 1) << 30) 791 #define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31) 792 #define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F) 793 #define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1) 794 #define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1) 795 #define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1) 796 #define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1) 797 #define G_008010_VC_BUSY(x) (((x) >> 11) & 1) 798 #define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1) 799 #define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1) 800 #define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1) 801 #define G_008010_VGT_BUSY(x) (((x) >> 17) & 1) 802 #define G_008010_TA03_BUSY(x) (((x) >> 18) & 1) 803 #define G_008010_TC_BUSY(x) (((x) >> 19) & 1) 804 #define G_008010_SX_BUSY(x) (((x) >> 20) & 1) 805 #define G_008010_SH_BUSY(x) (((x) >> 21) & 1) 806 #define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1) 807 #define G_008010_SMX_BUSY(x) (((x) >> 23) & 1) 808 #define G_008010_SC_BUSY(x) (((x) >> 24) & 1) 809 #define G_008010_PA_BUSY(x) (((x) >> 25) & 1) 810 #define G_008010_DB03_BUSY(x) (((x) >> 26) & 1) 811 #define G_008010_CR_BUSY(x) (((x) >> 27) & 1) 812 #define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1) 813 #define G_008010_CP_BUSY(x) (((x) >> 29) & 1) 814 #define G_008010_CB03_BUSY(x) (((x) >> 30) & 1) 815 #define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1) 816 #define R_008014_GRBM_STATUS2 0x8014 817 #define S_008014_CR_CLEAN(x) (((x) & 1) << 0) 818 #define S_008014_SMX_CLEAN(x) (((x) & 1) << 1) 819 #define S_008014_SPI0_BUSY(x) (((x) & 1) << 8) 820 #define S_008014_SPI1_BUSY(x) (((x) & 1) << 9) 821 #define S_008014_SPI2_BUSY(x) (((x) & 1) << 10) 822 #define S_008014_SPI3_BUSY(x) (((x) & 1) << 11) 823 #define S_008014_TA0_BUSY(x) (((x) & 1) << 12) 824 #define S_008014_TA1_BUSY(x) (((x) & 1) << 13) 825 #define S_008014_TA2_BUSY(x) (((x) & 1) << 14) 826 #define S_008014_TA3_BUSY(x) (((x) & 1) << 15) 827 #define S_008014_DB0_BUSY(x) (((x) & 1) << 16) 828 #define S_008014_DB1_BUSY(x) (((x) & 1) << 17) 829 #define S_008014_DB2_BUSY(x) (((x) & 1) << 18) 830 #define S_008014_DB3_BUSY(x) (((x) & 1) << 19) 831 #define S_008014_CB0_BUSY(x) (((x) & 1) << 20) 832 #define S_008014_CB1_BUSY(x) (((x) & 1) << 21) 833 #define S_008014_CB2_BUSY(x) (((x) & 1) << 22) 834 #define S_008014_CB3_BUSY(x) (((x) & 1) << 23) 835 #define G_008014_CR_CLEAN(x) (((x) >> 0) & 1) 836 #define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1) 837 #define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1) 838 #define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1) 839 #define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1) 840 #define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1) 841 #define G_008014_TA0_BUSY(x) (((x) >> 12) & 1) 842 #define G_008014_TA1_BUSY(x) (((x) >> 13) & 1) 843 #define G_008014_TA2_BUSY(x) (((x) >> 14) & 1) 844 #define G_008014_TA3_BUSY(x) (((x) >> 15) & 1) 845 #define G_008014_DB0_BUSY(x) (((x) >> 16) & 1) 846 #define G_008014_DB1_BUSY(x) (((x) >> 17) & 1) 847 #define G_008014_DB2_BUSY(x) (((x) >> 18) & 1) 848 #define G_008014_DB3_BUSY(x) (((x) >> 19) & 1) 849 #define G_008014_CB0_BUSY(x) (((x) >> 20) & 1) 850 #define G_008014_CB1_BUSY(x) (((x) >> 21) & 1) 851 #define G_008014_CB2_BUSY(x) (((x) >> 22) & 1) 852 #define G_008014_CB3_BUSY(x) (((x) >> 23) & 1) 853 #define R_000E50_SRBM_STATUS 0x0E50 854 #define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1) 855 #define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1) 856 #define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1) 857 #define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1) 858 #define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1) 859 #define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1) 860 #define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1) 861 #define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1) 862 #define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1) 863 #define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1) 864 #define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1) 865 #define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1) 866 #define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1) 867 #define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1) 868 #define R_000E60_SRBM_SOFT_RESET 0x0E60 869 #define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1) 870 #define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2) 871 #define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3) 872 #define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4) 873 #define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5) 874 #define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8) 875 #define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9) 876 #define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10) 877 #define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11) 878 #define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13) 879 #define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14) 880 #define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15) 881 #define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16) 882 #define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17) 883 884 #define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 885 886 #define R_0280E0_CB_COLOR0_FRAG 0x0280E0 887 #define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) 888 #define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) 889 #define C_0280E0_BASE_256B 0x00000000 890 #define R_0280E4_CB_COLOR1_FRAG 0x0280E4 891 #define R_0280E8_CB_COLOR2_FRAG 0x0280E8 892 #define R_0280EC_CB_COLOR3_FRAG 0x0280EC 893 #define R_0280F0_CB_COLOR4_FRAG 0x0280F0 894 #define R_0280F4_CB_COLOR5_FRAG 0x0280F4 895 #define R_0280F8_CB_COLOR6_FRAG 0x0280F8 896 #define R_0280FC_CB_COLOR7_FRAG 0x0280FC 897 #define R_0280C0_CB_COLOR0_TILE 0x0280C0 898 #define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) 899 #define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) 900 #define C_0280C0_BASE_256B 0x00000000 901 #define R_0280C4_CB_COLOR1_TILE 0x0280C4 902 #define R_0280C8_CB_COLOR2_TILE 0x0280C8 903 #define R_0280CC_CB_COLOR3_TILE 0x0280CC 904 #define R_0280D0_CB_COLOR4_TILE 0x0280D0 905 #define R_0280D4_CB_COLOR5_TILE 0x0280D4 906 #define R_0280D8_CB_COLOR6_TILE 0x0280D8 907 #define R_0280DC_CB_COLOR7_TILE 0x0280DC 908 909 910 #endif 911