xref: /openbmc/linux/drivers/gpu/drm/radeon/r600_reg.h (revision fa6bee46)
1771fe6b9SJerome Glisse /*
2771fe6b9SJerome Glisse  * Copyright 2008 Advanced Micro Devices, Inc.
3771fe6b9SJerome Glisse  * Copyright 2008 Red Hat Inc.
4771fe6b9SJerome Glisse  * Copyright 2009 Jerome Glisse.
5771fe6b9SJerome Glisse  *
6771fe6b9SJerome Glisse  * Permission is hereby granted, free of charge, to any person obtaining a
7771fe6b9SJerome Glisse  * copy of this software and associated documentation files (the "Software"),
8771fe6b9SJerome Glisse  * to deal in the Software without restriction, including without limitation
9771fe6b9SJerome Glisse  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10771fe6b9SJerome Glisse  * and/or sell copies of the Software, and to permit persons to whom the
11771fe6b9SJerome Glisse  * Software is furnished to do so, subject to the following conditions:
12771fe6b9SJerome Glisse  *
13771fe6b9SJerome Glisse  * The above copyright notice and this permission notice shall be included in
14771fe6b9SJerome Glisse  * all copies or substantial portions of the Software.
15771fe6b9SJerome Glisse  *
16771fe6b9SJerome Glisse  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17771fe6b9SJerome Glisse  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18771fe6b9SJerome Glisse  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19771fe6b9SJerome Glisse  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20771fe6b9SJerome Glisse  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21771fe6b9SJerome Glisse  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22771fe6b9SJerome Glisse  * OTHER DEALINGS IN THE SOFTWARE.
23771fe6b9SJerome Glisse  *
24771fe6b9SJerome Glisse  * Authors: Dave Airlie
25771fe6b9SJerome Glisse  *          Alex Deucher
26771fe6b9SJerome Glisse  *          Jerome Glisse
27771fe6b9SJerome Glisse  */
28771fe6b9SJerome Glisse #ifndef __R600_REG_H__
29771fe6b9SJerome Glisse #define __R600_REG_H__
30771fe6b9SJerome Glisse 
31771fe6b9SJerome Glisse #define R600_PCIE_PORT_INDEX                0x0038
32771fe6b9SJerome Glisse #define R600_PCIE_PORT_DATA                 0x003c
33771fe6b9SJerome Glisse 
34771fe6b9SJerome Glisse #define R600_MC_VM_FB_LOCATION			0x2180
35771fe6b9SJerome Glisse #define		R600_MC_FB_BASE_MASK			0x0000FFFF
36771fe6b9SJerome Glisse #define		R600_MC_FB_BASE_SHIFT			0
37771fe6b9SJerome Glisse #define		R600_MC_FB_TOP_MASK			0xFFFF0000
38771fe6b9SJerome Glisse #define		R600_MC_FB_TOP_SHIFT			16
39771fe6b9SJerome Glisse #define R600_MC_VM_AGP_TOP			0x2184
40771fe6b9SJerome Glisse #define		R600_MC_AGP_TOP_MASK			0x0003FFFF
41771fe6b9SJerome Glisse #define		R600_MC_AGP_TOP_SHIFT			0
42771fe6b9SJerome Glisse #define R600_MC_VM_AGP_BOT			0x2188
43771fe6b9SJerome Glisse #define		R600_MC_AGP_BOT_MASK			0x0003FFFF
44771fe6b9SJerome Glisse #define		R600_MC_AGP_BOT_SHIFT			0
45771fe6b9SJerome Glisse #define R600_MC_VM_AGP_BASE			0x218c
46771fe6b9SJerome Glisse #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR	0x2190
47771fe6b9SJerome Glisse #define		R600_LOGICAL_PAGE_NUMBER_MASK		0x000FFFFF
48771fe6b9SJerome Glisse #define		R600_LOGICAL_PAGE_NUMBER_SHIFT		0
49771fe6b9SJerome Glisse #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR	0x2194
50771fe6b9SJerome Glisse #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR	0x2198
51771fe6b9SJerome Glisse 
52771fe6b9SJerome Glisse #define R700_MC_VM_FB_LOCATION			0x2024
53771fe6b9SJerome Glisse #define		R700_MC_FB_BASE_MASK			0x0000FFFF
54771fe6b9SJerome Glisse #define		R700_MC_FB_BASE_SHIFT			0
55771fe6b9SJerome Glisse #define		R700_MC_FB_TOP_MASK			0xFFFF0000
56771fe6b9SJerome Glisse #define		R700_MC_FB_TOP_SHIFT			16
57771fe6b9SJerome Glisse #define R700_MC_VM_AGP_TOP			0x2028
58771fe6b9SJerome Glisse #define		R700_MC_AGP_TOP_MASK			0x0003FFFF
59771fe6b9SJerome Glisse #define		R700_MC_AGP_TOP_SHIFT			0
60771fe6b9SJerome Glisse #define R700_MC_VM_AGP_BOT			0x202c
61771fe6b9SJerome Glisse #define		R700_MC_AGP_BOT_MASK			0x0003FFFF
62771fe6b9SJerome Glisse #define		R700_MC_AGP_BOT_SHIFT			0
63771fe6b9SJerome Glisse #define R700_MC_VM_AGP_BASE			0x2030
64771fe6b9SJerome Glisse #define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR	0x2034
65771fe6b9SJerome Glisse #define		R700_LOGICAL_PAGE_NUMBER_MASK		0x000FFFFF
66771fe6b9SJerome Glisse #define		R700_LOGICAL_PAGE_NUMBER_SHIFT		0
67771fe6b9SJerome Glisse #define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR	0x2038
68771fe6b9SJerome Glisse #define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR	0x203c
69771fe6b9SJerome Glisse 
70771fe6b9SJerome Glisse #define R600_RAMCFG				       0x2408
71771fe6b9SJerome Glisse #       define R600_CHANSIZE                           (1 << 7)
72771fe6b9SJerome Glisse #       define R600_CHANSIZE_OVERRIDE                  (1 << 10)
73771fe6b9SJerome Glisse 
74771fe6b9SJerome Glisse 
75771fe6b9SJerome Glisse #define R600_GENERAL_PWRMGT                                        0x618
76771fe6b9SJerome Glisse #	define R600_OPEN_DRAIN_PADS				   (1 << 11)
77771fe6b9SJerome Glisse 
78771fe6b9SJerome Glisse #define R600_LOWER_GPIO_ENABLE                                     0x710
79771fe6b9SJerome Glisse #define R600_CTXSW_VID_LOWER_GPIO_CNTL                             0x718
80771fe6b9SJerome Glisse #define R600_HIGH_VID_LOWER_GPIO_CNTL                              0x71c
81771fe6b9SJerome Glisse #define R600_MEDIUM_VID_LOWER_GPIO_CNTL                            0x720
82771fe6b9SJerome Glisse #define R600_LOW_VID_LOWER_GPIO_CNTL                               0x724
83771fe6b9SJerome Glisse 
84fa6bee46SAlex Deucher #define R600_D1GRPH_SWAP_CONTROL                               0x610C
85fa6bee46SAlex Deucher #       define R600_D1GRPH_SWAP_ENDIAN_NONE                    (0 << 0)
86fa6bee46SAlex Deucher #       define R600_D1GRPH_SWAP_ENDIAN_16BIT                   (1 << 0)
87fa6bee46SAlex Deucher #       define R600_D1GRPH_SWAP_ENDIAN_32BIT                   (2 << 0)
88fa6bee46SAlex Deucher #       define R600_D1GRPH_SWAP_ENDIAN_64BIT                   (3 << 0)
89771fe6b9SJerome Glisse 
90771fe6b9SJerome Glisse #define R600_HDP_NONSURFACE_BASE                                0x2c04
91771fe6b9SJerome Glisse 
92771fe6b9SJerome Glisse #define R600_BUS_CNTL                                           0x5420
930ec80d64SAlex Deucher #       define R600_BIOS_ROM_DIS                                (1 << 1)
94771fe6b9SJerome Glisse #define R600_CONFIG_CNTL                                        0x5424
95771fe6b9SJerome Glisse #define R600_CONFIG_MEMSIZE                                     0x5428
96771fe6b9SJerome Glisse #define R600_CONFIG_F0_BASE                                     0x542C
97771fe6b9SJerome Glisse #define R600_CONFIG_APER_SIZE                                   0x5430
98771fe6b9SJerome Glisse 
99771fe6b9SJerome Glisse #define R600_ROM_CNTL                              0x1600
100771fe6b9SJerome Glisse #       define R600_SCK_OVERWRITE                  (1 << 1)
101771fe6b9SJerome Glisse #       define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28
102771fe6b9SJerome Glisse #       define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK  (0xf << 28)
103771fe6b9SJerome Glisse 
104771fe6b9SJerome Glisse #define R600_CG_SPLL_FUNC_CNTL                     0x600
105771fe6b9SJerome Glisse #       define R600_SPLL_BYPASS_EN                 (1 << 3)
106771fe6b9SJerome Glisse #define R600_CG_SPLL_STATUS                        0x60c
107771fe6b9SJerome Glisse #       define R600_SPLL_CHG_STATUS                (1 << 1)
108771fe6b9SJerome Glisse 
109771fe6b9SJerome Glisse #define R600_BIOS_0_SCRATCH               0x1724
110771fe6b9SJerome Glisse #define R600_BIOS_1_SCRATCH               0x1728
111771fe6b9SJerome Glisse #define R600_BIOS_2_SCRATCH               0x172c
112771fe6b9SJerome Glisse #define R600_BIOS_3_SCRATCH               0x1730
113771fe6b9SJerome Glisse #define R600_BIOS_4_SCRATCH               0x1734
114771fe6b9SJerome Glisse #define R600_BIOS_5_SCRATCH               0x1738
115771fe6b9SJerome Glisse #define R600_BIOS_6_SCRATCH               0x173c
116771fe6b9SJerome Glisse #define R600_BIOS_7_SCRATCH               0x1740
117771fe6b9SJerome Glisse 
118dafc3bd5SChristian Koenig /* Audio, these regs were reverse enginered,
119dafc3bd5SChristian Koenig  * so the chance is high that the naming is wrong
120dafc3bd5SChristian Koenig  * R6xx+ ??? */
121dafc3bd5SChristian Koenig 
122dafc3bd5SChristian Koenig /* Audio clocks */
123dafc3bd5SChristian Koenig #define R600_AUDIO_PLL1_MUL               0x0514
124dafc3bd5SChristian Koenig #define R600_AUDIO_PLL1_DIV               0x0518
125dafc3bd5SChristian Koenig #define R600_AUDIO_PLL2_MUL               0x0524
126dafc3bd5SChristian Koenig #define R600_AUDIO_PLL2_DIV               0x0528
127dafc3bd5SChristian Koenig #define R600_AUDIO_CLK_SRCSEL             0x0534
128dafc3bd5SChristian Koenig 
129dafc3bd5SChristian Koenig /* Audio general */
130dafc3bd5SChristian Koenig #define R600_AUDIO_ENABLE                 0x7300
131dafc3bd5SChristian Koenig #define R600_AUDIO_TIMING                 0x7344
132dafc3bd5SChristian Koenig 
133dafc3bd5SChristian Koenig /* Audio params */
134dafc3bd5SChristian Koenig #define R600_AUDIO_VENDOR_ID              0x7380
135dafc3bd5SChristian Koenig #define R600_AUDIO_REVISION_ID            0x7384
136dafc3bd5SChristian Koenig #define R600_AUDIO_ROOT_NODE_COUNT        0x7388
137dafc3bd5SChristian Koenig #define R600_AUDIO_NID1_NODE_COUNT        0x738c
138dafc3bd5SChristian Koenig #define R600_AUDIO_NID1_TYPE              0x7390
139dafc3bd5SChristian Koenig #define R600_AUDIO_SUPPORTED_SIZE_RATE    0x7394
140dafc3bd5SChristian Koenig #define R600_AUDIO_SUPPORTED_CODEC        0x7398
141dafc3bd5SChristian Koenig #define R600_AUDIO_SUPPORTED_POWER_STATES 0x739c
142dafc3bd5SChristian Koenig #define R600_AUDIO_NID2_CAPS              0x73a0
143dafc3bd5SChristian Koenig #define R600_AUDIO_NID3_CAPS              0x73a4
144dafc3bd5SChristian Koenig #define R600_AUDIO_NID3_PIN_CAPS          0x73a8
145dafc3bd5SChristian Koenig 
146dafc3bd5SChristian Koenig /* Audio conn list */
147dafc3bd5SChristian Koenig #define R600_AUDIO_CONN_LIST_LEN          0x73ac
148dafc3bd5SChristian Koenig #define R600_AUDIO_CONN_LIST              0x73b0
149dafc3bd5SChristian Koenig 
150dafc3bd5SChristian Koenig /* Audio verbs */
151dafc3bd5SChristian Koenig #define R600_AUDIO_RATE_BPS_CHANNEL       0x73c0
152dafc3bd5SChristian Koenig #define R600_AUDIO_PLAYING                0x73c4
153dafc3bd5SChristian Koenig #define R600_AUDIO_IMPLEMENTATION_ID      0x73c8
154dafc3bd5SChristian Koenig #define R600_AUDIO_CONFIG_DEFAULT         0x73cc
155dafc3bd5SChristian Koenig #define R600_AUDIO_PIN_SENSE              0x73d0
156dafc3bd5SChristian Koenig #define R600_AUDIO_PIN_WIDGET_CNTL        0x73d4
157dafc3bd5SChristian Koenig #define R600_AUDIO_STATUS_BITS            0x73d8
158dafc3bd5SChristian Koenig 
159dafc3bd5SChristian Koenig /* HDMI base register addresses */
160808032eeSRafał Miłecki #define R600_HDMI_BLOCK1                  0x7400
161808032eeSRafał Miłecki #define R600_HDMI_BLOCK2                  0x7700
162808032eeSRafał Miłecki #define R600_HDMI_BLOCK3                  0x7800
163dafc3bd5SChristian Koenig 
164dafc3bd5SChristian Koenig /* HDMI registers */
165dafc3bd5SChristian Koenig #define R600_HDMI_ENABLE                0x00
166dafc3bd5SChristian Koenig #define R600_HDMI_STATUS                0x04
167f2594933SChristian Koenig #       define R600_HDMI_INT_PENDING    (1 << 29)
168dafc3bd5SChristian Koenig #define R600_HDMI_CNTL                  0x08
169f2594933SChristian Koenig #       define R600_HDMI_INT_EN         (1 << 28)
170f2594933SChristian Koenig #       define R600_HDMI_INT_ACK        (1 << 29)
171dafc3bd5SChristian Koenig #define R600_HDMI_UNKNOWN_0             0x0C
172dafc3bd5SChristian Koenig #define R600_HDMI_AUDIOCNTL             0x10
173dafc3bd5SChristian Koenig #define R600_HDMI_VIDEOCNTL             0x14
174dafc3bd5SChristian Koenig #define R600_HDMI_VERSION               0x18
175dafc3bd5SChristian Koenig #define R600_HDMI_UNKNOWN_1             0x28
176dafc3bd5SChristian Koenig #define R600_HDMI_VIDEOINFOFRAME_0      0x54
177dafc3bd5SChristian Koenig #define R600_HDMI_VIDEOINFOFRAME_1      0x58
178dafc3bd5SChristian Koenig #define R600_HDMI_VIDEOINFOFRAME_2      0x5c
179dafc3bd5SChristian Koenig #define R600_HDMI_VIDEOINFOFRAME_3      0x60
180dafc3bd5SChristian Koenig #define R600_HDMI_32kHz_CTS             0xac
181dafc3bd5SChristian Koenig #define R600_HDMI_32kHz_N               0xb0
182dafc3bd5SChristian Koenig #define R600_HDMI_44_1kHz_CTS           0xb4
183dafc3bd5SChristian Koenig #define R600_HDMI_44_1kHz_N             0xb8
184dafc3bd5SChristian Koenig #define R600_HDMI_48kHz_CTS             0xbc
185dafc3bd5SChristian Koenig #define R600_HDMI_48kHz_N               0xc0
186dafc3bd5SChristian Koenig #define R600_HDMI_AUDIOINFOFRAME_0      0xcc
187dafc3bd5SChristian Koenig #define R600_HDMI_AUDIOINFOFRAME_1      0xd0
188dafc3bd5SChristian Koenig #define R600_HDMI_IEC60958_1            0xd4
189dafc3bd5SChristian Koenig #define R600_HDMI_IEC60958_2            0xd8
190dafc3bd5SChristian Koenig #define R600_HDMI_UNKNOWN_2             0xdc
191dafc3bd5SChristian Koenig #define R600_HDMI_AUDIO_DEBUG_0         0xe0
192dafc3bd5SChristian Koenig #define R600_HDMI_AUDIO_DEBUG_1         0xe4
193dafc3bd5SChristian Koenig #define R600_HDMI_AUDIO_DEBUG_2         0xe8
194dafc3bd5SChristian Koenig #define R600_HDMI_AUDIO_DEBUG_3         0xec
195771fe6b9SJerome Glisse 
196808032eeSRafał Miłecki /* HDMI additional config base register addresses */
197808032eeSRafał Miłecki #define R600_HDMI_CONFIG1                 0x7600
198808032eeSRafał Miłecki #define R600_HDMI_CONFIG2                 0x7a00
199808032eeSRafał Miłecki 
200771fe6b9SJerome Glisse #endif
201