xref: /openbmc/linux/drivers/gpu/drm/radeon/r600_reg.h (revision 771fe6b9)
1771fe6b9SJerome Glisse /*
2771fe6b9SJerome Glisse  * Copyright 2008 Advanced Micro Devices, Inc.
3771fe6b9SJerome Glisse  * Copyright 2008 Red Hat Inc.
4771fe6b9SJerome Glisse  * Copyright 2009 Jerome Glisse.
5771fe6b9SJerome Glisse  *
6771fe6b9SJerome Glisse  * Permission is hereby granted, free of charge, to any person obtaining a
7771fe6b9SJerome Glisse  * copy of this software and associated documentation files (the "Software"),
8771fe6b9SJerome Glisse  * to deal in the Software without restriction, including without limitation
9771fe6b9SJerome Glisse  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10771fe6b9SJerome Glisse  * and/or sell copies of the Software, and to permit persons to whom the
11771fe6b9SJerome Glisse  * Software is furnished to do so, subject to the following conditions:
12771fe6b9SJerome Glisse  *
13771fe6b9SJerome Glisse  * The above copyright notice and this permission notice shall be included in
14771fe6b9SJerome Glisse  * all copies or substantial portions of the Software.
15771fe6b9SJerome Glisse  *
16771fe6b9SJerome Glisse  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17771fe6b9SJerome Glisse  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18771fe6b9SJerome Glisse  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19771fe6b9SJerome Glisse  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20771fe6b9SJerome Glisse  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21771fe6b9SJerome Glisse  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22771fe6b9SJerome Glisse  * OTHER DEALINGS IN THE SOFTWARE.
23771fe6b9SJerome Glisse  *
24771fe6b9SJerome Glisse  * Authors: Dave Airlie
25771fe6b9SJerome Glisse  *          Alex Deucher
26771fe6b9SJerome Glisse  *          Jerome Glisse
27771fe6b9SJerome Glisse  */
28771fe6b9SJerome Glisse #ifndef __R600_REG_H__
29771fe6b9SJerome Glisse #define __R600_REG_H__
30771fe6b9SJerome Glisse 
31771fe6b9SJerome Glisse #define R600_PCIE_PORT_INDEX                0x0038
32771fe6b9SJerome Glisse #define R600_PCIE_PORT_DATA                 0x003c
33771fe6b9SJerome Glisse 
34771fe6b9SJerome Glisse #define R600_MC_VM_FB_LOCATION			0x2180
35771fe6b9SJerome Glisse #define		R600_MC_FB_BASE_MASK			0x0000FFFF
36771fe6b9SJerome Glisse #define		R600_MC_FB_BASE_SHIFT			0
37771fe6b9SJerome Glisse #define		R600_MC_FB_TOP_MASK			0xFFFF0000
38771fe6b9SJerome Glisse #define		R600_MC_FB_TOP_SHIFT			16
39771fe6b9SJerome Glisse #define R600_MC_VM_AGP_TOP			0x2184
40771fe6b9SJerome Glisse #define		R600_MC_AGP_TOP_MASK			0x0003FFFF
41771fe6b9SJerome Glisse #define		R600_MC_AGP_TOP_SHIFT			0
42771fe6b9SJerome Glisse #define R600_MC_VM_AGP_BOT			0x2188
43771fe6b9SJerome Glisse #define		R600_MC_AGP_BOT_MASK			0x0003FFFF
44771fe6b9SJerome Glisse #define		R600_MC_AGP_BOT_SHIFT			0
45771fe6b9SJerome Glisse #define R600_MC_VM_AGP_BASE			0x218c
46771fe6b9SJerome Glisse #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR	0x2190
47771fe6b9SJerome Glisse #define		R600_LOGICAL_PAGE_NUMBER_MASK		0x000FFFFF
48771fe6b9SJerome Glisse #define		R600_LOGICAL_PAGE_NUMBER_SHIFT		0
49771fe6b9SJerome Glisse #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR	0x2194
50771fe6b9SJerome Glisse #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR	0x2198
51771fe6b9SJerome Glisse 
52771fe6b9SJerome Glisse #define R700_MC_VM_FB_LOCATION			0x2024
53771fe6b9SJerome Glisse #define		R700_MC_FB_BASE_MASK			0x0000FFFF
54771fe6b9SJerome Glisse #define		R700_MC_FB_BASE_SHIFT			0
55771fe6b9SJerome Glisse #define		R700_MC_FB_TOP_MASK			0xFFFF0000
56771fe6b9SJerome Glisse #define		R700_MC_FB_TOP_SHIFT			16
57771fe6b9SJerome Glisse #define R700_MC_VM_AGP_TOP			0x2028
58771fe6b9SJerome Glisse #define		R700_MC_AGP_TOP_MASK			0x0003FFFF
59771fe6b9SJerome Glisse #define		R700_MC_AGP_TOP_SHIFT			0
60771fe6b9SJerome Glisse #define R700_MC_VM_AGP_BOT			0x202c
61771fe6b9SJerome Glisse #define		R700_MC_AGP_BOT_MASK			0x0003FFFF
62771fe6b9SJerome Glisse #define		R700_MC_AGP_BOT_SHIFT			0
63771fe6b9SJerome Glisse #define R700_MC_VM_AGP_BASE			0x2030
64771fe6b9SJerome Glisse #define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR	0x2034
65771fe6b9SJerome Glisse #define		R700_LOGICAL_PAGE_NUMBER_MASK		0x000FFFFF
66771fe6b9SJerome Glisse #define		R700_LOGICAL_PAGE_NUMBER_SHIFT		0
67771fe6b9SJerome Glisse #define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR	0x2038
68771fe6b9SJerome Glisse #define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR	0x203c
69771fe6b9SJerome Glisse 
70771fe6b9SJerome Glisse #define R600_RAMCFG				       0x2408
71771fe6b9SJerome Glisse #       define R600_CHANSIZE                           (1 << 7)
72771fe6b9SJerome Glisse #       define R600_CHANSIZE_OVERRIDE                  (1 << 10)
73771fe6b9SJerome Glisse 
74771fe6b9SJerome Glisse 
75771fe6b9SJerome Glisse #define R600_GENERAL_PWRMGT                                        0x618
76771fe6b9SJerome Glisse #	define R600_OPEN_DRAIN_PADS				   (1 << 11)
77771fe6b9SJerome Glisse 
78771fe6b9SJerome Glisse #define R600_LOWER_GPIO_ENABLE                                     0x710
79771fe6b9SJerome Glisse #define R600_CTXSW_VID_LOWER_GPIO_CNTL                             0x718
80771fe6b9SJerome Glisse #define R600_HIGH_VID_LOWER_GPIO_CNTL                              0x71c
81771fe6b9SJerome Glisse #define R600_MEDIUM_VID_LOWER_GPIO_CNTL                            0x720
82771fe6b9SJerome Glisse #define R600_LOW_VID_LOWER_GPIO_CNTL                               0x724
83771fe6b9SJerome Glisse 
84771fe6b9SJerome Glisse 
85771fe6b9SJerome Glisse 
86771fe6b9SJerome Glisse #define R600_HDP_NONSURFACE_BASE                                0x2c04
87771fe6b9SJerome Glisse 
88771fe6b9SJerome Glisse #define R600_BUS_CNTL                                           0x5420
89771fe6b9SJerome Glisse #define R600_CONFIG_CNTL                                        0x5424
90771fe6b9SJerome Glisse #define R600_CONFIG_MEMSIZE                                     0x5428
91771fe6b9SJerome Glisse #define R600_CONFIG_F0_BASE                                     0x542C
92771fe6b9SJerome Glisse #define R600_CONFIG_APER_SIZE                                   0x5430
93771fe6b9SJerome Glisse 
94771fe6b9SJerome Glisse #define R600_ROM_CNTL                              0x1600
95771fe6b9SJerome Glisse #       define R600_SCK_OVERWRITE                  (1 << 1)
96771fe6b9SJerome Glisse #       define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28
97771fe6b9SJerome Glisse #       define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK  (0xf << 28)
98771fe6b9SJerome Glisse 
99771fe6b9SJerome Glisse #define R600_CG_SPLL_FUNC_CNTL                     0x600
100771fe6b9SJerome Glisse #       define R600_SPLL_BYPASS_EN                 (1 << 3)
101771fe6b9SJerome Glisse #define R600_CG_SPLL_STATUS                        0x60c
102771fe6b9SJerome Glisse #       define R600_SPLL_CHG_STATUS                (1 << 1)
103771fe6b9SJerome Glisse 
104771fe6b9SJerome Glisse #define R600_BIOS_0_SCRATCH               0x1724
105771fe6b9SJerome Glisse #define R600_BIOS_1_SCRATCH               0x1728
106771fe6b9SJerome Glisse #define R600_BIOS_2_SCRATCH               0x172c
107771fe6b9SJerome Glisse #define R600_BIOS_3_SCRATCH               0x1730
108771fe6b9SJerome Glisse #define R600_BIOS_4_SCRATCH               0x1734
109771fe6b9SJerome Glisse #define R600_BIOS_5_SCRATCH               0x1738
110771fe6b9SJerome Glisse #define R600_BIOS_6_SCRATCH               0x173c
111771fe6b9SJerome Glisse #define R600_BIOS_7_SCRATCH               0x1740
112771fe6b9SJerome Glisse 
113771fe6b9SJerome Glisse 
114771fe6b9SJerome Glisse #endif
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