1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Christian König. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Christian König 25 */ 26 #include <linux/hdmi.h> 27 #include <drm/drmP.h> 28 #include <drm/radeon_drm.h> 29 #include "radeon.h" 30 #include "radeon_asic.h" 31 #include "r600d.h" 32 #include "atom.h" 33 34 /* 35 * HDMI color format 36 */ 37 enum r600_hdmi_color_format { 38 RGB = 0, 39 YCC_422 = 1, 40 YCC_444 = 2 41 }; 42 43 /* 44 * IEC60958 status bits 45 */ 46 enum r600_hdmi_iec_status_bits { 47 AUDIO_STATUS_DIG_ENABLE = 0x01, 48 AUDIO_STATUS_V = 0x02, 49 AUDIO_STATUS_VCFG = 0x04, 50 AUDIO_STATUS_EMPHASIS = 0x08, 51 AUDIO_STATUS_COPYRIGHT = 0x10, 52 AUDIO_STATUS_NONAUDIO = 0x20, 53 AUDIO_STATUS_PROFESSIONAL = 0x40, 54 AUDIO_STATUS_LEVEL = 0x80 55 }; 56 57 static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = { 58 /* 32kHz 44.1kHz 48kHz */ 59 /* Clock N CTS N CTS N CTS */ 60 { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */ 61 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ 62 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ 63 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ 64 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ 65 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ 66 { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */ 67 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ 68 { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */ 69 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ 70 { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */ 71 }; 72 73 /* 74 * calculate CTS value if it's not found in the table 75 */ 76 static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq) 77 { 78 if (*CTS == 0) 79 *CTS = clock * N / (128 * freq) * 1000; 80 DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n", 81 N, *CTS, freq); 82 } 83 84 struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock) 85 { 86 struct radeon_hdmi_acr res; 87 u8 i; 88 89 for (i = 0; r600_hdmi_predefined_acr[i].clock != clock && 90 r600_hdmi_predefined_acr[i].clock != 0; i++) 91 ; 92 res = r600_hdmi_predefined_acr[i]; 93 94 /* In case some CTS are missing */ 95 r600_hdmi_calc_cts(clock, &res.cts_32khz, res.n_32khz, 32000); 96 r600_hdmi_calc_cts(clock, &res.cts_44_1khz, res.n_44_1khz, 44100); 97 r600_hdmi_calc_cts(clock, &res.cts_48khz, res.n_48khz, 48000); 98 99 return res; 100 } 101 102 /* 103 * update the N and CTS parameters for a given pixel clock rate 104 */ 105 static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) 106 { 107 struct drm_device *dev = encoder->dev; 108 struct radeon_device *rdev = dev->dev_private; 109 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); 110 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 111 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 112 uint32_t offset = dig->afmt->offset; 113 114 WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz)); 115 WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz); 116 117 WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz)); 118 WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz); 119 120 WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz)); 121 WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz); 122 } 123 124 /* 125 * build a HDMI Video Info Frame 126 */ 127 static void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, 128 void *buffer, size_t size) 129 { 130 struct drm_device *dev = encoder->dev; 131 struct radeon_device *rdev = dev->dev_private; 132 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 133 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 134 uint32_t offset = dig->afmt->offset; 135 uint8_t *frame = buffer + 3; 136 137 /* Our header values (type, version, length) should be alright, Intel 138 * is using the same. Checksum function also seems to be OK, it works 139 * fine for audio infoframe. However calculated value is always lower 140 * by 2 in comparison to fglrx. It breaks displaying anything in case 141 * of TVs that strictly check the checksum. Hack it manually here to 142 * workaround this issue. */ 143 frame[0x0] += 2; 144 145 WREG32(HDMI0_AVI_INFO0 + offset, 146 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 147 WREG32(HDMI0_AVI_INFO1 + offset, 148 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 149 WREG32(HDMI0_AVI_INFO2 + offset, 150 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 151 WREG32(HDMI0_AVI_INFO3 + offset, 152 frame[0xC] | (frame[0xD] << 8)); 153 } 154 155 /* 156 * build a Audio Info Frame 157 */ 158 static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder, 159 const void *buffer, size_t size) 160 { 161 struct drm_device *dev = encoder->dev; 162 struct radeon_device *rdev = dev->dev_private; 163 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 164 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 165 uint32_t offset = dig->afmt->offset; 166 const u8 *frame = buffer + 3; 167 168 WREG32(HDMI0_AUDIO_INFO0 + offset, 169 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 170 WREG32(HDMI0_AUDIO_INFO1 + offset, 171 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24)); 172 } 173 174 /* 175 * test if audio buffer is filled enough to start playing 176 */ 177 static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder) 178 { 179 struct drm_device *dev = encoder->dev; 180 struct radeon_device *rdev = dev->dev_private; 181 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 182 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 183 uint32_t offset = dig->afmt->offset; 184 185 return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0; 186 } 187 188 /* 189 * have buffer status changed since last call? 190 */ 191 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder) 192 { 193 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 194 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 195 int status, result; 196 197 if (!dig->afmt || !dig->afmt->enabled) 198 return 0; 199 200 status = r600_hdmi_is_audio_buffer_filled(encoder); 201 result = dig->afmt->last_buffer_filled_status != status; 202 dig->afmt->last_buffer_filled_status = status; 203 204 return result; 205 } 206 207 /* 208 * write the audio workaround status to the hardware 209 */ 210 static void r600_hdmi_audio_workaround(struct drm_encoder *encoder) 211 { 212 struct drm_device *dev = encoder->dev; 213 struct radeon_device *rdev = dev->dev_private; 214 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 215 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 216 uint32_t offset = dig->afmt->offset; 217 bool hdmi_audio_workaround = false; /* FIXME */ 218 u32 value; 219 220 if (!hdmi_audio_workaround || 221 r600_hdmi_is_audio_buffer_filled(encoder)) 222 value = 0; /* disable workaround */ 223 else 224 value = HDMI0_AUDIO_TEST_EN; /* enable workaround */ 225 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, 226 value, ~HDMI0_AUDIO_TEST_EN); 227 } 228 229 void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock) 230 { 231 struct drm_device *dev = encoder->dev; 232 struct radeon_device *rdev = dev->dev_private; 233 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 234 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 235 u32 base_rate = 48000; 236 237 if (!dig || !dig->afmt) 238 return; 239 240 /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT. 241 * doesn't matter which one you use. Just use the first one. 242 */ 243 /* XXX: properly calculate this */ 244 /* XXX two dtos; generally use dto0 for hdmi */ 245 /* Express [24MHz / target pixel clock] as an exact rational 246 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 247 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 248 */ 249 if (ASIC_IS_DCE3(rdev)) { 250 /* according to the reg specs, this should DCE3.2 only, but in 251 * practice it seems to cover DCE3.0 as well. 252 */ 253 WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 50); 254 WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); 255 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ 256 } else { 257 /* according to the reg specs, this should be DCE2.0 and DCE3.0 */ 258 WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate * 50) | 259 AUDIO_DTO_MODULE(clock * 100)); 260 } 261 } 262 263 /* 264 * update the info frames with the data from the current display mode 265 */ 266 void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) 267 { 268 struct drm_device *dev = encoder->dev; 269 struct radeon_device *rdev = dev->dev_private; 270 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 271 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 272 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 273 struct hdmi_avi_infoframe frame; 274 uint32_t offset; 275 ssize_t err; 276 277 /* Silent, r600_hdmi_enable will raise WARN for us */ 278 if (!dig->afmt->enabled) 279 return; 280 offset = dig->afmt->offset; 281 282 r600_audio_set_dto(encoder, mode->clock); 283 284 WREG32(HDMI0_VBI_PACKET_CONTROL + offset, 285 HDMI0_NULL_SEND); /* send null packets when required */ 286 287 WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); 288 289 if (ASIC_IS_DCE32(rdev)) { 290 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, 291 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ 292 HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ 293 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, 294 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */ 295 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ 296 } else { 297 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, 298 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ 299 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ 300 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */ 301 HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ 302 } 303 304 WREG32(HDMI0_ACR_PACKET_CONTROL + offset, 305 HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ 306 HDMI0_ACR_SOURCE); /* select SW CTS value */ 307 308 WREG32(HDMI0_VBI_PACKET_CONTROL + offset, 309 HDMI0_NULL_SEND | /* send null packets when required */ 310 HDMI0_GC_SEND | /* send general control packets */ 311 HDMI0_GC_CONT); /* send general control packets every frame */ 312 313 /* TODO: HDMI0_AUDIO_INFO_UPDATE */ 314 WREG32(HDMI0_INFOFRAME_CONTROL0 + offset, 315 HDMI0_AVI_INFO_SEND | /* enable AVI info frames */ 316 HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */ 317 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ 318 HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */ 319 320 WREG32(HDMI0_INFOFRAME_CONTROL1 + offset, 321 HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */ 322 HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */ 323 324 WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */ 325 326 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 327 if (err < 0) { 328 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 329 return; 330 } 331 332 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 333 if (err < 0) { 334 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 335 return; 336 } 337 338 r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 339 r600_hdmi_update_ACR(encoder, mode->clock); 340 341 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ 342 WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF); 343 WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF); 344 WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001); 345 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); 346 347 r600_hdmi_audio_workaround(encoder); 348 } 349 350 /* 351 * update settings with current parameters from audio engine 352 */ 353 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder) 354 { 355 struct drm_device *dev = encoder->dev; 356 struct radeon_device *rdev = dev->dev_private; 357 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 358 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 359 struct r600_audio audio = r600_audio_status(rdev); 360 uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; 361 struct hdmi_audio_infoframe frame; 362 uint32_t offset; 363 uint32_t iec; 364 ssize_t err; 365 366 if (!dig->afmt || !dig->afmt->enabled) 367 return; 368 offset = dig->afmt->offset; 369 370 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n", 371 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped", 372 audio.channels, audio.rate, audio.bits_per_sample); 373 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n", 374 (int)audio.status_bits, (int)audio.category_code); 375 376 iec = 0; 377 if (audio.status_bits & AUDIO_STATUS_PROFESSIONAL) 378 iec |= 1 << 0; 379 if (audio.status_bits & AUDIO_STATUS_NONAUDIO) 380 iec |= 1 << 1; 381 if (audio.status_bits & AUDIO_STATUS_COPYRIGHT) 382 iec |= 1 << 2; 383 if (audio.status_bits & AUDIO_STATUS_EMPHASIS) 384 iec |= 1 << 3; 385 386 iec |= HDMI0_60958_CS_CATEGORY_CODE(audio.category_code); 387 388 switch (audio.rate) { 389 case 32000: 390 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3); 391 break; 392 case 44100: 393 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0); 394 break; 395 case 48000: 396 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2); 397 break; 398 case 88200: 399 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8); 400 break; 401 case 96000: 402 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa); 403 break; 404 case 176400: 405 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc); 406 break; 407 case 192000: 408 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe); 409 break; 410 } 411 412 WREG32(HDMI0_60958_0 + offset, iec); 413 414 iec = 0; 415 switch (audio.bits_per_sample) { 416 case 16: 417 iec |= HDMI0_60958_CS_WORD_LENGTH(0x2); 418 break; 419 case 20: 420 iec |= HDMI0_60958_CS_WORD_LENGTH(0x3); 421 break; 422 case 24: 423 iec |= HDMI0_60958_CS_WORD_LENGTH(0xb); 424 break; 425 } 426 if (audio.status_bits & AUDIO_STATUS_V) 427 iec |= 0x5 << 16; 428 WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f); 429 430 err = hdmi_audio_infoframe_init(&frame); 431 if (err < 0) { 432 DRM_ERROR("failed to setup audio infoframe\n"); 433 return; 434 } 435 436 frame.channels = audio.channels; 437 438 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 439 if (err < 0) { 440 DRM_ERROR("failed to pack audio infoframe\n"); 441 return; 442 } 443 444 r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer)); 445 r600_hdmi_audio_workaround(encoder); 446 } 447 448 /* 449 * enable the HDMI engine 450 */ 451 void r600_hdmi_enable(struct drm_encoder *encoder, bool enable) 452 { 453 struct drm_device *dev = encoder->dev; 454 struct radeon_device *rdev = dev->dev_private; 455 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 456 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 457 u32 hdmi = HDMI0_ERROR_ACK; 458 459 /* Silent, r600_hdmi_enable will raise WARN for us */ 460 if (enable && dig->afmt->enabled) 461 return; 462 if (!enable && !dig->afmt->enabled) 463 return; 464 465 /* Older chipsets require setting HDMI and routing manually */ 466 if (!ASIC_IS_DCE3(rdev)) { 467 if (enable) 468 hdmi |= HDMI0_ENABLE; 469 switch (radeon_encoder->encoder_id) { 470 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 471 if (enable) { 472 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN); 473 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA); 474 } else { 475 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN); 476 } 477 break; 478 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 479 if (enable) { 480 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN); 481 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA); 482 } else { 483 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN); 484 } 485 break; 486 case ENCODER_OBJECT_ID_INTERNAL_DDI: 487 if (enable) { 488 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN); 489 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA); 490 } else { 491 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN); 492 } 493 break; 494 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 495 if (enable) 496 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA); 497 break; 498 default: 499 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n", 500 radeon_encoder->encoder_id); 501 break; 502 } 503 WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi); 504 } 505 506 if (rdev->irq.installed) { 507 /* if irq is available use it */ 508 /* XXX: shouldn't need this on any asics. Double check DCE2/3 */ 509 if (enable) 510 radeon_irq_kms_enable_afmt(rdev, dig->afmt->id); 511 else 512 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id); 513 } 514 515 dig->afmt->enabled = enable; 516 517 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", 518 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); 519 } 520 521