1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Christian König. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Christian König 25 */ 26 #include <linux/hdmi.h> 27 #include <drm/drmP.h> 28 #include <drm/radeon_drm.h> 29 #include "radeon.h" 30 #include "radeon_asic.h" 31 #include "r600d.h" 32 #include "atom.h" 33 34 /* 35 * HDMI color format 36 */ 37 enum r600_hdmi_color_format { 38 RGB = 0, 39 YCC_422 = 1, 40 YCC_444 = 2 41 }; 42 43 /* 44 * IEC60958 status bits 45 */ 46 enum r600_hdmi_iec_status_bits { 47 AUDIO_STATUS_DIG_ENABLE = 0x01, 48 AUDIO_STATUS_V = 0x02, 49 AUDIO_STATUS_VCFG = 0x04, 50 AUDIO_STATUS_EMPHASIS = 0x08, 51 AUDIO_STATUS_COPYRIGHT = 0x10, 52 AUDIO_STATUS_NONAUDIO = 0x20, 53 AUDIO_STATUS_PROFESSIONAL = 0x40, 54 AUDIO_STATUS_LEVEL = 0x80 55 }; 56 57 static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = { 58 /* 32kHz 44.1kHz 48kHz */ 59 /* Clock N CTS N CTS N CTS */ 60 { 25175, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */ 61 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ 62 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ 63 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ 64 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ 65 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ 66 { 74176, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */ 67 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ 68 { 148352, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */ 69 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ 70 { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */ 71 }; 72 73 /* 74 * calculate CTS value if it's not found in the table 75 */ 76 static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq) 77 { 78 u64 n; 79 u32 d; 80 81 if (*CTS == 0) { 82 n = (u64)clock * (u64)N * 1000ULL; 83 d = 128 * freq; 84 do_div(n, d); 85 *CTS = n; 86 } 87 DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n", 88 N, *CTS, freq); 89 } 90 91 struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock) 92 { 93 struct radeon_hdmi_acr res; 94 u8 i; 95 96 for (i = 0; r600_hdmi_predefined_acr[i].clock != clock && 97 r600_hdmi_predefined_acr[i].clock != 0; i++) 98 ; 99 res = r600_hdmi_predefined_acr[i]; 100 101 /* In case some CTS are missing */ 102 r600_hdmi_calc_cts(clock, &res.cts_32khz, res.n_32khz, 32000); 103 r600_hdmi_calc_cts(clock, &res.cts_44_1khz, res.n_44_1khz, 44100); 104 r600_hdmi_calc_cts(clock, &res.cts_48khz, res.n_48khz, 48000); 105 106 return res; 107 } 108 109 /* 110 * update the N and CTS parameters for a given pixel clock rate 111 */ 112 static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) 113 { 114 struct drm_device *dev = encoder->dev; 115 struct radeon_device *rdev = dev->dev_private; 116 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); 117 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 118 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 119 uint32_t offset = dig->afmt->offset; 120 121 WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz)); 122 WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz); 123 124 WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz)); 125 WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz); 126 127 WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz)); 128 WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz); 129 } 130 131 /* 132 * build a HDMI Video Info Frame 133 */ 134 static void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, 135 void *buffer, size_t size) 136 { 137 struct drm_device *dev = encoder->dev; 138 struct radeon_device *rdev = dev->dev_private; 139 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 140 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 141 uint32_t offset = dig->afmt->offset; 142 uint8_t *frame = buffer + 3; 143 uint8_t *header = buffer; 144 145 WREG32(HDMI0_AVI_INFO0 + offset, 146 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 147 WREG32(HDMI0_AVI_INFO1 + offset, 148 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 149 WREG32(HDMI0_AVI_INFO2 + offset, 150 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 151 WREG32(HDMI0_AVI_INFO3 + offset, 152 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 153 } 154 155 /* 156 * build a Audio Info Frame 157 */ 158 static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder, 159 const void *buffer, size_t size) 160 { 161 struct drm_device *dev = encoder->dev; 162 struct radeon_device *rdev = dev->dev_private; 163 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 164 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 165 uint32_t offset = dig->afmt->offset; 166 const u8 *frame = buffer + 3; 167 168 WREG32(HDMI0_AUDIO_INFO0 + offset, 169 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 170 WREG32(HDMI0_AUDIO_INFO1 + offset, 171 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24)); 172 } 173 174 /* 175 * test if audio buffer is filled enough to start playing 176 */ 177 static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder) 178 { 179 struct drm_device *dev = encoder->dev; 180 struct radeon_device *rdev = dev->dev_private; 181 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 182 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 183 uint32_t offset = dig->afmt->offset; 184 185 return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0; 186 } 187 188 /* 189 * have buffer status changed since last call? 190 */ 191 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder) 192 { 193 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 194 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 195 int status, result; 196 197 if (!dig->afmt || !dig->afmt->enabled) 198 return 0; 199 200 status = r600_hdmi_is_audio_buffer_filled(encoder); 201 result = dig->afmt->last_buffer_filled_status != status; 202 dig->afmt->last_buffer_filled_status = status; 203 204 return result; 205 } 206 207 /* 208 * write the audio workaround status to the hardware 209 */ 210 static void r600_hdmi_audio_workaround(struct drm_encoder *encoder) 211 { 212 struct drm_device *dev = encoder->dev; 213 struct radeon_device *rdev = dev->dev_private; 214 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 215 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 216 uint32_t offset = dig->afmt->offset; 217 bool hdmi_audio_workaround = false; /* FIXME */ 218 u32 value; 219 220 if (!hdmi_audio_workaround || 221 r600_hdmi_is_audio_buffer_filled(encoder)) 222 value = 0; /* disable workaround */ 223 else 224 value = HDMI0_AUDIO_TEST_EN; /* enable workaround */ 225 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, 226 value, ~HDMI0_AUDIO_TEST_EN); 227 } 228 229 void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock) 230 { 231 struct drm_device *dev = encoder->dev; 232 struct radeon_device *rdev = dev->dev_private; 233 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 234 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 235 u32 base_rate = 24000; 236 u32 max_ratio = clock / base_rate; 237 u32 dto_phase; 238 u32 dto_modulo = clock; 239 u32 wallclock_ratio; 240 u32 dto_cntl; 241 242 if (!dig || !dig->afmt) 243 return; 244 245 if (max_ratio >= 8) { 246 dto_phase = 192 * 1000; 247 wallclock_ratio = 3; 248 } else if (max_ratio >= 4) { 249 dto_phase = 96 * 1000; 250 wallclock_ratio = 2; 251 } else if (max_ratio >= 2) { 252 dto_phase = 48 * 1000; 253 wallclock_ratio = 1; 254 } else { 255 dto_phase = 24 * 1000; 256 wallclock_ratio = 0; 257 } 258 259 /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT. 260 * doesn't matter which one you use. Just use the first one. 261 */ 262 /* XXX two dtos; generally use dto0 for hdmi */ 263 /* Express [24MHz / target pixel clock] as an exact rational 264 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 265 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 266 */ 267 if (ASIC_IS_DCE32(rdev)) { 268 if (dig->dig_encoder == 0) { 269 dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; 270 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); 271 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl); 272 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); 273 WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo); 274 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ 275 } else { 276 dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; 277 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); 278 WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl); 279 WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase); 280 WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo); 281 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ 282 } 283 } else if (ASIC_IS_DCE3(rdev)) { 284 /* according to the reg specs, this should DCE3.2 only, but in 285 * practice it seems to cover DCE3.0/3.1 as well. 286 */ 287 if (dig->dig_encoder == 0) { 288 WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100); 289 WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); 290 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ 291 } else { 292 WREG32(DCCG_AUDIO_DTO1_PHASE, base_rate * 100); 293 WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100); 294 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ 295 } 296 } else { 297 /* according to the reg specs, this should be DCE2.0 and DCE3.0/3.1 */ 298 WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) | 299 AUDIO_DTO_MODULE(clock / 10)); 300 } 301 } 302 303 static void dce3_2_afmt_write_speaker_allocation(struct drm_encoder *encoder) 304 { 305 struct radeon_device *rdev = encoder->dev->dev_private; 306 struct drm_connector *connector; 307 struct radeon_connector *radeon_connector = NULL; 308 u32 tmp; 309 u8 *sadb; 310 int sad_count; 311 312 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 313 if (connector->encoder == encoder) 314 radeon_connector = to_radeon_connector(connector); 315 } 316 317 if (!radeon_connector) { 318 DRM_ERROR("Couldn't find encoder's connector\n"); 319 return; 320 } 321 322 sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb); 323 if (sad_count < 0) { 324 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 325 return; 326 } 327 328 /* program the speaker allocation */ 329 tmp = RREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); 330 tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); 331 /* set HDMI mode */ 332 tmp |= HDMI_CONNECTION; 333 if (sad_count) 334 tmp |= SPEAKER_ALLOCATION(sadb[0]); 335 else 336 tmp |= SPEAKER_ALLOCATION(5); /* stereo */ 337 WREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); 338 339 kfree(sadb); 340 } 341 342 static void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder) 343 { 344 struct radeon_device *rdev = encoder->dev->dev_private; 345 struct drm_connector *connector; 346 struct radeon_connector *radeon_connector = NULL; 347 struct cea_sad *sads; 348 int i, sad_count; 349 350 static const u16 eld_reg_to_type[][2] = { 351 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 352 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 353 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 354 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 355 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 356 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 357 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 358 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 359 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 360 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 361 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 362 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 363 }; 364 365 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 366 if (connector->encoder == encoder) 367 radeon_connector = to_radeon_connector(connector); 368 } 369 370 if (!radeon_connector) { 371 DRM_ERROR("Couldn't find encoder's connector\n"); 372 return; 373 } 374 375 sad_count = drm_edid_to_sad(radeon_connector->edid, &sads); 376 if (sad_count < 0) { 377 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 378 return; 379 } 380 BUG_ON(!sads); 381 382 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 383 u32 value = 0; 384 int j; 385 386 for (j = 0; j < sad_count; j++) { 387 struct cea_sad *sad = &sads[j]; 388 389 if (sad->format == eld_reg_to_type[i][1]) { 390 value = MAX_CHANNELS(sad->channels) | 391 DESCRIPTOR_BYTE_2(sad->byte2) | 392 SUPPORTED_FREQUENCIES(sad->freq); 393 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 394 value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq); 395 break; 396 } 397 } 398 WREG32(eld_reg_to_type[i][0], value); 399 } 400 401 kfree(sads); 402 } 403 404 /* 405 * update the info frames with the data from the current display mode 406 */ 407 void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) 408 { 409 struct drm_device *dev = encoder->dev; 410 struct radeon_device *rdev = dev->dev_private; 411 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 412 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 413 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 414 struct hdmi_avi_infoframe frame; 415 uint32_t offset; 416 ssize_t err; 417 418 if (!dig || !dig->afmt) 419 return; 420 421 /* Silent, r600_hdmi_enable will raise WARN for us */ 422 if (!dig->afmt->enabled) 423 return; 424 offset = dig->afmt->offset; 425 426 r600_audio_set_dto(encoder, mode->clock); 427 428 WREG32(HDMI0_VBI_PACKET_CONTROL + offset, 429 HDMI0_NULL_SEND); /* send null packets when required */ 430 431 WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); 432 433 if (ASIC_IS_DCE32(rdev)) { 434 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, 435 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ 436 HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ 437 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, 438 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */ 439 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ 440 } else { 441 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, 442 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ 443 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ 444 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */ 445 HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ 446 } 447 448 if (ASIC_IS_DCE32(rdev)) { 449 dce3_2_afmt_write_speaker_allocation(encoder); 450 dce3_2_afmt_write_sad_regs(encoder); 451 } 452 453 WREG32(HDMI0_ACR_PACKET_CONTROL + offset, 454 HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */ 455 HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ 456 457 WREG32(HDMI0_VBI_PACKET_CONTROL + offset, 458 HDMI0_NULL_SEND | /* send null packets when required */ 459 HDMI0_GC_SEND | /* send general control packets */ 460 HDMI0_GC_CONT); /* send general control packets every frame */ 461 462 /* TODO: HDMI0_AUDIO_INFO_UPDATE */ 463 WREG32(HDMI0_INFOFRAME_CONTROL0 + offset, 464 HDMI0_AVI_INFO_SEND | /* enable AVI info frames */ 465 HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */ 466 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ 467 HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */ 468 469 WREG32(HDMI0_INFOFRAME_CONTROL1 + offset, 470 HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */ 471 HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */ 472 473 WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */ 474 475 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 476 if (err < 0) { 477 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 478 return; 479 } 480 481 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 482 if (err < 0) { 483 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 484 return; 485 } 486 487 r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 488 r600_hdmi_update_ACR(encoder, mode->clock); 489 490 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ 491 WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF); 492 WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF); 493 WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001); 494 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); 495 496 r600_hdmi_audio_workaround(encoder); 497 } 498 499 /* 500 * update settings with current parameters from audio engine 501 */ 502 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder) 503 { 504 struct drm_device *dev = encoder->dev; 505 struct radeon_device *rdev = dev->dev_private; 506 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 507 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 508 struct r600_audio_pin audio = r600_audio_status(rdev); 509 uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; 510 struct hdmi_audio_infoframe frame; 511 uint32_t offset; 512 uint32_t iec; 513 ssize_t err; 514 515 if (!dig->afmt || !dig->afmt->enabled) 516 return; 517 offset = dig->afmt->offset; 518 519 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n", 520 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped", 521 audio.channels, audio.rate, audio.bits_per_sample); 522 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n", 523 (int)audio.status_bits, (int)audio.category_code); 524 525 iec = 0; 526 if (audio.status_bits & AUDIO_STATUS_PROFESSIONAL) 527 iec |= 1 << 0; 528 if (audio.status_bits & AUDIO_STATUS_NONAUDIO) 529 iec |= 1 << 1; 530 if (audio.status_bits & AUDIO_STATUS_COPYRIGHT) 531 iec |= 1 << 2; 532 if (audio.status_bits & AUDIO_STATUS_EMPHASIS) 533 iec |= 1 << 3; 534 535 iec |= HDMI0_60958_CS_CATEGORY_CODE(audio.category_code); 536 537 switch (audio.rate) { 538 case 32000: 539 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3); 540 break; 541 case 44100: 542 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0); 543 break; 544 case 48000: 545 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2); 546 break; 547 case 88200: 548 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8); 549 break; 550 case 96000: 551 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa); 552 break; 553 case 176400: 554 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc); 555 break; 556 case 192000: 557 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe); 558 break; 559 } 560 561 WREG32(HDMI0_60958_0 + offset, iec); 562 563 iec = 0; 564 switch (audio.bits_per_sample) { 565 case 16: 566 iec |= HDMI0_60958_CS_WORD_LENGTH(0x2); 567 break; 568 case 20: 569 iec |= HDMI0_60958_CS_WORD_LENGTH(0x3); 570 break; 571 case 24: 572 iec |= HDMI0_60958_CS_WORD_LENGTH(0xb); 573 break; 574 } 575 if (audio.status_bits & AUDIO_STATUS_V) 576 iec |= 0x5 << 16; 577 WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f); 578 579 err = hdmi_audio_infoframe_init(&frame); 580 if (err < 0) { 581 DRM_ERROR("failed to setup audio infoframe\n"); 582 return; 583 } 584 585 frame.channels = audio.channels; 586 587 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 588 if (err < 0) { 589 DRM_ERROR("failed to pack audio infoframe\n"); 590 return; 591 } 592 593 r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer)); 594 r600_hdmi_audio_workaround(encoder); 595 } 596 597 /* 598 * enable the HDMI engine 599 */ 600 void r600_hdmi_enable(struct drm_encoder *encoder, bool enable) 601 { 602 struct drm_device *dev = encoder->dev; 603 struct radeon_device *rdev = dev->dev_private; 604 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 605 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 606 u32 hdmi = HDMI0_ERROR_ACK; 607 608 if (!dig || !dig->afmt) 609 return; 610 611 /* Silent, r600_hdmi_enable will raise WARN for us */ 612 if (enable && dig->afmt->enabled) 613 return; 614 if (!enable && !dig->afmt->enabled) 615 return; 616 617 if (enable) 618 dig->afmt->pin = r600_audio_get_pin(rdev); 619 else 620 dig->afmt->pin = NULL; 621 622 /* Older chipsets require setting HDMI and routing manually */ 623 if (!ASIC_IS_DCE3(rdev)) { 624 if (enable) 625 hdmi |= HDMI0_ENABLE; 626 switch (radeon_encoder->encoder_id) { 627 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 628 if (enable) { 629 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN); 630 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA); 631 } else { 632 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN); 633 } 634 break; 635 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 636 if (enable) { 637 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN); 638 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA); 639 } else { 640 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN); 641 } 642 break; 643 case ENCODER_OBJECT_ID_INTERNAL_DDI: 644 if (enable) { 645 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN); 646 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA); 647 } else { 648 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN); 649 } 650 break; 651 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 652 if (enable) 653 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA); 654 break; 655 default: 656 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n", 657 radeon_encoder->encoder_id); 658 break; 659 } 660 WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi); 661 } 662 663 if (rdev->irq.installed) { 664 /* if irq is available use it */ 665 /* XXX: shouldn't need this on any asics. Double check DCE2/3 */ 666 if (enable) 667 radeon_irq_kms_enable_afmt(rdev, dig->afmt->id); 668 else 669 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id); 670 } 671 672 dig->afmt->enabled = enable; 673 674 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", 675 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); 676 } 677 678