1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Christian König. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Christian König 25 */ 26 #include <linux/hdmi.h> 27 #include <drm/drmP.h> 28 #include <drm/radeon_drm.h> 29 #include "radeon.h" 30 #include "radeon_asic.h" 31 #include "r600d.h" 32 #include "atom.h" 33 34 /* 35 * HDMI color format 36 */ 37 enum r600_hdmi_color_format { 38 RGB = 0, 39 YCC_422 = 1, 40 YCC_444 = 2 41 }; 42 43 /* 44 * IEC60958 status bits 45 */ 46 enum r600_hdmi_iec_status_bits { 47 AUDIO_STATUS_DIG_ENABLE = 0x01, 48 AUDIO_STATUS_V = 0x02, 49 AUDIO_STATUS_VCFG = 0x04, 50 AUDIO_STATUS_EMPHASIS = 0x08, 51 AUDIO_STATUS_COPYRIGHT = 0x10, 52 AUDIO_STATUS_NONAUDIO = 0x20, 53 AUDIO_STATUS_PROFESSIONAL = 0x40, 54 AUDIO_STATUS_LEVEL = 0x80 55 }; 56 57 static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = { 58 /* 32kHz 44.1kHz 48kHz */ 59 /* Clock N CTS N CTS N CTS */ 60 { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */ 61 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ 62 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ 63 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ 64 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ 65 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ 66 { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */ 67 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ 68 { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */ 69 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ 70 { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */ 71 }; 72 73 /* 74 * calculate CTS value if it's not found in the table 75 */ 76 static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq) 77 { 78 if (*CTS == 0) 79 *CTS = clock * N / (128 * freq) * 1000; 80 DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n", 81 N, *CTS, freq); 82 } 83 84 struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock) 85 { 86 struct radeon_hdmi_acr res; 87 u8 i; 88 89 for (i = 0; r600_hdmi_predefined_acr[i].clock != clock && 90 r600_hdmi_predefined_acr[i].clock != 0; i++) 91 ; 92 res = r600_hdmi_predefined_acr[i]; 93 94 /* In case some CTS are missing */ 95 r600_hdmi_calc_cts(clock, &res.cts_32khz, res.n_32khz, 32000); 96 r600_hdmi_calc_cts(clock, &res.cts_44_1khz, res.n_44_1khz, 44100); 97 r600_hdmi_calc_cts(clock, &res.cts_48khz, res.n_48khz, 48000); 98 99 return res; 100 } 101 102 /* 103 * update the N and CTS parameters for a given pixel clock rate 104 */ 105 static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) 106 { 107 struct drm_device *dev = encoder->dev; 108 struct radeon_device *rdev = dev->dev_private; 109 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); 110 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 111 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 112 uint32_t offset = dig->afmt->offset; 113 114 WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz)); 115 WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz); 116 117 WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz)); 118 WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz); 119 120 WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz)); 121 WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz); 122 } 123 124 /* 125 * build a HDMI Video Info Frame 126 */ 127 static void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, 128 void *buffer, size_t size) 129 { 130 struct drm_device *dev = encoder->dev; 131 struct radeon_device *rdev = dev->dev_private; 132 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 133 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 134 uint32_t offset = dig->afmt->offset; 135 uint8_t *frame = buffer + 3; 136 137 /* Our header values (type, version, length) should be alright, Intel 138 * is using the same. Checksum function also seems to be OK, it works 139 * fine for audio infoframe. However calculated value is always lower 140 * by 2 in comparison to fglrx. It breaks displaying anything in case 141 * of TVs that strictly check the checksum. Hack it manually here to 142 * workaround this issue. */ 143 frame[0x0] += 2; 144 145 WREG32(HDMI0_AVI_INFO0 + offset, 146 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 147 WREG32(HDMI0_AVI_INFO1 + offset, 148 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 149 WREG32(HDMI0_AVI_INFO2 + offset, 150 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 151 WREG32(HDMI0_AVI_INFO3 + offset, 152 frame[0xC] | (frame[0xD] << 8)); 153 } 154 155 /* 156 * build a Audio Info Frame 157 */ 158 static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder, 159 const void *buffer, size_t size) 160 { 161 struct drm_device *dev = encoder->dev; 162 struct radeon_device *rdev = dev->dev_private; 163 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 164 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 165 uint32_t offset = dig->afmt->offset; 166 const u8 *frame = buffer + 3; 167 168 WREG32(HDMI0_AUDIO_INFO0 + offset, 169 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 170 WREG32(HDMI0_AUDIO_INFO1 + offset, 171 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24)); 172 } 173 174 /* 175 * test if audio buffer is filled enough to start playing 176 */ 177 static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder) 178 { 179 struct drm_device *dev = encoder->dev; 180 struct radeon_device *rdev = dev->dev_private; 181 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 182 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 183 uint32_t offset = dig->afmt->offset; 184 185 return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0; 186 } 187 188 /* 189 * have buffer status changed since last call? 190 */ 191 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder) 192 { 193 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 194 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 195 int status, result; 196 197 if (!dig->afmt || !dig->afmt->enabled) 198 return 0; 199 200 status = r600_hdmi_is_audio_buffer_filled(encoder); 201 result = dig->afmt->last_buffer_filled_status != status; 202 dig->afmt->last_buffer_filled_status = status; 203 204 return result; 205 } 206 207 /* 208 * write the audio workaround status to the hardware 209 */ 210 static void r600_hdmi_audio_workaround(struct drm_encoder *encoder) 211 { 212 struct drm_device *dev = encoder->dev; 213 struct radeon_device *rdev = dev->dev_private; 214 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 215 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 216 uint32_t offset = dig->afmt->offset; 217 bool hdmi_audio_workaround = false; /* FIXME */ 218 u32 value; 219 220 if (!hdmi_audio_workaround || 221 r600_hdmi_is_audio_buffer_filled(encoder)) 222 value = 0; /* disable workaround */ 223 else 224 value = HDMI0_AUDIO_TEST_EN; /* enable workaround */ 225 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, 226 value, ~HDMI0_AUDIO_TEST_EN); 227 } 228 229 230 /* 231 * update the info frames with the data from the current display mode 232 */ 233 void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) 234 { 235 struct drm_device *dev = encoder->dev; 236 struct radeon_device *rdev = dev->dev_private; 237 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 238 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 239 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 240 struct hdmi_avi_infoframe frame; 241 uint32_t offset; 242 ssize_t err; 243 244 /* Silent, r600_hdmi_enable will raise WARN for us */ 245 if (!dig->afmt->enabled) 246 return; 247 offset = dig->afmt->offset; 248 249 r600_audio_set_clock(encoder, mode->clock); 250 251 WREG32(HDMI0_VBI_PACKET_CONTROL + offset, 252 HDMI0_NULL_SEND); /* send null packets when required */ 253 254 WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); 255 256 if (ASIC_IS_DCE32(rdev)) { 257 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, 258 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ 259 HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ 260 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, 261 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */ 262 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ 263 } else { 264 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, 265 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ 266 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ 267 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */ 268 HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ 269 } 270 271 WREG32(HDMI0_ACR_PACKET_CONTROL + offset, 272 HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ 273 HDMI0_ACR_SOURCE); /* select SW CTS value */ 274 275 WREG32(HDMI0_VBI_PACKET_CONTROL + offset, 276 HDMI0_NULL_SEND | /* send null packets when required */ 277 HDMI0_GC_SEND | /* send general control packets */ 278 HDMI0_GC_CONT); /* send general control packets every frame */ 279 280 /* TODO: HDMI0_AUDIO_INFO_UPDATE */ 281 WREG32(HDMI0_INFOFRAME_CONTROL0 + offset, 282 HDMI0_AVI_INFO_SEND | /* enable AVI info frames */ 283 HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */ 284 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ 285 HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */ 286 287 WREG32(HDMI0_INFOFRAME_CONTROL1 + offset, 288 HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */ 289 HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */ 290 291 WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */ 292 293 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 294 if (err < 0) { 295 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 296 return; 297 } 298 299 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 300 if (err < 0) { 301 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 302 return; 303 } 304 305 r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 306 r600_hdmi_update_ACR(encoder, mode->clock); 307 308 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ 309 WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF); 310 WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF); 311 WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001); 312 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); 313 314 r600_hdmi_audio_workaround(encoder); 315 } 316 317 /* 318 * update settings with current parameters from audio engine 319 */ 320 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder) 321 { 322 struct drm_device *dev = encoder->dev; 323 struct radeon_device *rdev = dev->dev_private; 324 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 325 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 326 struct r600_audio audio = r600_audio_status(rdev); 327 uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; 328 struct hdmi_audio_infoframe frame; 329 uint32_t offset; 330 uint32_t iec; 331 ssize_t err; 332 333 if (!dig->afmt || !dig->afmt->enabled) 334 return; 335 offset = dig->afmt->offset; 336 337 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n", 338 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped", 339 audio.channels, audio.rate, audio.bits_per_sample); 340 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n", 341 (int)audio.status_bits, (int)audio.category_code); 342 343 iec = 0; 344 if (audio.status_bits & AUDIO_STATUS_PROFESSIONAL) 345 iec |= 1 << 0; 346 if (audio.status_bits & AUDIO_STATUS_NONAUDIO) 347 iec |= 1 << 1; 348 if (audio.status_bits & AUDIO_STATUS_COPYRIGHT) 349 iec |= 1 << 2; 350 if (audio.status_bits & AUDIO_STATUS_EMPHASIS) 351 iec |= 1 << 3; 352 353 iec |= HDMI0_60958_CS_CATEGORY_CODE(audio.category_code); 354 355 switch (audio.rate) { 356 case 32000: 357 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3); 358 break; 359 case 44100: 360 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0); 361 break; 362 case 48000: 363 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2); 364 break; 365 case 88200: 366 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8); 367 break; 368 case 96000: 369 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa); 370 break; 371 case 176400: 372 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc); 373 break; 374 case 192000: 375 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe); 376 break; 377 } 378 379 WREG32(HDMI0_60958_0 + offset, iec); 380 381 iec = 0; 382 switch (audio.bits_per_sample) { 383 case 16: 384 iec |= HDMI0_60958_CS_WORD_LENGTH(0x2); 385 break; 386 case 20: 387 iec |= HDMI0_60958_CS_WORD_LENGTH(0x3); 388 break; 389 case 24: 390 iec |= HDMI0_60958_CS_WORD_LENGTH(0xb); 391 break; 392 } 393 if (audio.status_bits & AUDIO_STATUS_V) 394 iec |= 0x5 << 16; 395 WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f); 396 397 err = hdmi_audio_infoframe_init(&frame); 398 if (err < 0) { 399 DRM_ERROR("failed to setup audio infoframe\n"); 400 return; 401 } 402 403 frame.channels = audio.channels; 404 405 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 406 if (err < 0) { 407 DRM_ERROR("failed to pack audio infoframe\n"); 408 return; 409 } 410 411 r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer)); 412 r600_hdmi_audio_workaround(encoder); 413 } 414 415 /* 416 * enable the HDMI engine 417 */ 418 void r600_hdmi_enable(struct drm_encoder *encoder) 419 { 420 struct drm_device *dev = encoder->dev; 421 struct radeon_device *rdev = dev->dev_private; 422 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 423 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 424 uint32_t offset; 425 u32 hdmi; 426 427 if (ASIC_IS_DCE6(rdev)) 428 return; 429 430 /* Silent, r600_hdmi_enable will raise WARN for us */ 431 if (dig->afmt->enabled) 432 return; 433 offset = dig->afmt->offset; 434 435 /* Older chipsets require setting HDMI and routing manually */ 436 if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { 437 hdmi = HDMI0_ERROR_ACK | HDMI0_ENABLE; 438 switch (radeon_encoder->encoder_id) { 439 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 440 WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN, 441 ~AVIVO_TMDSA_CNTL_HDMI_EN); 442 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA); 443 break; 444 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 445 WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN, 446 ~AVIVO_LVTMA_CNTL_HDMI_EN); 447 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA); 448 break; 449 case ENCODER_OBJECT_ID_INTERNAL_DDI: 450 WREG32_P(DDIA_CNTL, DDIA_HDMI_EN, ~DDIA_HDMI_EN); 451 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA); 452 break; 453 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 454 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA); 455 break; 456 default: 457 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n", 458 radeon_encoder->encoder_id); 459 break; 460 } 461 WREG32(HDMI0_CONTROL + offset, hdmi); 462 } 463 464 if (rdev->irq.installed) { 465 /* if irq is available use it */ 466 radeon_irq_kms_enable_afmt(rdev, dig->afmt->id); 467 } 468 469 dig->afmt->enabled = true; 470 471 DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n", 472 offset, radeon_encoder->encoder_id); 473 } 474 475 /* 476 * disable the HDMI engine 477 */ 478 void r600_hdmi_disable(struct drm_encoder *encoder) 479 { 480 struct drm_device *dev = encoder->dev; 481 struct radeon_device *rdev = dev->dev_private; 482 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 483 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 484 uint32_t offset; 485 486 if (ASIC_IS_DCE6(rdev)) 487 return; 488 489 /* Called for ATOM_ENCODER_MODE_HDMI only */ 490 if (!dig || !dig->afmt) { 491 return; 492 } 493 if (!dig->afmt->enabled) 494 return; 495 offset = dig->afmt->offset; 496 497 DRM_DEBUG("Disabling HDMI interface @ 0x%04X for encoder 0x%x\n", 498 offset, radeon_encoder->encoder_id); 499 500 /* disable irq */ 501 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id); 502 503 /* Older chipsets not handled by AtomBIOS */ 504 if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { 505 switch (radeon_encoder->encoder_id) { 506 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 507 WREG32_P(AVIVO_TMDSA_CNTL, 0, 508 ~AVIVO_TMDSA_CNTL_HDMI_EN); 509 break; 510 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 511 WREG32_P(AVIVO_LVTMA_CNTL, 0, 512 ~AVIVO_LVTMA_CNTL_HDMI_EN); 513 break; 514 case ENCODER_OBJECT_ID_INTERNAL_DDI: 515 WREG32_P(DDIA_CNTL, 0, ~DDIA_HDMI_EN); 516 break; 517 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 518 break; 519 default: 520 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n", 521 radeon_encoder->encoder_id); 522 break; 523 } 524 WREG32(HDMI0_CONTROL + offset, HDMI0_ERROR_ACK); 525 } 526 527 dig->afmt->enabled = false; 528 } 529