1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/kernel.h> 29 30 #include "radeon.h" 31 #include "radeon_asic.h" 32 #include "r600.h" 33 #include "r600d.h" 34 #include "r600_reg_safe.h" 35 36 static int r600_nomm; 37 extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size); 38 39 40 struct r600_cs_track { 41 /* configuration we miror so that we use same code btw kms/ums */ 42 u32 group_size; 43 u32 nbanks; 44 u32 npipes; 45 /* value we track */ 46 u32 sq_config; 47 u32 log_nsamples; 48 u32 nsamples; 49 u32 cb_color_base_last[8]; 50 struct radeon_bo *cb_color_bo[8]; 51 u64 cb_color_bo_mc[8]; 52 u64 cb_color_bo_offset[8]; 53 struct radeon_bo *cb_color_frag_bo[8]; 54 u64 cb_color_frag_offset[8]; 55 struct radeon_bo *cb_color_tile_bo[8]; 56 u64 cb_color_tile_offset[8]; 57 u32 cb_color_mask[8]; 58 u32 cb_color_info[8]; 59 u32 cb_color_view[8]; 60 u32 cb_color_size_idx[8]; /* unused */ 61 u32 cb_target_mask; 62 u32 cb_shader_mask; /* unused */ 63 bool is_resolve; 64 u32 cb_color_size[8]; 65 u32 vgt_strmout_en; 66 u32 vgt_strmout_buffer_en; 67 struct radeon_bo *vgt_strmout_bo[4]; 68 u64 vgt_strmout_bo_mc[4]; /* unused */ 69 u32 vgt_strmout_bo_offset[4]; 70 u32 vgt_strmout_size[4]; 71 u32 db_depth_control; 72 u32 db_depth_info; 73 u32 db_depth_size_idx; 74 u32 db_depth_view; 75 u32 db_depth_size; 76 u32 db_offset; 77 struct radeon_bo *db_bo; 78 u64 db_bo_mc; 79 bool sx_misc_kill_all_prims; 80 bool cb_dirty; 81 bool db_dirty; 82 bool streamout_dirty; 83 struct radeon_bo *htile_bo; 84 u64 htile_offset; 85 u32 htile_surface; 86 }; 87 88 #define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 } 89 #define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc, CHIP_R600 } 90 #define FMT_24_BIT(fmt) [fmt] = { 1, 1, 4, 0, CHIP_R600 } 91 #define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc, CHIP_R600 } 92 #define FMT_48_BIT(fmt) [fmt] = { 1, 1, 8, 0, CHIP_R600 } 93 #define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 } 94 #define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0, CHIP_R600 } 95 #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 } 96 97 struct gpu_formats { 98 unsigned blockwidth; 99 unsigned blockheight; 100 unsigned blocksize; 101 unsigned valid_color; 102 enum radeon_family min_family; 103 }; 104 105 static const struct gpu_formats color_formats_table[] = { 106 /* 8 bit */ 107 FMT_8_BIT(V_038004_COLOR_8, 1), 108 FMT_8_BIT(V_038004_COLOR_4_4, 1), 109 FMT_8_BIT(V_038004_COLOR_3_3_2, 1), 110 FMT_8_BIT(V_038004_FMT_1, 0), 111 112 /* 16-bit */ 113 FMT_16_BIT(V_038004_COLOR_16, 1), 114 FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1), 115 FMT_16_BIT(V_038004_COLOR_8_8, 1), 116 FMT_16_BIT(V_038004_COLOR_5_6_5, 1), 117 FMT_16_BIT(V_038004_COLOR_6_5_5, 1), 118 FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1), 119 FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1), 120 FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1), 121 122 /* 24-bit */ 123 FMT_24_BIT(V_038004_FMT_8_8_8), 124 125 /* 32-bit */ 126 FMT_32_BIT(V_038004_COLOR_32, 1), 127 FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1), 128 FMT_32_BIT(V_038004_COLOR_16_16, 1), 129 FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1), 130 FMT_32_BIT(V_038004_COLOR_8_24, 1), 131 FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1), 132 FMT_32_BIT(V_038004_COLOR_24_8, 1), 133 FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1), 134 FMT_32_BIT(V_038004_COLOR_10_11_11, 1), 135 FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1), 136 FMT_32_BIT(V_038004_COLOR_11_11_10, 1), 137 FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1), 138 FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1), 139 FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1), 140 FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1), 141 FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0), 142 FMT_32_BIT(V_038004_FMT_32_AS_8, 0), 143 FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0), 144 145 /* 48-bit */ 146 FMT_48_BIT(V_038004_FMT_16_16_16), 147 FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT), 148 149 /* 64-bit */ 150 FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1), 151 FMT_64_BIT(V_038004_COLOR_32_32, 1), 152 FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1), 153 FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1), 154 FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1), 155 156 FMT_96_BIT(V_038004_FMT_32_32_32), 157 FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT), 158 159 /* 128-bit */ 160 FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1), 161 FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1), 162 163 [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 }, 164 [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 }, 165 166 /* block compressed formats */ 167 [V_038004_FMT_BC1] = { 4, 4, 8, 0 }, 168 [V_038004_FMT_BC2] = { 4, 4, 16, 0 }, 169 [V_038004_FMT_BC3] = { 4, 4, 16, 0 }, 170 [V_038004_FMT_BC4] = { 4, 4, 8, 0 }, 171 [V_038004_FMT_BC5] = { 4, 4, 16, 0}, 172 [V_038004_FMT_BC6] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */ 173 [V_038004_FMT_BC7] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */ 174 175 /* The other Evergreen formats */ 176 [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR}, 177 }; 178 179 bool r600_fmt_is_valid_color(u32 format) 180 { 181 if (format >= ARRAY_SIZE(color_formats_table)) 182 return false; 183 184 if (color_formats_table[format].valid_color) 185 return true; 186 187 return false; 188 } 189 190 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family) 191 { 192 if (format >= ARRAY_SIZE(color_formats_table)) 193 return false; 194 195 if (family < color_formats_table[format].min_family) 196 return false; 197 198 if (color_formats_table[format].blockwidth > 0) 199 return true; 200 201 return false; 202 } 203 204 int r600_fmt_get_blocksize(u32 format) 205 { 206 if (format >= ARRAY_SIZE(color_formats_table)) 207 return 0; 208 209 return color_formats_table[format].blocksize; 210 } 211 212 int r600_fmt_get_nblocksx(u32 format, u32 w) 213 { 214 unsigned bw; 215 216 if (format >= ARRAY_SIZE(color_formats_table)) 217 return 0; 218 219 bw = color_formats_table[format].blockwidth; 220 if (bw == 0) 221 return 0; 222 223 return DIV_ROUND_UP(w, bw); 224 } 225 226 int r600_fmt_get_nblocksy(u32 format, u32 h) 227 { 228 unsigned bh; 229 230 if (format >= ARRAY_SIZE(color_formats_table)) 231 return 0; 232 233 bh = color_formats_table[format].blockheight; 234 if (bh == 0) 235 return 0; 236 237 return DIV_ROUND_UP(h, bh); 238 } 239 240 struct array_mode_checker { 241 int array_mode; 242 u32 group_size; 243 u32 nbanks; 244 u32 npipes; 245 u32 nsamples; 246 u32 blocksize; 247 }; 248 249 /* returns alignment in pixels for pitch/height/depth and bytes for base */ 250 static int r600_get_array_mode_alignment(struct array_mode_checker *values, 251 u32 *pitch_align, 252 u32 *height_align, 253 u32 *depth_align, 254 u64 *base_align) 255 { 256 u32 tile_width = 8; 257 u32 tile_height = 8; 258 u32 macro_tile_width = values->nbanks; 259 u32 macro_tile_height = values->npipes; 260 u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples; 261 u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes; 262 263 switch (values->array_mode) { 264 case ARRAY_LINEAR_GENERAL: 265 /* technically tile_width/_height for pitch/height */ 266 *pitch_align = 1; /* tile_width */ 267 *height_align = 1; /* tile_height */ 268 *depth_align = 1; 269 *base_align = 1; 270 break; 271 case ARRAY_LINEAR_ALIGNED: 272 *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize)); 273 *height_align = 1; 274 *depth_align = 1; 275 *base_align = values->group_size; 276 break; 277 case ARRAY_1D_TILED_THIN1: 278 *pitch_align = max((u32)tile_width, 279 (u32)(values->group_size / 280 (tile_height * values->blocksize * values->nsamples))); 281 *height_align = tile_height; 282 *depth_align = 1; 283 *base_align = values->group_size; 284 break; 285 case ARRAY_2D_TILED_THIN1: 286 *pitch_align = max((u32)macro_tile_width * tile_width, 287 (u32)((values->group_size * values->nbanks) / 288 (values->blocksize * values->nsamples * tile_width))); 289 *height_align = macro_tile_height * tile_height; 290 *depth_align = 1; 291 *base_align = max(macro_tile_bytes, 292 (*pitch_align) * values->blocksize * (*height_align) * values->nsamples); 293 break; 294 default: 295 return -EINVAL; 296 } 297 298 return 0; 299 } 300 301 static void r600_cs_track_init(struct r600_cs_track *track) 302 { 303 int i; 304 305 /* assume DX9 mode */ 306 track->sq_config = DX9_CONSTS; 307 for (i = 0; i < 8; i++) { 308 track->cb_color_base_last[i] = 0; 309 track->cb_color_size[i] = 0; 310 track->cb_color_size_idx[i] = 0; 311 track->cb_color_info[i] = 0; 312 track->cb_color_view[i] = 0xFFFFFFFF; 313 track->cb_color_bo[i] = NULL; 314 track->cb_color_bo_offset[i] = 0xFFFFFFFF; 315 track->cb_color_bo_mc[i] = 0xFFFFFFFF; 316 track->cb_color_frag_bo[i] = NULL; 317 track->cb_color_frag_offset[i] = 0xFFFFFFFF; 318 track->cb_color_tile_bo[i] = NULL; 319 track->cb_color_tile_offset[i] = 0xFFFFFFFF; 320 track->cb_color_mask[i] = 0xFFFFFFFF; 321 } 322 track->is_resolve = false; 323 track->nsamples = 16; 324 track->log_nsamples = 4; 325 track->cb_target_mask = 0xFFFFFFFF; 326 track->cb_shader_mask = 0xFFFFFFFF; 327 track->cb_dirty = true; 328 track->db_bo = NULL; 329 track->db_bo_mc = 0xFFFFFFFF; 330 /* assume the biggest format and that htile is enabled */ 331 track->db_depth_info = 7 | (1 << 25); 332 track->db_depth_view = 0xFFFFC000; 333 track->db_depth_size = 0xFFFFFFFF; 334 track->db_depth_size_idx = 0; 335 track->db_depth_control = 0xFFFFFFFF; 336 track->db_dirty = true; 337 track->htile_bo = NULL; 338 track->htile_offset = 0xFFFFFFFF; 339 track->htile_surface = 0; 340 341 for (i = 0; i < 4; i++) { 342 track->vgt_strmout_size[i] = 0; 343 track->vgt_strmout_bo[i] = NULL; 344 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF; 345 track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF; 346 } 347 track->streamout_dirty = true; 348 track->sx_misc_kill_all_prims = false; 349 } 350 351 static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) 352 { 353 struct r600_cs_track *track = p->track; 354 u32 slice_tile_max, tmp; 355 u32 height, height_align, pitch, pitch_align, depth_align; 356 u64 base_offset, base_align; 357 struct array_mode_checker array_check; 358 volatile u32 *ib = p->ib.ptr; 359 unsigned array_mode; 360 u32 format; 361 /* When resolve is used, the second colorbuffer has always 1 sample. */ 362 unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples; 363 364 format = G_0280A0_FORMAT(track->cb_color_info[i]); 365 if (!r600_fmt_is_valid_color(format)) { 366 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n", 367 __func__, __LINE__, format, 368 i, track->cb_color_info[i]); 369 return -EINVAL; 370 } 371 /* pitch in pixels */ 372 pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8; 373 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1; 374 slice_tile_max *= 64; 375 height = slice_tile_max / pitch; 376 if (height > 8192) 377 height = 8192; 378 array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]); 379 380 base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i]; 381 array_check.array_mode = array_mode; 382 array_check.group_size = track->group_size; 383 array_check.nbanks = track->nbanks; 384 array_check.npipes = track->npipes; 385 array_check.nsamples = nsamples; 386 array_check.blocksize = r600_fmt_get_blocksize(format); 387 if (r600_get_array_mode_alignment(&array_check, 388 &pitch_align, &height_align, &depth_align, &base_align)) { 389 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, 390 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i, 391 track->cb_color_info[i]); 392 return -EINVAL; 393 } 394 switch (array_mode) { 395 case V_0280A0_ARRAY_LINEAR_GENERAL: 396 break; 397 case V_0280A0_ARRAY_LINEAR_ALIGNED: 398 break; 399 case V_0280A0_ARRAY_1D_TILED_THIN1: 400 /* avoid breaking userspace */ 401 if (height > 7) 402 height &= ~0x7; 403 break; 404 case V_0280A0_ARRAY_2D_TILED_THIN1: 405 break; 406 default: 407 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, 408 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i, 409 track->cb_color_info[i]); 410 return -EINVAL; 411 } 412 413 if (!IS_ALIGNED(pitch, pitch_align)) { 414 dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n", 415 __func__, __LINE__, pitch, pitch_align, array_mode); 416 return -EINVAL; 417 } 418 if (!IS_ALIGNED(height, height_align)) { 419 dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n", 420 __func__, __LINE__, height, height_align, array_mode); 421 return -EINVAL; 422 } 423 if (!IS_ALIGNED(base_offset, base_align)) { 424 dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i, 425 base_offset, base_align, array_mode); 426 return -EINVAL; 427 } 428 429 /* check offset */ 430 tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) * 431 r600_fmt_get_blocksize(format) * nsamples; 432 switch (array_mode) { 433 default: 434 case V_0280A0_ARRAY_LINEAR_GENERAL: 435 case V_0280A0_ARRAY_LINEAR_ALIGNED: 436 tmp += track->cb_color_view[i] & 0xFF; 437 break; 438 case V_0280A0_ARRAY_1D_TILED_THIN1: 439 case V_0280A0_ARRAY_2D_TILED_THIN1: 440 tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp; 441 break; 442 } 443 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) { 444 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) { 445 /* the initial DDX does bad things with the CB size occasionally */ 446 /* it rounds up height too far for slice tile max but the BO is smaller */ 447 /* r600c,g also seem to flush at bad times in some apps resulting in 448 * bogus values here. So for linear just allow anything to avoid breaking 449 * broken userspace. 450 */ 451 } else { 452 dev_warn(p->dev, "%s offset[%d] %d %llu %d %lu too big (%d %d) (%d %d %d)\n", 453 __func__, i, array_mode, 454 track->cb_color_bo_offset[i], tmp, 455 radeon_bo_size(track->cb_color_bo[i]), 456 pitch, height, r600_fmt_get_nblocksx(format, pitch), 457 r600_fmt_get_nblocksy(format, height), 458 r600_fmt_get_blocksize(format)); 459 return -EINVAL; 460 } 461 } 462 /* limit max tile */ 463 tmp = (height * pitch) >> 6; 464 if (tmp < slice_tile_max) 465 slice_tile_max = tmp; 466 tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) | 467 S_028060_SLICE_TILE_MAX(slice_tile_max - 1); 468 ib[track->cb_color_size_idx[i]] = tmp; 469 470 /* FMASK/CMASK */ 471 switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) { 472 case V_0280A0_TILE_DISABLE: 473 break; 474 case V_0280A0_FRAG_ENABLE: 475 if (track->nsamples > 1) { 476 uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]); 477 /* the tile size is 8x8, but the size is in units of bits. 478 * for bytes, do just * 8. */ 479 uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1); 480 481 if (bytes + track->cb_color_frag_offset[i] > 482 radeon_bo_size(track->cb_color_frag_bo[i])) { 483 dev_warn(p->dev, "%s FMASK_TILE_MAX too large " 484 "(tile_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n", 485 __func__, tile_max, bytes, 486 track->cb_color_frag_offset[i], 487 radeon_bo_size(track->cb_color_frag_bo[i])); 488 return -EINVAL; 489 } 490 } 491 fallthrough; 492 case V_0280A0_CLEAR_ENABLE: 493 { 494 uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]); 495 /* One block = 128x128 pixels, one 8x8 tile has 4 bits.. 496 * (128*128) / (8*8) / 2 = 128 bytes per block. */ 497 uint32_t bytes = (block_max + 1) * 128; 498 499 if (bytes + track->cb_color_tile_offset[i] > 500 radeon_bo_size(track->cb_color_tile_bo[i])) { 501 dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large " 502 "(block_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n", 503 __func__, block_max, bytes, 504 track->cb_color_tile_offset[i], 505 radeon_bo_size(track->cb_color_tile_bo[i])); 506 return -EINVAL; 507 } 508 break; 509 } 510 default: 511 dev_warn(p->dev, "%s invalid tile mode\n", __func__); 512 return -EINVAL; 513 } 514 return 0; 515 } 516 517 static int r600_cs_track_validate_db(struct radeon_cs_parser *p) 518 { 519 struct r600_cs_track *track = p->track; 520 u32 nviews, bpe, ntiles, slice_tile_max, tmp; 521 u32 height_align, pitch_align, depth_align; 522 u32 pitch = 8192; 523 u32 height = 8192; 524 u64 base_offset, base_align; 525 struct array_mode_checker array_check; 526 int array_mode; 527 volatile u32 *ib = p->ib.ptr; 528 529 530 if (track->db_bo == NULL) { 531 dev_warn(p->dev, "z/stencil with no depth buffer\n"); 532 return -EINVAL; 533 } 534 switch (G_028010_FORMAT(track->db_depth_info)) { 535 case V_028010_DEPTH_16: 536 bpe = 2; 537 break; 538 case V_028010_DEPTH_X8_24: 539 case V_028010_DEPTH_8_24: 540 case V_028010_DEPTH_X8_24_FLOAT: 541 case V_028010_DEPTH_8_24_FLOAT: 542 case V_028010_DEPTH_32_FLOAT: 543 bpe = 4; 544 break; 545 case V_028010_DEPTH_X24_8_32_FLOAT: 546 bpe = 8; 547 break; 548 default: 549 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info)); 550 return -EINVAL; 551 } 552 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) { 553 if (!track->db_depth_size_idx) { 554 dev_warn(p->dev, "z/stencil buffer size not set\n"); 555 return -EINVAL; 556 } 557 tmp = radeon_bo_size(track->db_bo) - track->db_offset; 558 tmp = (tmp / bpe) >> 6; 559 if (!tmp) { 560 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n", 561 track->db_depth_size, bpe, track->db_offset, 562 radeon_bo_size(track->db_bo)); 563 return -EINVAL; 564 } 565 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF); 566 } else { 567 /* pitch in pixels */ 568 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8; 569 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; 570 slice_tile_max *= 64; 571 height = slice_tile_max / pitch; 572 if (height > 8192) 573 height = 8192; 574 base_offset = track->db_bo_mc + track->db_offset; 575 array_mode = G_028010_ARRAY_MODE(track->db_depth_info); 576 array_check.array_mode = array_mode; 577 array_check.group_size = track->group_size; 578 array_check.nbanks = track->nbanks; 579 array_check.npipes = track->npipes; 580 array_check.nsamples = track->nsamples; 581 array_check.blocksize = bpe; 582 if (r600_get_array_mode_alignment(&array_check, 583 &pitch_align, &height_align, &depth_align, &base_align)) { 584 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, 585 G_028010_ARRAY_MODE(track->db_depth_info), 586 track->db_depth_info); 587 return -EINVAL; 588 } 589 switch (array_mode) { 590 case V_028010_ARRAY_1D_TILED_THIN1: 591 /* don't break userspace */ 592 height &= ~0x7; 593 break; 594 case V_028010_ARRAY_2D_TILED_THIN1: 595 break; 596 default: 597 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, 598 G_028010_ARRAY_MODE(track->db_depth_info), 599 track->db_depth_info); 600 return -EINVAL; 601 } 602 603 if (!IS_ALIGNED(pitch, pitch_align)) { 604 dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n", 605 __func__, __LINE__, pitch, pitch_align, array_mode); 606 return -EINVAL; 607 } 608 if (!IS_ALIGNED(height, height_align)) { 609 dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n", 610 __func__, __LINE__, height, height_align, array_mode); 611 return -EINVAL; 612 } 613 if (!IS_ALIGNED(base_offset, base_align)) { 614 dev_warn(p->dev, "%s offset 0x%llx, 0x%llx, %d not aligned\n", __func__, 615 base_offset, base_align, array_mode); 616 return -EINVAL; 617 } 618 619 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; 620 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1; 621 tmp = ntiles * bpe * 64 * nviews * track->nsamples; 622 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) { 623 dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n", 624 array_mode, 625 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset, 626 radeon_bo_size(track->db_bo)); 627 return -EINVAL; 628 } 629 } 630 631 /* hyperz */ 632 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) { 633 unsigned long size; 634 unsigned nbx, nby; 635 636 if (track->htile_bo == NULL) { 637 dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n", 638 __func__, __LINE__, track->db_depth_info); 639 return -EINVAL; 640 } 641 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) { 642 dev_warn(p->dev, "%s:%d htile can't be enabled with bogus db_depth_size 0x%08x\n", 643 __func__, __LINE__, track->db_depth_size); 644 return -EINVAL; 645 } 646 647 nbx = pitch; 648 nby = height; 649 if (G_028D24_LINEAR(track->htile_surface)) { 650 /* nbx must be 16 htiles aligned == 16 * 8 pixel aligned */ 651 nbx = round_up(nbx, 16 * 8); 652 /* nby is npipes htiles aligned == npipes * 8 pixel aligned */ 653 nby = round_up(nby, track->npipes * 8); 654 } else { 655 /* always assume 8x8 htile */ 656 /* align is htile align * 8, htile align vary according to 657 * number of pipe and tile width and nby 658 */ 659 switch (track->npipes) { 660 case 8: 661 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ 662 nbx = round_up(nbx, 64 * 8); 663 nby = round_up(nby, 64 * 8); 664 break; 665 case 4: 666 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ 667 nbx = round_up(nbx, 64 * 8); 668 nby = round_up(nby, 32 * 8); 669 break; 670 case 2: 671 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ 672 nbx = round_up(nbx, 32 * 8); 673 nby = round_up(nby, 32 * 8); 674 break; 675 case 1: 676 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ 677 nbx = round_up(nbx, 32 * 8); 678 nby = round_up(nby, 16 * 8); 679 break; 680 default: 681 dev_warn(p->dev, "%s:%d invalid num pipes %d\n", 682 __func__, __LINE__, track->npipes); 683 return -EINVAL; 684 } 685 } 686 /* compute number of htile */ 687 nbx = nbx >> 3; 688 nby = nby >> 3; 689 /* size must be aligned on npipes * 2K boundary */ 690 size = roundup(nbx * nby * 4, track->npipes * (2 << 10)); 691 size += track->htile_offset; 692 693 if (size > radeon_bo_size(track->htile_bo)) { 694 dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n", 695 __func__, __LINE__, radeon_bo_size(track->htile_bo), 696 size, nbx, nby); 697 return -EINVAL; 698 } 699 } 700 701 track->db_dirty = false; 702 return 0; 703 } 704 705 static int r600_cs_track_check(struct radeon_cs_parser *p) 706 { 707 struct r600_cs_track *track = p->track; 708 u32 tmp; 709 int r, i; 710 711 /* on legacy kernel we don't perform advanced check */ 712 if (p->rdev == NULL) 713 return 0; 714 715 /* check streamout */ 716 if (track->streamout_dirty && track->vgt_strmout_en) { 717 for (i = 0; i < 4; i++) { 718 if (track->vgt_strmout_buffer_en & (1 << i)) { 719 if (track->vgt_strmout_bo[i]) { 720 u64 offset = (u64)track->vgt_strmout_bo_offset[i] + 721 (u64)track->vgt_strmout_size[i]; 722 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) { 723 DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n", 724 i, offset, 725 radeon_bo_size(track->vgt_strmout_bo[i])); 726 return -EINVAL; 727 } 728 } else { 729 dev_warn(p->dev, "No buffer for streamout %d\n", i); 730 return -EINVAL; 731 } 732 } 733 } 734 track->streamout_dirty = false; 735 } 736 737 if (track->sx_misc_kill_all_prims) 738 return 0; 739 740 /* check that we have a cb for each enabled target, we don't check 741 * shader_mask because it seems mesa isn't always setting it :( 742 */ 743 if (track->cb_dirty) { 744 tmp = track->cb_target_mask; 745 746 /* We must check both colorbuffers for RESOLVE. */ 747 if (track->is_resolve) { 748 tmp |= 0xff; 749 } 750 751 for (i = 0; i < 8; i++) { 752 u32 format = G_0280A0_FORMAT(track->cb_color_info[i]); 753 754 if (format != V_0280A0_COLOR_INVALID && 755 (tmp >> (i * 4)) & 0xF) { 756 /* at least one component is enabled */ 757 if (track->cb_color_bo[i] == NULL) { 758 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", 759 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i); 760 return -EINVAL; 761 } 762 /* perform rewrite of CB_COLOR[0-7]_SIZE */ 763 r = r600_cs_track_validate_cb(p, i); 764 if (r) 765 return r; 766 } 767 } 768 track->cb_dirty = false; 769 } 770 771 /* Check depth buffer */ 772 if (track->db_dirty && 773 G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID && 774 (G_028800_STENCIL_ENABLE(track->db_depth_control) || 775 G_028800_Z_ENABLE(track->db_depth_control))) { 776 r = r600_cs_track_validate_db(p); 777 if (r) 778 return r; 779 } 780 781 return 0; 782 } 783 784 /** 785 * r600_cs_packet_parse_vline() - parse userspace VLINE packet 786 * @p: parser structure holding parsing context. 787 * 788 * This is an R600-specific function for parsing VLINE packets. 789 * Real work is done by r600_cs_common_vline_parse function. 790 * Here we just set up ASIC-specific register table and call 791 * the common implementation function. 792 */ 793 static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p) 794 { 795 static uint32_t vline_start_end[2] = {AVIVO_D1MODE_VLINE_START_END, 796 AVIVO_D2MODE_VLINE_START_END}; 797 static uint32_t vline_status[2] = {AVIVO_D1MODE_VLINE_STATUS, 798 AVIVO_D2MODE_VLINE_STATUS}; 799 800 return r600_cs_common_vline_parse(p, vline_start_end, vline_status); 801 } 802 803 /** 804 * r600_cs_common_vline_parse() - common vline parser 805 * @p: parser structure holding parsing context. 806 * @vline_start_end: table of vline_start_end registers 807 * @vline_status: table of vline_status registers 808 * 809 * Userspace sends a special sequence for VLINE waits. 810 * PACKET0 - VLINE_START_END + value 811 * PACKET3 - WAIT_REG_MEM poll vline status reg 812 * RELOC (P3) - crtc_id in reloc. 813 * 814 * This function parses this and relocates the VLINE START END 815 * and WAIT_REG_MEM packets to the correct crtc. 816 * It also detects a switched off crtc and nulls out the 817 * wait in that case. This function is common for all ASICs that 818 * are R600 and newer. The parsing algorithm is the same, and only 819 * differs in which registers are used. 820 * 821 * Caller is the ASIC-specific function which passes the parser 822 * context and ASIC-specific register table 823 */ 824 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 825 uint32_t *vline_start_end, 826 uint32_t *vline_status) 827 { 828 struct drm_crtc *crtc; 829 struct radeon_crtc *radeon_crtc; 830 struct radeon_cs_packet p3reloc, wait_reg_mem; 831 int crtc_id; 832 int r; 833 uint32_t header, h_idx, reg, wait_reg_mem_info; 834 volatile uint32_t *ib; 835 836 ib = p->ib.ptr; 837 838 /* parse the WAIT_REG_MEM */ 839 r = radeon_cs_packet_parse(p, &wait_reg_mem, p->idx); 840 if (r) 841 return r; 842 843 /* check its a WAIT_REG_MEM */ 844 if (wait_reg_mem.type != RADEON_PACKET_TYPE3 || 845 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) { 846 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n"); 847 return -EINVAL; 848 } 849 850 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); 851 /* bit 4 is reg (0) or mem (1) */ 852 if (wait_reg_mem_info & 0x10) { 853 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM instead of REG\n"); 854 return -EINVAL; 855 } 856 /* bit 8 is me (0) or pfp (1) */ 857 if (wait_reg_mem_info & 0x100) { 858 DRM_ERROR("vline WAIT_REG_MEM waiting on PFP instead of ME\n"); 859 return -EINVAL; 860 } 861 /* waiting for value to be equal */ 862 if ((wait_reg_mem_info & 0x7) != 0x3) { 863 DRM_ERROR("vline WAIT_REG_MEM function not equal\n"); 864 return -EINVAL; 865 } 866 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) { 867 DRM_ERROR("vline WAIT_REG_MEM bad reg\n"); 868 return -EINVAL; 869 } 870 871 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) { 872 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n"); 873 return -EINVAL; 874 } 875 876 /* jump over the NOP */ 877 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2); 878 if (r) 879 return r; 880 881 h_idx = p->idx - 2; 882 p->idx += wait_reg_mem.count + 2; 883 p->idx += p3reloc.count + 2; 884 885 header = radeon_get_ib_value(p, h_idx); 886 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1); 887 reg = R600_CP_PACKET0_GET_REG(header); 888 889 crtc = drm_crtc_find(p->rdev->ddev, p->filp, crtc_id); 890 if (!crtc) { 891 DRM_ERROR("cannot find crtc %d\n", crtc_id); 892 return -ENOENT; 893 } 894 radeon_crtc = to_radeon_crtc(crtc); 895 crtc_id = radeon_crtc->crtc_id; 896 897 if (!crtc->enabled) { 898 /* CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */ 899 ib[h_idx + 2] = PACKET2(0); 900 ib[h_idx + 3] = PACKET2(0); 901 ib[h_idx + 4] = PACKET2(0); 902 ib[h_idx + 5] = PACKET2(0); 903 ib[h_idx + 6] = PACKET2(0); 904 ib[h_idx + 7] = PACKET2(0); 905 ib[h_idx + 8] = PACKET2(0); 906 } else if (reg == vline_start_end[0]) { 907 header &= ~R600_CP_PACKET0_REG_MASK; 908 header |= vline_start_end[crtc_id] >> 2; 909 ib[h_idx] = header; 910 ib[h_idx + 4] = vline_status[crtc_id] >> 2; 911 } else { 912 DRM_ERROR("unknown crtc reloc\n"); 913 return -EINVAL; 914 } 915 return 0; 916 } 917 918 static int r600_packet0_check(struct radeon_cs_parser *p, 919 struct radeon_cs_packet *pkt, 920 unsigned idx, unsigned reg) 921 { 922 int r; 923 924 switch (reg) { 925 case AVIVO_D1MODE_VLINE_START_END: 926 r = r600_cs_packet_parse_vline(p); 927 if (r) { 928 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 929 idx, reg); 930 return r; 931 } 932 break; 933 default: 934 pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx); 935 return -EINVAL; 936 } 937 return 0; 938 } 939 940 static int r600_cs_parse_packet0(struct radeon_cs_parser *p, 941 struct radeon_cs_packet *pkt) 942 { 943 unsigned reg, i; 944 unsigned idx; 945 int r; 946 947 idx = pkt->idx + 1; 948 reg = pkt->reg; 949 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { 950 r = r600_packet0_check(p, pkt, idx, reg); 951 if (r) { 952 return r; 953 } 954 } 955 return 0; 956 } 957 958 /** 959 * r600_cs_check_reg() - check if register is authorized or not 960 * @p: parser structure holding parsing context 961 * @reg: register we are testing 962 * @idx: index into the cs buffer 963 * 964 * This function will test against r600_reg_safe_bm and return 0 965 * if register is safe. If register is not flag as safe this function 966 * will test it against a list of register needind special handling. 967 */ 968 static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) 969 { 970 struct r600_cs_track *track = (struct r600_cs_track *)p->track; 971 struct radeon_bo_list *reloc; 972 u32 m, i, tmp, *ib; 973 int r; 974 975 i = (reg >> 7); 976 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) { 977 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 978 return -EINVAL; 979 } 980 m = 1 << ((reg >> 2) & 31); 981 if (!(r600_reg_safe_bm[i] & m)) 982 return 0; 983 ib = p->ib.ptr; 984 switch (reg) { 985 /* force following reg to 0 in an attempt to disable out buffer 986 * which will need us to better understand how it works to perform 987 * security check on it (Jerome) 988 */ 989 case R_0288A8_SQ_ESGS_RING_ITEMSIZE: 990 case R_008C44_SQ_ESGS_RING_SIZE: 991 case R_0288B0_SQ_ESTMP_RING_ITEMSIZE: 992 case R_008C54_SQ_ESTMP_RING_SIZE: 993 case R_0288C0_SQ_FBUF_RING_ITEMSIZE: 994 case R_008C74_SQ_FBUF_RING_SIZE: 995 case R_0288B4_SQ_GSTMP_RING_ITEMSIZE: 996 case R_008C5C_SQ_GSTMP_RING_SIZE: 997 case R_0288AC_SQ_GSVS_RING_ITEMSIZE: 998 case R_008C4C_SQ_GSVS_RING_SIZE: 999 case R_0288BC_SQ_PSTMP_RING_ITEMSIZE: 1000 case R_008C6C_SQ_PSTMP_RING_SIZE: 1001 case R_0288C4_SQ_REDUC_RING_ITEMSIZE: 1002 case R_008C7C_SQ_REDUC_RING_SIZE: 1003 case R_0288B8_SQ_VSTMP_RING_ITEMSIZE: 1004 case R_008C64_SQ_VSTMP_RING_SIZE: 1005 case R_0288C8_SQ_GS_VERT_ITEMSIZE: 1006 /* get value to populate the IB don't remove */ 1007 /*tmp =radeon_get_ib_value(p, idx); 1008 ib[idx] = 0;*/ 1009 break; 1010 case SQ_ESGS_RING_BASE: 1011 case SQ_GSVS_RING_BASE: 1012 case SQ_ESTMP_RING_BASE: 1013 case SQ_GSTMP_RING_BASE: 1014 case SQ_PSTMP_RING_BASE: 1015 case SQ_VSTMP_RING_BASE: 1016 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1017 if (r) { 1018 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1019 "0x%04X\n", reg); 1020 return -EINVAL; 1021 } 1022 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1023 break; 1024 case SQ_CONFIG: 1025 track->sq_config = radeon_get_ib_value(p, idx); 1026 break; 1027 case R_028800_DB_DEPTH_CONTROL: 1028 track->db_depth_control = radeon_get_ib_value(p, idx); 1029 track->db_dirty = true; 1030 break; 1031 case R_028010_DB_DEPTH_INFO: 1032 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) && 1033 radeon_cs_packet_next_is_pkt3_nop(p)) { 1034 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1035 if (r) { 1036 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1037 "0x%04X\n", reg); 1038 return -EINVAL; 1039 } 1040 track->db_depth_info = radeon_get_ib_value(p, idx); 1041 ib[idx] &= C_028010_ARRAY_MODE; 1042 track->db_depth_info &= C_028010_ARRAY_MODE; 1043 if (reloc->tiling_flags & RADEON_TILING_MACRO) { 1044 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1); 1045 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1); 1046 } else { 1047 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1); 1048 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1); 1049 } 1050 } else { 1051 track->db_depth_info = radeon_get_ib_value(p, idx); 1052 } 1053 track->db_dirty = true; 1054 break; 1055 case R_028004_DB_DEPTH_VIEW: 1056 track->db_depth_view = radeon_get_ib_value(p, idx); 1057 track->db_dirty = true; 1058 break; 1059 case R_028000_DB_DEPTH_SIZE: 1060 track->db_depth_size = radeon_get_ib_value(p, idx); 1061 track->db_depth_size_idx = idx; 1062 track->db_dirty = true; 1063 break; 1064 case R_028AB0_VGT_STRMOUT_EN: 1065 track->vgt_strmout_en = radeon_get_ib_value(p, idx); 1066 track->streamout_dirty = true; 1067 break; 1068 case R_028B20_VGT_STRMOUT_BUFFER_EN: 1069 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx); 1070 track->streamout_dirty = true; 1071 break; 1072 case VGT_STRMOUT_BUFFER_BASE_0: 1073 case VGT_STRMOUT_BUFFER_BASE_1: 1074 case VGT_STRMOUT_BUFFER_BASE_2: 1075 case VGT_STRMOUT_BUFFER_BASE_3: 1076 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1077 if (r) { 1078 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1079 "0x%04X\n", reg); 1080 return -EINVAL; 1081 } 1082 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16; 1083 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; 1084 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1085 track->vgt_strmout_bo[tmp] = reloc->robj; 1086 track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset; 1087 track->streamout_dirty = true; 1088 break; 1089 case VGT_STRMOUT_BUFFER_SIZE_0: 1090 case VGT_STRMOUT_BUFFER_SIZE_1: 1091 case VGT_STRMOUT_BUFFER_SIZE_2: 1092 case VGT_STRMOUT_BUFFER_SIZE_3: 1093 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16; 1094 /* size in register is DWs, convert to bytes */ 1095 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; 1096 track->streamout_dirty = true; 1097 break; 1098 case CP_COHER_BASE: 1099 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1100 if (r) { 1101 dev_warn(p->dev, "missing reloc for CP_COHER_BASE " 1102 "0x%04X\n", reg); 1103 return -EINVAL; 1104 } 1105 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1106 break; 1107 case R_028238_CB_TARGET_MASK: 1108 track->cb_target_mask = radeon_get_ib_value(p, idx); 1109 track->cb_dirty = true; 1110 break; 1111 case R_02823C_CB_SHADER_MASK: 1112 track->cb_shader_mask = radeon_get_ib_value(p, idx); 1113 break; 1114 case R_028C04_PA_SC_AA_CONFIG: 1115 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx)); 1116 track->log_nsamples = tmp; 1117 track->nsamples = 1 << tmp; 1118 track->cb_dirty = true; 1119 break; 1120 case R_028808_CB_COLOR_CONTROL: 1121 tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx)); 1122 track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX; 1123 track->cb_dirty = true; 1124 break; 1125 case R_0280A0_CB_COLOR0_INFO: 1126 case R_0280A4_CB_COLOR1_INFO: 1127 case R_0280A8_CB_COLOR2_INFO: 1128 case R_0280AC_CB_COLOR3_INFO: 1129 case R_0280B0_CB_COLOR4_INFO: 1130 case R_0280B4_CB_COLOR5_INFO: 1131 case R_0280B8_CB_COLOR6_INFO: 1132 case R_0280BC_CB_COLOR7_INFO: 1133 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) && 1134 radeon_cs_packet_next_is_pkt3_nop(p)) { 1135 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1136 if (r) { 1137 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1138 return -EINVAL; 1139 } 1140 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4; 1141 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); 1142 if (reloc->tiling_flags & RADEON_TILING_MACRO) { 1143 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1); 1144 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1); 1145 } else if (reloc->tiling_flags & RADEON_TILING_MICRO) { 1146 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1); 1147 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1); 1148 } 1149 } else { 1150 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4; 1151 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); 1152 } 1153 track->cb_dirty = true; 1154 break; 1155 case R_028080_CB_COLOR0_VIEW: 1156 case R_028084_CB_COLOR1_VIEW: 1157 case R_028088_CB_COLOR2_VIEW: 1158 case R_02808C_CB_COLOR3_VIEW: 1159 case R_028090_CB_COLOR4_VIEW: 1160 case R_028094_CB_COLOR5_VIEW: 1161 case R_028098_CB_COLOR6_VIEW: 1162 case R_02809C_CB_COLOR7_VIEW: 1163 tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4; 1164 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); 1165 track->cb_dirty = true; 1166 break; 1167 case R_028060_CB_COLOR0_SIZE: 1168 case R_028064_CB_COLOR1_SIZE: 1169 case R_028068_CB_COLOR2_SIZE: 1170 case R_02806C_CB_COLOR3_SIZE: 1171 case R_028070_CB_COLOR4_SIZE: 1172 case R_028074_CB_COLOR5_SIZE: 1173 case R_028078_CB_COLOR6_SIZE: 1174 case R_02807C_CB_COLOR7_SIZE: 1175 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4; 1176 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx); 1177 track->cb_color_size_idx[tmp] = idx; 1178 track->cb_dirty = true; 1179 break; 1180 /* This register were added late, there is userspace 1181 * which does provide relocation for those but set 1182 * 0 offset. In order to avoid breaking old userspace 1183 * we detect this and set address to point to last 1184 * CB_COLOR0_BASE, note that if userspace doesn't set 1185 * CB_COLOR0_BASE before this register we will report 1186 * error. Old userspace always set CB_COLOR0_BASE 1187 * before any of this. 1188 */ 1189 case R_0280E0_CB_COLOR0_FRAG: 1190 case R_0280E4_CB_COLOR1_FRAG: 1191 case R_0280E8_CB_COLOR2_FRAG: 1192 case R_0280EC_CB_COLOR3_FRAG: 1193 case R_0280F0_CB_COLOR4_FRAG: 1194 case R_0280F4_CB_COLOR5_FRAG: 1195 case R_0280F8_CB_COLOR6_FRAG: 1196 case R_0280FC_CB_COLOR7_FRAG: 1197 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4; 1198 if (!radeon_cs_packet_next_is_pkt3_nop(p)) { 1199 if (!track->cb_color_base_last[tmp]) { 1200 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg); 1201 return -EINVAL; 1202 } 1203 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp]; 1204 track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp]; 1205 ib[idx] = track->cb_color_base_last[tmp]; 1206 } else { 1207 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1208 if (r) { 1209 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1210 return -EINVAL; 1211 } 1212 track->cb_color_frag_bo[tmp] = reloc->robj; 1213 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8; 1214 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1215 } 1216 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { 1217 track->cb_dirty = true; 1218 } 1219 break; 1220 case R_0280C0_CB_COLOR0_TILE: 1221 case R_0280C4_CB_COLOR1_TILE: 1222 case R_0280C8_CB_COLOR2_TILE: 1223 case R_0280CC_CB_COLOR3_TILE: 1224 case R_0280D0_CB_COLOR4_TILE: 1225 case R_0280D4_CB_COLOR5_TILE: 1226 case R_0280D8_CB_COLOR6_TILE: 1227 case R_0280DC_CB_COLOR7_TILE: 1228 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4; 1229 if (!radeon_cs_packet_next_is_pkt3_nop(p)) { 1230 if (!track->cb_color_base_last[tmp]) { 1231 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg); 1232 return -EINVAL; 1233 } 1234 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp]; 1235 track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp]; 1236 ib[idx] = track->cb_color_base_last[tmp]; 1237 } else { 1238 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1239 if (r) { 1240 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1241 return -EINVAL; 1242 } 1243 track->cb_color_tile_bo[tmp] = reloc->robj; 1244 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8; 1245 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1246 } 1247 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { 1248 track->cb_dirty = true; 1249 } 1250 break; 1251 case R_028100_CB_COLOR0_MASK: 1252 case R_028104_CB_COLOR1_MASK: 1253 case R_028108_CB_COLOR2_MASK: 1254 case R_02810C_CB_COLOR3_MASK: 1255 case R_028110_CB_COLOR4_MASK: 1256 case R_028114_CB_COLOR5_MASK: 1257 case R_028118_CB_COLOR6_MASK: 1258 case R_02811C_CB_COLOR7_MASK: 1259 tmp = (reg - R_028100_CB_COLOR0_MASK) / 4; 1260 track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx); 1261 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { 1262 track->cb_dirty = true; 1263 } 1264 break; 1265 case CB_COLOR0_BASE: 1266 case CB_COLOR1_BASE: 1267 case CB_COLOR2_BASE: 1268 case CB_COLOR3_BASE: 1269 case CB_COLOR4_BASE: 1270 case CB_COLOR5_BASE: 1271 case CB_COLOR6_BASE: 1272 case CB_COLOR7_BASE: 1273 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1274 if (r) { 1275 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1276 "0x%04X\n", reg); 1277 return -EINVAL; 1278 } 1279 tmp = (reg - CB_COLOR0_BASE) / 4; 1280 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; 1281 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1282 track->cb_color_base_last[tmp] = ib[idx]; 1283 track->cb_color_bo[tmp] = reloc->robj; 1284 track->cb_color_bo_mc[tmp] = reloc->gpu_offset; 1285 track->cb_dirty = true; 1286 break; 1287 case DB_DEPTH_BASE: 1288 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1289 if (r) { 1290 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1291 "0x%04X\n", reg); 1292 return -EINVAL; 1293 } 1294 track->db_offset = radeon_get_ib_value(p, idx) << 8; 1295 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1296 track->db_bo = reloc->robj; 1297 track->db_bo_mc = reloc->gpu_offset; 1298 track->db_dirty = true; 1299 break; 1300 case DB_HTILE_DATA_BASE: 1301 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1302 if (r) { 1303 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1304 "0x%04X\n", reg); 1305 return -EINVAL; 1306 } 1307 track->htile_offset = radeon_get_ib_value(p, idx) << 8; 1308 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1309 track->htile_bo = reloc->robj; 1310 track->db_dirty = true; 1311 break; 1312 case DB_HTILE_SURFACE: 1313 track->htile_surface = radeon_get_ib_value(p, idx); 1314 /* force 8x8 htile width and height */ 1315 ib[idx] |= 3; 1316 track->db_dirty = true; 1317 break; 1318 case SQ_PGM_START_FS: 1319 case SQ_PGM_START_ES: 1320 case SQ_PGM_START_VS: 1321 case SQ_PGM_START_GS: 1322 case SQ_PGM_START_PS: 1323 case SQ_ALU_CONST_CACHE_GS_0: 1324 case SQ_ALU_CONST_CACHE_GS_1: 1325 case SQ_ALU_CONST_CACHE_GS_2: 1326 case SQ_ALU_CONST_CACHE_GS_3: 1327 case SQ_ALU_CONST_CACHE_GS_4: 1328 case SQ_ALU_CONST_CACHE_GS_5: 1329 case SQ_ALU_CONST_CACHE_GS_6: 1330 case SQ_ALU_CONST_CACHE_GS_7: 1331 case SQ_ALU_CONST_CACHE_GS_8: 1332 case SQ_ALU_CONST_CACHE_GS_9: 1333 case SQ_ALU_CONST_CACHE_GS_10: 1334 case SQ_ALU_CONST_CACHE_GS_11: 1335 case SQ_ALU_CONST_CACHE_GS_12: 1336 case SQ_ALU_CONST_CACHE_GS_13: 1337 case SQ_ALU_CONST_CACHE_GS_14: 1338 case SQ_ALU_CONST_CACHE_GS_15: 1339 case SQ_ALU_CONST_CACHE_PS_0: 1340 case SQ_ALU_CONST_CACHE_PS_1: 1341 case SQ_ALU_CONST_CACHE_PS_2: 1342 case SQ_ALU_CONST_CACHE_PS_3: 1343 case SQ_ALU_CONST_CACHE_PS_4: 1344 case SQ_ALU_CONST_CACHE_PS_5: 1345 case SQ_ALU_CONST_CACHE_PS_6: 1346 case SQ_ALU_CONST_CACHE_PS_7: 1347 case SQ_ALU_CONST_CACHE_PS_8: 1348 case SQ_ALU_CONST_CACHE_PS_9: 1349 case SQ_ALU_CONST_CACHE_PS_10: 1350 case SQ_ALU_CONST_CACHE_PS_11: 1351 case SQ_ALU_CONST_CACHE_PS_12: 1352 case SQ_ALU_CONST_CACHE_PS_13: 1353 case SQ_ALU_CONST_CACHE_PS_14: 1354 case SQ_ALU_CONST_CACHE_PS_15: 1355 case SQ_ALU_CONST_CACHE_VS_0: 1356 case SQ_ALU_CONST_CACHE_VS_1: 1357 case SQ_ALU_CONST_CACHE_VS_2: 1358 case SQ_ALU_CONST_CACHE_VS_3: 1359 case SQ_ALU_CONST_CACHE_VS_4: 1360 case SQ_ALU_CONST_CACHE_VS_5: 1361 case SQ_ALU_CONST_CACHE_VS_6: 1362 case SQ_ALU_CONST_CACHE_VS_7: 1363 case SQ_ALU_CONST_CACHE_VS_8: 1364 case SQ_ALU_CONST_CACHE_VS_9: 1365 case SQ_ALU_CONST_CACHE_VS_10: 1366 case SQ_ALU_CONST_CACHE_VS_11: 1367 case SQ_ALU_CONST_CACHE_VS_12: 1368 case SQ_ALU_CONST_CACHE_VS_13: 1369 case SQ_ALU_CONST_CACHE_VS_14: 1370 case SQ_ALU_CONST_CACHE_VS_15: 1371 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1372 if (r) { 1373 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1374 "0x%04X\n", reg); 1375 return -EINVAL; 1376 } 1377 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1378 break; 1379 case SX_MEMORY_EXPORT_BASE: 1380 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1381 if (r) { 1382 dev_warn(p->dev, "bad SET_CONFIG_REG " 1383 "0x%04X\n", reg); 1384 return -EINVAL; 1385 } 1386 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1387 break; 1388 case SX_MISC: 1389 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; 1390 break; 1391 default: 1392 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 1393 return -EINVAL; 1394 } 1395 return 0; 1396 } 1397 1398 unsigned r600_mip_minify(unsigned size, unsigned level) 1399 { 1400 unsigned val; 1401 1402 val = max(1U, size >> level); 1403 if (level > 0) 1404 val = roundup_pow_of_two(val); 1405 return val; 1406 } 1407 1408 static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel, 1409 unsigned w0, unsigned h0, unsigned d0, unsigned nsamples, unsigned format, 1410 unsigned block_align, unsigned height_align, unsigned base_align, 1411 unsigned *l0_size, unsigned *mipmap_size) 1412 { 1413 unsigned offset, i, level; 1414 unsigned width, height, depth, size; 1415 unsigned blocksize; 1416 unsigned nbx, nby; 1417 unsigned nlevels = llevel - blevel + 1; 1418 1419 *l0_size = -1; 1420 blocksize = r600_fmt_get_blocksize(format); 1421 1422 w0 = r600_mip_minify(w0, 0); 1423 h0 = r600_mip_minify(h0, 0); 1424 d0 = r600_mip_minify(d0, 0); 1425 for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) { 1426 width = r600_mip_minify(w0, i); 1427 nbx = r600_fmt_get_nblocksx(format, width); 1428 1429 nbx = round_up(nbx, block_align); 1430 1431 height = r600_mip_minify(h0, i); 1432 nby = r600_fmt_get_nblocksy(format, height); 1433 nby = round_up(nby, height_align); 1434 1435 depth = r600_mip_minify(d0, i); 1436 1437 size = nbx * nby * blocksize * nsamples; 1438 if (nfaces) 1439 size *= nfaces; 1440 else 1441 size *= depth; 1442 1443 if (i == 0) 1444 *l0_size = size; 1445 1446 if (i == 0 || i == 1) 1447 offset = round_up(offset, base_align); 1448 1449 offset += size; 1450 } 1451 *mipmap_size = offset; 1452 if (llevel == 0) 1453 *mipmap_size = *l0_size; 1454 if (!blevel) 1455 *mipmap_size -= *l0_size; 1456 } 1457 1458 /** 1459 * r600_check_texture_resource() - check if register is authorized or not 1460 * @p: parser structure holding parsing context 1461 * @idx: index into the cs buffer 1462 * @texture: texture's bo structure 1463 * @mipmap: mipmap's bo structure 1464 * @base_offset: base offset (used for error checking) 1465 * @mip_offset: mip offset (used for error checking) 1466 * @tiling_flags: tiling flags 1467 * 1468 * This function will check that the resource has valid field and that 1469 * the texture and mipmap bo object are big enough to cover this resource. 1470 */ 1471 static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, 1472 struct radeon_bo *texture, 1473 struct radeon_bo *mipmap, 1474 u64 base_offset, 1475 u64 mip_offset, 1476 u32 tiling_flags) 1477 { 1478 struct r600_cs_track *track = p->track; 1479 u32 dim, nfaces, llevel, blevel, w0, h0, d0; 1480 u32 word0, word1, l0_size, mipmap_size, word2, word3, word4, word5; 1481 u32 height_align, pitch, pitch_align, depth_align; 1482 u32 barray, larray; 1483 u64 base_align; 1484 struct array_mode_checker array_check; 1485 u32 format; 1486 bool is_array; 1487 1488 /* on legacy kernel we don't perform advanced check */ 1489 if (p->rdev == NULL) 1490 return 0; 1491 1492 /* convert to bytes */ 1493 base_offset <<= 8; 1494 mip_offset <<= 8; 1495 1496 word0 = radeon_get_ib_value(p, idx + 0); 1497 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1498 if (tiling_flags & RADEON_TILING_MACRO) 1499 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1); 1500 else if (tiling_flags & RADEON_TILING_MICRO) 1501 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1); 1502 } 1503 word1 = radeon_get_ib_value(p, idx + 1); 1504 word2 = radeon_get_ib_value(p, idx + 2) << 8; 1505 word3 = radeon_get_ib_value(p, idx + 3) << 8; 1506 word4 = radeon_get_ib_value(p, idx + 4); 1507 word5 = radeon_get_ib_value(p, idx + 5); 1508 dim = G_038000_DIM(word0); 1509 w0 = G_038000_TEX_WIDTH(word0) + 1; 1510 pitch = (G_038000_PITCH(word0) + 1) * 8; 1511 h0 = G_038004_TEX_HEIGHT(word1) + 1; 1512 d0 = G_038004_TEX_DEPTH(word1); 1513 format = G_038004_DATA_FORMAT(word1); 1514 blevel = G_038010_BASE_LEVEL(word4); 1515 llevel = G_038014_LAST_LEVEL(word5); 1516 /* pitch in texels */ 1517 array_check.array_mode = G_038000_TILE_MODE(word0); 1518 array_check.group_size = track->group_size; 1519 array_check.nbanks = track->nbanks; 1520 array_check.npipes = track->npipes; 1521 array_check.nsamples = 1; 1522 array_check.blocksize = r600_fmt_get_blocksize(format); 1523 nfaces = 1; 1524 is_array = false; 1525 switch (dim) { 1526 case V_038000_SQ_TEX_DIM_1D: 1527 case V_038000_SQ_TEX_DIM_2D: 1528 case V_038000_SQ_TEX_DIM_3D: 1529 break; 1530 case V_038000_SQ_TEX_DIM_CUBEMAP: 1531 if (p->family >= CHIP_RV770) 1532 nfaces = 8; 1533 else 1534 nfaces = 6; 1535 break; 1536 case V_038000_SQ_TEX_DIM_1D_ARRAY: 1537 case V_038000_SQ_TEX_DIM_2D_ARRAY: 1538 is_array = true; 1539 break; 1540 case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA: 1541 is_array = true; 1542 fallthrough; 1543 case V_038000_SQ_TEX_DIM_2D_MSAA: 1544 array_check.nsamples = 1 << llevel; 1545 llevel = 0; 1546 break; 1547 default: 1548 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0)); 1549 return -EINVAL; 1550 } 1551 if (!r600_fmt_is_valid_texture(format, p->family)) { 1552 dev_warn(p->dev, "%s:%d texture invalid format %d\n", 1553 __func__, __LINE__, format); 1554 return -EINVAL; 1555 } 1556 1557 if (r600_get_array_mode_alignment(&array_check, 1558 &pitch_align, &height_align, &depth_align, &base_align)) { 1559 dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n", 1560 __func__, __LINE__, G_038000_TILE_MODE(word0)); 1561 return -EINVAL; 1562 } 1563 1564 /* XXX check height as well... */ 1565 1566 if (!IS_ALIGNED(pitch, pitch_align)) { 1567 dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n", 1568 __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0)); 1569 return -EINVAL; 1570 } 1571 if (!IS_ALIGNED(base_offset, base_align)) { 1572 dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n", 1573 __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0)); 1574 return -EINVAL; 1575 } 1576 if (!IS_ALIGNED(mip_offset, base_align)) { 1577 dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n", 1578 __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0)); 1579 return -EINVAL; 1580 } 1581 1582 if (blevel > llevel) { 1583 dev_warn(p->dev, "texture blevel %d > llevel %d\n", 1584 blevel, llevel); 1585 } 1586 if (is_array) { 1587 barray = G_038014_BASE_ARRAY(word5); 1588 larray = G_038014_LAST_ARRAY(word5); 1589 1590 nfaces = larray - barray + 1; 1591 } 1592 r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, array_check.nsamples, format, 1593 pitch_align, height_align, base_align, 1594 &l0_size, &mipmap_size); 1595 /* using get ib will give us the offset into the texture bo */ 1596 if ((l0_size + word2) > radeon_bo_size(texture)) { 1597 dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n", 1598 w0, h0, pitch_align, height_align, 1599 array_check.array_mode, format, word2, 1600 l0_size, radeon_bo_size(texture)); 1601 dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align); 1602 return -EINVAL; 1603 } 1604 /* using get ib will give us the offset into the mipmap bo */ 1605 if ((mipmap_size + word3) > radeon_bo_size(mipmap)) { 1606 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n", 1607 w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/ 1608 } 1609 return 0; 1610 } 1611 1612 static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) 1613 { 1614 u32 m, i; 1615 1616 i = (reg >> 7); 1617 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) { 1618 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 1619 return false; 1620 } 1621 m = 1 << ((reg >> 2) & 31); 1622 if (!(r600_reg_safe_bm[i] & m)) 1623 return true; 1624 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 1625 return false; 1626 } 1627 1628 static int r600_packet3_check(struct radeon_cs_parser *p, 1629 struct radeon_cs_packet *pkt) 1630 { 1631 struct radeon_bo_list *reloc; 1632 struct r600_cs_track *track; 1633 volatile u32 *ib; 1634 unsigned idx; 1635 unsigned i; 1636 unsigned start_reg, end_reg, reg; 1637 int r; 1638 u32 idx_value; 1639 1640 track = (struct r600_cs_track *)p->track; 1641 ib = p->ib.ptr; 1642 idx = pkt->idx + 1; 1643 idx_value = radeon_get_ib_value(p, idx); 1644 1645 switch (pkt->opcode) { 1646 case PACKET3_SET_PREDICATION: 1647 { 1648 int pred_op; 1649 int tmp; 1650 uint64_t offset; 1651 1652 if (pkt->count != 1) { 1653 DRM_ERROR("bad SET PREDICATION\n"); 1654 return -EINVAL; 1655 } 1656 1657 tmp = radeon_get_ib_value(p, idx + 1); 1658 pred_op = (tmp >> 16) & 0x7; 1659 1660 /* for the clear predicate operation */ 1661 if (pred_op == 0) 1662 return 0; 1663 1664 if (pred_op > 2) { 1665 DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op); 1666 return -EINVAL; 1667 } 1668 1669 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1670 if (r) { 1671 DRM_ERROR("bad SET PREDICATION\n"); 1672 return -EINVAL; 1673 } 1674 1675 offset = reloc->gpu_offset + 1676 (idx_value & 0xfffffff0) + 1677 ((u64)(tmp & 0xff) << 32); 1678 1679 ib[idx + 0] = offset; 1680 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); 1681 } 1682 break; 1683 1684 case PACKET3_START_3D_CMDBUF: 1685 if (p->family >= CHIP_RV770 || pkt->count) { 1686 DRM_ERROR("bad START_3D\n"); 1687 return -EINVAL; 1688 } 1689 break; 1690 case PACKET3_CONTEXT_CONTROL: 1691 if (pkt->count != 1) { 1692 DRM_ERROR("bad CONTEXT_CONTROL\n"); 1693 return -EINVAL; 1694 } 1695 break; 1696 case PACKET3_INDEX_TYPE: 1697 case PACKET3_NUM_INSTANCES: 1698 if (pkt->count) { 1699 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n"); 1700 return -EINVAL; 1701 } 1702 break; 1703 case PACKET3_DRAW_INDEX: 1704 { 1705 uint64_t offset; 1706 if (pkt->count != 3) { 1707 DRM_ERROR("bad DRAW_INDEX\n"); 1708 return -EINVAL; 1709 } 1710 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1711 if (r) { 1712 DRM_ERROR("bad DRAW_INDEX\n"); 1713 return -EINVAL; 1714 } 1715 1716 offset = reloc->gpu_offset + 1717 idx_value + 1718 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); 1719 1720 ib[idx+0] = offset; 1721 ib[idx+1] = upper_32_bits(offset) & 0xff; 1722 1723 r = r600_cs_track_check(p); 1724 if (r) { 1725 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1726 return r; 1727 } 1728 break; 1729 } 1730 case PACKET3_DRAW_INDEX_AUTO: 1731 if (pkt->count != 1) { 1732 DRM_ERROR("bad DRAW_INDEX_AUTO\n"); 1733 return -EINVAL; 1734 } 1735 r = r600_cs_track_check(p); 1736 if (r) { 1737 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); 1738 return r; 1739 } 1740 break; 1741 case PACKET3_DRAW_INDEX_IMMD_BE: 1742 case PACKET3_DRAW_INDEX_IMMD: 1743 if (pkt->count < 2) { 1744 DRM_ERROR("bad DRAW_INDEX_IMMD\n"); 1745 return -EINVAL; 1746 } 1747 r = r600_cs_track_check(p); 1748 if (r) { 1749 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1750 return r; 1751 } 1752 break; 1753 case PACKET3_WAIT_REG_MEM: 1754 if (pkt->count != 5) { 1755 DRM_ERROR("bad WAIT_REG_MEM\n"); 1756 return -EINVAL; 1757 } 1758 /* bit 4 is reg (0) or mem (1) */ 1759 if (idx_value & 0x10) { 1760 uint64_t offset; 1761 1762 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1763 if (r) { 1764 DRM_ERROR("bad WAIT_REG_MEM\n"); 1765 return -EINVAL; 1766 } 1767 1768 offset = reloc->gpu_offset + 1769 (radeon_get_ib_value(p, idx+1) & 0xfffffff0) + 1770 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 1771 1772 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0); 1773 ib[idx+2] = upper_32_bits(offset) & 0xff; 1774 } else if (idx_value & 0x100) { 1775 DRM_ERROR("cannot use PFP on REG wait\n"); 1776 return -EINVAL; 1777 } 1778 break; 1779 case PACKET3_CP_DMA: 1780 { 1781 u32 command, size; 1782 u64 offset, tmp; 1783 if (pkt->count != 4) { 1784 DRM_ERROR("bad CP DMA\n"); 1785 return -EINVAL; 1786 } 1787 command = radeon_get_ib_value(p, idx+4); 1788 size = command & 0x1fffff; 1789 if (command & PACKET3_CP_DMA_CMD_SAS) { 1790 /* src address space is register */ 1791 DRM_ERROR("CP DMA SAS not supported\n"); 1792 return -EINVAL; 1793 } else { 1794 if (command & PACKET3_CP_DMA_CMD_SAIC) { 1795 DRM_ERROR("CP DMA SAIC only supported for registers\n"); 1796 return -EINVAL; 1797 } 1798 /* src address space is memory */ 1799 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1800 if (r) { 1801 DRM_ERROR("bad CP DMA SRC\n"); 1802 return -EINVAL; 1803 } 1804 1805 tmp = radeon_get_ib_value(p, idx) + 1806 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); 1807 1808 offset = reloc->gpu_offset + tmp; 1809 1810 if ((tmp + size) > radeon_bo_size(reloc->robj)) { 1811 dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n", 1812 tmp + size, radeon_bo_size(reloc->robj)); 1813 return -EINVAL; 1814 } 1815 1816 ib[idx] = offset; 1817 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff); 1818 } 1819 if (command & PACKET3_CP_DMA_CMD_DAS) { 1820 /* dst address space is register */ 1821 DRM_ERROR("CP DMA DAS not supported\n"); 1822 return -EINVAL; 1823 } else { 1824 /* dst address space is memory */ 1825 if (command & PACKET3_CP_DMA_CMD_DAIC) { 1826 DRM_ERROR("CP DMA DAIC only supported for registers\n"); 1827 return -EINVAL; 1828 } 1829 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1830 if (r) { 1831 DRM_ERROR("bad CP DMA DST\n"); 1832 return -EINVAL; 1833 } 1834 1835 tmp = radeon_get_ib_value(p, idx+2) + 1836 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32); 1837 1838 offset = reloc->gpu_offset + tmp; 1839 1840 if ((tmp + size) > radeon_bo_size(reloc->robj)) { 1841 dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n", 1842 tmp + size, radeon_bo_size(reloc->robj)); 1843 return -EINVAL; 1844 } 1845 1846 ib[idx+2] = offset; 1847 ib[idx+3] = upper_32_bits(offset) & 0xff; 1848 } 1849 break; 1850 } 1851 case PACKET3_SURFACE_SYNC: 1852 if (pkt->count != 3) { 1853 DRM_ERROR("bad SURFACE_SYNC\n"); 1854 return -EINVAL; 1855 } 1856 /* 0xffffffff/0x0 is flush all cache flag */ 1857 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || 1858 radeon_get_ib_value(p, idx + 2) != 0) { 1859 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1860 if (r) { 1861 DRM_ERROR("bad SURFACE_SYNC\n"); 1862 return -EINVAL; 1863 } 1864 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1865 } 1866 break; 1867 case PACKET3_EVENT_WRITE: 1868 if (pkt->count != 2 && pkt->count != 0) { 1869 DRM_ERROR("bad EVENT_WRITE\n"); 1870 return -EINVAL; 1871 } 1872 if (pkt->count) { 1873 uint64_t offset; 1874 1875 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1876 if (r) { 1877 DRM_ERROR("bad EVENT_WRITE\n"); 1878 return -EINVAL; 1879 } 1880 offset = reloc->gpu_offset + 1881 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + 1882 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 1883 1884 ib[idx+1] = offset & 0xfffffff8; 1885 ib[idx+2] = upper_32_bits(offset) & 0xff; 1886 } 1887 break; 1888 case PACKET3_EVENT_WRITE_EOP: 1889 { 1890 uint64_t offset; 1891 1892 if (pkt->count != 4) { 1893 DRM_ERROR("bad EVENT_WRITE_EOP\n"); 1894 return -EINVAL; 1895 } 1896 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1897 if (r) { 1898 DRM_ERROR("bad EVENT_WRITE\n"); 1899 return -EINVAL; 1900 } 1901 1902 offset = reloc->gpu_offset + 1903 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + 1904 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 1905 1906 ib[idx+1] = offset & 0xfffffffc; 1907 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); 1908 break; 1909 } 1910 case PACKET3_SET_CONFIG_REG: 1911 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET; 1912 end_reg = 4 * pkt->count + start_reg - 4; 1913 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) || 1914 (start_reg >= PACKET3_SET_CONFIG_REG_END) || 1915 (end_reg >= PACKET3_SET_CONFIG_REG_END)) { 1916 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n"); 1917 return -EINVAL; 1918 } 1919 for (i = 0; i < pkt->count; i++) { 1920 reg = start_reg + (4 * i); 1921 r = r600_cs_check_reg(p, reg, idx+1+i); 1922 if (r) 1923 return r; 1924 } 1925 break; 1926 case PACKET3_SET_CONTEXT_REG: 1927 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET; 1928 end_reg = 4 * pkt->count + start_reg - 4; 1929 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) || 1930 (start_reg >= PACKET3_SET_CONTEXT_REG_END) || 1931 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) { 1932 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n"); 1933 return -EINVAL; 1934 } 1935 for (i = 0; i < pkt->count; i++) { 1936 reg = start_reg + (4 * i); 1937 r = r600_cs_check_reg(p, reg, idx+1+i); 1938 if (r) 1939 return r; 1940 } 1941 break; 1942 case PACKET3_SET_RESOURCE: 1943 if (pkt->count % 7) { 1944 DRM_ERROR("bad SET_RESOURCE\n"); 1945 return -EINVAL; 1946 } 1947 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET; 1948 end_reg = 4 * pkt->count + start_reg - 4; 1949 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) || 1950 (start_reg >= PACKET3_SET_RESOURCE_END) || 1951 (end_reg >= PACKET3_SET_RESOURCE_END)) { 1952 DRM_ERROR("bad SET_RESOURCE\n"); 1953 return -EINVAL; 1954 } 1955 for (i = 0; i < (pkt->count / 7); i++) { 1956 struct radeon_bo *texture, *mipmap; 1957 u32 size, offset, base_offset, mip_offset; 1958 1959 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) { 1960 case SQ_TEX_VTX_VALID_TEXTURE: 1961 /* tex base */ 1962 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1963 if (r) { 1964 DRM_ERROR("bad SET_RESOURCE\n"); 1965 return -EINVAL; 1966 } 1967 base_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1968 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1969 if (reloc->tiling_flags & RADEON_TILING_MACRO) 1970 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1); 1971 else if (reloc->tiling_flags & RADEON_TILING_MICRO) 1972 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1); 1973 } 1974 texture = reloc->robj; 1975 /* tex mip base */ 1976 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1977 if (r) { 1978 DRM_ERROR("bad SET_RESOURCE\n"); 1979 return -EINVAL; 1980 } 1981 mip_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1982 mipmap = reloc->robj; 1983 r = r600_check_texture_resource(p, idx+(i*7)+1, 1984 texture, mipmap, 1985 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2), 1986 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3), 1987 reloc->tiling_flags); 1988 if (r) 1989 return r; 1990 ib[idx+1+(i*7)+2] += base_offset; 1991 ib[idx+1+(i*7)+3] += mip_offset; 1992 break; 1993 case SQ_TEX_VTX_VALID_BUFFER: 1994 { 1995 uint64_t offset64; 1996 /* vtx base */ 1997 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1998 if (r) { 1999 DRM_ERROR("bad SET_RESOURCE\n"); 2000 return -EINVAL; 2001 } 2002 offset = radeon_get_ib_value(p, idx+1+(i*7)+0); 2003 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1; 2004 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) { 2005 /* force size to size of the buffer */ 2006 dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n", 2007 size + offset, radeon_bo_size(reloc->robj)); 2008 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset; 2009 } 2010 2011 offset64 = reloc->gpu_offset + offset; 2012 ib[idx+1+(i*8)+0] = offset64; 2013 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | 2014 (upper_32_bits(offset64) & 0xff); 2015 break; 2016 } 2017 case SQ_TEX_VTX_INVALID_TEXTURE: 2018 case SQ_TEX_VTX_INVALID_BUFFER: 2019 default: 2020 DRM_ERROR("bad SET_RESOURCE\n"); 2021 return -EINVAL; 2022 } 2023 } 2024 break; 2025 case PACKET3_SET_ALU_CONST: 2026 if (track->sq_config & DX9_CONSTS) { 2027 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET; 2028 end_reg = 4 * pkt->count + start_reg - 4; 2029 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) || 2030 (start_reg >= PACKET3_SET_ALU_CONST_END) || 2031 (end_reg >= PACKET3_SET_ALU_CONST_END)) { 2032 DRM_ERROR("bad SET_ALU_CONST\n"); 2033 return -EINVAL; 2034 } 2035 } 2036 break; 2037 case PACKET3_SET_BOOL_CONST: 2038 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET; 2039 end_reg = 4 * pkt->count + start_reg - 4; 2040 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) || 2041 (start_reg >= PACKET3_SET_BOOL_CONST_END) || 2042 (end_reg >= PACKET3_SET_BOOL_CONST_END)) { 2043 DRM_ERROR("bad SET_BOOL_CONST\n"); 2044 return -EINVAL; 2045 } 2046 break; 2047 case PACKET3_SET_LOOP_CONST: 2048 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET; 2049 end_reg = 4 * pkt->count + start_reg - 4; 2050 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) || 2051 (start_reg >= PACKET3_SET_LOOP_CONST_END) || 2052 (end_reg >= PACKET3_SET_LOOP_CONST_END)) { 2053 DRM_ERROR("bad SET_LOOP_CONST\n"); 2054 return -EINVAL; 2055 } 2056 break; 2057 case PACKET3_SET_CTL_CONST: 2058 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET; 2059 end_reg = 4 * pkt->count + start_reg - 4; 2060 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) || 2061 (start_reg >= PACKET3_SET_CTL_CONST_END) || 2062 (end_reg >= PACKET3_SET_CTL_CONST_END)) { 2063 DRM_ERROR("bad SET_CTL_CONST\n"); 2064 return -EINVAL; 2065 } 2066 break; 2067 case PACKET3_SET_SAMPLER: 2068 if (pkt->count % 3) { 2069 DRM_ERROR("bad SET_SAMPLER\n"); 2070 return -EINVAL; 2071 } 2072 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET; 2073 end_reg = 4 * pkt->count + start_reg - 4; 2074 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) || 2075 (start_reg >= PACKET3_SET_SAMPLER_END) || 2076 (end_reg >= PACKET3_SET_SAMPLER_END)) { 2077 DRM_ERROR("bad SET_SAMPLER\n"); 2078 return -EINVAL; 2079 } 2080 break; 2081 case PACKET3_STRMOUT_BASE_UPDATE: 2082 /* RS780 and RS880 also need this */ 2083 if (p->family < CHIP_RS780) { 2084 DRM_ERROR("STRMOUT_BASE_UPDATE only supported on 7xx\n"); 2085 return -EINVAL; 2086 } 2087 if (pkt->count != 1) { 2088 DRM_ERROR("bad STRMOUT_BASE_UPDATE packet count\n"); 2089 return -EINVAL; 2090 } 2091 if (idx_value > 3) { 2092 DRM_ERROR("bad STRMOUT_BASE_UPDATE index\n"); 2093 return -EINVAL; 2094 } 2095 { 2096 u64 offset; 2097 2098 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2099 if (r) { 2100 DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n"); 2101 return -EINVAL; 2102 } 2103 2104 if (reloc->robj != track->vgt_strmout_bo[idx_value]) { 2105 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo does not match\n"); 2106 return -EINVAL; 2107 } 2108 2109 offset = radeon_get_ib_value(p, idx+1) << 8; 2110 if (offset != track->vgt_strmout_bo_offset[idx_value]) { 2111 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%llx, 0x%x\n", 2112 offset, track->vgt_strmout_bo_offset[idx_value]); 2113 return -EINVAL; 2114 } 2115 2116 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2117 DRM_ERROR("bad STRMOUT_BASE_UPDATE bo too small: 0x%llx, 0x%lx\n", 2118 offset + 4, radeon_bo_size(reloc->robj)); 2119 return -EINVAL; 2120 } 2121 ib[idx+1] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 2122 } 2123 break; 2124 case PACKET3_SURFACE_BASE_UPDATE: 2125 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) { 2126 DRM_ERROR("bad SURFACE_BASE_UPDATE\n"); 2127 return -EINVAL; 2128 } 2129 if (pkt->count) { 2130 DRM_ERROR("bad SURFACE_BASE_UPDATE\n"); 2131 return -EINVAL; 2132 } 2133 break; 2134 case PACKET3_STRMOUT_BUFFER_UPDATE: 2135 if (pkt->count != 4) { 2136 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n"); 2137 return -EINVAL; 2138 } 2139 /* Updating memory at DST_ADDRESS. */ 2140 if (idx_value & 0x1) { 2141 u64 offset; 2142 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2143 if (r) { 2144 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n"); 2145 return -EINVAL; 2146 } 2147 offset = radeon_get_ib_value(p, idx+1); 2148 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; 2149 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2150 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n", 2151 offset + 4, radeon_bo_size(reloc->robj)); 2152 return -EINVAL; 2153 } 2154 offset += reloc->gpu_offset; 2155 ib[idx+1] = offset; 2156 ib[idx+2] = upper_32_bits(offset) & 0xff; 2157 } 2158 /* Reading data from SRC_ADDRESS. */ 2159 if (((idx_value >> 1) & 0x3) == 2) { 2160 u64 offset; 2161 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2162 if (r) { 2163 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n"); 2164 return -EINVAL; 2165 } 2166 offset = radeon_get_ib_value(p, idx+3); 2167 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; 2168 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2169 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n", 2170 offset + 4, radeon_bo_size(reloc->robj)); 2171 return -EINVAL; 2172 } 2173 offset += reloc->gpu_offset; 2174 ib[idx+3] = offset; 2175 ib[idx+4] = upper_32_bits(offset) & 0xff; 2176 } 2177 break; 2178 case PACKET3_MEM_WRITE: 2179 { 2180 u64 offset; 2181 2182 if (pkt->count != 3) { 2183 DRM_ERROR("bad MEM_WRITE (invalid count)\n"); 2184 return -EINVAL; 2185 } 2186 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2187 if (r) { 2188 DRM_ERROR("bad MEM_WRITE (missing reloc)\n"); 2189 return -EINVAL; 2190 } 2191 offset = radeon_get_ib_value(p, idx+0); 2192 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL; 2193 if (offset & 0x7) { 2194 DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n"); 2195 return -EINVAL; 2196 } 2197 if ((offset + 8) > radeon_bo_size(reloc->robj)) { 2198 DRM_ERROR("bad MEM_WRITE bo too small: 0x%llx, 0x%lx\n", 2199 offset + 8, radeon_bo_size(reloc->robj)); 2200 return -EINVAL; 2201 } 2202 offset += reloc->gpu_offset; 2203 ib[idx+0] = offset; 2204 ib[idx+1] = upper_32_bits(offset) & 0xff; 2205 break; 2206 } 2207 case PACKET3_COPY_DW: 2208 if (pkt->count != 4) { 2209 DRM_ERROR("bad COPY_DW (invalid count)\n"); 2210 return -EINVAL; 2211 } 2212 if (idx_value & 0x1) { 2213 u64 offset; 2214 /* SRC is memory. */ 2215 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2216 if (r) { 2217 DRM_ERROR("bad COPY_DW (missing src reloc)\n"); 2218 return -EINVAL; 2219 } 2220 offset = radeon_get_ib_value(p, idx+1); 2221 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; 2222 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2223 DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n", 2224 offset + 4, radeon_bo_size(reloc->robj)); 2225 return -EINVAL; 2226 } 2227 offset += reloc->gpu_offset; 2228 ib[idx+1] = offset; 2229 ib[idx+2] = upper_32_bits(offset) & 0xff; 2230 } else { 2231 /* SRC is a reg. */ 2232 reg = radeon_get_ib_value(p, idx+1) << 2; 2233 if (!r600_is_safe_reg(p, reg, idx+1)) 2234 return -EINVAL; 2235 } 2236 if (idx_value & 0x2) { 2237 u64 offset; 2238 /* DST is memory. */ 2239 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2240 if (r) { 2241 DRM_ERROR("bad COPY_DW (missing dst reloc)\n"); 2242 return -EINVAL; 2243 } 2244 offset = radeon_get_ib_value(p, idx+3); 2245 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; 2246 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2247 DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n", 2248 offset + 4, radeon_bo_size(reloc->robj)); 2249 return -EINVAL; 2250 } 2251 offset += reloc->gpu_offset; 2252 ib[idx+3] = offset; 2253 ib[idx+4] = upper_32_bits(offset) & 0xff; 2254 } else { 2255 /* DST is a reg. */ 2256 reg = radeon_get_ib_value(p, idx+3) << 2; 2257 if (!r600_is_safe_reg(p, reg, idx+3)) 2258 return -EINVAL; 2259 } 2260 break; 2261 case PACKET3_NOP: 2262 break; 2263 default: 2264 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 2265 return -EINVAL; 2266 } 2267 return 0; 2268 } 2269 2270 int r600_cs_parse(struct radeon_cs_parser *p) 2271 { 2272 struct radeon_cs_packet pkt; 2273 struct r600_cs_track *track; 2274 int r; 2275 2276 if (p->track == NULL) { 2277 /* initialize tracker, we are in kms */ 2278 track = kzalloc(sizeof(*track), GFP_KERNEL); 2279 if (track == NULL) 2280 return -ENOMEM; 2281 r600_cs_track_init(track); 2282 if (p->rdev->family < CHIP_RV770) { 2283 track->npipes = p->rdev->config.r600.tiling_npipes; 2284 track->nbanks = p->rdev->config.r600.tiling_nbanks; 2285 track->group_size = p->rdev->config.r600.tiling_group_size; 2286 } else if (p->rdev->family <= CHIP_RV740) { 2287 track->npipes = p->rdev->config.rv770.tiling_npipes; 2288 track->nbanks = p->rdev->config.rv770.tiling_nbanks; 2289 track->group_size = p->rdev->config.rv770.tiling_group_size; 2290 } 2291 p->track = track; 2292 } 2293 do { 2294 r = radeon_cs_packet_parse(p, &pkt, p->idx); 2295 if (r) { 2296 kfree(p->track); 2297 p->track = NULL; 2298 return r; 2299 } 2300 p->idx += pkt.count + 2; 2301 switch (pkt.type) { 2302 case RADEON_PACKET_TYPE0: 2303 r = r600_cs_parse_packet0(p, &pkt); 2304 break; 2305 case RADEON_PACKET_TYPE2: 2306 break; 2307 case RADEON_PACKET_TYPE3: 2308 r = r600_packet3_check(p, &pkt); 2309 break; 2310 default: 2311 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 2312 kfree(p->track); 2313 p->track = NULL; 2314 return -EINVAL; 2315 } 2316 if (r) { 2317 kfree(p->track); 2318 p->track = NULL; 2319 return r; 2320 } 2321 } while (p->idx < p->chunk_ib->length_dw); 2322 #if 0 2323 for (r = 0; r < p->ib.length_dw; r++) { 2324 pr_info("%05d 0x%08X\n", r, p->ib.ptr[r]); 2325 mdelay(1); 2326 } 2327 #endif 2328 kfree(p->track); 2329 p->track = NULL; 2330 return 0; 2331 } 2332 2333 /* 2334 * DMA 2335 */ 2336 /** 2337 * r600_dma_cs_next_reloc() - parse next reloc 2338 * @p: parser structure holding parsing context. 2339 * @cs_reloc: reloc informations 2340 * 2341 * Return the next reloc, do bo validation and compute 2342 * GPU offset using the provided start. 2343 **/ 2344 int r600_dma_cs_next_reloc(struct radeon_cs_parser *p, 2345 struct radeon_bo_list **cs_reloc) 2346 { 2347 unsigned idx; 2348 2349 *cs_reloc = NULL; 2350 if (p->chunk_relocs == NULL) { 2351 DRM_ERROR("No relocation chunk !\n"); 2352 return -EINVAL; 2353 } 2354 idx = p->dma_reloc_idx; 2355 if (idx >= p->nrelocs) { 2356 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 2357 idx, p->nrelocs); 2358 return -EINVAL; 2359 } 2360 *cs_reloc = &p->relocs[idx]; 2361 p->dma_reloc_idx++; 2362 return 0; 2363 } 2364 2365 #define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28) 2366 #define GET_DMA_COUNT(h) ((h) & 0x0000ffff) 2367 #define GET_DMA_T(h) (((h) & 0x00800000) >> 23) 2368 2369 /** 2370 * r600_dma_cs_parse() - parse the DMA IB 2371 * @p: parser structure holding parsing context. 2372 * 2373 * Parses the DMA IB from the CS ioctl and updates 2374 * the GPU addresses based on the reloc information and 2375 * checks for errors. (R6xx-R7xx) 2376 * Returns 0 for success and an error on failure. 2377 **/ 2378 int r600_dma_cs_parse(struct radeon_cs_parser *p) 2379 { 2380 struct radeon_cs_chunk *ib_chunk = p->chunk_ib; 2381 struct radeon_bo_list *src_reloc, *dst_reloc; 2382 u32 header, cmd, count, tiled; 2383 volatile u32 *ib = p->ib.ptr; 2384 u32 idx, idx_value; 2385 u64 src_offset, dst_offset; 2386 int r; 2387 2388 do { 2389 if (p->idx >= ib_chunk->length_dw) { 2390 DRM_ERROR("Can not parse packet at %d after CS end %d !\n", 2391 p->idx, ib_chunk->length_dw); 2392 return -EINVAL; 2393 } 2394 idx = p->idx; 2395 header = radeon_get_ib_value(p, idx); 2396 cmd = GET_DMA_CMD(header); 2397 count = GET_DMA_COUNT(header); 2398 tiled = GET_DMA_T(header); 2399 2400 switch (cmd) { 2401 case DMA_PACKET_WRITE: 2402 r = r600_dma_cs_next_reloc(p, &dst_reloc); 2403 if (r) { 2404 DRM_ERROR("bad DMA_PACKET_WRITE\n"); 2405 return -EINVAL; 2406 } 2407 if (tiled) { 2408 dst_offset = radeon_get_ib_value(p, idx+1); 2409 dst_offset <<= 8; 2410 2411 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); 2412 p->idx += count + 5; 2413 } else { 2414 dst_offset = radeon_get_ib_value(p, idx+1); 2415 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; 2416 2417 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 2418 ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 2419 p->idx += count + 3; 2420 } 2421 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 2422 dev_warn(p->dev, "DMA write buffer too small (%llu %lu)\n", 2423 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 2424 return -EINVAL; 2425 } 2426 break; 2427 case DMA_PACKET_COPY: 2428 r = r600_dma_cs_next_reloc(p, &src_reloc); 2429 if (r) { 2430 DRM_ERROR("bad DMA_PACKET_COPY\n"); 2431 return -EINVAL; 2432 } 2433 r = r600_dma_cs_next_reloc(p, &dst_reloc); 2434 if (r) { 2435 DRM_ERROR("bad DMA_PACKET_COPY\n"); 2436 return -EINVAL; 2437 } 2438 if (tiled) { 2439 idx_value = radeon_get_ib_value(p, idx + 2); 2440 /* detile bit */ 2441 if (idx_value & (1 << 31)) { 2442 /* tiled src, linear dst */ 2443 src_offset = radeon_get_ib_value(p, idx+1); 2444 src_offset <<= 8; 2445 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); 2446 2447 dst_offset = radeon_get_ib_value(p, idx+5); 2448 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; 2449 ib[idx+5] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 2450 ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 2451 } else { 2452 /* linear src, tiled dst */ 2453 src_offset = radeon_get_ib_value(p, idx+5); 2454 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; 2455 ib[idx+5] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 2456 ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 2457 2458 dst_offset = radeon_get_ib_value(p, idx+1); 2459 dst_offset <<= 8; 2460 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); 2461 } 2462 p->idx += 7; 2463 } else { 2464 if (p->family >= CHIP_RV770) { 2465 src_offset = radeon_get_ib_value(p, idx+2); 2466 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; 2467 dst_offset = radeon_get_ib_value(p, idx+1); 2468 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; 2469 2470 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 2471 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 2472 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; 2473 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 2474 p->idx += 5; 2475 } else { 2476 src_offset = radeon_get_ib_value(p, idx+2); 2477 src_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; 2478 dst_offset = radeon_get_ib_value(p, idx+1); 2479 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16; 2480 2481 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 2482 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); 2483 ib[idx+3] += upper_32_bits(src_reloc->gpu_offset) & 0xff; 2484 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16; 2485 p->idx += 4; 2486 } 2487 } 2488 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { 2489 dev_warn(p->dev, "DMA copy src buffer too small (%llu %lu)\n", 2490 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 2491 return -EINVAL; 2492 } 2493 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 2494 dev_warn(p->dev, "DMA write dst buffer too small (%llu %lu)\n", 2495 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 2496 return -EINVAL; 2497 } 2498 break; 2499 case DMA_PACKET_CONSTANT_FILL: 2500 if (p->family < CHIP_RV770) { 2501 DRM_ERROR("Constant Fill is 7xx only !\n"); 2502 return -EINVAL; 2503 } 2504 r = r600_dma_cs_next_reloc(p, &dst_reloc); 2505 if (r) { 2506 DRM_ERROR("bad DMA_PACKET_WRITE\n"); 2507 return -EINVAL; 2508 } 2509 dst_offset = radeon_get_ib_value(p, idx+1); 2510 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16; 2511 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 2512 dev_warn(p->dev, "DMA constant fill buffer too small (%llu %lu)\n", 2513 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 2514 return -EINVAL; 2515 } 2516 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); 2517 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; 2518 p->idx += 4; 2519 break; 2520 case DMA_PACKET_NOP: 2521 p->idx += 1; 2522 break; 2523 default: 2524 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx); 2525 return -EINVAL; 2526 } 2527 } while (p->idx < p->chunk_ib->length_dw); 2528 #if 0 2529 for (r = 0; r < p->ib->length_dw; r++) { 2530 pr_info("%05d 0x%08X\n", r, p->ib.ptr[r]); 2531 mdelay(1); 2532 } 2533 #endif 2534 return 0; 2535 } 2536