1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/slab.h> 29 #include <linux/seq_file.h> 30 #include <linux/firmware.h> 31 #include <linux/module.h> 32 #include <drm/drmP.h> 33 #include <drm/radeon_drm.h> 34 #include "radeon.h" 35 #include "radeon_asic.h" 36 #include "radeon_mode.h" 37 #include "r600d.h" 38 #include "atom.h" 39 #include "avivod.h" 40 #include "radeon_ucode.h" 41 42 /* Firmware Names */ 43 MODULE_FIRMWARE("radeon/R600_pfp.bin"); 44 MODULE_FIRMWARE("radeon/R600_me.bin"); 45 MODULE_FIRMWARE("radeon/RV610_pfp.bin"); 46 MODULE_FIRMWARE("radeon/RV610_me.bin"); 47 MODULE_FIRMWARE("radeon/RV630_pfp.bin"); 48 MODULE_FIRMWARE("radeon/RV630_me.bin"); 49 MODULE_FIRMWARE("radeon/RV620_pfp.bin"); 50 MODULE_FIRMWARE("radeon/RV620_me.bin"); 51 MODULE_FIRMWARE("radeon/RV635_pfp.bin"); 52 MODULE_FIRMWARE("radeon/RV635_me.bin"); 53 MODULE_FIRMWARE("radeon/RV670_pfp.bin"); 54 MODULE_FIRMWARE("radeon/RV670_me.bin"); 55 MODULE_FIRMWARE("radeon/RS780_pfp.bin"); 56 MODULE_FIRMWARE("radeon/RS780_me.bin"); 57 MODULE_FIRMWARE("radeon/RV770_pfp.bin"); 58 MODULE_FIRMWARE("radeon/RV770_me.bin"); 59 MODULE_FIRMWARE("radeon/RV770_smc.bin"); 60 MODULE_FIRMWARE("radeon/RV730_pfp.bin"); 61 MODULE_FIRMWARE("radeon/RV730_me.bin"); 62 MODULE_FIRMWARE("radeon/RV730_smc.bin"); 63 MODULE_FIRMWARE("radeon/RV740_smc.bin"); 64 MODULE_FIRMWARE("radeon/RV710_pfp.bin"); 65 MODULE_FIRMWARE("radeon/RV710_me.bin"); 66 MODULE_FIRMWARE("radeon/RV710_smc.bin"); 67 MODULE_FIRMWARE("radeon/R600_rlc.bin"); 68 MODULE_FIRMWARE("radeon/R700_rlc.bin"); 69 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); 70 MODULE_FIRMWARE("radeon/CEDAR_me.bin"); 71 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); 72 MODULE_FIRMWARE("radeon/CEDAR_smc.bin"); 73 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); 74 MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); 75 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); 76 MODULE_FIRMWARE("radeon/REDWOOD_smc.bin"); 77 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); 78 MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); 79 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); 80 MODULE_FIRMWARE("radeon/JUNIPER_smc.bin"); 81 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); 82 MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); 83 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); 84 MODULE_FIRMWARE("radeon/CYPRESS_smc.bin"); 85 MODULE_FIRMWARE("radeon/PALM_pfp.bin"); 86 MODULE_FIRMWARE("radeon/PALM_me.bin"); 87 MODULE_FIRMWARE("radeon/SUMO_rlc.bin"); 88 MODULE_FIRMWARE("radeon/SUMO_pfp.bin"); 89 MODULE_FIRMWARE("radeon/SUMO_me.bin"); 90 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin"); 91 MODULE_FIRMWARE("radeon/SUMO2_me.bin"); 92 93 static const u32 crtc_offsets[2] = 94 { 95 0, 96 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 97 }; 98 99 int r600_debugfs_mc_info_init(struct radeon_device *rdev); 100 101 /* r600,rv610,rv630,rv620,rv635,rv670 */ 102 int r600_mc_wait_for_idle(struct radeon_device *rdev); 103 static void r600_gpu_init(struct radeon_device *rdev); 104 void r600_fini(struct radeon_device *rdev); 105 void r600_irq_disable(struct radeon_device *rdev); 106 static void r600_pcie_gen2_enable(struct radeon_device *rdev); 107 extern int evergreen_rlc_resume(struct radeon_device *rdev); 108 109 /** 110 * r600_get_xclk - get the xclk 111 * 112 * @rdev: radeon_device pointer 113 * 114 * Returns the reference clock used by the gfx engine 115 * (r6xx, IGPs, APUs). 116 */ 117 u32 r600_get_xclk(struct radeon_device *rdev) 118 { 119 return rdev->clock.spll.reference_freq; 120 } 121 122 /* get temperature in millidegrees */ 123 int rv6xx_get_temp(struct radeon_device *rdev) 124 { 125 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> 126 ASIC_T_SHIFT; 127 int actual_temp = temp & 0xff; 128 129 if (temp & 0x100) 130 actual_temp -= 256; 131 132 return actual_temp * 1000; 133 } 134 135 void r600_pm_get_dynpm_state(struct radeon_device *rdev) 136 { 137 int i; 138 139 rdev->pm.dynpm_can_upclock = true; 140 rdev->pm.dynpm_can_downclock = true; 141 142 /* power state array is low to high, default is first */ 143 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { 144 int min_power_state_index = 0; 145 146 if (rdev->pm.num_power_states > 2) 147 min_power_state_index = 1; 148 149 switch (rdev->pm.dynpm_planned_action) { 150 case DYNPM_ACTION_MINIMUM: 151 rdev->pm.requested_power_state_index = min_power_state_index; 152 rdev->pm.requested_clock_mode_index = 0; 153 rdev->pm.dynpm_can_downclock = false; 154 break; 155 case DYNPM_ACTION_DOWNCLOCK: 156 if (rdev->pm.current_power_state_index == min_power_state_index) { 157 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 158 rdev->pm.dynpm_can_downclock = false; 159 } else { 160 if (rdev->pm.active_crtc_count > 1) { 161 for (i = 0; i < rdev->pm.num_power_states; i++) { 162 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 163 continue; 164 else if (i >= rdev->pm.current_power_state_index) { 165 rdev->pm.requested_power_state_index = 166 rdev->pm.current_power_state_index; 167 break; 168 } else { 169 rdev->pm.requested_power_state_index = i; 170 break; 171 } 172 } 173 } else { 174 if (rdev->pm.current_power_state_index == 0) 175 rdev->pm.requested_power_state_index = 176 rdev->pm.num_power_states - 1; 177 else 178 rdev->pm.requested_power_state_index = 179 rdev->pm.current_power_state_index - 1; 180 } 181 } 182 rdev->pm.requested_clock_mode_index = 0; 183 /* don't use the power state if crtcs are active and no display flag is set */ 184 if ((rdev->pm.active_crtc_count > 0) && 185 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 186 clock_info[rdev->pm.requested_clock_mode_index].flags & 187 RADEON_PM_MODE_NO_DISPLAY)) { 188 rdev->pm.requested_power_state_index++; 189 } 190 break; 191 case DYNPM_ACTION_UPCLOCK: 192 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 193 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 194 rdev->pm.dynpm_can_upclock = false; 195 } else { 196 if (rdev->pm.active_crtc_count > 1) { 197 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 198 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 199 continue; 200 else if (i <= rdev->pm.current_power_state_index) { 201 rdev->pm.requested_power_state_index = 202 rdev->pm.current_power_state_index; 203 break; 204 } else { 205 rdev->pm.requested_power_state_index = i; 206 break; 207 } 208 } 209 } else 210 rdev->pm.requested_power_state_index = 211 rdev->pm.current_power_state_index + 1; 212 } 213 rdev->pm.requested_clock_mode_index = 0; 214 break; 215 case DYNPM_ACTION_DEFAULT: 216 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 217 rdev->pm.requested_clock_mode_index = 0; 218 rdev->pm.dynpm_can_upclock = false; 219 break; 220 case DYNPM_ACTION_NONE: 221 default: 222 DRM_ERROR("Requested mode for not defined action\n"); 223 return; 224 } 225 } else { 226 /* XXX select a power state based on AC/DC, single/dualhead, etc. */ 227 /* for now just select the first power state and switch between clock modes */ 228 /* power state array is low to high, default is first (0) */ 229 if (rdev->pm.active_crtc_count > 1) { 230 rdev->pm.requested_power_state_index = -1; 231 /* start at 1 as we don't want the default mode */ 232 for (i = 1; i < rdev->pm.num_power_states; i++) { 233 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 234 continue; 235 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || 236 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { 237 rdev->pm.requested_power_state_index = i; 238 break; 239 } 240 } 241 /* if nothing selected, grab the default state. */ 242 if (rdev->pm.requested_power_state_index == -1) 243 rdev->pm.requested_power_state_index = 0; 244 } else 245 rdev->pm.requested_power_state_index = 1; 246 247 switch (rdev->pm.dynpm_planned_action) { 248 case DYNPM_ACTION_MINIMUM: 249 rdev->pm.requested_clock_mode_index = 0; 250 rdev->pm.dynpm_can_downclock = false; 251 break; 252 case DYNPM_ACTION_DOWNCLOCK: 253 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 254 if (rdev->pm.current_clock_mode_index == 0) { 255 rdev->pm.requested_clock_mode_index = 0; 256 rdev->pm.dynpm_can_downclock = false; 257 } else 258 rdev->pm.requested_clock_mode_index = 259 rdev->pm.current_clock_mode_index - 1; 260 } else { 261 rdev->pm.requested_clock_mode_index = 0; 262 rdev->pm.dynpm_can_downclock = false; 263 } 264 /* don't use the power state if crtcs are active and no display flag is set */ 265 if ((rdev->pm.active_crtc_count > 0) && 266 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 267 clock_info[rdev->pm.requested_clock_mode_index].flags & 268 RADEON_PM_MODE_NO_DISPLAY)) { 269 rdev->pm.requested_clock_mode_index++; 270 } 271 break; 272 case DYNPM_ACTION_UPCLOCK: 273 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 274 if (rdev->pm.current_clock_mode_index == 275 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { 276 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; 277 rdev->pm.dynpm_can_upclock = false; 278 } else 279 rdev->pm.requested_clock_mode_index = 280 rdev->pm.current_clock_mode_index + 1; 281 } else { 282 rdev->pm.requested_clock_mode_index = 283 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; 284 rdev->pm.dynpm_can_upclock = false; 285 } 286 break; 287 case DYNPM_ACTION_DEFAULT: 288 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 289 rdev->pm.requested_clock_mode_index = 0; 290 rdev->pm.dynpm_can_upclock = false; 291 break; 292 case DYNPM_ACTION_NONE: 293 default: 294 DRM_ERROR("Requested mode for not defined action\n"); 295 return; 296 } 297 } 298 299 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 300 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 301 clock_info[rdev->pm.requested_clock_mode_index].sclk, 302 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 303 clock_info[rdev->pm.requested_clock_mode_index].mclk, 304 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 305 pcie_lanes); 306 } 307 308 void rs780_pm_init_profile(struct radeon_device *rdev) 309 { 310 if (rdev->pm.num_power_states == 2) { 311 /* default */ 312 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 313 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 314 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 315 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 316 /* low sh */ 317 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 318 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 319 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 320 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 321 /* mid sh */ 322 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 323 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 324 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 325 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 326 /* high sh */ 327 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 328 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 329 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 330 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 331 /* low mh */ 332 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 333 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 334 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 335 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 336 /* mid mh */ 337 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 338 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 339 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 340 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 341 /* high mh */ 342 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 343 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; 344 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 345 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 346 } else if (rdev->pm.num_power_states == 3) { 347 /* default */ 348 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 349 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 350 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 351 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 352 /* low sh */ 353 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 354 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 355 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 356 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 357 /* mid sh */ 358 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 359 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 360 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 361 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 362 /* high sh */ 363 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 364 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; 365 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 366 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 367 /* low mh */ 368 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; 369 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; 370 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 371 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 372 /* mid mh */ 373 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; 374 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; 375 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 376 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 377 /* high mh */ 378 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; 379 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 380 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 381 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 382 } else { 383 /* default */ 384 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 385 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 386 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 387 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 388 /* low sh */ 389 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; 390 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; 391 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 392 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 393 /* mid sh */ 394 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; 395 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; 396 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 397 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 398 /* high sh */ 399 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; 400 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; 401 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 402 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 403 /* low mh */ 404 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 405 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 406 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 407 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 408 /* mid mh */ 409 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 410 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 411 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 412 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 413 /* high mh */ 414 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 415 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; 416 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 417 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 418 } 419 } 420 421 void r600_pm_init_profile(struct radeon_device *rdev) 422 { 423 int idx; 424 425 if (rdev->family == CHIP_R600) { 426 /* XXX */ 427 /* default */ 428 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 429 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 430 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 431 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 432 /* low sh */ 433 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 434 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 435 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 436 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 437 /* mid sh */ 438 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 439 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 440 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 441 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 442 /* high sh */ 443 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 444 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 445 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 446 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 447 /* low mh */ 448 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 449 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 450 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 451 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 452 /* mid mh */ 453 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 454 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 455 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 456 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 457 /* high mh */ 458 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 459 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 460 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 461 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 462 } else { 463 if (rdev->pm.num_power_states < 4) { 464 /* default */ 465 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 466 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 467 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 468 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 469 /* low sh */ 470 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 471 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 472 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 473 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 474 /* mid sh */ 475 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 476 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 477 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 478 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 479 /* high sh */ 480 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 481 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 482 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 483 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 484 /* low mh */ 485 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 486 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; 487 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 488 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 489 /* low mh */ 490 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 491 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; 492 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 493 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 494 /* high mh */ 495 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 496 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 497 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 498 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 499 } else { 500 /* default */ 501 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 502 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 503 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 504 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 505 /* low sh */ 506 if (rdev->flags & RADEON_IS_MOBILITY) 507 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 508 else 509 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 510 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; 511 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; 512 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 513 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 514 /* mid sh */ 515 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; 516 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; 517 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 518 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 519 /* high sh */ 520 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 521 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; 522 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; 523 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 524 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 525 /* low mh */ 526 if (rdev->flags & RADEON_IS_MOBILITY) 527 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); 528 else 529 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 530 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; 531 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; 532 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 533 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 534 /* mid mh */ 535 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; 536 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; 537 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 538 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 539 /* high mh */ 540 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 541 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; 542 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; 543 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 544 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 545 } 546 } 547 } 548 549 void r600_pm_misc(struct radeon_device *rdev) 550 { 551 int req_ps_idx = rdev->pm.requested_power_state_index; 552 int req_cm_idx = rdev->pm.requested_clock_mode_index; 553 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 554 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 555 556 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 557 /* 0xff01 is a flag rather then an actual voltage */ 558 if (voltage->voltage == 0xff01) 559 return; 560 if (voltage->voltage != rdev->pm.current_vddc) { 561 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 562 rdev->pm.current_vddc = voltage->voltage; 563 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); 564 } 565 } 566 } 567 568 bool r600_gui_idle(struct radeon_device *rdev) 569 { 570 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) 571 return false; 572 else 573 return true; 574 } 575 576 /* hpd for digital panel detect/disconnect */ 577 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 578 { 579 bool connected = false; 580 581 if (ASIC_IS_DCE3(rdev)) { 582 switch (hpd) { 583 case RADEON_HPD_1: 584 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) 585 connected = true; 586 break; 587 case RADEON_HPD_2: 588 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) 589 connected = true; 590 break; 591 case RADEON_HPD_3: 592 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) 593 connected = true; 594 break; 595 case RADEON_HPD_4: 596 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) 597 connected = true; 598 break; 599 /* DCE 3.2 */ 600 case RADEON_HPD_5: 601 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) 602 connected = true; 603 break; 604 case RADEON_HPD_6: 605 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 606 connected = true; 607 break; 608 default: 609 break; 610 } 611 } else { 612 switch (hpd) { 613 case RADEON_HPD_1: 614 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 615 connected = true; 616 break; 617 case RADEON_HPD_2: 618 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 619 connected = true; 620 break; 621 case RADEON_HPD_3: 622 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 623 connected = true; 624 break; 625 default: 626 break; 627 } 628 } 629 return connected; 630 } 631 632 void r600_hpd_set_polarity(struct radeon_device *rdev, 633 enum radeon_hpd_id hpd) 634 { 635 u32 tmp; 636 bool connected = r600_hpd_sense(rdev, hpd); 637 638 if (ASIC_IS_DCE3(rdev)) { 639 switch (hpd) { 640 case RADEON_HPD_1: 641 tmp = RREG32(DC_HPD1_INT_CONTROL); 642 if (connected) 643 tmp &= ~DC_HPDx_INT_POLARITY; 644 else 645 tmp |= DC_HPDx_INT_POLARITY; 646 WREG32(DC_HPD1_INT_CONTROL, tmp); 647 break; 648 case RADEON_HPD_2: 649 tmp = RREG32(DC_HPD2_INT_CONTROL); 650 if (connected) 651 tmp &= ~DC_HPDx_INT_POLARITY; 652 else 653 tmp |= DC_HPDx_INT_POLARITY; 654 WREG32(DC_HPD2_INT_CONTROL, tmp); 655 break; 656 case RADEON_HPD_3: 657 tmp = RREG32(DC_HPD3_INT_CONTROL); 658 if (connected) 659 tmp &= ~DC_HPDx_INT_POLARITY; 660 else 661 tmp |= DC_HPDx_INT_POLARITY; 662 WREG32(DC_HPD3_INT_CONTROL, tmp); 663 break; 664 case RADEON_HPD_4: 665 tmp = RREG32(DC_HPD4_INT_CONTROL); 666 if (connected) 667 tmp &= ~DC_HPDx_INT_POLARITY; 668 else 669 tmp |= DC_HPDx_INT_POLARITY; 670 WREG32(DC_HPD4_INT_CONTROL, tmp); 671 break; 672 case RADEON_HPD_5: 673 tmp = RREG32(DC_HPD5_INT_CONTROL); 674 if (connected) 675 tmp &= ~DC_HPDx_INT_POLARITY; 676 else 677 tmp |= DC_HPDx_INT_POLARITY; 678 WREG32(DC_HPD5_INT_CONTROL, tmp); 679 break; 680 /* DCE 3.2 */ 681 case RADEON_HPD_6: 682 tmp = RREG32(DC_HPD6_INT_CONTROL); 683 if (connected) 684 tmp &= ~DC_HPDx_INT_POLARITY; 685 else 686 tmp |= DC_HPDx_INT_POLARITY; 687 WREG32(DC_HPD6_INT_CONTROL, tmp); 688 break; 689 default: 690 break; 691 } 692 } else { 693 switch (hpd) { 694 case RADEON_HPD_1: 695 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 696 if (connected) 697 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 698 else 699 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 700 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 701 break; 702 case RADEON_HPD_2: 703 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 704 if (connected) 705 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 706 else 707 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 708 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 709 break; 710 case RADEON_HPD_3: 711 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 712 if (connected) 713 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 714 else 715 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 716 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 717 break; 718 default: 719 break; 720 } 721 } 722 } 723 724 void r600_hpd_init(struct radeon_device *rdev) 725 { 726 struct drm_device *dev = rdev->ddev; 727 struct drm_connector *connector; 728 unsigned enable = 0; 729 730 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 731 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 732 733 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 734 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 735 /* don't try to enable hpd on eDP or LVDS avoid breaking the 736 * aux dp channel on imac and help (but not completely fix) 737 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 738 */ 739 continue; 740 } 741 if (ASIC_IS_DCE3(rdev)) { 742 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); 743 if (ASIC_IS_DCE32(rdev)) 744 tmp |= DC_HPDx_EN; 745 746 switch (radeon_connector->hpd.hpd) { 747 case RADEON_HPD_1: 748 WREG32(DC_HPD1_CONTROL, tmp); 749 break; 750 case RADEON_HPD_2: 751 WREG32(DC_HPD2_CONTROL, tmp); 752 break; 753 case RADEON_HPD_3: 754 WREG32(DC_HPD3_CONTROL, tmp); 755 break; 756 case RADEON_HPD_4: 757 WREG32(DC_HPD4_CONTROL, tmp); 758 break; 759 /* DCE 3.2 */ 760 case RADEON_HPD_5: 761 WREG32(DC_HPD5_CONTROL, tmp); 762 break; 763 case RADEON_HPD_6: 764 WREG32(DC_HPD6_CONTROL, tmp); 765 break; 766 default: 767 break; 768 } 769 } else { 770 switch (radeon_connector->hpd.hpd) { 771 case RADEON_HPD_1: 772 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); 773 break; 774 case RADEON_HPD_2: 775 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); 776 break; 777 case RADEON_HPD_3: 778 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); 779 break; 780 default: 781 break; 782 } 783 } 784 enable |= 1 << radeon_connector->hpd.hpd; 785 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 786 } 787 radeon_irq_kms_enable_hpd(rdev, enable); 788 } 789 790 void r600_hpd_fini(struct radeon_device *rdev) 791 { 792 struct drm_device *dev = rdev->ddev; 793 struct drm_connector *connector; 794 unsigned disable = 0; 795 796 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 797 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 798 if (ASIC_IS_DCE3(rdev)) { 799 switch (radeon_connector->hpd.hpd) { 800 case RADEON_HPD_1: 801 WREG32(DC_HPD1_CONTROL, 0); 802 break; 803 case RADEON_HPD_2: 804 WREG32(DC_HPD2_CONTROL, 0); 805 break; 806 case RADEON_HPD_3: 807 WREG32(DC_HPD3_CONTROL, 0); 808 break; 809 case RADEON_HPD_4: 810 WREG32(DC_HPD4_CONTROL, 0); 811 break; 812 /* DCE 3.2 */ 813 case RADEON_HPD_5: 814 WREG32(DC_HPD5_CONTROL, 0); 815 break; 816 case RADEON_HPD_6: 817 WREG32(DC_HPD6_CONTROL, 0); 818 break; 819 default: 820 break; 821 } 822 } else { 823 switch (radeon_connector->hpd.hpd) { 824 case RADEON_HPD_1: 825 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); 826 break; 827 case RADEON_HPD_2: 828 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); 829 break; 830 case RADEON_HPD_3: 831 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); 832 break; 833 default: 834 break; 835 } 836 } 837 disable |= 1 << radeon_connector->hpd.hpd; 838 } 839 radeon_irq_kms_disable_hpd(rdev, disable); 840 } 841 842 /* 843 * R600 PCIE GART 844 */ 845 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) 846 { 847 unsigned i; 848 u32 tmp; 849 850 /* flush hdp cache so updates hit vram */ 851 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 852 !(rdev->flags & RADEON_IS_AGP)) { 853 void __iomem *ptr = (void *)rdev->gart.ptr; 854 u32 tmp; 855 856 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 857 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 858 * This seems to cause problems on some AGP cards. Just use the old 859 * method for them. 860 */ 861 WREG32(HDP_DEBUG1, 0); 862 tmp = readl((void __iomem *)ptr); 863 } else 864 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 865 866 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); 867 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); 868 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 869 for (i = 0; i < rdev->usec_timeout; i++) { 870 /* read MC_STATUS */ 871 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); 872 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; 873 if (tmp == 2) { 874 printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); 875 return; 876 } 877 if (tmp) { 878 return; 879 } 880 udelay(1); 881 } 882 } 883 884 int r600_pcie_gart_init(struct radeon_device *rdev) 885 { 886 int r; 887 888 if (rdev->gart.robj) { 889 WARN(1, "R600 PCIE GART already initialized\n"); 890 return 0; 891 } 892 /* Initialize common gart structure */ 893 r = radeon_gart_init(rdev); 894 if (r) 895 return r; 896 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 897 return radeon_gart_table_vram_alloc(rdev); 898 } 899 900 static int r600_pcie_gart_enable(struct radeon_device *rdev) 901 { 902 u32 tmp; 903 int r, i; 904 905 if (rdev->gart.robj == NULL) { 906 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 907 return -EINVAL; 908 } 909 r = radeon_gart_table_vram_pin(rdev); 910 if (r) 911 return r; 912 radeon_gart_restore(rdev); 913 914 /* Setup L2 cache */ 915 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 916 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 917 EFFECTIVE_L2_QUEUE_SIZE(7)); 918 WREG32(VM_L2_CNTL2, 0); 919 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 920 /* Setup TLB control */ 921 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 922 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 923 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 924 ENABLE_WAIT_L2_QUERY; 925 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 926 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 927 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 928 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 929 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 930 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 931 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 932 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 933 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 934 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 935 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 936 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 937 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 938 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 939 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 940 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 941 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 942 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 943 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 944 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 945 (u32)(rdev->dummy_page.addr >> 12)); 946 for (i = 1; i < 7; i++) 947 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 948 949 r600_pcie_gart_tlb_flush(rdev); 950 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 951 (unsigned)(rdev->mc.gtt_size >> 20), 952 (unsigned long long)rdev->gart.table_addr); 953 rdev->gart.ready = true; 954 return 0; 955 } 956 957 static void r600_pcie_gart_disable(struct radeon_device *rdev) 958 { 959 u32 tmp; 960 int i; 961 962 /* Disable all tables */ 963 for (i = 0; i < 7; i++) 964 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 965 966 /* Disable L2 cache */ 967 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 968 EFFECTIVE_L2_QUEUE_SIZE(7)); 969 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 970 /* Setup L1 TLB control */ 971 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 972 ENABLE_WAIT_L2_QUERY; 973 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 974 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 975 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 976 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 977 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 978 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 979 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 980 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 981 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); 982 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); 983 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 984 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 985 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); 986 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 987 radeon_gart_table_vram_unpin(rdev); 988 } 989 990 static void r600_pcie_gart_fini(struct radeon_device *rdev) 991 { 992 radeon_gart_fini(rdev); 993 r600_pcie_gart_disable(rdev); 994 radeon_gart_table_vram_free(rdev); 995 } 996 997 static void r600_agp_enable(struct radeon_device *rdev) 998 { 999 u32 tmp; 1000 int i; 1001 1002 /* Setup L2 cache */ 1003 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1004 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1005 EFFECTIVE_L2_QUEUE_SIZE(7)); 1006 WREG32(VM_L2_CNTL2, 0); 1007 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1008 /* Setup TLB control */ 1009 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1010 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1011 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1012 ENABLE_WAIT_L2_QUERY; 1013 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1014 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1015 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 1016 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1017 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1018 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1019 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1020 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1021 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1022 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1023 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1024 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1025 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1026 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1027 for (i = 0; i < 7; i++) 1028 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1029 } 1030 1031 int r600_mc_wait_for_idle(struct radeon_device *rdev) 1032 { 1033 unsigned i; 1034 u32 tmp; 1035 1036 for (i = 0; i < rdev->usec_timeout; i++) { 1037 /* read MC_STATUS */ 1038 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; 1039 if (!tmp) 1040 return 0; 1041 udelay(1); 1042 } 1043 return -1; 1044 } 1045 1046 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg) 1047 { 1048 uint32_t r; 1049 1050 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg)); 1051 r = RREG32(R_0028FC_MC_DATA); 1052 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR); 1053 return r; 1054 } 1055 1056 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1057 { 1058 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) | 1059 S_0028F8_MC_IND_WR_EN(1)); 1060 WREG32(R_0028FC_MC_DATA, v); 1061 WREG32(R_0028F8_MC_INDEX, 0x7F); 1062 } 1063 1064 static void r600_mc_program(struct radeon_device *rdev) 1065 { 1066 struct rv515_mc_save save; 1067 u32 tmp; 1068 int i, j; 1069 1070 /* Initialize HDP */ 1071 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1072 WREG32((0x2c14 + j), 0x00000000); 1073 WREG32((0x2c18 + j), 0x00000000); 1074 WREG32((0x2c1c + j), 0x00000000); 1075 WREG32((0x2c20 + j), 0x00000000); 1076 WREG32((0x2c24 + j), 0x00000000); 1077 } 1078 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 1079 1080 rv515_mc_stop(rdev, &save); 1081 if (r600_mc_wait_for_idle(rdev)) { 1082 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1083 } 1084 /* Lockout access through VGA aperture (doesn't exist before R600) */ 1085 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1086 /* Update configuration */ 1087 if (rdev->flags & RADEON_IS_AGP) { 1088 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1089 /* VRAM before AGP */ 1090 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1091 rdev->mc.vram_start >> 12); 1092 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1093 rdev->mc.gtt_end >> 12); 1094 } else { 1095 /* VRAM after AGP */ 1096 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1097 rdev->mc.gtt_start >> 12); 1098 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1099 rdev->mc.vram_end >> 12); 1100 } 1101 } else { 1102 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); 1103 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); 1104 } 1105 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 1106 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1107 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1108 WREG32(MC_VM_FB_LOCATION, tmp); 1109 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1110 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 1111 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1112 if (rdev->flags & RADEON_IS_AGP) { 1113 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); 1114 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); 1115 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1116 } else { 1117 WREG32(MC_VM_AGP_BASE, 0); 1118 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1119 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1120 } 1121 if (r600_mc_wait_for_idle(rdev)) { 1122 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1123 } 1124 rv515_mc_resume(rdev, &save); 1125 /* we need to own VRAM, so turn off the VGA renderer here 1126 * to stop it overwriting our objects */ 1127 rv515_vga_render_disable(rdev); 1128 } 1129 1130 /** 1131 * r600_vram_gtt_location - try to find VRAM & GTT location 1132 * @rdev: radeon device structure holding all necessary informations 1133 * @mc: memory controller structure holding memory informations 1134 * 1135 * Function will place try to place VRAM at same place as in CPU (PCI) 1136 * address space as some GPU seems to have issue when we reprogram at 1137 * different address space. 1138 * 1139 * If there is not enough space to fit the unvisible VRAM after the 1140 * aperture then we limit the VRAM size to the aperture. 1141 * 1142 * If we are using AGP then place VRAM adjacent to AGP aperture are we need 1143 * them to be in one from GPU point of view so that we can program GPU to 1144 * catch access outside them (weird GPU policy see ??). 1145 * 1146 * This function will never fails, worst case are limiting VRAM or GTT. 1147 * 1148 * Note: GTT start, end, size should be initialized before calling this 1149 * function on AGP platform. 1150 */ 1151 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 1152 { 1153 u64 size_bf, size_af; 1154 1155 if (mc->mc_vram_size > 0xE0000000) { 1156 /* leave room for at least 512M GTT */ 1157 dev_warn(rdev->dev, "limiting VRAM\n"); 1158 mc->real_vram_size = 0xE0000000; 1159 mc->mc_vram_size = 0xE0000000; 1160 } 1161 if (rdev->flags & RADEON_IS_AGP) { 1162 size_bf = mc->gtt_start; 1163 size_af = mc->mc_mask - mc->gtt_end; 1164 if (size_bf > size_af) { 1165 if (mc->mc_vram_size > size_bf) { 1166 dev_warn(rdev->dev, "limiting VRAM\n"); 1167 mc->real_vram_size = size_bf; 1168 mc->mc_vram_size = size_bf; 1169 } 1170 mc->vram_start = mc->gtt_start - mc->mc_vram_size; 1171 } else { 1172 if (mc->mc_vram_size > size_af) { 1173 dev_warn(rdev->dev, "limiting VRAM\n"); 1174 mc->real_vram_size = size_af; 1175 mc->mc_vram_size = size_af; 1176 } 1177 mc->vram_start = mc->gtt_end + 1; 1178 } 1179 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 1180 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", 1181 mc->mc_vram_size >> 20, mc->vram_start, 1182 mc->vram_end, mc->real_vram_size >> 20); 1183 } else { 1184 u64 base = 0; 1185 if (rdev->flags & RADEON_IS_IGP) { 1186 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; 1187 base <<= 24; 1188 } 1189 radeon_vram_location(rdev, &rdev->mc, base); 1190 rdev->mc.gtt_base_align = 0; 1191 radeon_gtt_location(rdev, mc); 1192 } 1193 } 1194 1195 static int r600_mc_init(struct radeon_device *rdev) 1196 { 1197 u32 tmp; 1198 int chansize, numchan; 1199 uint32_t h_addr, l_addr; 1200 unsigned long long k8_addr; 1201 1202 /* Get VRAM informations */ 1203 rdev->mc.vram_is_ddr = true; 1204 tmp = RREG32(RAMCFG); 1205 if (tmp & CHANSIZE_OVERRIDE) { 1206 chansize = 16; 1207 } else if (tmp & CHANSIZE_MASK) { 1208 chansize = 64; 1209 } else { 1210 chansize = 32; 1211 } 1212 tmp = RREG32(CHMAP); 1213 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1214 case 0: 1215 default: 1216 numchan = 1; 1217 break; 1218 case 1: 1219 numchan = 2; 1220 break; 1221 case 2: 1222 numchan = 4; 1223 break; 1224 case 3: 1225 numchan = 8; 1226 break; 1227 } 1228 rdev->mc.vram_width = numchan * chansize; 1229 /* Could aper size report 0 ? */ 1230 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 1231 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 1232 /* Setup GPU memory space */ 1233 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1234 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1235 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1236 r600_vram_gtt_location(rdev, &rdev->mc); 1237 1238 if (rdev->flags & RADEON_IS_IGP) { 1239 rs690_pm_info(rdev); 1240 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 1241 1242 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 1243 /* Use K8 direct mapping for fast fb access. */ 1244 rdev->fastfb_working = false; 1245 h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL)); 1246 l_addr = RREG32_MC(R_000011_K8_FB_LOCATION); 1247 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr; 1248 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE) 1249 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) 1250 #endif 1251 { 1252 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport 1253 * memory is present. 1254 */ 1255 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { 1256 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n", 1257 (unsigned long long)rdev->mc.aper_base, k8_addr); 1258 rdev->mc.aper_base = (resource_size_t)k8_addr; 1259 rdev->fastfb_working = true; 1260 } 1261 } 1262 } 1263 } 1264 1265 radeon_update_bandwidth_info(rdev); 1266 return 0; 1267 } 1268 1269 int r600_vram_scratch_init(struct radeon_device *rdev) 1270 { 1271 int r; 1272 1273 if (rdev->vram_scratch.robj == NULL) { 1274 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, 1275 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 1276 NULL, &rdev->vram_scratch.robj); 1277 if (r) { 1278 return r; 1279 } 1280 } 1281 1282 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1283 if (unlikely(r != 0)) 1284 return r; 1285 r = radeon_bo_pin(rdev->vram_scratch.robj, 1286 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); 1287 if (r) { 1288 radeon_bo_unreserve(rdev->vram_scratch.robj); 1289 return r; 1290 } 1291 r = radeon_bo_kmap(rdev->vram_scratch.robj, 1292 (void **)&rdev->vram_scratch.ptr); 1293 if (r) 1294 radeon_bo_unpin(rdev->vram_scratch.robj); 1295 radeon_bo_unreserve(rdev->vram_scratch.robj); 1296 1297 return r; 1298 } 1299 1300 void r600_vram_scratch_fini(struct radeon_device *rdev) 1301 { 1302 int r; 1303 1304 if (rdev->vram_scratch.robj == NULL) { 1305 return; 1306 } 1307 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1308 if (likely(r == 0)) { 1309 radeon_bo_kunmap(rdev->vram_scratch.robj); 1310 radeon_bo_unpin(rdev->vram_scratch.robj); 1311 radeon_bo_unreserve(rdev->vram_scratch.robj); 1312 } 1313 radeon_bo_unref(&rdev->vram_scratch.robj); 1314 } 1315 1316 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung) 1317 { 1318 u32 tmp = RREG32(R600_BIOS_3_SCRATCH); 1319 1320 if (hung) 1321 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1322 else 1323 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1324 1325 WREG32(R600_BIOS_3_SCRATCH, tmp); 1326 } 1327 1328 static void r600_print_gpu_status_regs(struct radeon_device *rdev) 1329 { 1330 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", 1331 RREG32(R_008010_GRBM_STATUS)); 1332 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", 1333 RREG32(R_008014_GRBM_STATUS2)); 1334 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", 1335 RREG32(R_000E50_SRBM_STATUS)); 1336 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1337 RREG32(CP_STALLED_STAT1)); 1338 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 1339 RREG32(CP_STALLED_STAT2)); 1340 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 1341 RREG32(CP_BUSY_STAT)); 1342 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 1343 RREG32(CP_STAT)); 1344 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 1345 RREG32(DMA_STATUS_REG)); 1346 } 1347 1348 static bool r600_is_display_hung(struct radeon_device *rdev) 1349 { 1350 u32 crtc_hung = 0; 1351 u32 crtc_status[2]; 1352 u32 i, j, tmp; 1353 1354 for (i = 0; i < rdev->num_crtc; i++) { 1355 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { 1356 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1357 crtc_hung |= (1 << i); 1358 } 1359 } 1360 1361 for (j = 0; j < 10; j++) { 1362 for (i = 0; i < rdev->num_crtc; i++) { 1363 if (crtc_hung & (1 << i)) { 1364 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1365 if (tmp != crtc_status[i]) 1366 crtc_hung &= ~(1 << i); 1367 } 1368 } 1369 if (crtc_hung == 0) 1370 return false; 1371 udelay(100); 1372 } 1373 1374 return true; 1375 } 1376 1377 static u32 r600_gpu_check_soft_reset(struct radeon_device *rdev) 1378 { 1379 u32 reset_mask = 0; 1380 u32 tmp; 1381 1382 /* GRBM_STATUS */ 1383 tmp = RREG32(R_008010_GRBM_STATUS); 1384 if (rdev->family >= CHIP_RV770) { 1385 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1386 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1387 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1388 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1389 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1390 reset_mask |= RADEON_RESET_GFX; 1391 } else { 1392 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1393 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1394 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1395 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1396 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1397 reset_mask |= RADEON_RESET_GFX; 1398 } 1399 1400 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) | 1401 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp)) 1402 reset_mask |= RADEON_RESET_CP; 1403 1404 if (G_008010_GRBM_EE_BUSY(tmp)) 1405 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; 1406 1407 /* DMA_STATUS_REG */ 1408 tmp = RREG32(DMA_STATUS_REG); 1409 if (!(tmp & DMA_IDLE)) 1410 reset_mask |= RADEON_RESET_DMA; 1411 1412 /* SRBM_STATUS */ 1413 tmp = RREG32(R_000E50_SRBM_STATUS); 1414 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp)) 1415 reset_mask |= RADEON_RESET_RLC; 1416 1417 if (G_000E50_IH_BUSY(tmp)) 1418 reset_mask |= RADEON_RESET_IH; 1419 1420 if (G_000E50_SEM_BUSY(tmp)) 1421 reset_mask |= RADEON_RESET_SEM; 1422 1423 if (G_000E50_GRBM_RQ_PENDING(tmp)) 1424 reset_mask |= RADEON_RESET_GRBM; 1425 1426 if (G_000E50_VMC_BUSY(tmp)) 1427 reset_mask |= RADEON_RESET_VMC; 1428 1429 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) | 1430 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) | 1431 G_000E50_MCDW_BUSY(tmp)) 1432 reset_mask |= RADEON_RESET_MC; 1433 1434 if (r600_is_display_hung(rdev)) 1435 reset_mask |= RADEON_RESET_DISPLAY; 1436 1437 /* Skip MC reset as it's mostly likely not hung, just busy */ 1438 if (reset_mask & RADEON_RESET_MC) { 1439 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); 1440 reset_mask &= ~RADEON_RESET_MC; 1441 } 1442 1443 return reset_mask; 1444 } 1445 1446 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 1447 { 1448 struct rv515_mc_save save; 1449 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 1450 u32 tmp; 1451 1452 if (reset_mask == 0) 1453 return; 1454 1455 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1456 1457 r600_print_gpu_status_regs(rdev); 1458 1459 /* Disable CP parsing/prefetching */ 1460 if (rdev->family >= CHIP_RV770) 1461 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); 1462 else 1463 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1464 1465 /* disable the RLC */ 1466 WREG32(RLC_CNTL, 0); 1467 1468 if (reset_mask & RADEON_RESET_DMA) { 1469 /* Disable DMA */ 1470 tmp = RREG32(DMA_RB_CNTL); 1471 tmp &= ~DMA_RB_ENABLE; 1472 WREG32(DMA_RB_CNTL, tmp); 1473 } 1474 1475 mdelay(50); 1476 1477 rv515_mc_stop(rdev, &save); 1478 if (r600_mc_wait_for_idle(rdev)) { 1479 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1480 } 1481 1482 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { 1483 if (rdev->family >= CHIP_RV770) 1484 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) | 1485 S_008020_SOFT_RESET_CB(1) | 1486 S_008020_SOFT_RESET_PA(1) | 1487 S_008020_SOFT_RESET_SC(1) | 1488 S_008020_SOFT_RESET_SPI(1) | 1489 S_008020_SOFT_RESET_SX(1) | 1490 S_008020_SOFT_RESET_SH(1) | 1491 S_008020_SOFT_RESET_TC(1) | 1492 S_008020_SOFT_RESET_TA(1) | 1493 S_008020_SOFT_RESET_VC(1) | 1494 S_008020_SOFT_RESET_VGT(1); 1495 else 1496 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) | 1497 S_008020_SOFT_RESET_DB(1) | 1498 S_008020_SOFT_RESET_CB(1) | 1499 S_008020_SOFT_RESET_PA(1) | 1500 S_008020_SOFT_RESET_SC(1) | 1501 S_008020_SOFT_RESET_SMX(1) | 1502 S_008020_SOFT_RESET_SPI(1) | 1503 S_008020_SOFT_RESET_SX(1) | 1504 S_008020_SOFT_RESET_SH(1) | 1505 S_008020_SOFT_RESET_TC(1) | 1506 S_008020_SOFT_RESET_TA(1) | 1507 S_008020_SOFT_RESET_VC(1) | 1508 S_008020_SOFT_RESET_VGT(1); 1509 } 1510 1511 if (reset_mask & RADEON_RESET_CP) { 1512 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) | 1513 S_008020_SOFT_RESET_VGT(1); 1514 1515 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1516 } 1517 1518 if (reset_mask & RADEON_RESET_DMA) { 1519 if (rdev->family >= CHIP_RV770) 1520 srbm_soft_reset |= RV770_SOFT_RESET_DMA; 1521 else 1522 srbm_soft_reset |= SOFT_RESET_DMA; 1523 } 1524 1525 if (reset_mask & RADEON_RESET_RLC) 1526 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1); 1527 1528 if (reset_mask & RADEON_RESET_SEM) 1529 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1); 1530 1531 if (reset_mask & RADEON_RESET_IH) 1532 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1); 1533 1534 if (reset_mask & RADEON_RESET_GRBM) 1535 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1536 1537 if (!(rdev->flags & RADEON_IS_IGP)) { 1538 if (reset_mask & RADEON_RESET_MC) 1539 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1); 1540 } 1541 1542 if (reset_mask & RADEON_RESET_VMC) 1543 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1); 1544 1545 if (grbm_soft_reset) { 1546 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1547 tmp |= grbm_soft_reset; 1548 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 1549 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1550 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1551 1552 udelay(50); 1553 1554 tmp &= ~grbm_soft_reset; 1555 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1556 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1557 } 1558 1559 if (srbm_soft_reset) { 1560 tmp = RREG32(SRBM_SOFT_RESET); 1561 tmp |= srbm_soft_reset; 1562 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1563 WREG32(SRBM_SOFT_RESET, tmp); 1564 tmp = RREG32(SRBM_SOFT_RESET); 1565 1566 udelay(50); 1567 1568 tmp &= ~srbm_soft_reset; 1569 WREG32(SRBM_SOFT_RESET, tmp); 1570 tmp = RREG32(SRBM_SOFT_RESET); 1571 } 1572 1573 /* Wait a little for things to settle down */ 1574 mdelay(1); 1575 1576 rv515_mc_resume(rdev, &save); 1577 udelay(50); 1578 1579 r600_print_gpu_status_regs(rdev); 1580 } 1581 1582 int r600_asic_reset(struct radeon_device *rdev) 1583 { 1584 u32 reset_mask; 1585 1586 reset_mask = r600_gpu_check_soft_reset(rdev); 1587 1588 if (reset_mask) 1589 r600_set_bios_scratch_engine_hung(rdev, true); 1590 1591 r600_gpu_soft_reset(rdev, reset_mask); 1592 1593 reset_mask = r600_gpu_check_soft_reset(rdev); 1594 1595 if (!reset_mask) 1596 r600_set_bios_scratch_engine_hung(rdev, false); 1597 1598 return 0; 1599 } 1600 1601 /** 1602 * r600_gfx_is_lockup - Check if the GFX engine is locked up 1603 * 1604 * @rdev: radeon_device pointer 1605 * @ring: radeon_ring structure holding ring information 1606 * 1607 * Check if the GFX engine is locked up. 1608 * Returns true if the engine appears to be locked up, false if not. 1609 */ 1610 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1611 { 1612 u32 reset_mask = r600_gpu_check_soft_reset(rdev); 1613 1614 if (!(reset_mask & (RADEON_RESET_GFX | 1615 RADEON_RESET_COMPUTE | 1616 RADEON_RESET_CP))) { 1617 radeon_ring_lockup_update(ring); 1618 return false; 1619 } 1620 /* force CP activities */ 1621 radeon_ring_force_activity(rdev, ring); 1622 return radeon_ring_test_lockup(rdev, ring); 1623 } 1624 1625 /** 1626 * r600_dma_is_lockup - Check if the DMA engine is locked up 1627 * 1628 * @rdev: radeon_device pointer 1629 * @ring: radeon_ring structure holding ring information 1630 * 1631 * Check if the async DMA engine is locked up. 1632 * Returns true if the engine appears to be locked up, false if not. 1633 */ 1634 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1635 { 1636 u32 reset_mask = r600_gpu_check_soft_reset(rdev); 1637 1638 if (!(reset_mask & RADEON_RESET_DMA)) { 1639 radeon_ring_lockup_update(ring); 1640 return false; 1641 } 1642 /* force ring activities */ 1643 radeon_ring_force_activity(rdev, ring); 1644 return radeon_ring_test_lockup(rdev, ring); 1645 } 1646 1647 u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1648 u32 tiling_pipe_num, 1649 u32 max_rb_num, 1650 u32 total_max_rb_num, 1651 u32 disabled_rb_mask) 1652 { 1653 u32 rendering_pipe_num, rb_num_width, req_rb_num; 1654 u32 pipe_rb_ratio, pipe_rb_remain, tmp; 1655 u32 data = 0, mask = 1 << (max_rb_num - 1); 1656 unsigned i, j; 1657 1658 /* mask out the RBs that don't exist on that asic */ 1659 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff); 1660 /* make sure at least one RB is available */ 1661 if ((tmp & 0xff) != 0xff) 1662 disabled_rb_mask = tmp; 1663 1664 rendering_pipe_num = 1 << tiling_pipe_num; 1665 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); 1666 BUG_ON(rendering_pipe_num < req_rb_num); 1667 1668 pipe_rb_ratio = rendering_pipe_num / req_rb_num; 1669 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num; 1670 1671 if (rdev->family <= CHIP_RV740) { 1672 /* r6xx/r7xx */ 1673 rb_num_width = 2; 1674 } else { 1675 /* eg+ */ 1676 rb_num_width = 4; 1677 } 1678 1679 for (i = 0; i < max_rb_num; i++) { 1680 if (!(mask & disabled_rb_mask)) { 1681 for (j = 0; j < pipe_rb_ratio; j++) { 1682 data <<= rb_num_width; 1683 data |= max_rb_num - i - 1; 1684 } 1685 if (pipe_rb_remain) { 1686 data <<= rb_num_width; 1687 data |= max_rb_num - i - 1; 1688 pipe_rb_remain--; 1689 } 1690 } 1691 mask >>= 1; 1692 } 1693 1694 return data; 1695 } 1696 1697 int r600_count_pipe_bits(uint32_t val) 1698 { 1699 return hweight32(val); 1700 } 1701 1702 static void r600_gpu_init(struct radeon_device *rdev) 1703 { 1704 u32 tiling_config; 1705 u32 ramcfg; 1706 u32 cc_rb_backend_disable; 1707 u32 cc_gc_shader_pipe_config; 1708 u32 tmp; 1709 int i, j; 1710 u32 sq_config; 1711 u32 sq_gpr_resource_mgmt_1 = 0; 1712 u32 sq_gpr_resource_mgmt_2 = 0; 1713 u32 sq_thread_resource_mgmt = 0; 1714 u32 sq_stack_resource_mgmt_1 = 0; 1715 u32 sq_stack_resource_mgmt_2 = 0; 1716 u32 disabled_rb_mask; 1717 1718 rdev->config.r600.tiling_group_size = 256; 1719 switch (rdev->family) { 1720 case CHIP_R600: 1721 rdev->config.r600.max_pipes = 4; 1722 rdev->config.r600.max_tile_pipes = 8; 1723 rdev->config.r600.max_simds = 4; 1724 rdev->config.r600.max_backends = 4; 1725 rdev->config.r600.max_gprs = 256; 1726 rdev->config.r600.max_threads = 192; 1727 rdev->config.r600.max_stack_entries = 256; 1728 rdev->config.r600.max_hw_contexts = 8; 1729 rdev->config.r600.max_gs_threads = 16; 1730 rdev->config.r600.sx_max_export_size = 128; 1731 rdev->config.r600.sx_max_export_pos_size = 16; 1732 rdev->config.r600.sx_max_export_smx_size = 128; 1733 rdev->config.r600.sq_num_cf_insts = 2; 1734 break; 1735 case CHIP_RV630: 1736 case CHIP_RV635: 1737 rdev->config.r600.max_pipes = 2; 1738 rdev->config.r600.max_tile_pipes = 2; 1739 rdev->config.r600.max_simds = 3; 1740 rdev->config.r600.max_backends = 1; 1741 rdev->config.r600.max_gprs = 128; 1742 rdev->config.r600.max_threads = 192; 1743 rdev->config.r600.max_stack_entries = 128; 1744 rdev->config.r600.max_hw_contexts = 8; 1745 rdev->config.r600.max_gs_threads = 4; 1746 rdev->config.r600.sx_max_export_size = 128; 1747 rdev->config.r600.sx_max_export_pos_size = 16; 1748 rdev->config.r600.sx_max_export_smx_size = 128; 1749 rdev->config.r600.sq_num_cf_insts = 2; 1750 break; 1751 case CHIP_RV610: 1752 case CHIP_RV620: 1753 case CHIP_RS780: 1754 case CHIP_RS880: 1755 rdev->config.r600.max_pipes = 1; 1756 rdev->config.r600.max_tile_pipes = 1; 1757 rdev->config.r600.max_simds = 2; 1758 rdev->config.r600.max_backends = 1; 1759 rdev->config.r600.max_gprs = 128; 1760 rdev->config.r600.max_threads = 192; 1761 rdev->config.r600.max_stack_entries = 128; 1762 rdev->config.r600.max_hw_contexts = 4; 1763 rdev->config.r600.max_gs_threads = 4; 1764 rdev->config.r600.sx_max_export_size = 128; 1765 rdev->config.r600.sx_max_export_pos_size = 16; 1766 rdev->config.r600.sx_max_export_smx_size = 128; 1767 rdev->config.r600.sq_num_cf_insts = 1; 1768 break; 1769 case CHIP_RV670: 1770 rdev->config.r600.max_pipes = 4; 1771 rdev->config.r600.max_tile_pipes = 4; 1772 rdev->config.r600.max_simds = 4; 1773 rdev->config.r600.max_backends = 4; 1774 rdev->config.r600.max_gprs = 192; 1775 rdev->config.r600.max_threads = 192; 1776 rdev->config.r600.max_stack_entries = 256; 1777 rdev->config.r600.max_hw_contexts = 8; 1778 rdev->config.r600.max_gs_threads = 16; 1779 rdev->config.r600.sx_max_export_size = 128; 1780 rdev->config.r600.sx_max_export_pos_size = 16; 1781 rdev->config.r600.sx_max_export_smx_size = 128; 1782 rdev->config.r600.sq_num_cf_insts = 2; 1783 break; 1784 default: 1785 break; 1786 } 1787 1788 /* Initialize HDP */ 1789 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1790 WREG32((0x2c14 + j), 0x00000000); 1791 WREG32((0x2c18 + j), 0x00000000); 1792 WREG32((0x2c1c + j), 0x00000000); 1793 WREG32((0x2c20 + j), 0x00000000); 1794 WREG32((0x2c24 + j), 0x00000000); 1795 } 1796 1797 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1798 1799 /* Setup tiling */ 1800 tiling_config = 0; 1801 ramcfg = RREG32(RAMCFG); 1802 switch (rdev->config.r600.max_tile_pipes) { 1803 case 1: 1804 tiling_config |= PIPE_TILING(0); 1805 break; 1806 case 2: 1807 tiling_config |= PIPE_TILING(1); 1808 break; 1809 case 4: 1810 tiling_config |= PIPE_TILING(2); 1811 break; 1812 case 8: 1813 tiling_config |= PIPE_TILING(3); 1814 break; 1815 default: 1816 break; 1817 } 1818 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; 1819 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1820 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1821 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 1822 1823 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 1824 if (tmp > 3) { 1825 tiling_config |= ROW_TILING(3); 1826 tiling_config |= SAMPLE_SPLIT(3); 1827 } else { 1828 tiling_config |= ROW_TILING(tmp); 1829 tiling_config |= SAMPLE_SPLIT(tmp); 1830 } 1831 tiling_config |= BANK_SWAPS(1); 1832 1833 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; 1834 tmp = R6XX_MAX_BACKENDS - 1835 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK); 1836 if (tmp < rdev->config.r600.max_backends) { 1837 rdev->config.r600.max_backends = tmp; 1838 } 1839 1840 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; 1841 tmp = R6XX_MAX_PIPES - 1842 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK); 1843 if (tmp < rdev->config.r600.max_pipes) { 1844 rdev->config.r600.max_pipes = tmp; 1845 } 1846 tmp = R6XX_MAX_SIMDS - 1847 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); 1848 if (tmp < rdev->config.r600.max_simds) { 1849 rdev->config.r600.max_simds = tmp; 1850 } 1851 1852 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; 1853 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; 1854 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, 1855 R6XX_MAX_BACKENDS, disabled_rb_mask); 1856 tiling_config |= tmp << 16; 1857 rdev->config.r600.backend_map = tmp; 1858 1859 rdev->config.r600.tile_config = tiling_config; 1860 WREG32(GB_TILING_CONFIG, tiling_config); 1861 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); 1862 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); 1863 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff); 1864 1865 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 1866 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); 1867 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); 1868 1869 /* Setup some CP states */ 1870 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); 1871 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); 1872 1873 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | 1874 SYNC_WALKER | SYNC_ALIGNER)); 1875 /* Setup various GPU states */ 1876 if (rdev->family == CHIP_RV670) 1877 WREG32(ARB_GDEC_RD_CNTL, 0x00000021); 1878 1879 tmp = RREG32(SX_DEBUG_1); 1880 tmp |= SMX_EVENT_RELEASE; 1881 if ((rdev->family > CHIP_R600)) 1882 tmp |= ENABLE_NEW_SMX_ADDRESS; 1883 WREG32(SX_DEBUG_1, tmp); 1884 1885 if (((rdev->family) == CHIP_R600) || 1886 ((rdev->family) == CHIP_RV630) || 1887 ((rdev->family) == CHIP_RV610) || 1888 ((rdev->family) == CHIP_RV620) || 1889 ((rdev->family) == CHIP_RS780) || 1890 ((rdev->family) == CHIP_RS880)) { 1891 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); 1892 } else { 1893 WREG32(DB_DEBUG, 0); 1894 } 1895 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | 1896 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); 1897 1898 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1899 WREG32(VGT_NUM_INSTANCES, 0); 1900 1901 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 1902 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); 1903 1904 tmp = RREG32(SQ_MS_FIFO_SIZES); 1905 if (((rdev->family) == CHIP_RV610) || 1906 ((rdev->family) == CHIP_RV620) || 1907 ((rdev->family) == CHIP_RS780) || 1908 ((rdev->family) == CHIP_RS880)) { 1909 tmp = (CACHE_FIFO_SIZE(0xa) | 1910 FETCH_FIFO_HIWATER(0xa) | 1911 DONE_FIFO_HIWATER(0xe0) | 1912 ALU_UPDATE_FIFO_HIWATER(0x8)); 1913 } else if (((rdev->family) == CHIP_R600) || 1914 ((rdev->family) == CHIP_RV630)) { 1915 tmp &= ~DONE_FIFO_HIWATER(0xff); 1916 tmp |= DONE_FIFO_HIWATER(0x4); 1917 } 1918 WREG32(SQ_MS_FIFO_SIZES, tmp); 1919 1920 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1921 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1922 */ 1923 sq_config = RREG32(SQ_CONFIG); 1924 sq_config &= ~(PS_PRIO(3) | 1925 VS_PRIO(3) | 1926 GS_PRIO(3) | 1927 ES_PRIO(3)); 1928 sq_config |= (DX9_CONSTS | 1929 VC_ENABLE | 1930 PS_PRIO(0) | 1931 VS_PRIO(1) | 1932 GS_PRIO(2) | 1933 ES_PRIO(3)); 1934 1935 if ((rdev->family) == CHIP_R600) { 1936 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | 1937 NUM_VS_GPRS(124) | 1938 NUM_CLAUSE_TEMP_GPRS(4)); 1939 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | 1940 NUM_ES_GPRS(0)); 1941 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | 1942 NUM_VS_THREADS(48) | 1943 NUM_GS_THREADS(4) | 1944 NUM_ES_THREADS(4)); 1945 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | 1946 NUM_VS_STACK_ENTRIES(128)); 1947 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | 1948 NUM_ES_STACK_ENTRIES(0)); 1949 } else if (((rdev->family) == CHIP_RV610) || 1950 ((rdev->family) == CHIP_RV620) || 1951 ((rdev->family) == CHIP_RS780) || 1952 ((rdev->family) == CHIP_RS880)) { 1953 /* no vertex cache */ 1954 sq_config &= ~VC_ENABLE; 1955 1956 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1957 NUM_VS_GPRS(44) | 1958 NUM_CLAUSE_TEMP_GPRS(2)); 1959 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 1960 NUM_ES_GPRS(17)); 1961 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1962 NUM_VS_THREADS(78) | 1963 NUM_GS_THREADS(4) | 1964 NUM_ES_THREADS(31)); 1965 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 1966 NUM_VS_STACK_ENTRIES(40)); 1967 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 1968 NUM_ES_STACK_ENTRIES(16)); 1969 } else if (((rdev->family) == CHIP_RV630) || 1970 ((rdev->family) == CHIP_RV635)) { 1971 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1972 NUM_VS_GPRS(44) | 1973 NUM_CLAUSE_TEMP_GPRS(2)); 1974 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | 1975 NUM_ES_GPRS(18)); 1976 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1977 NUM_VS_THREADS(78) | 1978 NUM_GS_THREADS(4) | 1979 NUM_ES_THREADS(31)); 1980 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 1981 NUM_VS_STACK_ENTRIES(40)); 1982 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 1983 NUM_ES_STACK_ENTRIES(16)); 1984 } else if ((rdev->family) == CHIP_RV670) { 1985 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1986 NUM_VS_GPRS(44) | 1987 NUM_CLAUSE_TEMP_GPRS(2)); 1988 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 1989 NUM_ES_GPRS(17)); 1990 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1991 NUM_VS_THREADS(78) | 1992 NUM_GS_THREADS(4) | 1993 NUM_ES_THREADS(31)); 1994 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | 1995 NUM_VS_STACK_ENTRIES(64)); 1996 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | 1997 NUM_ES_STACK_ENTRIES(64)); 1998 } 1999 2000 WREG32(SQ_CONFIG, sq_config); 2001 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 2002 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 2003 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 2004 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 2005 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 2006 2007 if (((rdev->family) == CHIP_RV610) || 2008 ((rdev->family) == CHIP_RV620) || 2009 ((rdev->family) == CHIP_RS780) || 2010 ((rdev->family) == CHIP_RS880)) { 2011 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); 2012 } else { 2013 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); 2014 } 2015 2016 /* More default values. 2D/3D driver should adjust as needed */ 2017 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | 2018 S1_X(0x4) | S1_Y(0xc))); 2019 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | 2020 S1_X(0x2) | S1_Y(0x2) | 2021 S2_X(0xa) | S2_Y(0x6) | 2022 S3_X(0x6) | S3_Y(0xa))); 2023 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | 2024 S1_X(0x4) | S1_Y(0xc) | 2025 S2_X(0x1) | S2_Y(0x6) | 2026 S3_X(0xa) | S3_Y(0xe))); 2027 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | 2028 S5_X(0x0) | S5_Y(0x0) | 2029 S6_X(0xb) | S6_Y(0x4) | 2030 S7_X(0x7) | S7_Y(0x8))); 2031 2032 WREG32(VGT_STRMOUT_EN, 0); 2033 tmp = rdev->config.r600.max_pipes * 16; 2034 switch (rdev->family) { 2035 case CHIP_RV610: 2036 case CHIP_RV620: 2037 case CHIP_RS780: 2038 case CHIP_RS880: 2039 tmp += 32; 2040 break; 2041 case CHIP_RV670: 2042 tmp += 128; 2043 break; 2044 default: 2045 break; 2046 } 2047 if (tmp > 256) { 2048 tmp = 256; 2049 } 2050 WREG32(VGT_ES_PER_GS, 128); 2051 WREG32(VGT_GS_PER_ES, tmp); 2052 WREG32(VGT_GS_PER_VS, 2); 2053 WREG32(VGT_GS_VERTEX_REUSE, 16); 2054 2055 /* more default values. 2D/3D driver should adjust as needed */ 2056 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 2057 WREG32(VGT_STRMOUT_EN, 0); 2058 WREG32(SX_MISC, 0); 2059 WREG32(PA_SC_MODE_CNTL, 0); 2060 WREG32(PA_SC_AA_CONFIG, 0); 2061 WREG32(PA_SC_LINE_STIPPLE, 0); 2062 WREG32(SPI_INPUT_Z, 0); 2063 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 2064 WREG32(CB_COLOR7_FRAG, 0); 2065 2066 /* Clear render buffer base addresses */ 2067 WREG32(CB_COLOR0_BASE, 0); 2068 WREG32(CB_COLOR1_BASE, 0); 2069 WREG32(CB_COLOR2_BASE, 0); 2070 WREG32(CB_COLOR3_BASE, 0); 2071 WREG32(CB_COLOR4_BASE, 0); 2072 WREG32(CB_COLOR5_BASE, 0); 2073 WREG32(CB_COLOR6_BASE, 0); 2074 WREG32(CB_COLOR7_BASE, 0); 2075 WREG32(CB_COLOR7_FRAG, 0); 2076 2077 switch (rdev->family) { 2078 case CHIP_RV610: 2079 case CHIP_RV620: 2080 case CHIP_RS780: 2081 case CHIP_RS880: 2082 tmp = TC_L2_SIZE(8); 2083 break; 2084 case CHIP_RV630: 2085 case CHIP_RV635: 2086 tmp = TC_L2_SIZE(4); 2087 break; 2088 case CHIP_R600: 2089 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; 2090 break; 2091 default: 2092 tmp = TC_L2_SIZE(0); 2093 break; 2094 } 2095 WREG32(TC_CNTL, tmp); 2096 2097 tmp = RREG32(HDP_HOST_PATH_CNTL); 2098 WREG32(HDP_HOST_PATH_CNTL, tmp); 2099 2100 tmp = RREG32(ARB_POP); 2101 tmp |= ENABLE_TC128; 2102 WREG32(ARB_POP, tmp); 2103 2104 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 2105 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 2106 NUM_CLIP_SEQ(3))); 2107 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); 2108 WREG32(VC_ENHANCE, 0); 2109 } 2110 2111 2112 /* 2113 * Indirect registers accessor 2114 */ 2115 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) 2116 { 2117 u32 r; 2118 2119 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2120 (void)RREG32(PCIE_PORT_INDEX); 2121 r = RREG32(PCIE_PORT_DATA); 2122 return r; 2123 } 2124 2125 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2126 { 2127 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2128 (void)RREG32(PCIE_PORT_INDEX); 2129 WREG32(PCIE_PORT_DATA, (v)); 2130 (void)RREG32(PCIE_PORT_DATA); 2131 } 2132 2133 /* 2134 * CP & Ring 2135 */ 2136 void r600_cp_stop(struct radeon_device *rdev) 2137 { 2138 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2139 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 2140 WREG32(SCRATCH_UMSK, 0); 2141 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 2142 } 2143 2144 int r600_init_microcode(struct radeon_device *rdev) 2145 { 2146 const char *chip_name; 2147 const char *rlc_chip_name; 2148 const char *smc_chip_name = "RV770"; 2149 size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0; 2150 char fw_name[30]; 2151 int err; 2152 2153 DRM_DEBUG("\n"); 2154 2155 switch (rdev->family) { 2156 case CHIP_R600: 2157 chip_name = "R600"; 2158 rlc_chip_name = "R600"; 2159 break; 2160 case CHIP_RV610: 2161 chip_name = "RV610"; 2162 rlc_chip_name = "R600"; 2163 break; 2164 case CHIP_RV630: 2165 chip_name = "RV630"; 2166 rlc_chip_name = "R600"; 2167 break; 2168 case CHIP_RV620: 2169 chip_name = "RV620"; 2170 rlc_chip_name = "R600"; 2171 break; 2172 case CHIP_RV635: 2173 chip_name = "RV635"; 2174 rlc_chip_name = "R600"; 2175 break; 2176 case CHIP_RV670: 2177 chip_name = "RV670"; 2178 rlc_chip_name = "R600"; 2179 break; 2180 case CHIP_RS780: 2181 case CHIP_RS880: 2182 chip_name = "RS780"; 2183 rlc_chip_name = "R600"; 2184 break; 2185 case CHIP_RV770: 2186 chip_name = "RV770"; 2187 rlc_chip_name = "R700"; 2188 smc_chip_name = "RV770"; 2189 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4); 2190 break; 2191 case CHIP_RV730: 2192 chip_name = "RV730"; 2193 rlc_chip_name = "R700"; 2194 smc_chip_name = "RV730"; 2195 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4); 2196 break; 2197 case CHIP_RV710: 2198 chip_name = "RV710"; 2199 rlc_chip_name = "R700"; 2200 smc_chip_name = "RV710"; 2201 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4); 2202 break; 2203 case CHIP_RV740: 2204 chip_name = "RV730"; 2205 rlc_chip_name = "R700"; 2206 smc_chip_name = "RV740"; 2207 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4); 2208 break; 2209 case CHIP_CEDAR: 2210 chip_name = "CEDAR"; 2211 rlc_chip_name = "CEDAR"; 2212 smc_chip_name = "CEDAR"; 2213 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4); 2214 break; 2215 case CHIP_REDWOOD: 2216 chip_name = "REDWOOD"; 2217 rlc_chip_name = "REDWOOD"; 2218 smc_chip_name = "REDWOOD"; 2219 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4); 2220 break; 2221 case CHIP_JUNIPER: 2222 chip_name = "JUNIPER"; 2223 rlc_chip_name = "JUNIPER"; 2224 smc_chip_name = "JUNIPER"; 2225 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4); 2226 break; 2227 case CHIP_CYPRESS: 2228 case CHIP_HEMLOCK: 2229 chip_name = "CYPRESS"; 2230 rlc_chip_name = "CYPRESS"; 2231 smc_chip_name = "CYPRESS"; 2232 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4); 2233 break; 2234 case CHIP_PALM: 2235 chip_name = "PALM"; 2236 rlc_chip_name = "SUMO"; 2237 break; 2238 case CHIP_SUMO: 2239 chip_name = "SUMO"; 2240 rlc_chip_name = "SUMO"; 2241 break; 2242 case CHIP_SUMO2: 2243 chip_name = "SUMO2"; 2244 rlc_chip_name = "SUMO"; 2245 break; 2246 default: BUG(); 2247 } 2248 2249 if (rdev->family >= CHIP_CEDAR) { 2250 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 2251 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 2252 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 2253 } else if (rdev->family >= CHIP_RV770) { 2254 pfp_req_size = R700_PFP_UCODE_SIZE * 4; 2255 me_req_size = R700_PM4_UCODE_SIZE * 4; 2256 rlc_req_size = R700_RLC_UCODE_SIZE * 4; 2257 } else { 2258 pfp_req_size = R600_PFP_UCODE_SIZE * 4; 2259 me_req_size = R600_PM4_UCODE_SIZE * 12; 2260 rlc_req_size = R600_RLC_UCODE_SIZE * 4; 2261 } 2262 2263 DRM_INFO("Loading %s Microcode\n", chip_name); 2264 2265 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 2266 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); 2267 if (err) 2268 goto out; 2269 if (rdev->pfp_fw->size != pfp_req_size) { 2270 printk(KERN_ERR 2271 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2272 rdev->pfp_fw->size, fw_name); 2273 err = -EINVAL; 2274 goto out; 2275 } 2276 2277 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 2278 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 2279 if (err) 2280 goto out; 2281 if (rdev->me_fw->size != me_req_size) { 2282 printk(KERN_ERR 2283 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2284 rdev->me_fw->size, fw_name); 2285 err = -EINVAL; 2286 } 2287 2288 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); 2289 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); 2290 if (err) 2291 goto out; 2292 if (rdev->rlc_fw->size != rlc_req_size) { 2293 printk(KERN_ERR 2294 "r600_rlc: Bogus length %zu in firmware \"%s\"\n", 2295 rdev->rlc_fw->size, fw_name); 2296 err = -EINVAL; 2297 } 2298 2299 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) { 2300 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", smc_chip_name); 2301 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); 2302 if (err) 2303 goto out; 2304 if (rdev->smc_fw->size != smc_req_size) { 2305 printk(KERN_ERR 2306 "smc: Bogus length %zu in firmware \"%s\"\n", 2307 rdev->smc_fw->size, fw_name); 2308 err = -EINVAL; 2309 } 2310 } 2311 2312 out: 2313 if (err) { 2314 if (err != -EINVAL) 2315 printk(KERN_ERR 2316 "r600_cp: Failed to load firmware \"%s\"\n", 2317 fw_name); 2318 release_firmware(rdev->pfp_fw); 2319 rdev->pfp_fw = NULL; 2320 release_firmware(rdev->me_fw); 2321 rdev->me_fw = NULL; 2322 release_firmware(rdev->rlc_fw); 2323 rdev->rlc_fw = NULL; 2324 release_firmware(rdev->smc_fw); 2325 rdev->smc_fw = NULL; 2326 } 2327 return err; 2328 } 2329 2330 static int r600_cp_load_microcode(struct radeon_device *rdev) 2331 { 2332 const __be32 *fw_data; 2333 int i; 2334 2335 if (!rdev->me_fw || !rdev->pfp_fw) 2336 return -EINVAL; 2337 2338 r600_cp_stop(rdev); 2339 2340 WREG32(CP_RB_CNTL, 2341 #ifdef __BIG_ENDIAN 2342 BUF_SWAP_32BIT | 2343 #endif 2344 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 2345 2346 /* Reset cp */ 2347 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2348 RREG32(GRBM_SOFT_RESET); 2349 mdelay(15); 2350 WREG32(GRBM_SOFT_RESET, 0); 2351 2352 WREG32(CP_ME_RAM_WADDR, 0); 2353 2354 fw_data = (const __be32 *)rdev->me_fw->data; 2355 WREG32(CP_ME_RAM_WADDR, 0); 2356 for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++) 2357 WREG32(CP_ME_RAM_DATA, 2358 be32_to_cpup(fw_data++)); 2359 2360 fw_data = (const __be32 *)rdev->pfp_fw->data; 2361 WREG32(CP_PFP_UCODE_ADDR, 0); 2362 for (i = 0; i < R600_PFP_UCODE_SIZE; i++) 2363 WREG32(CP_PFP_UCODE_DATA, 2364 be32_to_cpup(fw_data++)); 2365 2366 WREG32(CP_PFP_UCODE_ADDR, 0); 2367 WREG32(CP_ME_RAM_WADDR, 0); 2368 WREG32(CP_ME_RAM_RADDR, 0); 2369 return 0; 2370 } 2371 2372 int r600_cp_start(struct radeon_device *rdev) 2373 { 2374 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2375 int r; 2376 uint32_t cp_me; 2377 2378 r = radeon_ring_lock(rdev, ring, 7); 2379 if (r) { 2380 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 2381 return r; 2382 } 2383 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2384 radeon_ring_write(ring, 0x1); 2385 if (rdev->family >= CHIP_RV770) { 2386 radeon_ring_write(ring, 0x0); 2387 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); 2388 } else { 2389 radeon_ring_write(ring, 0x3); 2390 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); 2391 } 2392 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2393 radeon_ring_write(ring, 0); 2394 radeon_ring_write(ring, 0); 2395 radeon_ring_unlock_commit(rdev, ring); 2396 2397 cp_me = 0xff; 2398 WREG32(R_0086D8_CP_ME_CNTL, cp_me); 2399 return 0; 2400 } 2401 2402 int r600_cp_resume(struct radeon_device *rdev) 2403 { 2404 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2405 u32 tmp; 2406 u32 rb_bufsz; 2407 int r; 2408 2409 /* Reset cp */ 2410 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2411 RREG32(GRBM_SOFT_RESET); 2412 mdelay(15); 2413 WREG32(GRBM_SOFT_RESET, 0); 2414 2415 /* Set ring buffer size */ 2416 rb_bufsz = drm_order(ring->ring_size / 8); 2417 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2418 #ifdef __BIG_ENDIAN 2419 tmp |= BUF_SWAP_32BIT; 2420 #endif 2421 WREG32(CP_RB_CNTL, tmp); 2422 WREG32(CP_SEM_WAIT_TIMER, 0x0); 2423 2424 /* Set the write pointer delay */ 2425 WREG32(CP_RB_WPTR_DELAY, 0); 2426 2427 /* Initialize the ring buffer's read and write pointers */ 2428 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 2429 WREG32(CP_RB_RPTR_WR, 0); 2430 ring->wptr = 0; 2431 WREG32(CP_RB_WPTR, ring->wptr); 2432 2433 /* set the wb address whether it's enabled or not */ 2434 WREG32(CP_RB_RPTR_ADDR, 2435 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); 2436 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 2437 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 2438 2439 if (rdev->wb.enabled) 2440 WREG32(SCRATCH_UMSK, 0xff); 2441 else { 2442 tmp |= RB_NO_UPDATE; 2443 WREG32(SCRATCH_UMSK, 0); 2444 } 2445 2446 mdelay(1); 2447 WREG32(CP_RB_CNTL, tmp); 2448 2449 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); 2450 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 2451 2452 ring->rptr = RREG32(CP_RB_RPTR); 2453 2454 r600_cp_start(rdev); 2455 ring->ready = true; 2456 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 2457 if (r) { 2458 ring->ready = false; 2459 return r; 2460 } 2461 return 0; 2462 } 2463 2464 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) 2465 { 2466 u32 rb_bufsz; 2467 int r; 2468 2469 /* Align ring size */ 2470 rb_bufsz = drm_order(ring_size / 8); 2471 ring_size = (1 << (rb_bufsz + 1)) * 4; 2472 ring->ring_size = ring_size; 2473 ring->align_mask = 16 - 1; 2474 2475 if (radeon_ring_supports_scratch_reg(rdev, ring)) { 2476 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 2477 if (r) { 2478 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 2479 ring->rptr_save_reg = 0; 2480 } 2481 } 2482 } 2483 2484 void r600_cp_fini(struct radeon_device *rdev) 2485 { 2486 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2487 r600_cp_stop(rdev); 2488 radeon_ring_fini(rdev, ring); 2489 radeon_scratch_free(rdev, ring->rptr_save_reg); 2490 } 2491 2492 /* 2493 * DMA 2494 * Starting with R600, the GPU has an asynchronous 2495 * DMA engine. The programming model is very similar 2496 * to the 3D engine (ring buffer, IBs, etc.), but the 2497 * DMA controller has it's own packet format that is 2498 * different form the PM4 format used by the 3D engine. 2499 * It supports copying data, writing embedded data, 2500 * solid fills, and a number of other things. It also 2501 * has support for tiling/detiling of buffers. 2502 */ 2503 /** 2504 * r600_dma_stop - stop the async dma engine 2505 * 2506 * @rdev: radeon_device pointer 2507 * 2508 * Stop the async dma engine (r6xx-evergreen). 2509 */ 2510 void r600_dma_stop(struct radeon_device *rdev) 2511 { 2512 u32 rb_cntl = RREG32(DMA_RB_CNTL); 2513 2514 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2515 2516 rb_cntl &= ~DMA_RB_ENABLE; 2517 WREG32(DMA_RB_CNTL, rb_cntl); 2518 2519 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false; 2520 } 2521 2522 /** 2523 * r600_dma_resume - setup and start the async dma engine 2524 * 2525 * @rdev: radeon_device pointer 2526 * 2527 * Set up the DMA ring buffer and enable it. (r6xx-evergreen). 2528 * Returns 0 for success, error for failure. 2529 */ 2530 int r600_dma_resume(struct radeon_device *rdev) 2531 { 2532 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 2533 u32 rb_cntl, dma_cntl, ib_cntl; 2534 u32 rb_bufsz; 2535 int r; 2536 2537 /* Reset dma */ 2538 if (rdev->family >= CHIP_RV770) 2539 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA); 2540 else 2541 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA); 2542 RREG32(SRBM_SOFT_RESET); 2543 udelay(50); 2544 WREG32(SRBM_SOFT_RESET, 0); 2545 2546 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0); 2547 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); 2548 2549 /* Set ring buffer size in dwords */ 2550 rb_bufsz = drm_order(ring->ring_size / 4); 2551 rb_cntl = rb_bufsz << 1; 2552 #ifdef __BIG_ENDIAN 2553 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; 2554 #endif 2555 WREG32(DMA_RB_CNTL, rb_cntl); 2556 2557 /* Initialize the ring buffer's read and write pointers */ 2558 WREG32(DMA_RB_RPTR, 0); 2559 WREG32(DMA_RB_WPTR, 0); 2560 2561 /* set the wb address whether it's enabled or not */ 2562 WREG32(DMA_RB_RPTR_ADDR_HI, 2563 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); 2564 WREG32(DMA_RB_RPTR_ADDR_LO, 2565 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC)); 2566 2567 if (rdev->wb.enabled) 2568 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; 2569 2570 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); 2571 2572 /* enable DMA IBs */ 2573 ib_cntl = DMA_IB_ENABLE; 2574 #ifdef __BIG_ENDIAN 2575 ib_cntl |= DMA_IB_SWAP_ENABLE; 2576 #endif 2577 WREG32(DMA_IB_CNTL, ib_cntl); 2578 2579 dma_cntl = RREG32(DMA_CNTL); 2580 dma_cntl &= ~CTXEMPTY_INT_ENABLE; 2581 WREG32(DMA_CNTL, dma_cntl); 2582 2583 if (rdev->family >= CHIP_RV770) 2584 WREG32(DMA_MODE, 1); 2585 2586 ring->wptr = 0; 2587 WREG32(DMA_RB_WPTR, ring->wptr << 2); 2588 2589 ring->rptr = RREG32(DMA_RB_RPTR) >> 2; 2590 2591 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); 2592 2593 ring->ready = true; 2594 2595 r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring); 2596 if (r) { 2597 ring->ready = false; 2598 return r; 2599 } 2600 2601 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 2602 2603 return 0; 2604 } 2605 2606 /** 2607 * r600_dma_fini - tear down the async dma engine 2608 * 2609 * @rdev: radeon_device pointer 2610 * 2611 * Stop the async dma engine and free the ring (r6xx-evergreen). 2612 */ 2613 void r600_dma_fini(struct radeon_device *rdev) 2614 { 2615 r600_dma_stop(rdev); 2616 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); 2617 } 2618 2619 /* 2620 * UVD 2621 */ 2622 int r600_uvd_rbc_start(struct radeon_device *rdev) 2623 { 2624 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 2625 uint64_t rptr_addr; 2626 uint32_t rb_bufsz, tmp; 2627 int r; 2628 2629 rptr_addr = rdev->wb.gpu_addr + R600_WB_UVD_RPTR_OFFSET; 2630 2631 if (upper_32_bits(rptr_addr) != upper_32_bits(ring->gpu_addr)) { 2632 DRM_ERROR("UVD ring and rptr not in the same 4GB segment!\n"); 2633 return -EINVAL; 2634 } 2635 2636 /* force RBC into idle state */ 2637 WREG32(UVD_RBC_RB_CNTL, 0x11010101); 2638 2639 /* Set the write pointer delay */ 2640 WREG32(UVD_RBC_RB_WPTR_CNTL, 0); 2641 2642 /* set the wb address */ 2643 WREG32(UVD_RBC_RB_RPTR_ADDR, rptr_addr >> 2); 2644 2645 /* programm the 4GB memory segment for rptr and ring buffer */ 2646 WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(rptr_addr) | 2647 (0x7 << 16) | (0x1 << 31)); 2648 2649 /* Initialize the ring buffer's read and write pointers */ 2650 WREG32(UVD_RBC_RB_RPTR, 0x0); 2651 2652 ring->wptr = ring->rptr = RREG32(UVD_RBC_RB_RPTR); 2653 WREG32(UVD_RBC_RB_WPTR, ring->wptr); 2654 2655 /* set the ring address */ 2656 WREG32(UVD_RBC_RB_BASE, ring->gpu_addr); 2657 2658 /* Set ring buffer size */ 2659 rb_bufsz = drm_order(ring->ring_size); 2660 rb_bufsz = (0x1 << 8) | rb_bufsz; 2661 WREG32(UVD_RBC_RB_CNTL, rb_bufsz); 2662 2663 ring->ready = true; 2664 r = radeon_ring_test(rdev, R600_RING_TYPE_UVD_INDEX, ring); 2665 if (r) { 2666 ring->ready = false; 2667 return r; 2668 } 2669 2670 r = radeon_ring_lock(rdev, ring, 10); 2671 if (r) { 2672 DRM_ERROR("radeon: ring failed to lock UVD ring (%d).\n", r); 2673 return r; 2674 } 2675 2676 tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 2677 radeon_ring_write(ring, tmp); 2678 radeon_ring_write(ring, 0xFFFFF); 2679 2680 tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 2681 radeon_ring_write(ring, tmp); 2682 radeon_ring_write(ring, 0xFFFFF); 2683 2684 tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 2685 radeon_ring_write(ring, tmp); 2686 radeon_ring_write(ring, 0xFFFFF); 2687 2688 /* Clear timeout status bits */ 2689 radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0)); 2690 radeon_ring_write(ring, 0x8); 2691 2692 radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0)); 2693 radeon_ring_write(ring, 3); 2694 2695 radeon_ring_unlock_commit(rdev, ring); 2696 2697 return 0; 2698 } 2699 2700 void r600_uvd_rbc_stop(struct radeon_device *rdev) 2701 { 2702 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 2703 2704 /* force RBC into idle state */ 2705 WREG32(UVD_RBC_RB_CNTL, 0x11010101); 2706 ring->ready = false; 2707 } 2708 2709 int r600_uvd_init(struct radeon_device *rdev) 2710 { 2711 int i, j, r; 2712 /* disable byte swapping */ 2713 u32 lmi_swap_cntl = 0; 2714 u32 mp_swap_cntl = 0; 2715 2716 /* raise clocks while booting up the VCPU */ 2717 radeon_set_uvd_clocks(rdev, 53300, 40000); 2718 2719 /* disable clock gating */ 2720 WREG32(UVD_CGC_GATE, 0); 2721 2722 /* disable interupt */ 2723 WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1)); 2724 2725 /* put LMI, VCPU, RBC etc... into reset */ 2726 WREG32(UVD_SOFT_RESET, LMI_SOFT_RESET | VCPU_SOFT_RESET | 2727 LBSI_SOFT_RESET | RBC_SOFT_RESET | CSM_SOFT_RESET | 2728 CXW_SOFT_RESET | TAP_SOFT_RESET | LMI_UMC_SOFT_RESET); 2729 mdelay(5); 2730 2731 /* take UVD block out of reset */ 2732 WREG32_P(SRBM_SOFT_RESET, 0, ~SOFT_RESET_UVD); 2733 mdelay(5); 2734 2735 /* initialize UVD memory controller */ 2736 WREG32(UVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 2737 (1 << 21) | (1 << 9) | (1 << 20)); 2738 2739 #ifdef __BIG_ENDIAN 2740 /* swap (8 in 32) RB and IB */ 2741 lmi_swap_cntl = 0xa; 2742 mp_swap_cntl = 0; 2743 #endif 2744 WREG32(UVD_LMI_SWAP_CNTL, lmi_swap_cntl); 2745 WREG32(UVD_MP_SWAP_CNTL, mp_swap_cntl); 2746 2747 WREG32(UVD_MPC_SET_MUXA0, 0x40c2040); 2748 WREG32(UVD_MPC_SET_MUXA1, 0x0); 2749 WREG32(UVD_MPC_SET_MUXB0, 0x40c2040); 2750 WREG32(UVD_MPC_SET_MUXB1, 0x0); 2751 WREG32(UVD_MPC_SET_ALU, 0); 2752 WREG32(UVD_MPC_SET_MUX, 0x88); 2753 2754 /* Stall UMC */ 2755 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 2756 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); 2757 2758 /* take all subblocks out of reset, except VCPU */ 2759 WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET); 2760 mdelay(5); 2761 2762 /* enable VCPU clock */ 2763 WREG32(UVD_VCPU_CNTL, 1 << 9); 2764 2765 /* enable UMC */ 2766 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); 2767 2768 /* boot up the VCPU */ 2769 WREG32(UVD_SOFT_RESET, 0); 2770 mdelay(10); 2771 2772 WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3)); 2773 2774 for (i = 0; i < 10; ++i) { 2775 uint32_t status; 2776 for (j = 0; j < 100; ++j) { 2777 status = RREG32(UVD_STATUS); 2778 if (status & 2) 2779 break; 2780 mdelay(10); 2781 } 2782 r = 0; 2783 if (status & 2) 2784 break; 2785 2786 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 2787 WREG32_P(UVD_SOFT_RESET, VCPU_SOFT_RESET, ~VCPU_SOFT_RESET); 2788 mdelay(10); 2789 WREG32_P(UVD_SOFT_RESET, 0, ~VCPU_SOFT_RESET); 2790 mdelay(10); 2791 r = -1; 2792 } 2793 2794 if (r) { 2795 DRM_ERROR("UVD not responding, giving up!!!\n"); 2796 radeon_set_uvd_clocks(rdev, 0, 0); 2797 return r; 2798 } 2799 2800 /* enable interupt */ 2801 WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1)); 2802 2803 r = r600_uvd_rbc_start(rdev); 2804 if (!r) 2805 DRM_INFO("UVD initialized successfully.\n"); 2806 2807 /* lower clocks again */ 2808 radeon_set_uvd_clocks(rdev, 0, 0); 2809 2810 return r; 2811 } 2812 2813 /* 2814 * GPU scratch registers helpers function. 2815 */ 2816 void r600_scratch_init(struct radeon_device *rdev) 2817 { 2818 int i; 2819 2820 rdev->scratch.num_reg = 7; 2821 rdev->scratch.reg_base = SCRATCH_REG0; 2822 for (i = 0; i < rdev->scratch.num_reg; i++) { 2823 rdev->scratch.free[i] = true; 2824 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 2825 } 2826 } 2827 2828 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 2829 { 2830 uint32_t scratch; 2831 uint32_t tmp = 0; 2832 unsigned i; 2833 int r; 2834 2835 r = radeon_scratch_get(rdev, &scratch); 2836 if (r) { 2837 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 2838 return r; 2839 } 2840 WREG32(scratch, 0xCAFEDEAD); 2841 r = radeon_ring_lock(rdev, ring, 3); 2842 if (r) { 2843 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); 2844 radeon_scratch_free(rdev, scratch); 2845 return r; 2846 } 2847 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2848 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2849 radeon_ring_write(ring, 0xDEADBEEF); 2850 radeon_ring_unlock_commit(rdev, ring); 2851 for (i = 0; i < rdev->usec_timeout; i++) { 2852 tmp = RREG32(scratch); 2853 if (tmp == 0xDEADBEEF) 2854 break; 2855 DRM_UDELAY(1); 2856 } 2857 if (i < rdev->usec_timeout) { 2858 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2859 } else { 2860 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 2861 ring->idx, scratch, tmp); 2862 r = -EINVAL; 2863 } 2864 radeon_scratch_free(rdev, scratch); 2865 return r; 2866 } 2867 2868 /** 2869 * r600_dma_ring_test - simple async dma engine test 2870 * 2871 * @rdev: radeon_device pointer 2872 * @ring: radeon_ring structure holding ring information 2873 * 2874 * Test the DMA engine by writing using it to write an 2875 * value to memory. (r6xx-SI). 2876 * Returns 0 for success, error for failure. 2877 */ 2878 int r600_dma_ring_test(struct radeon_device *rdev, 2879 struct radeon_ring *ring) 2880 { 2881 unsigned i; 2882 int r; 2883 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; 2884 u32 tmp; 2885 2886 if (!ptr) { 2887 DRM_ERROR("invalid vram scratch pointer\n"); 2888 return -EINVAL; 2889 } 2890 2891 tmp = 0xCAFEDEAD; 2892 writel(tmp, ptr); 2893 2894 r = radeon_ring_lock(rdev, ring, 4); 2895 if (r) { 2896 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r); 2897 return r; 2898 } 2899 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); 2900 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc); 2901 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff); 2902 radeon_ring_write(ring, 0xDEADBEEF); 2903 radeon_ring_unlock_commit(rdev, ring); 2904 2905 for (i = 0; i < rdev->usec_timeout; i++) { 2906 tmp = readl(ptr); 2907 if (tmp == 0xDEADBEEF) 2908 break; 2909 DRM_UDELAY(1); 2910 } 2911 2912 if (i < rdev->usec_timeout) { 2913 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2914 } else { 2915 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n", 2916 ring->idx, tmp); 2917 r = -EINVAL; 2918 } 2919 return r; 2920 } 2921 2922 int r600_uvd_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 2923 { 2924 uint32_t tmp = 0; 2925 unsigned i; 2926 int r; 2927 2928 WREG32(UVD_CONTEXT_ID, 0xCAFEDEAD); 2929 r = radeon_ring_lock(rdev, ring, 3); 2930 if (r) { 2931 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", 2932 ring->idx, r); 2933 return r; 2934 } 2935 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); 2936 radeon_ring_write(ring, 0xDEADBEEF); 2937 radeon_ring_unlock_commit(rdev, ring); 2938 for (i = 0; i < rdev->usec_timeout; i++) { 2939 tmp = RREG32(UVD_CONTEXT_ID); 2940 if (tmp == 0xDEADBEEF) 2941 break; 2942 DRM_UDELAY(1); 2943 } 2944 2945 if (i < rdev->usec_timeout) { 2946 DRM_INFO("ring test on %d succeeded in %d usecs\n", 2947 ring->idx, i); 2948 } else { 2949 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n", 2950 ring->idx, tmp); 2951 r = -EINVAL; 2952 } 2953 return r; 2954 } 2955 2956 /* 2957 * CP fences/semaphores 2958 */ 2959 2960 void r600_fence_ring_emit(struct radeon_device *rdev, 2961 struct radeon_fence *fence) 2962 { 2963 struct radeon_ring *ring = &rdev->ring[fence->ring]; 2964 2965 if (rdev->wb.use_event) { 2966 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2967 /* flush read cache over gart */ 2968 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2969 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | 2970 PACKET3_VC_ACTION_ENA | 2971 PACKET3_SH_ACTION_ENA); 2972 radeon_ring_write(ring, 0xFFFFFFFF); 2973 radeon_ring_write(ring, 0); 2974 radeon_ring_write(ring, 10); /* poll interval */ 2975 /* EVENT_WRITE_EOP - flush caches, send int */ 2976 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2977 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 2978 radeon_ring_write(ring, addr & 0xffffffff); 2979 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 2980 radeon_ring_write(ring, fence->seq); 2981 radeon_ring_write(ring, 0); 2982 } else { 2983 /* flush read cache over gart */ 2984 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2985 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | 2986 PACKET3_VC_ACTION_ENA | 2987 PACKET3_SH_ACTION_ENA); 2988 radeon_ring_write(ring, 0xFFFFFFFF); 2989 radeon_ring_write(ring, 0); 2990 radeon_ring_write(ring, 10); /* poll interval */ 2991 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2992 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); 2993 /* wait for 3D idle clean */ 2994 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2995 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2996 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); 2997 /* Emit fence sequence & fire IRQ */ 2998 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2999 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 3000 radeon_ring_write(ring, fence->seq); 3001 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ 3002 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); 3003 radeon_ring_write(ring, RB_INT_STAT); 3004 } 3005 } 3006 3007 void r600_uvd_fence_emit(struct radeon_device *rdev, 3008 struct radeon_fence *fence) 3009 { 3010 struct radeon_ring *ring = &rdev->ring[fence->ring]; 3011 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; 3012 3013 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); 3014 radeon_ring_write(ring, fence->seq); 3015 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); 3016 radeon_ring_write(ring, addr & 0xffffffff); 3017 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); 3018 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); 3019 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); 3020 radeon_ring_write(ring, 0); 3021 3022 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); 3023 radeon_ring_write(ring, 0); 3024 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); 3025 radeon_ring_write(ring, 0); 3026 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); 3027 radeon_ring_write(ring, 2); 3028 return; 3029 } 3030 3031 void r600_semaphore_ring_emit(struct radeon_device *rdev, 3032 struct radeon_ring *ring, 3033 struct radeon_semaphore *semaphore, 3034 bool emit_wait) 3035 { 3036 uint64_t addr = semaphore->gpu_addr; 3037 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; 3038 3039 if (rdev->family < CHIP_CAYMAN) 3040 sel |= PACKET3_SEM_WAIT_ON_SIGNAL; 3041 3042 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); 3043 radeon_ring_write(ring, addr & 0xffffffff); 3044 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); 3045 } 3046 3047 /* 3048 * DMA fences/semaphores 3049 */ 3050 3051 /** 3052 * r600_dma_fence_ring_emit - emit a fence on the DMA ring 3053 * 3054 * @rdev: radeon_device pointer 3055 * @fence: radeon fence object 3056 * 3057 * Add a DMA fence packet to the ring to write 3058 * the fence seq number and DMA trap packet to generate 3059 * an interrupt if needed (r6xx-r7xx). 3060 */ 3061 void r600_dma_fence_ring_emit(struct radeon_device *rdev, 3062 struct radeon_fence *fence) 3063 { 3064 struct radeon_ring *ring = &rdev->ring[fence->ring]; 3065 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 3066 3067 /* write the fence */ 3068 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0)); 3069 radeon_ring_write(ring, addr & 0xfffffffc); 3070 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); 3071 radeon_ring_write(ring, lower_32_bits(fence->seq)); 3072 /* generate an interrupt */ 3073 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0)); 3074 } 3075 3076 /** 3077 * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring 3078 * 3079 * @rdev: radeon_device pointer 3080 * @ring: radeon_ring structure holding ring information 3081 * @semaphore: radeon semaphore object 3082 * @emit_wait: wait or signal semaphore 3083 * 3084 * Add a DMA semaphore packet to the ring wait on or signal 3085 * other rings (r6xx-SI). 3086 */ 3087 void r600_dma_semaphore_ring_emit(struct radeon_device *rdev, 3088 struct radeon_ring *ring, 3089 struct radeon_semaphore *semaphore, 3090 bool emit_wait) 3091 { 3092 u64 addr = semaphore->gpu_addr; 3093 u32 s = emit_wait ? 0 : 1; 3094 3095 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0)); 3096 radeon_ring_write(ring, addr & 0xfffffffc); 3097 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); 3098 } 3099 3100 void r600_uvd_semaphore_emit(struct radeon_device *rdev, 3101 struct radeon_ring *ring, 3102 struct radeon_semaphore *semaphore, 3103 bool emit_wait) 3104 { 3105 uint64_t addr = semaphore->gpu_addr; 3106 3107 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); 3108 radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF); 3109 3110 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); 3111 radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF); 3112 3113 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); 3114 radeon_ring_write(ring, emit_wait ? 1 : 0); 3115 } 3116 3117 int r600_copy_blit(struct radeon_device *rdev, 3118 uint64_t src_offset, 3119 uint64_t dst_offset, 3120 unsigned num_gpu_pages, 3121 struct radeon_fence **fence) 3122 { 3123 struct radeon_semaphore *sem = NULL; 3124 struct radeon_sa_bo *vb = NULL; 3125 int r; 3126 3127 r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem); 3128 if (r) { 3129 return r; 3130 } 3131 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb); 3132 r600_blit_done_copy(rdev, fence, vb, sem); 3133 return 0; 3134 } 3135 3136 /** 3137 * r600_copy_cpdma - copy pages using the CP DMA engine 3138 * 3139 * @rdev: radeon_device pointer 3140 * @src_offset: src GPU address 3141 * @dst_offset: dst GPU address 3142 * @num_gpu_pages: number of GPU pages to xfer 3143 * @fence: radeon fence object 3144 * 3145 * Copy GPU paging using the CP DMA engine (r6xx+). 3146 * Used by the radeon ttm implementation to move pages if 3147 * registered as the asic copy callback. 3148 */ 3149 int r600_copy_cpdma(struct radeon_device *rdev, 3150 uint64_t src_offset, uint64_t dst_offset, 3151 unsigned num_gpu_pages, 3152 struct radeon_fence **fence) 3153 { 3154 struct radeon_semaphore *sem = NULL; 3155 int ring_index = rdev->asic->copy.blit_ring_index; 3156 struct radeon_ring *ring = &rdev->ring[ring_index]; 3157 u32 size_in_bytes, cur_size_in_bytes, tmp; 3158 int i, num_loops; 3159 int r = 0; 3160 3161 r = radeon_semaphore_create(rdev, &sem); 3162 if (r) { 3163 DRM_ERROR("radeon: moving bo (%d).\n", r); 3164 return r; 3165 } 3166 3167 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); 3168 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); 3169 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24); 3170 if (r) { 3171 DRM_ERROR("radeon: moving bo (%d).\n", r); 3172 radeon_semaphore_free(rdev, &sem, NULL); 3173 return r; 3174 } 3175 3176 if (radeon_fence_need_sync(*fence, ring->idx)) { 3177 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring, 3178 ring->idx); 3179 radeon_fence_note_sync(*fence, ring->idx); 3180 } else { 3181 radeon_semaphore_free(rdev, &sem, NULL); 3182 } 3183 3184 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3185 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3186 radeon_ring_write(ring, WAIT_3D_IDLE_bit); 3187 for (i = 0; i < num_loops; i++) { 3188 cur_size_in_bytes = size_in_bytes; 3189 if (cur_size_in_bytes > 0x1fffff) 3190 cur_size_in_bytes = 0x1fffff; 3191 size_in_bytes -= cur_size_in_bytes; 3192 tmp = upper_32_bits(src_offset) & 0xff; 3193 if (size_in_bytes == 0) 3194 tmp |= PACKET3_CP_DMA_CP_SYNC; 3195 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)); 3196 radeon_ring_write(ring, src_offset & 0xffffffff); 3197 radeon_ring_write(ring, tmp); 3198 radeon_ring_write(ring, dst_offset & 0xffffffff); 3199 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); 3200 radeon_ring_write(ring, cur_size_in_bytes); 3201 src_offset += cur_size_in_bytes; 3202 dst_offset += cur_size_in_bytes; 3203 } 3204 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3205 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3206 radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit); 3207 3208 r = radeon_fence_emit(rdev, fence, ring->idx); 3209 if (r) { 3210 radeon_ring_unlock_undo(rdev, ring); 3211 return r; 3212 } 3213 3214 radeon_ring_unlock_commit(rdev, ring); 3215 radeon_semaphore_free(rdev, &sem, *fence); 3216 3217 return r; 3218 } 3219 3220 /** 3221 * r600_copy_dma - copy pages using the DMA engine 3222 * 3223 * @rdev: radeon_device pointer 3224 * @src_offset: src GPU address 3225 * @dst_offset: dst GPU address 3226 * @num_gpu_pages: number of GPU pages to xfer 3227 * @fence: radeon fence object 3228 * 3229 * Copy GPU paging using the DMA engine (r6xx). 3230 * Used by the radeon ttm implementation to move pages if 3231 * registered as the asic copy callback. 3232 */ 3233 int r600_copy_dma(struct radeon_device *rdev, 3234 uint64_t src_offset, uint64_t dst_offset, 3235 unsigned num_gpu_pages, 3236 struct radeon_fence **fence) 3237 { 3238 struct radeon_semaphore *sem = NULL; 3239 int ring_index = rdev->asic->copy.dma_ring_index; 3240 struct radeon_ring *ring = &rdev->ring[ring_index]; 3241 u32 size_in_dw, cur_size_in_dw; 3242 int i, num_loops; 3243 int r = 0; 3244 3245 r = radeon_semaphore_create(rdev, &sem); 3246 if (r) { 3247 DRM_ERROR("radeon: moving bo (%d).\n", r); 3248 return r; 3249 } 3250 3251 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4; 3252 num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE); 3253 r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8); 3254 if (r) { 3255 DRM_ERROR("radeon: moving bo (%d).\n", r); 3256 radeon_semaphore_free(rdev, &sem, NULL); 3257 return r; 3258 } 3259 3260 if (radeon_fence_need_sync(*fence, ring->idx)) { 3261 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring, 3262 ring->idx); 3263 radeon_fence_note_sync(*fence, ring->idx); 3264 } else { 3265 radeon_semaphore_free(rdev, &sem, NULL); 3266 } 3267 3268 for (i = 0; i < num_loops; i++) { 3269 cur_size_in_dw = size_in_dw; 3270 if (cur_size_in_dw > 0xFFFE) 3271 cur_size_in_dw = 0xFFFE; 3272 size_in_dw -= cur_size_in_dw; 3273 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw)); 3274 radeon_ring_write(ring, dst_offset & 0xfffffffc); 3275 radeon_ring_write(ring, src_offset & 0xfffffffc); 3276 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) | 3277 (upper_32_bits(src_offset) & 0xff))); 3278 src_offset += cur_size_in_dw * 4; 3279 dst_offset += cur_size_in_dw * 4; 3280 } 3281 3282 r = radeon_fence_emit(rdev, fence, ring->idx); 3283 if (r) { 3284 radeon_ring_unlock_undo(rdev, ring); 3285 return r; 3286 } 3287 3288 radeon_ring_unlock_commit(rdev, ring); 3289 radeon_semaphore_free(rdev, &sem, *fence); 3290 3291 return r; 3292 } 3293 3294 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 3295 uint32_t tiling_flags, uint32_t pitch, 3296 uint32_t offset, uint32_t obj_size) 3297 { 3298 /* FIXME: implement */ 3299 return 0; 3300 } 3301 3302 void r600_clear_surface_reg(struct radeon_device *rdev, int reg) 3303 { 3304 /* FIXME: implement */ 3305 } 3306 3307 static int r600_startup(struct radeon_device *rdev) 3308 { 3309 struct radeon_ring *ring; 3310 int r; 3311 3312 /* enable pcie gen2 link */ 3313 r600_pcie_gen2_enable(rdev); 3314 3315 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 3316 r = r600_init_microcode(rdev); 3317 if (r) { 3318 DRM_ERROR("Failed to load firmware!\n"); 3319 return r; 3320 } 3321 } 3322 3323 r = r600_vram_scratch_init(rdev); 3324 if (r) 3325 return r; 3326 3327 r600_mc_program(rdev); 3328 if (rdev->flags & RADEON_IS_AGP) { 3329 r600_agp_enable(rdev); 3330 } else { 3331 r = r600_pcie_gart_enable(rdev); 3332 if (r) 3333 return r; 3334 } 3335 r600_gpu_init(rdev); 3336 r = r600_blit_init(rdev); 3337 if (r) { 3338 r600_blit_fini(rdev); 3339 rdev->asic->copy.copy = NULL; 3340 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 3341 } 3342 3343 /* allocate wb buffer */ 3344 r = radeon_wb_init(rdev); 3345 if (r) 3346 return r; 3347 3348 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 3349 if (r) { 3350 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 3351 return r; 3352 } 3353 3354 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); 3355 if (r) { 3356 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 3357 return r; 3358 } 3359 3360 /* Enable IRQ */ 3361 if (!rdev->irq.installed) { 3362 r = radeon_irq_kms_init(rdev); 3363 if (r) 3364 return r; 3365 } 3366 3367 r = r600_irq_init(rdev); 3368 if (r) { 3369 DRM_ERROR("radeon: IH init failed (%d).\n", r); 3370 radeon_irq_kms_fini(rdev); 3371 return r; 3372 } 3373 r600_irq_set(rdev); 3374 3375 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3376 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 3377 R600_CP_RB_RPTR, R600_CP_RB_WPTR, 3378 0, 0xfffff, RADEON_CP_PACKET2); 3379 if (r) 3380 return r; 3381 3382 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 3383 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 3384 DMA_RB_RPTR, DMA_RB_WPTR, 3385 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 3386 if (r) 3387 return r; 3388 3389 r = r600_cp_load_microcode(rdev); 3390 if (r) 3391 return r; 3392 r = r600_cp_resume(rdev); 3393 if (r) 3394 return r; 3395 3396 r = r600_dma_resume(rdev); 3397 if (r) 3398 return r; 3399 3400 r = radeon_ib_pool_init(rdev); 3401 if (r) { 3402 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3403 return r; 3404 } 3405 3406 r = r600_audio_init(rdev); 3407 if (r) { 3408 DRM_ERROR("radeon: audio init failed\n"); 3409 return r; 3410 } 3411 3412 return 0; 3413 } 3414 3415 void r600_vga_set_state(struct radeon_device *rdev, bool state) 3416 { 3417 uint32_t temp; 3418 3419 temp = RREG32(CONFIG_CNTL); 3420 if (state == false) { 3421 temp &= ~(1<<0); 3422 temp |= (1<<1); 3423 } else { 3424 temp &= ~(1<<1); 3425 } 3426 WREG32(CONFIG_CNTL, temp); 3427 } 3428 3429 int r600_resume(struct radeon_device *rdev) 3430 { 3431 int r; 3432 3433 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, 3434 * posting will perform necessary task to bring back GPU into good 3435 * shape. 3436 */ 3437 /* post card */ 3438 atom_asic_init(rdev->mode_info.atom_context); 3439 3440 rdev->accel_working = true; 3441 r = r600_startup(rdev); 3442 if (r) { 3443 DRM_ERROR("r600 startup failed on resume\n"); 3444 rdev->accel_working = false; 3445 return r; 3446 } 3447 3448 return r; 3449 } 3450 3451 int r600_suspend(struct radeon_device *rdev) 3452 { 3453 r600_audio_fini(rdev); 3454 r600_cp_stop(rdev); 3455 r600_dma_stop(rdev); 3456 r600_irq_suspend(rdev); 3457 radeon_wb_disable(rdev); 3458 r600_pcie_gart_disable(rdev); 3459 3460 return 0; 3461 } 3462 3463 /* Plan is to move initialization in that function and use 3464 * helper function so that radeon_device_init pretty much 3465 * do nothing more than calling asic specific function. This 3466 * should also allow to remove a bunch of callback function 3467 * like vram_info. 3468 */ 3469 int r600_init(struct radeon_device *rdev) 3470 { 3471 int r; 3472 3473 if (r600_debugfs_mc_info_init(rdev)) { 3474 DRM_ERROR("Failed to register debugfs file for mc !\n"); 3475 } 3476 /* Read BIOS */ 3477 if (!radeon_get_bios(rdev)) { 3478 if (ASIC_IS_AVIVO(rdev)) 3479 return -EINVAL; 3480 } 3481 /* Must be an ATOMBIOS */ 3482 if (!rdev->is_atom_bios) { 3483 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 3484 return -EINVAL; 3485 } 3486 r = radeon_atombios_init(rdev); 3487 if (r) 3488 return r; 3489 /* Post card if necessary */ 3490 if (!radeon_card_posted(rdev)) { 3491 if (!rdev->bios) { 3492 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 3493 return -EINVAL; 3494 } 3495 DRM_INFO("GPU not posted. posting now...\n"); 3496 atom_asic_init(rdev->mode_info.atom_context); 3497 } 3498 /* Initialize scratch registers */ 3499 r600_scratch_init(rdev); 3500 /* Initialize surface registers */ 3501 radeon_surface_init(rdev); 3502 /* Initialize clocks */ 3503 radeon_get_clock_info(rdev->ddev); 3504 /* Fence driver */ 3505 r = radeon_fence_driver_init(rdev); 3506 if (r) 3507 return r; 3508 if (rdev->flags & RADEON_IS_AGP) { 3509 r = radeon_agp_init(rdev); 3510 if (r) 3511 radeon_agp_disable(rdev); 3512 } 3513 r = r600_mc_init(rdev); 3514 if (r) 3515 return r; 3516 /* Memory manager */ 3517 r = radeon_bo_init(rdev); 3518 if (r) 3519 return r; 3520 3521 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 3522 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 3523 3524 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; 3525 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); 3526 3527 rdev->ih.ring_obj = NULL; 3528 r600_ih_ring_init(rdev, 64 * 1024); 3529 3530 r = r600_pcie_gart_init(rdev); 3531 if (r) 3532 return r; 3533 3534 rdev->accel_working = true; 3535 r = r600_startup(rdev); 3536 if (r) { 3537 dev_err(rdev->dev, "disabling GPU acceleration\n"); 3538 r600_cp_fini(rdev); 3539 r600_dma_fini(rdev); 3540 r600_irq_fini(rdev); 3541 radeon_wb_fini(rdev); 3542 radeon_ib_pool_fini(rdev); 3543 radeon_irq_kms_fini(rdev); 3544 r600_pcie_gart_fini(rdev); 3545 rdev->accel_working = false; 3546 } 3547 3548 return 0; 3549 } 3550 3551 void r600_fini(struct radeon_device *rdev) 3552 { 3553 r600_audio_fini(rdev); 3554 r600_blit_fini(rdev); 3555 r600_cp_fini(rdev); 3556 r600_dma_fini(rdev); 3557 r600_irq_fini(rdev); 3558 radeon_wb_fini(rdev); 3559 radeon_ib_pool_fini(rdev); 3560 radeon_irq_kms_fini(rdev); 3561 r600_pcie_gart_fini(rdev); 3562 r600_vram_scratch_fini(rdev); 3563 radeon_agp_fini(rdev); 3564 radeon_gem_fini(rdev); 3565 radeon_fence_driver_fini(rdev); 3566 radeon_bo_fini(rdev); 3567 radeon_atombios_fini(rdev); 3568 kfree(rdev->bios); 3569 rdev->bios = NULL; 3570 } 3571 3572 3573 /* 3574 * CS stuff 3575 */ 3576 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3577 { 3578 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3579 u32 next_rptr; 3580 3581 if (ring->rptr_save_reg) { 3582 next_rptr = ring->wptr + 3 + 4; 3583 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3584 radeon_ring_write(ring, ((ring->rptr_save_reg - 3585 PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 3586 radeon_ring_write(ring, next_rptr); 3587 } else if (rdev->wb.enabled) { 3588 next_rptr = ring->wptr + 5 + 4; 3589 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); 3590 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3591 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); 3592 radeon_ring_write(ring, next_rptr); 3593 radeon_ring_write(ring, 0); 3594 } 3595 3596 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3597 radeon_ring_write(ring, 3598 #ifdef __BIG_ENDIAN 3599 (2 << 0) | 3600 #endif 3601 (ib->gpu_addr & 0xFFFFFFFC)); 3602 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); 3603 radeon_ring_write(ring, ib->length_dw); 3604 } 3605 3606 void r600_uvd_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3607 { 3608 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3609 3610 radeon_ring_write(ring, PACKET0(UVD_RBC_IB_BASE, 0)); 3611 radeon_ring_write(ring, ib->gpu_addr); 3612 radeon_ring_write(ring, PACKET0(UVD_RBC_IB_SIZE, 0)); 3613 radeon_ring_write(ring, ib->length_dw); 3614 } 3615 3616 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3617 { 3618 struct radeon_ib ib; 3619 uint32_t scratch; 3620 uint32_t tmp = 0; 3621 unsigned i; 3622 int r; 3623 3624 r = radeon_scratch_get(rdev, &scratch); 3625 if (r) { 3626 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3627 return r; 3628 } 3629 WREG32(scratch, 0xCAFEDEAD); 3630 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3631 if (r) { 3632 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3633 goto free_scratch; 3634 } 3635 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 3636 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3637 ib.ptr[2] = 0xDEADBEEF; 3638 ib.length_dw = 3; 3639 r = radeon_ib_schedule(rdev, &ib, NULL); 3640 if (r) { 3641 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3642 goto free_ib; 3643 } 3644 r = radeon_fence_wait(ib.fence, false); 3645 if (r) { 3646 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3647 goto free_ib; 3648 } 3649 for (i = 0; i < rdev->usec_timeout; i++) { 3650 tmp = RREG32(scratch); 3651 if (tmp == 0xDEADBEEF) 3652 break; 3653 DRM_UDELAY(1); 3654 } 3655 if (i < rdev->usec_timeout) { 3656 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3657 } else { 3658 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3659 scratch, tmp); 3660 r = -EINVAL; 3661 } 3662 free_ib: 3663 radeon_ib_free(rdev, &ib); 3664 free_scratch: 3665 radeon_scratch_free(rdev, scratch); 3666 return r; 3667 } 3668 3669 /** 3670 * r600_dma_ib_test - test an IB on the DMA engine 3671 * 3672 * @rdev: radeon_device pointer 3673 * @ring: radeon_ring structure holding ring information 3674 * 3675 * Test a simple IB in the DMA ring (r6xx-SI). 3676 * Returns 0 on success, error on failure. 3677 */ 3678 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3679 { 3680 struct radeon_ib ib; 3681 unsigned i; 3682 int r; 3683 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; 3684 u32 tmp = 0; 3685 3686 if (!ptr) { 3687 DRM_ERROR("invalid vram scratch pointer\n"); 3688 return -EINVAL; 3689 } 3690 3691 tmp = 0xCAFEDEAD; 3692 writel(tmp, ptr); 3693 3694 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3695 if (r) { 3696 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3697 return r; 3698 } 3699 3700 ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1); 3701 ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc; 3702 ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff; 3703 ib.ptr[3] = 0xDEADBEEF; 3704 ib.length_dw = 4; 3705 3706 r = radeon_ib_schedule(rdev, &ib, NULL); 3707 if (r) { 3708 radeon_ib_free(rdev, &ib); 3709 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3710 return r; 3711 } 3712 r = radeon_fence_wait(ib.fence, false); 3713 if (r) { 3714 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3715 return r; 3716 } 3717 for (i = 0; i < rdev->usec_timeout; i++) { 3718 tmp = readl(ptr); 3719 if (tmp == 0xDEADBEEF) 3720 break; 3721 DRM_UDELAY(1); 3722 } 3723 if (i < rdev->usec_timeout) { 3724 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3725 } else { 3726 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp); 3727 r = -EINVAL; 3728 } 3729 radeon_ib_free(rdev, &ib); 3730 return r; 3731 } 3732 3733 int r600_uvd_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3734 { 3735 struct radeon_fence *fence = NULL; 3736 int r; 3737 3738 r = radeon_set_uvd_clocks(rdev, 53300, 40000); 3739 if (r) { 3740 DRM_ERROR("radeon: failed to raise UVD clocks (%d).\n", r); 3741 return r; 3742 } 3743 3744 r = radeon_uvd_get_create_msg(rdev, ring->idx, 1, NULL); 3745 if (r) { 3746 DRM_ERROR("radeon: failed to get create msg (%d).\n", r); 3747 goto error; 3748 } 3749 3750 r = radeon_uvd_get_destroy_msg(rdev, ring->idx, 1, &fence); 3751 if (r) { 3752 DRM_ERROR("radeon: failed to get destroy ib (%d).\n", r); 3753 goto error; 3754 } 3755 3756 r = radeon_fence_wait(fence, false); 3757 if (r) { 3758 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3759 goto error; 3760 } 3761 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 3762 error: 3763 radeon_fence_unref(&fence); 3764 radeon_set_uvd_clocks(rdev, 0, 0); 3765 return r; 3766 } 3767 3768 /** 3769 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine 3770 * 3771 * @rdev: radeon_device pointer 3772 * @ib: IB object to schedule 3773 * 3774 * Schedule an IB in the DMA ring (r6xx-r7xx). 3775 */ 3776 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3777 { 3778 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3779 3780 if (rdev->wb.enabled) { 3781 u32 next_rptr = ring->wptr + 4; 3782 while ((next_rptr & 7) != 5) 3783 next_rptr++; 3784 next_rptr += 3; 3785 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); 3786 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3787 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); 3788 radeon_ring_write(ring, next_rptr); 3789 } 3790 3791 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring. 3792 * Pad as necessary with NOPs. 3793 */ 3794 while ((ring->wptr & 7) != 5) 3795 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 3796 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0)); 3797 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); 3798 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF)); 3799 3800 } 3801 3802 /* 3803 * Interrupts 3804 * 3805 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty 3806 * the same as the CP ring buffer, but in reverse. Rather than the CPU 3807 * writing to the ring and the GPU consuming, the GPU writes to the ring 3808 * and host consumes. As the host irq handler processes interrupts, it 3809 * increments the rptr. When the rptr catches up with the wptr, all the 3810 * current interrupts have been processed. 3811 */ 3812 3813 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) 3814 { 3815 u32 rb_bufsz; 3816 3817 /* Align ring size */ 3818 rb_bufsz = drm_order(ring_size / 4); 3819 ring_size = (1 << rb_bufsz) * 4; 3820 rdev->ih.ring_size = ring_size; 3821 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; 3822 rdev->ih.rptr = 0; 3823 } 3824 3825 int r600_ih_ring_alloc(struct radeon_device *rdev) 3826 { 3827 int r; 3828 3829 /* Allocate ring buffer */ 3830 if (rdev->ih.ring_obj == NULL) { 3831 r = radeon_bo_create(rdev, rdev->ih.ring_size, 3832 PAGE_SIZE, true, 3833 RADEON_GEM_DOMAIN_GTT, 3834 NULL, &rdev->ih.ring_obj); 3835 if (r) { 3836 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); 3837 return r; 3838 } 3839 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3840 if (unlikely(r != 0)) 3841 return r; 3842 r = radeon_bo_pin(rdev->ih.ring_obj, 3843 RADEON_GEM_DOMAIN_GTT, 3844 &rdev->ih.gpu_addr); 3845 if (r) { 3846 radeon_bo_unreserve(rdev->ih.ring_obj); 3847 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); 3848 return r; 3849 } 3850 r = radeon_bo_kmap(rdev->ih.ring_obj, 3851 (void **)&rdev->ih.ring); 3852 radeon_bo_unreserve(rdev->ih.ring_obj); 3853 if (r) { 3854 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); 3855 return r; 3856 } 3857 } 3858 return 0; 3859 } 3860 3861 void r600_ih_ring_fini(struct radeon_device *rdev) 3862 { 3863 int r; 3864 if (rdev->ih.ring_obj) { 3865 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3866 if (likely(r == 0)) { 3867 radeon_bo_kunmap(rdev->ih.ring_obj); 3868 radeon_bo_unpin(rdev->ih.ring_obj); 3869 radeon_bo_unreserve(rdev->ih.ring_obj); 3870 } 3871 radeon_bo_unref(&rdev->ih.ring_obj); 3872 rdev->ih.ring = NULL; 3873 rdev->ih.ring_obj = NULL; 3874 } 3875 } 3876 3877 void r600_rlc_stop(struct radeon_device *rdev) 3878 { 3879 3880 if ((rdev->family >= CHIP_RV770) && 3881 (rdev->family <= CHIP_RV740)) { 3882 /* r7xx asics need to soft reset RLC before halting */ 3883 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); 3884 RREG32(SRBM_SOFT_RESET); 3885 mdelay(15); 3886 WREG32(SRBM_SOFT_RESET, 0); 3887 RREG32(SRBM_SOFT_RESET); 3888 } 3889 3890 WREG32(RLC_CNTL, 0); 3891 } 3892 3893 static void r600_rlc_start(struct radeon_device *rdev) 3894 { 3895 WREG32(RLC_CNTL, RLC_ENABLE); 3896 } 3897 3898 static int r600_rlc_resume(struct radeon_device *rdev) 3899 { 3900 u32 i; 3901 const __be32 *fw_data; 3902 3903 if (!rdev->rlc_fw) 3904 return -EINVAL; 3905 3906 r600_rlc_stop(rdev); 3907 3908 WREG32(RLC_HB_CNTL, 0); 3909 3910 WREG32(RLC_HB_BASE, 0); 3911 WREG32(RLC_HB_RPTR, 0); 3912 WREG32(RLC_HB_WPTR, 0); 3913 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); 3914 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); 3915 WREG32(RLC_MC_CNTL, 0); 3916 WREG32(RLC_UCODE_CNTL, 0); 3917 3918 fw_data = (const __be32 *)rdev->rlc_fw->data; 3919 if (rdev->family >= CHIP_RV770) { 3920 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { 3921 WREG32(RLC_UCODE_ADDR, i); 3922 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3923 } 3924 } else { 3925 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) { 3926 WREG32(RLC_UCODE_ADDR, i); 3927 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3928 } 3929 } 3930 WREG32(RLC_UCODE_ADDR, 0); 3931 3932 r600_rlc_start(rdev); 3933 3934 return 0; 3935 } 3936 3937 static void r600_enable_interrupts(struct radeon_device *rdev) 3938 { 3939 u32 ih_cntl = RREG32(IH_CNTL); 3940 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3941 3942 ih_cntl |= ENABLE_INTR; 3943 ih_rb_cntl |= IH_RB_ENABLE; 3944 WREG32(IH_CNTL, ih_cntl); 3945 WREG32(IH_RB_CNTL, ih_rb_cntl); 3946 rdev->ih.enabled = true; 3947 } 3948 3949 void r600_disable_interrupts(struct radeon_device *rdev) 3950 { 3951 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3952 u32 ih_cntl = RREG32(IH_CNTL); 3953 3954 ih_rb_cntl &= ~IH_RB_ENABLE; 3955 ih_cntl &= ~ENABLE_INTR; 3956 WREG32(IH_RB_CNTL, ih_rb_cntl); 3957 WREG32(IH_CNTL, ih_cntl); 3958 /* set rptr, wptr to 0 */ 3959 WREG32(IH_RB_RPTR, 0); 3960 WREG32(IH_RB_WPTR, 0); 3961 rdev->ih.enabled = false; 3962 rdev->ih.rptr = 0; 3963 } 3964 3965 static void r600_disable_interrupt_state(struct radeon_device *rdev) 3966 { 3967 u32 tmp; 3968 3969 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 3970 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3971 WREG32(DMA_CNTL, tmp); 3972 WREG32(GRBM_INT_CNTL, 0); 3973 WREG32(DxMODE_INT_MASK, 0); 3974 WREG32(D1GRPH_INTERRUPT_CONTROL, 0); 3975 WREG32(D2GRPH_INTERRUPT_CONTROL, 0); 3976 if (ASIC_IS_DCE3(rdev)) { 3977 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); 3978 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); 3979 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3980 WREG32(DC_HPD1_INT_CONTROL, tmp); 3981 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3982 WREG32(DC_HPD2_INT_CONTROL, tmp); 3983 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3984 WREG32(DC_HPD3_INT_CONTROL, tmp); 3985 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3986 WREG32(DC_HPD4_INT_CONTROL, tmp); 3987 if (ASIC_IS_DCE32(rdev)) { 3988 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3989 WREG32(DC_HPD5_INT_CONTROL, tmp); 3990 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3991 WREG32(DC_HPD6_INT_CONTROL, tmp); 3992 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3993 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3994 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3995 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3996 } else { 3997 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3998 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3999 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 4000 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 4001 } 4002 } else { 4003 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 4004 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 4005 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 4006 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 4007 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 4008 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 4009 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 4010 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 4011 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 4012 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 4013 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 4014 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 4015 } 4016 } 4017 4018 int r600_irq_init(struct radeon_device *rdev) 4019 { 4020 int ret = 0; 4021 int rb_bufsz; 4022 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 4023 4024 /* allocate ring */ 4025 ret = r600_ih_ring_alloc(rdev); 4026 if (ret) 4027 return ret; 4028 4029 /* disable irqs */ 4030 r600_disable_interrupts(rdev); 4031 4032 /* init rlc */ 4033 if (rdev->family >= CHIP_CEDAR) 4034 ret = evergreen_rlc_resume(rdev); 4035 else 4036 ret = r600_rlc_resume(rdev); 4037 if (ret) { 4038 r600_ih_ring_fini(rdev); 4039 return ret; 4040 } 4041 4042 /* setup interrupt control */ 4043 /* set dummy read address to ring address */ 4044 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); 4045 interrupt_cntl = RREG32(INTERRUPT_CNTL); 4046 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi 4047 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN 4048 */ 4049 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 4050 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ 4051 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 4052 WREG32(INTERRUPT_CNTL, interrupt_cntl); 4053 4054 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); 4055 rb_bufsz = drm_order(rdev->ih.ring_size / 4); 4056 4057 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | 4058 IH_WPTR_OVERFLOW_CLEAR | 4059 (rb_bufsz << 1)); 4060 4061 if (rdev->wb.enabled) 4062 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; 4063 4064 /* set the writeback address whether it's enabled or not */ 4065 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); 4066 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); 4067 4068 WREG32(IH_RB_CNTL, ih_rb_cntl); 4069 4070 /* set rptr, wptr to 0 */ 4071 WREG32(IH_RB_RPTR, 0); 4072 WREG32(IH_RB_WPTR, 0); 4073 4074 /* Default settings for IH_CNTL (disabled at first) */ 4075 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); 4076 /* RPTR_REARM only works if msi's are enabled */ 4077 if (rdev->msi_enabled) 4078 ih_cntl |= RPTR_REARM; 4079 WREG32(IH_CNTL, ih_cntl); 4080 4081 /* force the active interrupt state to all disabled */ 4082 if (rdev->family >= CHIP_CEDAR) 4083 evergreen_disable_interrupt_state(rdev); 4084 else 4085 r600_disable_interrupt_state(rdev); 4086 4087 /* at this point everything should be setup correctly to enable master */ 4088 pci_set_master(rdev->pdev); 4089 4090 /* enable irqs */ 4091 r600_enable_interrupts(rdev); 4092 4093 return ret; 4094 } 4095 4096 void r600_irq_suspend(struct radeon_device *rdev) 4097 { 4098 r600_irq_disable(rdev); 4099 r600_rlc_stop(rdev); 4100 } 4101 4102 void r600_irq_fini(struct radeon_device *rdev) 4103 { 4104 r600_irq_suspend(rdev); 4105 r600_ih_ring_fini(rdev); 4106 } 4107 4108 int r600_irq_set(struct radeon_device *rdev) 4109 { 4110 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 4111 u32 mode_int = 0; 4112 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 4113 u32 grbm_int_cntl = 0; 4114 u32 hdmi0, hdmi1; 4115 u32 d1grph = 0, d2grph = 0; 4116 u32 dma_cntl; 4117 u32 thermal_int = 0; 4118 4119 if (!rdev->irq.installed) { 4120 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 4121 return -EINVAL; 4122 } 4123 /* don't enable anything if the ih is disabled */ 4124 if (!rdev->ih.enabled) { 4125 r600_disable_interrupts(rdev); 4126 /* force the active interrupt state to all disabled */ 4127 r600_disable_interrupt_state(rdev); 4128 return 0; 4129 } 4130 4131 if (ASIC_IS_DCE3(rdev)) { 4132 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 4133 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 4134 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 4135 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 4136 if (ASIC_IS_DCE32(rdev)) { 4137 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 4138 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 4139 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 4140 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 4141 } else { 4142 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 4143 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 4144 } 4145 } else { 4146 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; 4147 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; 4148 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; 4149 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 4150 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 4151 } 4152 4153 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 4154 4155 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { 4156 thermal_int = RREG32(CG_THERMAL_INT) & 4157 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 4158 } else if (rdev->family >= CHIP_RV770) { 4159 thermal_int = RREG32(RV770_CG_THERMAL_INT) & 4160 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 4161 } 4162 if (rdev->irq.dpm_thermal) { 4163 DRM_DEBUG("dpm thermal\n"); 4164 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 4165 } 4166 4167 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 4168 DRM_DEBUG("r600_irq_set: sw int\n"); 4169 cp_int_cntl |= RB_INT_ENABLE; 4170 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 4171 } 4172 4173 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { 4174 DRM_DEBUG("r600_irq_set: sw int dma\n"); 4175 dma_cntl |= TRAP_ENABLE; 4176 } 4177 4178 if (rdev->irq.crtc_vblank_int[0] || 4179 atomic_read(&rdev->irq.pflip[0])) { 4180 DRM_DEBUG("r600_irq_set: vblank 0\n"); 4181 mode_int |= D1MODE_VBLANK_INT_MASK; 4182 } 4183 if (rdev->irq.crtc_vblank_int[1] || 4184 atomic_read(&rdev->irq.pflip[1])) { 4185 DRM_DEBUG("r600_irq_set: vblank 1\n"); 4186 mode_int |= D2MODE_VBLANK_INT_MASK; 4187 } 4188 if (rdev->irq.hpd[0]) { 4189 DRM_DEBUG("r600_irq_set: hpd 1\n"); 4190 hpd1 |= DC_HPDx_INT_EN; 4191 } 4192 if (rdev->irq.hpd[1]) { 4193 DRM_DEBUG("r600_irq_set: hpd 2\n"); 4194 hpd2 |= DC_HPDx_INT_EN; 4195 } 4196 if (rdev->irq.hpd[2]) { 4197 DRM_DEBUG("r600_irq_set: hpd 3\n"); 4198 hpd3 |= DC_HPDx_INT_EN; 4199 } 4200 if (rdev->irq.hpd[3]) { 4201 DRM_DEBUG("r600_irq_set: hpd 4\n"); 4202 hpd4 |= DC_HPDx_INT_EN; 4203 } 4204 if (rdev->irq.hpd[4]) { 4205 DRM_DEBUG("r600_irq_set: hpd 5\n"); 4206 hpd5 |= DC_HPDx_INT_EN; 4207 } 4208 if (rdev->irq.hpd[5]) { 4209 DRM_DEBUG("r600_irq_set: hpd 6\n"); 4210 hpd6 |= DC_HPDx_INT_EN; 4211 } 4212 if (rdev->irq.afmt[0]) { 4213 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 4214 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 4215 } 4216 if (rdev->irq.afmt[1]) { 4217 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 4218 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 4219 } 4220 4221 WREG32(CP_INT_CNTL, cp_int_cntl); 4222 WREG32(DMA_CNTL, dma_cntl); 4223 WREG32(DxMODE_INT_MASK, mode_int); 4224 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph); 4225 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph); 4226 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 4227 if (ASIC_IS_DCE3(rdev)) { 4228 WREG32(DC_HPD1_INT_CONTROL, hpd1); 4229 WREG32(DC_HPD2_INT_CONTROL, hpd2); 4230 WREG32(DC_HPD3_INT_CONTROL, hpd3); 4231 WREG32(DC_HPD4_INT_CONTROL, hpd4); 4232 if (ASIC_IS_DCE32(rdev)) { 4233 WREG32(DC_HPD5_INT_CONTROL, hpd5); 4234 WREG32(DC_HPD6_INT_CONTROL, hpd6); 4235 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); 4236 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); 4237 } else { 4238 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 4239 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 4240 } 4241 } else { 4242 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 4243 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 4244 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); 4245 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 4246 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 4247 } 4248 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { 4249 WREG32(CG_THERMAL_INT, thermal_int); 4250 } else if (rdev->family >= CHIP_RV770) { 4251 WREG32(RV770_CG_THERMAL_INT, thermal_int); 4252 } 4253 4254 return 0; 4255 } 4256 4257 static void r600_irq_ack(struct radeon_device *rdev) 4258 { 4259 u32 tmp; 4260 4261 if (ASIC_IS_DCE3(rdev)) { 4262 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); 4263 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); 4264 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); 4265 if (ASIC_IS_DCE32(rdev)) { 4266 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); 4267 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); 4268 } else { 4269 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 4270 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); 4271 } 4272 } else { 4273 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); 4274 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 4275 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; 4276 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 4277 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); 4278 } 4279 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); 4280 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); 4281 4282 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) 4283 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 4284 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) 4285 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 4286 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) 4287 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 4288 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) 4289 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 4290 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) 4291 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 4292 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) 4293 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 4294 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 4295 if (ASIC_IS_DCE3(rdev)) { 4296 tmp = RREG32(DC_HPD1_INT_CONTROL); 4297 tmp |= DC_HPDx_INT_ACK; 4298 WREG32(DC_HPD1_INT_CONTROL, tmp); 4299 } else { 4300 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 4301 tmp |= DC_HPDx_INT_ACK; 4302 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 4303 } 4304 } 4305 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 4306 if (ASIC_IS_DCE3(rdev)) { 4307 tmp = RREG32(DC_HPD2_INT_CONTROL); 4308 tmp |= DC_HPDx_INT_ACK; 4309 WREG32(DC_HPD2_INT_CONTROL, tmp); 4310 } else { 4311 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 4312 tmp |= DC_HPDx_INT_ACK; 4313 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 4314 } 4315 } 4316 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 4317 if (ASIC_IS_DCE3(rdev)) { 4318 tmp = RREG32(DC_HPD3_INT_CONTROL); 4319 tmp |= DC_HPDx_INT_ACK; 4320 WREG32(DC_HPD3_INT_CONTROL, tmp); 4321 } else { 4322 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 4323 tmp |= DC_HPDx_INT_ACK; 4324 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 4325 } 4326 } 4327 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 4328 tmp = RREG32(DC_HPD4_INT_CONTROL); 4329 tmp |= DC_HPDx_INT_ACK; 4330 WREG32(DC_HPD4_INT_CONTROL, tmp); 4331 } 4332 if (ASIC_IS_DCE32(rdev)) { 4333 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 4334 tmp = RREG32(DC_HPD5_INT_CONTROL); 4335 tmp |= DC_HPDx_INT_ACK; 4336 WREG32(DC_HPD5_INT_CONTROL, tmp); 4337 } 4338 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 4339 tmp = RREG32(DC_HPD5_INT_CONTROL); 4340 tmp |= DC_HPDx_INT_ACK; 4341 WREG32(DC_HPD6_INT_CONTROL, tmp); 4342 } 4343 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { 4344 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); 4345 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 4346 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 4347 } 4348 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { 4349 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); 4350 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 4351 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 4352 } 4353 } else { 4354 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 4355 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); 4356 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4357 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 4358 } 4359 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 4360 if (ASIC_IS_DCE3(rdev)) { 4361 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); 4362 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4363 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 4364 } else { 4365 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); 4366 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 4367 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 4368 } 4369 } 4370 } 4371 } 4372 4373 void r600_irq_disable(struct radeon_device *rdev) 4374 { 4375 r600_disable_interrupts(rdev); 4376 /* Wait and acknowledge irq */ 4377 mdelay(1); 4378 r600_irq_ack(rdev); 4379 r600_disable_interrupt_state(rdev); 4380 } 4381 4382 static u32 r600_get_ih_wptr(struct radeon_device *rdev) 4383 { 4384 u32 wptr, tmp; 4385 4386 if (rdev->wb.enabled) 4387 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 4388 else 4389 wptr = RREG32(IH_RB_WPTR); 4390 4391 if (wptr & RB_OVERFLOW) { 4392 /* When a ring buffer overflow happen start parsing interrupt 4393 * from the last not overwritten vector (wptr + 16). Hopefully 4394 * this should allow us to catchup. 4395 */ 4396 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", 4397 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); 4398 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 4399 tmp = RREG32(IH_RB_CNTL); 4400 tmp |= IH_WPTR_OVERFLOW_CLEAR; 4401 WREG32(IH_RB_CNTL, tmp); 4402 } 4403 return (wptr & rdev->ih.ptr_mask); 4404 } 4405 4406 /* r600 IV Ring 4407 * Each IV ring entry is 128 bits: 4408 * [7:0] - interrupt source id 4409 * [31:8] - reserved 4410 * [59:32] - interrupt source data 4411 * [127:60] - reserved 4412 * 4413 * The basic interrupt vector entries 4414 * are decoded as follows: 4415 * src_id src_data description 4416 * 1 0 D1 Vblank 4417 * 1 1 D1 Vline 4418 * 5 0 D2 Vblank 4419 * 5 1 D2 Vline 4420 * 19 0 FP Hot plug detection A 4421 * 19 1 FP Hot plug detection B 4422 * 19 2 DAC A auto-detection 4423 * 19 3 DAC B auto-detection 4424 * 21 4 HDMI block A 4425 * 21 5 HDMI block B 4426 * 176 - CP_INT RB 4427 * 177 - CP_INT IB1 4428 * 178 - CP_INT IB2 4429 * 181 - EOP Interrupt 4430 * 233 - GUI Idle 4431 * 4432 * Note, these are based on r600 and may need to be 4433 * adjusted or added to on newer asics 4434 */ 4435 4436 int r600_irq_process(struct radeon_device *rdev) 4437 { 4438 u32 wptr; 4439 u32 rptr; 4440 u32 src_id, src_data; 4441 u32 ring_index; 4442 bool queue_hotplug = false; 4443 bool queue_hdmi = false; 4444 bool queue_thermal = false; 4445 4446 if (!rdev->ih.enabled || rdev->shutdown) 4447 return IRQ_NONE; 4448 4449 /* No MSIs, need a dummy read to flush PCI DMAs */ 4450 if (!rdev->msi_enabled) 4451 RREG32(IH_RB_WPTR); 4452 4453 wptr = r600_get_ih_wptr(rdev); 4454 4455 restart_ih: 4456 /* is somebody else already processing irqs? */ 4457 if (atomic_xchg(&rdev->ih.lock, 1)) 4458 return IRQ_NONE; 4459 4460 rptr = rdev->ih.rptr; 4461 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 4462 4463 /* Order reading of wptr vs. reading of IH ring data */ 4464 rmb(); 4465 4466 /* display interrupts */ 4467 r600_irq_ack(rdev); 4468 4469 while (rptr != wptr) { 4470 /* wptr/rptr are in bytes! */ 4471 ring_index = rptr / 4; 4472 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 4473 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 4474 4475 switch (src_id) { 4476 case 1: /* D1 vblank/vline */ 4477 switch (src_data) { 4478 case 0: /* D1 vblank */ 4479 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) { 4480 if (rdev->irq.crtc_vblank_int[0]) { 4481 drm_handle_vblank(rdev->ddev, 0); 4482 rdev->pm.vblank_sync = true; 4483 wake_up(&rdev->irq.vblank_queue); 4484 } 4485 if (atomic_read(&rdev->irq.pflip[0])) 4486 radeon_crtc_handle_flip(rdev, 0); 4487 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 4488 DRM_DEBUG("IH: D1 vblank\n"); 4489 } 4490 break; 4491 case 1: /* D1 vline */ 4492 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) { 4493 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; 4494 DRM_DEBUG("IH: D1 vline\n"); 4495 } 4496 break; 4497 default: 4498 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4499 break; 4500 } 4501 break; 4502 case 5: /* D2 vblank/vline */ 4503 switch (src_data) { 4504 case 0: /* D2 vblank */ 4505 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) { 4506 if (rdev->irq.crtc_vblank_int[1]) { 4507 drm_handle_vblank(rdev->ddev, 1); 4508 rdev->pm.vblank_sync = true; 4509 wake_up(&rdev->irq.vblank_queue); 4510 } 4511 if (atomic_read(&rdev->irq.pflip[1])) 4512 radeon_crtc_handle_flip(rdev, 1); 4513 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; 4514 DRM_DEBUG("IH: D2 vblank\n"); 4515 } 4516 break; 4517 case 1: /* D1 vline */ 4518 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) { 4519 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; 4520 DRM_DEBUG("IH: D2 vline\n"); 4521 } 4522 break; 4523 default: 4524 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4525 break; 4526 } 4527 break; 4528 case 19: /* HPD/DAC hotplug */ 4529 switch (src_data) { 4530 case 0: 4531 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 4532 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; 4533 queue_hotplug = true; 4534 DRM_DEBUG("IH: HPD1\n"); 4535 } 4536 break; 4537 case 1: 4538 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 4539 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; 4540 queue_hotplug = true; 4541 DRM_DEBUG("IH: HPD2\n"); 4542 } 4543 break; 4544 case 4: 4545 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 4546 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; 4547 queue_hotplug = true; 4548 DRM_DEBUG("IH: HPD3\n"); 4549 } 4550 break; 4551 case 5: 4552 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 4553 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; 4554 queue_hotplug = true; 4555 DRM_DEBUG("IH: HPD4\n"); 4556 } 4557 break; 4558 case 10: 4559 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 4560 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; 4561 queue_hotplug = true; 4562 DRM_DEBUG("IH: HPD5\n"); 4563 } 4564 break; 4565 case 12: 4566 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 4567 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; 4568 queue_hotplug = true; 4569 DRM_DEBUG("IH: HPD6\n"); 4570 } 4571 break; 4572 default: 4573 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4574 break; 4575 } 4576 break; 4577 case 21: /* hdmi */ 4578 switch (src_data) { 4579 case 4: 4580 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 4581 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4582 queue_hdmi = true; 4583 DRM_DEBUG("IH: HDMI0\n"); 4584 } 4585 break; 4586 case 5: 4587 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 4588 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4589 queue_hdmi = true; 4590 DRM_DEBUG("IH: HDMI1\n"); 4591 } 4592 break; 4593 default: 4594 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 4595 break; 4596 } 4597 break; 4598 case 176: /* CP_INT in ring buffer */ 4599 case 177: /* CP_INT in IB1 */ 4600 case 178: /* CP_INT in IB2 */ 4601 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); 4602 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4603 break; 4604 case 181: /* CP EOP event */ 4605 DRM_DEBUG("IH: CP EOP\n"); 4606 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4607 break; 4608 case 224: /* DMA trap event */ 4609 DRM_DEBUG("IH: DMA trap\n"); 4610 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); 4611 break; 4612 case 230: /* thermal low to high */ 4613 DRM_DEBUG("IH: thermal low to high\n"); 4614 rdev->pm.dpm.thermal.high_to_low = false; 4615 queue_thermal = true; 4616 break; 4617 case 231: /* thermal high to low */ 4618 DRM_DEBUG("IH: thermal high to low\n"); 4619 rdev->pm.dpm.thermal.high_to_low = true; 4620 queue_thermal = true; 4621 break; 4622 case 233: /* GUI IDLE */ 4623 DRM_DEBUG("IH: GUI idle\n"); 4624 break; 4625 default: 4626 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4627 break; 4628 } 4629 4630 /* wptr/rptr are in bytes! */ 4631 rptr += 16; 4632 rptr &= rdev->ih.ptr_mask; 4633 } 4634 if (queue_hotplug) 4635 schedule_work(&rdev->hotplug_work); 4636 if (queue_hdmi) 4637 schedule_work(&rdev->audio_work); 4638 if (queue_thermal && rdev->pm.dpm_enabled) 4639 schedule_work(&rdev->pm.dpm.thermal.work); 4640 rdev->ih.rptr = rptr; 4641 WREG32(IH_RB_RPTR, rdev->ih.rptr); 4642 atomic_set(&rdev->ih.lock, 0); 4643 4644 /* make sure wptr hasn't changed while processing */ 4645 wptr = r600_get_ih_wptr(rdev); 4646 if (wptr != rptr) 4647 goto restart_ih; 4648 4649 return IRQ_HANDLED; 4650 } 4651 4652 /* 4653 * Debugfs info 4654 */ 4655 #if defined(CONFIG_DEBUG_FS) 4656 4657 static int r600_debugfs_mc_info(struct seq_file *m, void *data) 4658 { 4659 struct drm_info_node *node = (struct drm_info_node *) m->private; 4660 struct drm_device *dev = node->minor->dev; 4661 struct radeon_device *rdev = dev->dev_private; 4662 4663 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); 4664 DREG32_SYS(m, rdev, VM_L2_STATUS); 4665 return 0; 4666 } 4667 4668 static struct drm_info_list r600_mc_info_list[] = { 4669 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, 4670 }; 4671 #endif 4672 4673 int r600_debugfs_mc_info_init(struct radeon_device *rdev) 4674 { 4675 #if defined(CONFIG_DEBUG_FS) 4676 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); 4677 #else 4678 return 0; 4679 #endif 4680 } 4681 4682 /** 4683 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl 4684 * rdev: radeon device structure 4685 * bo: buffer object struct which userspace is waiting for idle 4686 * 4687 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed 4688 * through ring buffer, this leads to corruption in rendering, see 4689 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we 4690 * directly perform HDP flush by writing register through MMIO. 4691 */ 4692 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo) 4693 { 4694 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 4695 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL. 4696 * This seems to cause problems on some AGP cards. Just use the old 4697 * method for them. 4698 */ 4699 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 4700 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { 4701 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; 4702 u32 tmp; 4703 4704 WREG32(HDP_DEBUG1, 0); 4705 tmp = readl((void __iomem *)ptr); 4706 } else 4707 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 4708 } 4709 4710 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) 4711 { 4712 u32 link_width_cntl, mask; 4713 4714 if (rdev->flags & RADEON_IS_IGP) 4715 return; 4716 4717 if (!(rdev->flags & RADEON_IS_PCIE)) 4718 return; 4719 4720 /* x2 cards have a special sequence */ 4721 if (ASIC_IS_X2(rdev)) 4722 return; 4723 4724 radeon_gui_idle(rdev); 4725 4726 switch (lanes) { 4727 case 0: 4728 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 4729 break; 4730 case 1: 4731 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 4732 break; 4733 case 2: 4734 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 4735 break; 4736 case 4: 4737 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 4738 break; 4739 case 8: 4740 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 4741 break; 4742 case 12: 4743 /* not actually supported */ 4744 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 4745 break; 4746 case 16: 4747 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 4748 break; 4749 default: 4750 DRM_ERROR("invalid pcie lane request: %d\n", lanes); 4751 return; 4752 } 4753 4754 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4755 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK; 4756 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT; 4757 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW | 4758 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); 4759 4760 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4761 } 4762 4763 int r600_get_pcie_lanes(struct radeon_device *rdev) 4764 { 4765 u32 link_width_cntl; 4766 4767 if (rdev->flags & RADEON_IS_IGP) 4768 return 0; 4769 4770 if (!(rdev->flags & RADEON_IS_PCIE)) 4771 return 0; 4772 4773 /* x2 cards have a special sequence */ 4774 if (ASIC_IS_X2(rdev)) 4775 return 0; 4776 4777 radeon_gui_idle(rdev); 4778 4779 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4780 4781 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 4782 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4783 return 1; 4784 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4785 return 2; 4786 case RADEON_PCIE_LC_LINK_WIDTH_X4: 4787 return 4; 4788 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4789 return 8; 4790 case RADEON_PCIE_LC_LINK_WIDTH_X12: 4791 /* not actually supported */ 4792 return 12; 4793 case RADEON_PCIE_LC_LINK_WIDTH_X0: 4794 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4795 default: 4796 return 16; 4797 } 4798 } 4799 4800 static void r600_pcie_gen2_enable(struct radeon_device *rdev) 4801 { 4802 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; 4803 u16 link_cntl2; 4804 4805 if (radeon_pcie_gen2 == 0) 4806 return; 4807 4808 if (rdev->flags & RADEON_IS_IGP) 4809 return; 4810 4811 if (!(rdev->flags & RADEON_IS_PCIE)) 4812 return; 4813 4814 /* x2 cards have a special sequence */ 4815 if (ASIC_IS_X2(rdev)) 4816 return; 4817 4818 /* only RV6xx+ chips are supported */ 4819 if (rdev->family <= CHIP_R600) 4820 return; 4821 4822 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && 4823 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) 4824 return; 4825 4826 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4827 if (speed_cntl & LC_CURRENT_DATA_RATE) { 4828 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 4829 return; 4830 } 4831 4832 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 4833 4834 /* 55 nm r6xx asics */ 4835 if ((rdev->family == CHIP_RV670) || 4836 (rdev->family == CHIP_RV620) || 4837 (rdev->family == CHIP_RV635)) { 4838 /* advertise upconfig capability */ 4839 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4840 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4841 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4842 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4843 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 4844 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 4845 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 4846 LC_RECONFIG_ARC_MISSING_ESCAPE); 4847 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; 4848 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4849 } else { 4850 link_width_cntl |= LC_UPCONFIGURE_DIS; 4851 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4852 } 4853 } 4854 4855 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4856 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 4857 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 4858 4859 /* 55 nm r6xx asics */ 4860 if ((rdev->family == CHIP_RV670) || 4861 (rdev->family == CHIP_RV620) || 4862 (rdev->family == CHIP_RV635)) { 4863 WREG32(MM_CFGREGS_CNTL, 0x8); 4864 link_cntl2 = RREG32(0x4088); 4865 WREG32(MM_CFGREGS_CNTL, 0); 4866 /* not supported yet */ 4867 if (link_cntl2 & SELECTABLE_DEEMPHASIS) 4868 return; 4869 } 4870 4871 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; 4872 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); 4873 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; 4874 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; 4875 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; 4876 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4877 4878 tmp = RREG32(0x541c); 4879 WREG32(0x541c, tmp | 0x8); 4880 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); 4881 link_cntl2 = RREG16(0x4088); 4882 link_cntl2 &= ~TARGET_LINK_SPEED_MASK; 4883 link_cntl2 |= 0x2; 4884 WREG16(0x4088, link_cntl2); 4885 WREG32(MM_CFGREGS_CNTL, 0); 4886 4887 if ((rdev->family == CHIP_RV670) || 4888 (rdev->family == CHIP_RV620) || 4889 (rdev->family == CHIP_RV635)) { 4890 training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL); 4891 training_cntl &= ~LC_POINT_7_PLUS_EN; 4892 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl); 4893 } else { 4894 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4895 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 4896 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4897 } 4898 4899 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4900 speed_cntl |= LC_GEN2_EN_STRAP; 4901 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4902 4903 } else { 4904 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4905 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 4906 if (1) 4907 link_width_cntl |= LC_UPCONFIGURE_DIS; 4908 else 4909 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4910 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4911 } 4912 } 4913 4914 /** 4915 * r600_get_gpu_clock_counter - return GPU clock counter snapshot 4916 * 4917 * @rdev: radeon_device pointer 4918 * 4919 * Fetches a GPU clock counter snapshot (R6xx-cayman). 4920 * Returns the 64 bit clock counter snapshot. 4921 */ 4922 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev) 4923 { 4924 uint64_t clock; 4925 4926 mutex_lock(&rdev->gpu_clock_mutex); 4927 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4928 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | 4929 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4930 mutex_unlock(&rdev->gpu_clock_mutex); 4931 return clock; 4932 } 4933