1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/slab.h> 29 #include <linux/seq_file.h> 30 #include <linux/firmware.h> 31 #include <linux/module.h> 32 #include <drm/drmP.h> 33 #include <drm/radeon_drm.h> 34 #include "radeon.h" 35 #include "radeon_asic.h" 36 #include "radeon_audio.h" 37 #include "radeon_mode.h" 38 #include "r600d.h" 39 #include "atom.h" 40 #include "avivod.h" 41 #include "radeon_ucode.h" 42 43 /* Firmware Names */ 44 MODULE_FIRMWARE("radeon/R600_pfp.bin"); 45 MODULE_FIRMWARE("radeon/R600_me.bin"); 46 MODULE_FIRMWARE("radeon/RV610_pfp.bin"); 47 MODULE_FIRMWARE("radeon/RV610_me.bin"); 48 MODULE_FIRMWARE("radeon/RV630_pfp.bin"); 49 MODULE_FIRMWARE("radeon/RV630_me.bin"); 50 MODULE_FIRMWARE("radeon/RV620_pfp.bin"); 51 MODULE_FIRMWARE("radeon/RV620_me.bin"); 52 MODULE_FIRMWARE("radeon/RV635_pfp.bin"); 53 MODULE_FIRMWARE("radeon/RV635_me.bin"); 54 MODULE_FIRMWARE("radeon/RV670_pfp.bin"); 55 MODULE_FIRMWARE("radeon/RV670_me.bin"); 56 MODULE_FIRMWARE("radeon/RS780_pfp.bin"); 57 MODULE_FIRMWARE("radeon/RS780_me.bin"); 58 MODULE_FIRMWARE("radeon/RV770_pfp.bin"); 59 MODULE_FIRMWARE("radeon/RV770_me.bin"); 60 MODULE_FIRMWARE("radeon/RV770_smc.bin"); 61 MODULE_FIRMWARE("radeon/RV730_pfp.bin"); 62 MODULE_FIRMWARE("radeon/RV730_me.bin"); 63 MODULE_FIRMWARE("radeon/RV730_smc.bin"); 64 MODULE_FIRMWARE("radeon/RV740_smc.bin"); 65 MODULE_FIRMWARE("radeon/RV710_pfp.bin"); 66 MODULE_FIRMWARE("radeon/RV710_me.bin"); 67 MODULE_FIRMWARE("radeon/RV710_smc.bin"); 68 MODULE_FIRMWARE("radeon/R600_rlc.bin"); 69 MODULE_FIRMWARE("radeon/R700_rlc.bin"); 70 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); 71 MODULE_FIRMWARE("radeon/CEDAR_me.bin"); 72 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); 73 MODULE_FIRMWARE("radeon/CEDAR_smc.bin"); 74 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); 75 MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); 76 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); 77 MODULE_FIRMWARE("radeon/REDWOOD_smc.bin"); 78 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); 79 MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); 80 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); 81 MODULE_FIRMWARE("radeon/JUNIPER_smc.bin"); 82 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); 83 MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); 84 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); 85 MODULE_FIRMWARE("radeon/CYPRESS_smc.bin"); 86 MODULE_FIRMWARE("radeon/PALM_pfp.bin"); 87 MODULE_FIRMWARE("radeon/PALM_me.bin"); 88 MODULE_FIRMWARE("radeon/SUMO_rlc.bin"); 89 MODULE_FIRMWARE("radeon/SUMO_pfp.bin"); 90 MODULE_FIRMWARE("radeon/SUMO_me.bin"); 91 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin"); 92 MODULE_FIRMWARE("radeon/SUMO2_me.bin"); 93 94 static const u32 crtc_offsets[2] = 95 { 96 0, 97 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 98 }; 99 100 int r600_debugfs_mc_info_init(struct radeon_device *rdev); 101 102 /* r600,rv610,rv630,rv620,rv635,rv670 */ 103 int r600_mc_wait_for_idle(struct radeon_device *rdev); 104 static void r600_gpu_init(struct radeon_device *rdev); 105 void r600_fini(struct radeon_device *rdev); 106 void r600_irq_disable(struct radeon_device *rdev); 107 static void r600_pcie_gen2_enable(struct radeon_device *rdev); 108 extern int evergreen_rlc_resume(struct radeon_device *rdev); 109 extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev); 110 111 /** 112 * r600_get_allowed_info_register - fetch the register for the info ioctl 113 * 114 * @rdev: radeon_device pointer 115 * @reg: register offset in bytes 116 * @val: register value 117 * 118 * Returns 0 for success or -EINVAL for an invalid register 119 * 120 */ 121 int r600_get_allowed_info_register(struct radeon_device *rdev, 122 u32 reg, u32 *val) 123 { 124 switch (reg) { 125 case GRBM_STATUS: 126 case GRBM_STATUS2: 127 case R_000E50_SRBM_STATUS: 128 case DMA_STATUS_REG: 129 case UVD_STATUS: 130 *val = RREG32(reg); 131 return 0; 132 default: 133 return -EINVAL; 134 } 135 } 136 137 /** 138 * r600_get_xclk - get the xclk 139 * 140 * @rdev: radeon_device pointer 141 * 142 * Returns the reference clock used by the gfx engine 143 * (r6xx, IGPs, APUs). 144 */ 145 u32 r600_get_xclk(struct radeon_device *rdev) 146 { 147 return rdev->clock.spll.reference_freq; 148 } 149 150 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) 151 { 152 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; 153 int r; 154 155 /* bypass vclk and dclk with bclk */ 156 WREG32_P(CG_UPLL_FUNC_CNTL_2, 157 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1), 158 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 159 160 /* assert BYPASS_EN, deassert UPLL_RESET, UPLL_SLEEP and UPLL_CTLREQ */ 161 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~( 162 UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK)); 163 164 if (rdev->family >= CHIP_RS780) 165 WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL, 166 ~UPLL_BYPASS_CNTL); 167 168 if (!vclk || !dclk) { 169 /* keep the Bypass mode, put PLL to sleep */ 170 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); 171 return 0; 172 } 173 174 if (rdev->clock.spll.reference_freq == 10000) 175 ref_div = 34; 176 else 177 ref_div = 4; 178 179 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, 180 ref_div + 1, 0xFFF, 2, 30, ~0, 181 &fb_div, &vclk_div, &dclk_div); 182 if (r) 183 return r; 184 185 if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780) 186 fb_div >>= 1; 187 else 188 fb_div |= 1; 189 190 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); 191 if (r) 192 return r; 193 194 /* assert PLL_RESET */ 195 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); 196 197 /* For RS780 we have to choose ref clk */ 198 if (rdev->family >= CHIP_RS780) 199 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK, 200 ~UPLL_REFCLK_SRC_SEL_MASK); 201 202 /* set the required fb, ref and post divder values */ 203 WREG32_P(CG_UPLL_FUNC_CNTL, 204 UPLL_FB_DIV(fb_div) | 205 UPLL_REF_DIV(ref_div), 206 ~(UPLL_FB_DIV_MASK | UPLL_REF_DIV_MASK)); 207 WREG32_P(CG_UPLL_FUNC_CNTL_2, 208 UPLL_SW_HILEN(vclk_div >> 1) | 209 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | 210 UPLL_SW_HILEN2(dclk_div >> 1) | 211 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) | 212 UPLL_DIVEN_MASK | UPLL_DIVEN2_MASK, 213 ~UPLL_SW_MASK); 214 215 /* give the PLL some time to settle */ 216 mdelay(15); 217 218 /* deassert PLL_RESET */ 219 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); 220 221 mdelay(15); 222 223 /* deassert BYPASS EN */ 224 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); 225 226 if (rdev->family >= CHIP_RS780) 227 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~UPLL_BYPASS_CNTL); 228 229 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); 230 if (r) 231 return r; 232 233 /* switch VCLK and DCLK selection */ 234 WREG32_P(CG_UPLL_FUNC_CNTL_2, 235 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2), 236 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 237 238 mdelay(100); 239 240 return 0; 241 } 242 243 void dce3_program_fmt(struct drm_encoder *encoder) 244 { 245 struct drm_device *dev = encoder->dev; 246 struct radeon_device *rdev = dev->dev_private; 247 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 248 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 249 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 250 int bpc = 0; 251 u32 tmp = 0; 252 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE; 253 254 if (connector) { 255 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 256 bpc = radeon_get_monitor_bpc(connector); 257 dither = radeon_connector->dither; 258 } 259 260 /* LVDS FMT is set up by atom */ 261 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 262 return; 263 264 /* not needed for analog */ 265 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 266 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 267 return; 268 269 if (bpc == 0) 270 return; 271 272 switch (bpc) { 273 case 6: 274 if (dither == RADEON_FMT_DITHER_ENABLE) 275 /* XXX sort out optimal dither settings */ 276 tmp |= FMT_SPATIAL_DITHER_EN; 277 else 278 tmp |= FMT_TRUNCATE_EN; 279 break; 280 case 8: 281 if (dither == RADEON_FMT_DITHER_ENABLE) 282 /* XXX sort out optimal dither settings */ 283 tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH); 284 else 285 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH); 286 break; 287 case 10: 288 default: 289 /* not needed */ 290 break; 291 } 292 293 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); 294 } 295 296 /* get temperature in millidegrees */ 297 int rv6xx_get_temp(struct radeon_device *rdev) 298 { 299 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> 300 ASIC_T_SHIFT; 301 int actual_temp = temp & 0xff; 302 303 if (temp & 0x100) 304 actual_temp -= 256; 305 306 return actual_temp * 1000; 307 } 308 309 void r600_pm_get_dynpm_state(struct radeon_device *rdev) 310 { 311 int i; 312 313 rdev->pm.dynpm_can_upclock = true; 314 rdev->pm.dynpm_can_downclock = true; 315 316 /* power state array is low to high, default is first */ 317 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { 318 int min_power_state_index = 0; 319 320 if (rdev->pm.num_power_states > 2) 321 min_power_state_index = 1; 322 323 switch (rdev->pm.dynpm_planned_action) { 324 case DYNPM_ACTION_MINIMUM: 325 rdev->pm.requested_power_state_index = min_power_state_index; 326 rdev->pm.requested_clock_mode_index = 0; 327 rdev->pm.dynpm_can_downclock = false; 328 break; 329 case DYNPM_ACTION_DOWNCLOCK: 330 if (rdev->pm.current_power_state_index == min_power_state_index) { 331 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 332 rdev->pm.dynpm_can_downclock = false; 333 } else { 334 if (rdev->pm.active_crtc_count > 1) { 335 for (i = 0; i < rdev->pm.num_power_states; i++) { 336 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 337 continue; 338 else if (i >= rdev->pm.current_power_state_index) { 339 rdev->pm.requested_power_state_index = 340 rdev->pm.current_power_state_index; 341 break; 342 } else { 343 rdev->pm.requested_power_state_index = i; 344 break; 345 } 346 } 347 } else { 348 if (rdev->pm.current_power_state_index == 0) 349 rdev->pm.requested_power_state_index = 350 rdev->pm.num_power_states - 1; 351 else 352 rdev->pm.requested_power_state_index = 353 rdev->pm.current_power_state_index - 1; 354 } 355 } 356 rdev->pm.requested_clock_mode_index = 0; 357 /* don't use the power state if crtcs are active and no display flag is set */ 358 if ((rdev->pm.active_crtc_count > 0) && 359 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 360 clock_info[rdev->pm.requested_clock_mode_index].flags & 361 RADEON_PM_MODE_NO_DISPLAY)) { 362 rdev->pm.requested_power_state_index++; 363 } 364 break; 365 case DYNPM_ACTION_UPCLOCK: 366 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 367 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 368 rdev->pm.dynpm_can_upclock = false; 369 } else { 370 if (rdev->pm.active_crtc_count > 1) { 371 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 372 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 373 continue; 374 else if (i <= rdev->pm.current_power_state_index) { 375 rdev->pm.requested_power_state_index = 376 rdev->pm.current_power_state_index; 377 break; 378 } else { 379 rdev->pm.requested_power_state_index = i; 380 break; 381 } 382 } 383 } else 384 rdev->pm.requested_power_state_index = 385 rdev->pm.current_power_state_index + 1; 386 } 387 rdev->pm.requested_clock_mode_index = 0; 388 break; 389 case DYNPM_ACTION_DEFAULT: 390 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 391 rdev->pm.requested_clock_mode_index = 0; 392 rdev->pm.dynpm_can_upclock = false; 393 break; 394 case DYNPM_ACTION_NONE: 395 default: 396 DRM_ERROR("Requested mode for not defined action\n"); 397 return; 398 } 399 } else { 400 /* XXX select a power state based on AC/DC, single/dualhead, etc. */ 401 /* for now just select the first power state and switch between clock modes */ 402 /* power state array is low to high, default is first (0) */ 403 if (rdev->pm.active_crtc_count > 1) { 404 rdev->pm.requested_power_state_index = -1; 405 /* start at 1 as we don't want the default mode */ 406 for (i = 1; i < rdev->pm.num_power_states; i++) { 407 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 408 continue; 409 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || 410 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { 411 rdev->pm.requested_power_state_index = i; 412 break; 413 } 414 } 415 /* if nothing selected, grab the default state. */ 416 if (rdev->pm.requested_power_state_index == -1) 417 rdev->pm.requested_power_state_index = 0; 418 } else 419 rdev->pm.requested_power_state_index = 1; 420 421 switch (rdev->pm.dynpm_planned_action) { 422 case DYNPM_ACTION_MINIMUM: 423 rdev->pm.requested_clock_mode_index = 0; 424 rdev->pm.dynpm_can_downclock = false; 425 break; 426 case DYNPM_ACTION_DOWNCLOCK: 427 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 428 if (rdev->pm.current_clock_mode_index == 0) { 429 rdev->pm.requested_clock_mode_index = 0; 430 rdev->pm.dynpm_can_downclock = false; 431 } else 432 rdev->pm.requested_clock_mode_index = 433 rdev->pm.current_clock_mode_index - 1; 434 } else { 435 rdev->pm.requested_clock_mode_index = 0; 436 rdev->pm.dynpm_can_downclock = false; 437 } 438 /* don't use the power state if crtcs are active and no display flag is set */ 439 if ((rdev->pm.active_crtc_count > 0) && 440 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 441 clock_info[rdev->pm.requested_clock_mode_index].flags & 442 RADEON_PM_MODE_NO_DISPLAY)) { 443 rdev->pm.requested_clock_mode_index++; 444 } 445 break; 446 case DYNPM_ACTION_UPCLOCK: 447 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 448 if (rdev->pm.current_clock_mode_index == 449 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { 450 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; 451 rdev->pm.dynpm_can_upclock = false; 452 } else 453 rdev->pm.requested_clock_mode_index = 454 rdev->pm.current_clock_mode_index + 1; 455 } else { 456 rdev->pm.requested_clock_mode_index = 457 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; 458 rdev->pm.dynpm_can_upclock = false; 459 } 460 break; 461 case DYNPM_ACTION_DEFAULT: 462 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 463 rdev->pm.requested_clock_mode_index = 0; 464 rdev->pm.dynpm_can_upclock = false; 465 break; 466 case DYNPM_ACTION_NONE: 467 default: 468 DRM_ERROR("Requested mode for not defined action\n"); 469 return; 470 } 471 } 472 473 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 474 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 475 clock_info[rdev->pm.requested_clock_mode_index].sclk, 476 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 477 clock_info[rdev->pm.requested_clock_mode_index].mclk, 478 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 479 pcie_lanes); 480 } 481 482 void rs780_pm_init_profile(struct radeon_device *rdev) 483 { 484 if (rdev->pm.num_power_states == 2) { 485 /* default */ 486 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 487 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 488 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 489 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 490 /* low sh */ 491 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 492 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 493 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 494 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 495 /* mid sh */ 496 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 497 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 498 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 499 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 500 /* high sh */ 501 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 502 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 503 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 504 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 505 /* low mh */ 506 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 507 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 508 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 509 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 510 /* mid mh */ 511 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 512 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 513 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 514 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 515 /* high mh */ 516 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 517 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; 518 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 519 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 520 } else if (rdev->pm.num_power_states == 3) { 521 /* default */ 522 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 523 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 524 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 525 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 526 /* low sh */ 527 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 528 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 529 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 530 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 531 /* mid sh */ 532 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 533 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 534 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 535 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 536 /* high sh */ 537 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 538 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; 539 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 540 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 541 /* low mh */ 542 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; 543 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; 544 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 545 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 546 /* mid mh */ 547 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; 548 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; 549 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 550 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 551 /* high mh */ 552 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; 553 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 554 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 555 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 556 } else { 557 /* default */ 558 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 559 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 560 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 561 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 562 /* low sh */ 563 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; 564 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; 565 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 566 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 567 /* mid sh */ 568 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; 569 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; 570 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 571 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 572 /* high sh */ 573 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; 574 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; 575 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 576 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 577 /* low mh */ 578 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 579 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 580 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 581 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 582 /* mid mh */ 583 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 584 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 585 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 586 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 587 /* high mh */ 588 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 589 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; 590 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 591 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 592 } 593 } 594 595 void r600_pm_init_profile(struct radeon_device *rdev) 596 { 597 int idx; 598 599 if (rdev->family == CHIP_R600) { 600 /* XXX */ 601 /* default */ 602 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 603 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 604 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 605 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 606 /* low sh */ 607 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 608 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 609 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 610 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 611 /* mid sh */ 612 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 613 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 614 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 615 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 616 /* high sh */ 617 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 618 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 619 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 620 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 621 /* low mh */ 622 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 623 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 624 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 625 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 626 /* mid mh */ 627 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 628 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 629 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 630 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 631 /* high mh */ 632 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 633 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 634 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 635 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 636 } else { 637 if (rdev->pm.num_power_states < 4) { 638 /* default */ 639 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 640 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 641 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 642 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 643 /* low sh */ 644 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 645 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 646 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 647 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 648 /* mid sh */ 649 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 650 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 651 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 652 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 653 /* high sh */ 654 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 655 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 656 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 657 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 658 /* low mh */ 659 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 660 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; 661 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 662 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 663 /* low mh */ 664 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 665 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; 666 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 667 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 668 /* high mh */ 669 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 670 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 671 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 672 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 673 } else { 674 /* default */ 675 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 676 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 677 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 678 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 679 /* low sh */ 680 if (rdev->flags & RADEON_IS_MOBILITY) 681 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 682 else 683 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 684 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; 685 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; 686 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 687 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 688 /* mid sh */ 689 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; 690 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; 691 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 692 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 693 /* high sh */ 694 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 695 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; 696 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; 697 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 698 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 699 /* low mh */ 700 if (rdev->flags & RADEON_IS_MOBILITY) 701 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); 702 else 703 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 704 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; 705 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; 706 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 707 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 708 /* mid mh */ 709 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; 710 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; 711 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 712 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 713 /* high mh */ 714 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 715 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; 716 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; 717 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 718 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 719 } 720 } 721 } 722 723 void r600_pm_misc(struct radeon_device *rdev) 724 { 725 int req_ps_idx = rdev->pm.requested_power_state_index; 726 int req_cm_idx = rdev->pm.requested_clock_mode_index; 727 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 728 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 729 730 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 731 /* 0xff01 is a flag rather then an actual voltage */ 732 if (voltage->voltage == 0xff01) 733 return; 734 if (voltage->voltage != rdev->pm.current_vddc) { 735 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 736 rdev->pm.current_vddc = voltage->voltage; 737 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); 738 } 739 } 740 } 741 742 bool r600_gui_idle(struct radeon_device *rdev) 743 { 744 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) 745 return false; 746 else 747 return true; 748 } 749 750 /* hpd for digital panel detect/disconnect */ 751 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 752 { 753 bool connected = false; 754 755 if (ASIC_IS_DCE3(rdev)) { 756 switch (hpd) { 757 case RADEON_HPD_1: 758 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) 759 connected = true; 760 break; 761 case RADEON_HPD_2: 762 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) 763 connected = true; 764 break; 765 case RADEON_HPD_3: 766 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) 767 connected = true; 768 break; 769 case RADEON_HPD_4: 770 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) 771 connected = true; 772 break; 773 /* DCE 3.2 */ 774 case RADEON_HPD_5: 775 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) 776 connected = true; 777 break; 778 case RADEON_HPD_6: 779 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 780 connected = true; 781 break; 782 default: 783 break; 784 } 785 } else { 786 switch (hpd) { 787 case RADEON_HPD_1: 788 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 789 connected = true; 790 break; 791 case RADEON_HPD_2: 792 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 793 connected = true; 794 break; 795 case RADEON_HPD_3: 796 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 797 connected = true; 798 break; 799 default: 800 break; 801 } 802 } 803 return connected; 804 } 805 806 void r600_hpd_set_polarity(struct radeon_device *rdev, 807 enum radeon_hpd_id hpd) 808 { 809 u32 tmp; 810 bool connected = r600_hpd_sense(rdev, hpd); 811 812 if (ASIC_IS_DCE3(rdev)) { 813 switch (hpd) { 814 case RADEON_HPD_1: 815 tmp = RREG32(DC_HPD1_INT_CONTROL); 816 if (connected) 817 tmp &= ~DC_HPDx_INT_POLARITY; 818 else 819 tmp |= DC_HPDx_INT_POLARITY; 820 WREG32(DC_HPD1_INT_CONTROL, tmp); 821 break; 822 case RADEON_HPD_2: 823 tmp = RREG32(DC_HPD2_INT_CONTROL); 824 if (connected) 825 tmp &= ~DC_HPDx_INT_POLARITY; 826 else 827 tmp |= DC_HPDx_INT_POLARITY; 828 WREG32(DC_HPD2_INT_CONTROL, tmp); 829 break; 830 case RADEON_HPD_3: 831 tmp = RREG32(DC_HPD3_INT_CONTROL); 832 if (connected) 833 tmp &= ~DC_HPDx_INT_POLARITY; 834 else 835 tmp |= DC_HPDx_INT_POLARITY; 836 WREG32(DC_HPD3_INT_CONTROL, tmp); 837 break; 838 case RADEON_HPD_4: 839 tmp = RREG32(DC_HPD4_INT_CONTROL); 840 if (connected) 841 tmp &= ~DC_HPDx_INT_POLARITY; 842 else 843 tmp |= DC_HPDx_INT_POLARITY; 844 WREG32(DC_HPD4_INT_CONTROL, tmp); 845 break; 846 case RADEON_HPD_5: 847 tmp = RREG32(DC_HPD5_INT_CONTROL); 848 if (connected) 849 tmp &= ~DC_HPDx_INT_POLARITY; 850 else 851 tmp |= DC_HPDx_INT_POLARITY; 852 WREG32(DC_HPD5_INT_CONTROL, tmp); 853 break; 854 /* DCE 3.2 */ 855 case RADEON_HPD_6: 856 tmp = RREG32(DC_HPD6_INT_CONTROL); 857 if (connected) 858 tmp &= ~DC_HPDx_INT_POLARITY; 859 else 860 tmp |= DC_HPDx_INT_POLARITY; 861 WREG32(DC_HPD6_INT_CONTROL, tmp); 862 break; 863 default: 864 break; 865 } 866 } else { 867 switch (hpd) { 868 case RADEON_HPD_1: 869 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 870 if (connected) 871 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 872 else 873 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 874 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 875 break; 876 case RADEON_HPD_2: 877 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 878 if (connected) 879 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 880 else 881 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 882 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 883 break; 884 case RADEON_HPD_3: 885 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 886 if (connected) 887 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 888 else 889 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 890 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 891 break; 892 default: 893 break; 894 } 895 } 896 } 897 898 void r600_hpd_init(struct radeon_device *rdev) 899 { 900 struct drm_device *dev = rdev->ddev; 901 struct drm_connector *connector; 902 unsigned enable = 0; 903 904 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 905 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 906 907 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 908 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 909 /* don't try to enable hpd on eDP or LVDS avoid breaking the 910 * aux dp channel on imac and help (but not completely fix) 911 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 912 */ 913 continue; 914 } 915 if (ASIC_IS_DCE3(rdev)) { 916 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); 917 if (ASIC_IS_DCE32(rdev)) 918 tmp |= DC_HPDx_EN; 919 920 switch (radeon_connector->hpd.hpd) { 921 case RADEON_HPD_1: 922 WREG32(DC_HPD1_CONTROL, tmp); 923 break; 924 case RADEON_HPD_2: 925 WREG32(DC_HPD2_CONTROL, tmp); 926 break; 927 case RADEON_HPD_3: 928 WREG32(DC_HPD3_CONTROL, tmp); 929 break; 930 case RADEON_HPD_4: 931 WREG32(DC_HPD4_CONTROL, tmp); 932 break; 933 /* DCE 3.2 */ 934 case RADEON_HPD_5: 935 WREG32(DC_HPD5_CONTROL, tmp); 936 break; 937 case RADEON_HPD_6: 938 WREG32(DC_HPD6_CONTROL, tmp); 939 break; 940 default: 941 break; 942 } 943 } else { 944 switch (radeon_connector->hpd.hpd) { 945 case RADEON_HPD_1: 946 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); 947 break; 948 case RADEON_HPD_2: 949 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); 950 break; 951 case RADEON_HPD_3: 952 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); 953 break; 954 default: 955 break; 956 } 957 } 958 enable |= 1 << radeon_connector->hpd.hpd; 959 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 960 } 961 radeon_irq_kms_enable_hpd(rdev, enable); 962 } 963 964 void r600_hpd_fini(struct radeon_device *rdev) 965 { 966 struct drm_device *dev = rdev->ddev; 967 struct drm_connector *connector; 968 unsigned disable = 0; 969 970 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 971 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 972 if (ASIC_IS_DCE3(rdev)) { 973 switch (radeon_connector->hpd.hpd) { 974 case RADEON_HPD_1: 975 WREG32(DC_HPD1_CONTROL, 0); 976 break; 977 case RADEON_HPD_2: 978 WREG32(DC_HPD2_CONTROL, 0); 979 break; 980 case RADEON_HPD_3: 981 WREG32(DC_HPD3_CONTROL, 0); 982 break; 983 case RADEON_HPD_4: 984 WREG32(DC_HPD4_CONTROL, 0); 985 break; 986 /* DCE 3.2 */ 987 case RADEON_HPD_5: 988 WREG32(DC_HPD5_CONTROL, 0); 989 break; 990 case RADEON_HPD_6: 991 WREG32(DC_HPD6_CONTROL, 0); 992 break; 993 default: 994 break; 995 } 996 } else { 997 switch (radeon_connector->hpd.hpd) { 998 case RADEON_HPD_1: 999 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); 1000 break; 1001 case RADEON_HPD_2: 1002 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); 1003 break; 1004 case RADEON_HPD_3: 1005 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); 1006 break; 1007 default: 1008 break; 1009 } 1010 } 1011 disable |= 1 << radeon_connector->hpd.hpd; 1012 } 1013 radeon_irq_kms_disable_hpd(rdev, disable); 1014 } 1015 1016 /* 1017 * R600 PCIE GART 1018 */ 1019 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) 1020 { 1021 unsigned i; 1022 u32 tmp; 1023 1024 /* flush hdp cache so updates hit vram */ 1025 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 1026 !(rdev->flags & RADEON_IS_AGP)) { 1027 void __iomem *ptr = (void *)rdev->gart.ptr; 1028 u32 tmp; 1029 1030 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 1031 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 1032 * This seems to cause problems on some AGP cards. Just use the old 1033 * method for them. 1034 */ 1035 WREG32(HDP_DEBUG1, 0); 1036 tmp = readl((void __iomem *)ptr); 1037 } else 1038 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 1039 1040 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); 1041 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); 1042 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 1043 for (i = 0; i < rdev->usec_timeout; i++) { 1044 /* read MC_STATUS */ 1045 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); 1046 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; 1047 if (tmp == 2) { 1048 printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); 1049 return; 1050 } 1051 if (tmp) { 1052 return; 1053 } 1054 udelay(1); 1055 } 1056 } 1057 1058 int r600_pcie_gart_init(struct radeon_device *rdev) 1059 { 1060 int r; 1061 1062 if (rdev->gart.robj) { 1063 WARN(1, "R600 PCIE GART already initialized\n"); 1064 return 0; 1065 } 1066 /* Initialize common gart structure */ 1067 r = radeon_gart_init(rdev); 1068 if (r) 1069 return r; 1070 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 1071 return radeon_gart_table_vram_alloc(rdev); 1072 } 1073 1074 static int r600_pcie_gart_enable(struct radeon_device *rdev) 1075 { 1076 u32 tmp; 1077 int r, i; 1078 1079 if (rdev->gart.robj == NULL) { 1080 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 1081 return -EINVAL; 1082 } 1083 r = radeon_gart_table_vram_pin(rdev); 1084 if (r) 1085 return r; 1086 1087 /* Setup L2 cache */ 1088 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1089 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1090 EFFECTIVE_L2_QUEUE_SIZE(7)); 1091 WREG32(VM_L2_CNTL2, 0); 1092 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1093 /* Setup TLB control */ 1094 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1095 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1096 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1097 ENABLE_WAIT_L2_QUERY; 1098 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1099 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1100 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 1101 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1102 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1103 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1104 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1105 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1106 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1107 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1108 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1109 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1110 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); 1111 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); 1112 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1113 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1114 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 1115 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 1116 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 1117 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 1118 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 1119 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 1120 (u32)(rdev->dummy_page.addr >> 12)); 1121 for (i = 1; i < 7; i++) 1122 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1123 1124 r600_pcie_gart_tlb_flush(rdev); 1125 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1126 (unsigned)(rdev->mc.gtt_size >> 20), 1127 (unsigned long long)rdev->gart.table_addr); 1128 rdev->gart.ready = true; 1129 return 0; 1130 } 1131 1132 static void r600_pcie_gart_disable(struct radeon_device *rdev) 1133 { 1134 u32 tmp; 1135 int i; 1136 1137 /* Disable all tables */ 1138 for (i = 0; i < 7; i++) 1139 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1140 1141 /* Disable L2 cache */ 1142 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 1143 EFFECTIVE_L2_QUEUE_SIZE(7)); 1144 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1145 /* Setup L1 TLB control */ 1146 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1147 ENABLE_WAIT_L2_QUERY; 1148 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1149 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1150 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1151 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1152 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1153 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1154 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1155 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1156 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); 1157 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); 1158 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1159 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1160 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); 1161 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1162 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); 1163 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); 1164 radeon_gart_table_vram_unpin(rdev); 1165 } 1166 1167 static void r600_pcie_gart_fini(struct radeon_device *rdev) 1168 { 1169 radeon_gart_fini(rdev); 1170 r600_pcie_gart_disable(rdev); 1171 radeon_gart_table_vram_free(rdev); 1172 } 1173 1174 static void r600_agp_enable(struct radeon_device *rdev) 1175 { 1176 u32 tmp; 1177 int i; 1178 1179 /* Setup L2 cache */ 1180 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1181 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1182 EFFECTIVE_L2_QUEUE_SIZE(7)); 1183 WREG32(VM_L2_CNTL2, 0); 1184 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 1185 /* Setup TLB control */ 1186 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1187 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1188 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 1189 ENABLE_WAIT_L2_QUERY; 1190 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 1191 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 1192 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 1193 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1194 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1195 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1196 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1197 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1198 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1199 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1200 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1201 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1202 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1203 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1204 for (i = 0; i < 7; i++) 1205 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1206 } 1207 1208 int r600_mc_wait_for_idle(struct radeon_device *rdev) 1209 { 1210 unsigned i; 1211 u32 tmp; 1212 1213 for (i = 0; i < rdev->usec_timeout; i++) { 1214 /* read MC_STATUS */ 1215 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; 1216 if (!tmp) 1217 return 0; 1218 udelay(1); 1219 } 1220 return -1; 1221 } 1222 1223 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg) 1224 { 1225 unsigned long flags; 1226 uint32_t r; 1227 1228 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 1229 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg)); 1230 r = RREG32(R_0028FC_MC_DATA); 1231 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR); 1232 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 1233 return r; 1234 } 1235 1236 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1237 { 1238 unsigned long flags; 1239 1240 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 1241 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) | 1242 S_0028F8_MC_IND_WR_EN(1)); 1243 WREG32(R_0028FC_MC_DATA, v); 1244 WREG32(R_0028F8_MC_INDEX, 0x7F); 1245 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 1246 } 1247 1248 static void r600_mc_program(struct radeon_device *rdev) 1249 { 1250 struct rv515_mc_save save; 1251 u32 tmp; 1252 int i, j; 1253 1254 /* Initialize HDP */ 1255 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1256 WREG32((0x2c14 + j), 0x00000000); 1257 WREG32((0x2c18 + j), 0x00000000); 1258 WREG32((0x2c1c + j), 0x00000000); 1259 WREG32((0x2c20 + j), 0x00000000); 1260 WREG32((0x2c24 + j), 0x00000000); 1261 } 1262 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 1263 1264 rv515_mc_stop(rdev, &save); 1265 if (r600_mc_wait_for_idle(rdev)) { 1266 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1267 } 1268 /* Lockout access through VGA aperture (doesn't exist before R600) */ 1269 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1270 /* Update configuration */ 1271 if (rdev->flags & RADEON_IS_AGP) { 1272 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1273 /* VRAM before AGP */ 1274 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1275 rdev->mc.vram_start >> 12); 1276 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1277 rdev->mc.gtt_end >> 12); 1278 } else { 1279 /* VRAM after AGP */ 1280 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1281 rdev->mc.gtt_start >> 12); 1282 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1283 rdev->mc.vram_end >> 12); 1284 } 1285 } else { 1286 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); 1287 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); 1288 } 1289 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 1290 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1291 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1292 WREG32(MC_VM_FB_LOCATION, tmp); 1293 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1294 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 1295 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1296 if (rdev->flags & RADEON_IS_AGP) { 1297 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); 1298 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); 1299 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1300 } else { 1301 WREG32(MC_VM_AGP_BASE, 0); 1302 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1303 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1304 } 1305 if (r600_mc_wait_for_idle(rdev)) { 1306 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1307 } 1308 rv515_mc_resume(rdev, &save); 1309 /* we need to own VRAM, so turn off the VGA renderer here 1310 * to stop it overwriting our objects */ 1311 rv515_vga_render_disable(rdev); 1312 } 1313 1314 /** 1315 * r600_vram_gtt_location - try to find VRAM & GTT location 1316 * @rdev: radeon device structure holding all necessary informations 1317 * @mc: memory controller structure holding memory informations 1318 * 1319 * Function will place try to place VRAM at same place as in CPU (PCI) 1320 * address space as some GPU seems to have issue when we reprogram at 1321 * different address space. 1322 * 1323 * If there is not enough space to fit the unvisible VRAM after the 1324 * aperture then we limit the VRAM size to the aperture. 1325 * 1326 * If we are using AGP then place VRAM adjacent to AGP aperture are we need 1327 * them to be in one from GPU point of view so that we can program GPU to 1328 * catch access outside them (weird GPU policy see ??). 1329 * 1330 * This function will never fails, worst case are limiting VRAM or GTT. 1331 * 1332 * Note: GTT start, end, size should be initialized before calling this 1333 * function on AGP platform. 1334 */ 1335 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 1336 { 1337 u64 size_bf, size_af; 1338 1339 if (mc->mc_vram_size > 0xE0000000) { 1340 /* leave room for at least 512M GTT */ 1341 dev_warn(rdev->dev, "limiting VRAM\n"); 1342 mc->real_vram_size = 0xE0000000; 1343 mc->mc_vram_size = 0xE0000000; 1344 } 1345 if (rdev->flags & RADEON_IS_AGP) { 1346 size_bf = mc->gtt_start; 1347 size_af = mc->mc_mask - mc->gtt_end; 1348 if (size_bf > size_af) { 1349 if (mc->mc_vram_size > size_bf) { 1350 dev_warn(rdev->dev, "limiting VRAM\n"); 1351 mc->real_vram_size = size_bf; 1352 mc->mc_vram_size = size_bf; 1353 } 1354 mc->vram_start = mc->gtt_start - mc->mc_vram_size; 1355 } else { 1356 if (mc->mc_vram_size > size_af) { 1357 dev_warn(rdev->dev, "limiting VRAM\n"); 1358 mc->real_vram_size = size_af; 1359 mc->mc_vram_size = size_af; 1360 } 1361 mc->vram_start = mc->gtt_end + 1; 1362 } 1363 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 1364 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", 1365 mc->mc_vram_size >> 20, mc->vram_start, 1366 mc->vram_end, mc->real_vram_size >> 20); 1367 } else { 1368 u64 base = 0; 1369 if (rdev->flags & RADEON_IS_IGP) { 1370 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; 1371 base <<= 24; 1372 } 1373 radeon_vram_location(rdev, &rdev->mc, base); 1374 rdev->mc.gtt_base_align = 0; 1375 radeon_gtt_location(rdev, mc); 1376 } 1377 } 1378 1379 static int r600_mc_init(struct radeon_device *rdev) 1380 { 1381 u32 tmp; 1382 int chansize, numchan; 1383 uint32_t h_addr, l_addr; 1384 unsigned long long k8_addr; 1385 1386 /* Get VRAM informations */ 1387 rdev->mc.vram_is_ddr = true; 1388 tmp = RREG32(RAMCFG); 1389 if (tmp & CHANSIZE_OVERRIDE) { 1390 chansize = 16; 1391 } else if (tmp & CHANSIZE_MASK) { 1392 chansize = 64; 1393 } else { 1394 chansize = 32; 1395 } 1396 tmp = RREG32(CHMAP); 1397 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1398 case 0: 1399 default: 1400 numchan = 1; 1401 break; 1402 case 1: 1403 numchan = 2; 1404 break; 1405 case 2: 1406 numchan = 4; 1407 break; 1408 case 3: 1409 numchan = 8; 1410 break; 1411 } 1412 rdev->mc.vram_width = numchan * chansize; 1413 /* Could aper size report 0 ? */ 1414 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 1415 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 1416 /* Setup GPU memory space */ 1417 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1418 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1419 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1420 r600_vram_gtt_location(rdev, &rdev->mc); 1421 1422 if (rdev->flags & RADEON_IS_IGP) { 1423 rs690_pm_info(rdev); 1424 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 1425 1426 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 1427 /* Use K8 direct mapping for fast fb access. */ 1428 rdev->fastfb_working = false; 1429 h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL)); 1430 l_addr = RREG32_MC(R_000011_K8_FB_LOCATION); 1431 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr; 1432 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE) 1433 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) 1434 #endif 1435 { 1436 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport 1437 * memory is present. 1438 */ 1439 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { 1440 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n", 1441 (unsigned long long)rdev->mc.aper_base, k8_addr); 1442 rdev->mc.aper_base = (resource_size_t)k8_addr; 1443 rdev->fastfb_working = true; 1444 } 1445 } 1446 } 1447 } 1448 1449 radeon_update_bandwidth_info(rdev); 1450 return 0; 1451 } 1452 1453 int r600_vram_scratch_init(struct radeon_device *rdev) 1454 { 1455 int r; 1456 1457 if (rdev->vram_scratch.robj == NULL) { 1458 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, 1459 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 1460 0, NULL, NULL, &rdev->vram_scratch.robj); 1461 if (r) { 1462 return r; 1463 } 1464 } 1465 1466 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1467 if (unlikely(r != 0)) 1468 return r; 1469 r = radeon_bo_pin(rdev->vram_scratch.robj, 1470 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); 1471 if (r) { 1472 radeon_bo_unreserve(rdev->vram_scratch.robj); 1473 return r; 1474 } 1475 r = radeon_bo_kmap(rdev->vram_scratch.robj, 1476 (void **)&rdev->vram_scratch.ptr); 1477 if (r) 1478 radeon_bo_unpin(rdev->vram_scratch.robj); 1479 radeon_bo_unreserve(rdev->vram_scratch.robj); 1480 1481 return r; 1482 } 1483 1484 void r600_vram_scratch_fini(struct radeon_device *rdev) 1485 { 1486 int r; 1487 1488 if (rdev->vram_scratch.robj == NULL) { 1489 return; 1490 } 1491 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1492 if (likely(r == 0)) { 1493 radeon_bo_kunmap(rdev->vram_scratch.robj); 1494 radeon_bo_unpin(rdev->vram_scratch.robj); 1495 radeon_bo_unreserve(rdev->vram_scratch.robj); 1496 } 1497 radeon_bo_unref(&rdev->vram_scratch.robj); 1498 } 1499 1500 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung) 1501 { 1502 u32 tmp = RREG32(R600_BIOS_3_SCRATCH); 1503 1504 if (hung) 1505 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1506 else 1507 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1508 1509 WREG32(R600_BIOS_3_SCRATCH, tmp); 1510 } 1511 1512 static void r600_print_gpu_status_regs(struct radeon_device *rdev) 1513 { 1514 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", 1515 RREG32(R_008010_GRBM_STATUS)); 1516 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", 1517 RREG32(R_008014_GRBM_STATUS2)); 1518 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", 1519 RREG32(R_000E50_SRBM_STATUS)); 1520 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1521 RREG32(CP_STALLED_STAT1)); 1522 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 1523 RREG32(CP_STALLED_STAT2)); 1524 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 1525 RREG32(CP_BUSY_STAT)); 1526 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 1527 RREG32(CP_STAT)); 1528 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 1529 RREG32(DMA_STATUS_REG)); 1530 } 1531 1532 static bool r600_is_display_hung(struct radeon_device *rdev) 1533 { 1534 u32 crtc_hung = 0; 1535 u32 crtc_status[2]; 1536 u32 i, j, tmp; 1537 1538 for (i = 0; i < rdev->num_crtc; i++) { 1539 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { 1540 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1541 crtc_hung |= (1 << i); 1542 } 1543 } 1544 1545 for (j = 0; j < 10; j++) { 1546 for (i = 0; i < rdev->num_crtc; i++) { 1547 if (crtc_hung & (1 << i)) { 1548 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); 1549 if (tmp != crtc_status[i]) 1550 crtc_hung &= ~(1 << i); 1551 } 1552 } 1553 if (crtc_hung == 0) 1554 return false; 1555 udelay(100); 1556 } 1557 1558 return true; 1559 } 1560 1561 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev) 1562 { 1563 u32 reset_mask = 0; 1564 u32 tmp; 1565 1566 /* GRBM_STATUS */ 1567 tmp = RREG32(R_008010_GRBM_STATUS); 1568 if (rdev->family >= CHIP_RV770) { 1569 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1570 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1571 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1572 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1573 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1574 reset_mask |= RADEON_RESET_GFX; 1575 } else { 1576 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | 1577 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | 1578 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | 1579 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | 1580 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) 1581 reset_mask |= RADEON_RESET_GFX; 1582 } 1583 1584 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) | 1585 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp)) 1586 reset_mask |= RADEON_RESET_CP; 1587 1588 if (G_008010_GRBM_EE_BUSY(tmp)) 1589 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; 1590 1591 /* DMA_STATUS_REG */ 1592 tmp = RREG32(DMA_STATUS_REG); 1593 if (!(tmp & DMA_IDLE)) 1594 reset_mask |= RADEON_RESET_DMA; 1595 1596 /* SRBM_STATUS */ 1597 tmp = RREG32(R_000E50_SRBM_STATUS); 1598 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp)) 1599 reset_mask |= RADEON_RESET_RLC; 1600 1601 if (G_000E50_IH_BUSY(tmp)) 1602 reset_mask |= RADEON_RESET_IH; 1603 1604 if (G_000E50_SEM_BUSY(tmp)) 1605 reset_mask |= RADEON_RESET_SEM; 1606 1607 if (G_000E50_GRBM_RQ_PENDING(tmp)) 1608 reset_mask |= RADEON_RESET_GRBM; 1609 1610 if (G_000E50_VMC_BUSY(tmp)) 1611 reset_mask |= RADEON_RESET_VMC; 1612 1613 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) | 1614 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) | 1615 G_000E50_MCDW_BUSY(tmp)) 1616 reset_mask |= RADEON_RESET_MC; 1617 1618 if (r600_is_display_hung(rdev)) 1619 reset_mask |= RADEON_RESET_DISPLAY; 1620 1621 /* Skip MC reset as it's mostly likely not hung, just busy */ 1622 if (reset_mask & RADEON_RESET_MC) { 1623 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); 1624 reset_mask &= ~RADEON_RESET_MC; 1625 } 1626 1627 return reset_mask; 1628 } 1629 1630 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 1631 { 1632 struct rv515_mc_save save; 1633 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 1634 u32 tmp; 1635 1636 if (reset_mask == 0) 1637 return; 1638 1639 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1640 1641 r600_print_gpu_status_regs(rdev); 1642 1643 /* Disable CP parsing/prefetching */ 1644 if (rdev->family >= CHIP_RV770) 1645 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); 1646 else 1647 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1648 1649 /* disable the RLC */ 1650 WREG32(RLC_CNTL, 0); 1651 1652 if (reset_mask & RADEON_RESET_DMA) { 1653 /* Disable DMA */ 1654 tmp = RREG32(DMA_RB_CNTL); 1655 tmp &= ~DMA_RB_ENABLE; 1656 WREG32(DMA_RB_CNTL, tmp); 1657 } 1658 1659 mdelay(50); 1660 1661 rv515_mc_stop(rdev, &save); 1662 if (r600_mc_wait_for_idle(rdev)) { 1663 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1664 } 1665 1666 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { 1667 if (rdev->family >= CHIP_RV770) 1668 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) | 1669 S_008020_SOFT_RESET_CB(1) | 1670 S_008020_SOFT_RESET_PA(1) | 1671 S_008020_SOFT_RESET_SC(1) | 1672 S_008020_SOFT_RESET_SPI(1) | 1673 S_008020_SOFT_RESET_SX(1) | 1674 S_008020_SOFT_RESET_SH(1) | 1675 S_008020_SOFT_RESET_TC(1) | 1676 S_008020_SOFT_RESET_TA(1) | 1677 S_008020_SOFT_RESET_VC(1) | 1678 S_008020_SOFT_RESET_VGT(1); 1679 else 1680 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) | 1681 S_008020_SOFT_RESET_DB(1) | 1682 S_008020_SOFT_RESET_CB(1) | 1683 S_008020_SOFT_RESET_PA(1) | 1684 S_008020_SOFT_RESET_SC(1) | 1685 S_008020_SOFT_RESET_SMX(1) | 1686 S_008020_SOFT_RESET_SPI(1) | 1687 S_008020_SOFT_RESET_SX(1) | 1688 S_008020_SOFT_RESET_SH(1) | 1689 S_008020_SOFT_RESET_TC(1) | 1690 S_008020_SOFT_RESET_TA(1) | 1691 S_008020_SOFT_RESET_VC(1) | 1692 S_008020_SOFT_RESET_VGT(1); 1693 } 1694 1695 if (reset_mask & RADEON_RESET_CP) { 1696 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) | 1697 S_008020_SOFT_RESET_VGT(1); 1698 1699 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1700 } 1701 1702 if (reset_mask & RADEON_RESET_DMA) { 1703 if (rdev->family >= CHIP_RV770) 1704 srbm_soft_reset |= RV770_SOFT_RESET_DMA; 1705 else 1706 srbm_soft_reset |= SOFT_RESET_DMA; 1707 } 1708 1709 if (reset_mask & RADEON_RESET_RLC) 1710 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1); 1711 1712 if (reset_mask & RADEON_RESET_SEM) 1713 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1); 1714 1715 if (reset_mask & RADEON_RESET_IH) 1716 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1); 1717 1718 if (reset_mask & RADEON_RESET_GRBM) 1719 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); 1720 1721 if (!(rdev->flags & RADEON_IS_IGP)) { 1722 if (reset_mask & RADEON_RESET_MC) 1723 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1); 1724 } 1725 1726 if (reset_mask & RADEON_RESET_VMC) 1727 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1); 1728 1729 if (grbm_soft_reset) { 1730 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1731 tmp |= grbm_soft_reset; 1732 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 1733 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1734 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1735 1736 udelay(50); 1737 1738 tmp &= ~grbm_soft_reset; 1739 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1740 tmp = RREG32(R_008020_GRBM_SOFT_RESET); 1741 } 1742 1743 if (srbm_soft_reset) { 1744 tmp = RREG32(SRBM_SOFT_RESET); 1745 tmp |= srbm_soft_reset; 1746 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1747 WREG32(SRBM_SOFT_RESET, tmp); 1748 tmp = RREG32(SRBM_SOFT_RESET); 1749 1750 udelay(50); 1751 1752 tmp &= ~srbm_soft_reset; 1753 WREG32(SRBM_SOFT_RESET, tmp); 1754 tmp = RREG32(SRBM_SOFT_RESET); 1755 } 1756 1757 /* Wait a little for things to settle down */ 1758 mdelay(1); 1759 1760 rv515_mc_resume(rdev, &save); 1761 udelay(50); 1762 1763 r600_print_gpu_status_regs(rdev); 1764 } 1765 1766 static void r600_gpu_pci_config_reset(struct radeon_device *rdev) 1767 { 1768 struct rv515_mc_save save; 1769 u32 tmp, i; 1770 1771 dev_info(rdev->dev, "GPU pci config reset\n"); 1772 1773 /* disable dpm? */ 1774 1775 /* Disable CP parsing/prefetching */ 1776 if (rdev->family >= CHIP_RV770) 1777 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); 1778 else 1779 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1780 1781 /* disable the RLC */ 1782 WREG32(RLC_CNTL, 0); 1783 1784 /* Disable DMA */ 1785 tmp = RREG32(DMA_RB_CNTL); 1786 tmp &= ~DMA_RB_ENABLE; 1787 WREG32(DMA_RB_CNTL, tmp); 1788 1789 mdelay(50); 1790 1791 /* set mclk/sclk to bypass */ 1792 if (rdev->family >= CHIP_RV770) 1793 rv770_set_clk_bypass_mode(rdev); 1794 /* disable BM */ 1795 pci_clear_master(rdev->pdev); 1796 /* disable mem access */ 1797 rv515_mc_stop(rdev, &save); 1798 if (r600_mc_wait_for_idle(rdev)) { 1799 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1800 } 1801 1802 /* BIF reset workaround. Not sure if this is needed on 6xx */ 1803 tmp = RREG32(BUS_CNTL); 1804 tmp |= VGA_COHE_SPEC_TIMER_DIS; 1805 WREG32(BUS_CNTL, tmp); 1806 1807 tmp = RREG32(BIF_SCRATCH0); 1808 1809 /* reset */ 1810 radeon_pci_config_reset(rdev); 1811 mdelay(1); 1812 1813 /* BIF reset workaround. Not sure if this is needed on 6xx */ 1814 tmp = SOFT_RESET_BIF; 1815 WREG32(SRBM_SOFT_RESET, tmp); 1816 mdelay(1); 1817 WREG32(SRBM_SOFT_RESET, 0); 1818 1819 /* wait for asic to come out of reset */ 1820 for (i = 0; i < rdev->usec_timeout; i++) { 1821 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) 1822 break; 1823 udelay(1); 1824 } 1825 } 1826 1827 int r600_asic_reset(struct radeon_device *rdev) 1828 { 1829 u32 reset_mask; 1830 1831 reset_mask = r600_gpu_check_soft_reset(rdev); 1832 1833 if (reset_mask) 1834 r600_set_bios_scratch_engine_hung(rdev, true); 1835 1836 /* try soft reset */ 1837 r600_gpu_soft_reset(rdev, reset_mask); 1838 1839 reset_mask = r600_gpu_check_soft_reset(rdev); 1840 1841 /* try pci config reset */ 1842 if (reset_mask && radeon_hard_reset) 1843 r600_gpu_pci_config_reset(rdev); 1844 1845 reset_mask = r600_gpu_check_soft_reset(rdev); 1846 1847 if (!reset_mask) 1848 r600_set_bios_scratch_engine_hung(rdev, false); 1849 1850 return 0; 1851 } 1852 1853 /** 1854 * r600_gfx_is_lockup - Check if the GFX engine is locked up 1855 * 1856 * @rdev: radeon_device pointer 1857 * @ring: radeon_ring structure holding ring information 1858 * 1859 * Check if the GFX engine is locked up. 1860 * Returns true if the engine appears to be locked up, false if not. 1861 */ 1862 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1863 { 1864 u32 reset_mask = r600_gpu_check_soft_reset(rdev); 1865 1866 if (!(reset_mask & (RADEON_RESET_GFX | 1867 RADEON_RESET_COMPUTE | 1868 RADEON_RESET_CP))) { 1869 radeon_ring_lockup_update(rdev, ring); 1870 return false; 1871 } 1872 return radeon_ring_test_lockup(rdev, ring); 1873 } 1874 1875 u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1876 u32 tiling_pipe_num, 1877 u32 max_rb_num, 1878 u32 total_max_rb_num, 1879 u32 disabled_rb_mask) 1880 { 1881 u32 rendering_pipe_num, rb_num_width, req_rb_num; 1882 u32 pipe_rb_ratio, pipe_rb_remain, tmp; 1883 u32 data = 0, mask = 1 << (max_rb_num - 1); 1884 unsigned i, j; 1885 1886 /* mask out the RBs that don't exist on that asic */ 1887 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff); 1888 /* make sure at least one RB is available */ 1889 if ((tmp & 0xff) != 0xff) 1890 disabled_rb_mask = tmp; 1891 1892 rendering_pipe_num = 1 << tiling_pipe_num; 1893 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); 1894 BUG_ON(rendering_pipe_num < req_rb_num); 1895 1896 pipe_rb_ratio = rendering_pipe_num / req_rb_num; 1897 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num; 1898 1899 if (rdev->family <= CHIP_RV740) { 1900 /* r6xx/r7xx */ 1901 rb_num_width = 2; 1902 } else { 1903 /* eg+ */ 1904 rb_num_width = 4; 1905 } 1906 1907 for (i = 0; i < max_rb_num; i++) { 1908 if (!(mask & disabled_rb_mask)) { 1909 for (j = 0; j < pipe_rb_ratio; j++) { 1910 data <<= rb_num_width; 1911 data |= max_rb_num - i - 1; 1912 } 1913 if (pipe_rb_remain) { 1914 data <<= rb_num_width; 1915 data |= max_rb_num - i - 1; 1916 pipe_rb_remain--; 1917 } 1918 } 1919 mask >>= 1; 1920 } 1921 1922 return data; 1923 } 1924 1925 int r600_count_pipe_bits(uint32_t val) 1926 { 1927 return hweight32(val); 1928 } 1929 1930 static void r600_gpu_init(struct radeon_device *rdev) 1931 { 1932 u32 tiling_config; 1933 u32 ramcfg; 1934 u32 cc_gc_shader_pipe_config; 1935 u32 tmp; 1936 int i, j; 1937 u32 sq_config; 1938 u32 sq_gpr_resource_mgmt_1 = 0; 1939 u32 sq_gpr_resource_mgmt_2 = 0; 1940 u32 sq_thread_resource_mgmt = 0; 1941 u32 sq_stack_resource_mgmt_1 = 0; 1942 u32 sq_stack_resource_mgmt_2 = 0; 1943 u32 disabled_rb_mask; 1944 1945 rdev->config.r600.tiling_group_size = 256; 1946 switch (rdev->family) { 1947 case CHIP_R600: 1948 rdev->config.r600.max_pipes = 4; 1949 rdev->config.r600.max_tile_pipes = 8; 1950 rdev->config.r600.max_simds = 4; 1951 rdev->config.r600.max_backends = 4; 1952 rdev->config.r600.max_gprs = 256; 1953 rdev->config.r600.max_threads = 192; 1954 rdev->config.r600.max_stack_entries = 256; 1955 rdev->config.r600.max_hw_contexts = 8; 1956 rdev->config.r600.max_gs_threads = 16; 1957 rdev->config.r600.sx_max_export_size = 128; 1958 rdev->config.r600.sx_max_export_pos_size = 16; 1959 rdev->config.r600.sx_max_export_smx_size = 128; 1960 rdev->config.r600.sq_num_cf_insts = 2; 1961 break; 1962 case CHIP_RV630: 1963 case CHIP_RV635: 1964 rdev->config.r600.max_pipes = 2; 1965 rdev->config.r600.max_tile_pipes = 2; 1966 rdev->config.r600.max_simds = 3; 1967 rdev->config.r600.max_backends = 1; 1968 rdev->config.r600.max_gprs = 128; 1969 rdev->config.r600.max_threads = 192; 1970 rdev->config.r600.max_stack_entries = 128; 1971 rdev->config.r600.max_hw_contexts = 8; 1972 rdev->config.r600.max_gs_threads = 4; 1973 rdev->config.r600.sx_max_export_size = 128; 1974 rdev->config.r600.sx_max_export_pos_size = 16; 1975 rdev->config.r600.sx_max_export_smx_size = 128; 1976 rdev->config.r600.sq_num_cf_insts = 2; 1977 break; 1978 case CHIP_RV610: 1979 case CHIP_RV620: 1980 case CHIP_RS780: 1981 case CHIP_RS880: 1982 rdev->config.r600.max_pipes = 1; 1983 rdev->config.r600.max_tile_pipes = 1; 1984 rdev->config.r600.max_simds = 2; 1985 rdev->config.r600.max_backends = 1; 1986 rdev->config.r600.max_gprs = 128; 1987 rdev->config.r600.max_threads = 192; 1988 rdev->config.r600.max_stack_entries = 128; 1989 rdev->config.r600.max_hw_contexts = 4; 1990 rdev->config.r600.max_gs_threads = 4; 1991 rdev->config.r600.sx_max_export_size = 128; 1992 rdev->config.r600.sx_max_export_pos_size = 16; 1993 rdev->config.r600.sx_max_export_smx_size = 128; 1994 rdev->config.r600.sq_num_cf_insts = 1; 1995 break; 1996 case CHIP_RV670: 1997 rdev->config.r600.max_pipes = 4; 1998 rdev->config.r600.max_tile_pipes = 4; 1999 rdev->config.r600.max_simds = 4; 2000 rdev->config.r600.max_backends = 4; 2001 rdev->config.r600.max_gprs = 192; 2002 rdev->config.r600.max_threads = 192; 2003 rdev->config.r600.max_stack_entries = 256; 2004 rdev->config.r600.max_hw_contexts = 8; 2005 rdev->config.r600.max_gs_threads = 16; 2006 rdev->config.r600.sx_max_export_size = 128; 2007 rdev->config.r600.sx_max_export_pos_size = 16; 2008 rdev->config.r600.sx_max_export_smx_size = 128; 2009 rdev->config.r600.sq_num_cf_insts = 2; 2010 break; 2011 default: 2012 break; 2013 } 2014 2015 /* Initialize HDP */ 2016 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 2017 WREG32((0x2c14 + j), 0x00000000); 2018 WREG32((0x2c18 + j), 0x00000000); 2019 WREG32((0x2c1c + j), 0x00000000); 2020 WREG32((0x2c20 + j), 0x00000000); 2021 WREG32((0x2c24 + j), 0x00000000); 2022 } 2023 2024 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 2025 2026 /* Setup tiling */ 2027 tiling_config = 0; 2028 ramcfg = RREG32(RAMCFG); 2029 switch (rdev->config.r600.max_tile_pipes) { 2030 case 1: 2031 tiling_config |= PIPE_TILING(0); 2032 break; 2033 case 2: 2034 tiling_config |= PIPE_TILING(1); 2035 break; 2036 case 4: 2037 tiling_config |= PIPE_TILING(2); 2038 break; 2039 case 8: 2040 tiling_config |= PIPE_TILING(3); 2041 break; 2042 default: 2043 break; 2044 } 2045 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; 2046 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 2047 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 2048 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 2049 2050 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 2051 if (tmp > 3) { 2052 tiling_config |= ROW_TILING(3); 2053 tiling_config |= SAMPLE_SPLIT(3); 2054 } else { 2055 tiling_config |= ROW_TILING(tmp); 2056 tiling_config |= SAMPLE_SPLIT(tmp); 2057 } 2058 tiling_config |= BANK_SWAPS(1); 2059 2060 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; 2061 tmp = rdev->config.r600.max_simds - 2062 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); 2063 rdev->config.r600.active_simds = tmp; 2064 2065 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; 2066 tmp = 0; 2067 for (i = 0; i < rdev->config.r600.max_backends; i++) 2068 tmp |= (1 << i); 2069 /* if all the backends are disabled, fix it up here */ 2070 if ((disabled_rb_mask & tmp) == tmp) { 2071 for (i = 0; i < rdev->config.r600.max_backends; i++) 2072 disabled_rb_mask &= ~(1 << i); 2073 } 2074 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; 2075 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, 2076 R6XX_MAX_BACKENDS, disabled_rb_mask); 2077 tiling_config |= tmp << 16; 2078 rdev->config.r600.backend_map = tmp; 2079 2080 rdev->config.r600.tile_config = tiling_config; 2081 WREG32(GB_TILING_CONFIG, tiling_config); 2082 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); 2083 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); 2084 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff); 2085 2086 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 2087 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); 2088 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); 2089 2090 /* Setup some CP states */ 2091 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); 2092 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); 2093 2094 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | 2095 SYNC_WALKER | SYNC_ALIGNER)); 2096 /* Setup various GPU states */ 2097 if (rdev->family == CHIP_RV670) 2098 WREG32(ARB_GDEC_RD_CNTL, 0x00000021); 2099 2100 tmp = RREG32(SX_DEBUG_1); 2101 tmp |= SMX_EVENT_RELEASE; 2102 if ((rdev->family > CHIP_R600)) 2103 tmp |= ENABLE_NEW_SMX_ADDRESS; 2104 WREG32(SX_DEBUG_1, tmp); 2105 2106 if (((rdev->family) == CHIP_R600) || 2107 ((rdev->family) == CHIP_RV630) || 2108 ((rdev->family) == CHIP_RV610) || 2109 ((rdev->family) == CHIP_RV620) || 2110 ((rdev->family) == CHIP_RS780) || 2111 ((rdev->family) == CHIP_RS880)) { 2112 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); 2113 } else { 2114 WREG32(DB_DEBUG, 0); 2115 } 2116 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | 2117 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); 2118 2119 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 2120 WREG32(VGT_NUM_INSTANCES, 0); 2121 2122 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 2123 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); 2124 2125 tmp = RREG32(SQ_MS_FIFO_SIZES); 2126 if (((rdev->family) == CHIP_RV610) || 2127 ((rdev->family) == CHIP_RV620) || 2128 ((rdev->family) == CHIP_RS780) || 2129 ((rdev->family) == CHIP_RS880)) { 2130 tmp = (CACHE_FIFO_SIZE(0xa) | 2131 FETCH_FIFO_HIWATER(0xa) | 2132 DONE_FIFO_HIWATER(0xe0) | 2133 ALU_UPDATE_FIFO_HIWATER(0x8)); 2134 } else if (((rdev->family) == CHIP_R600) || 2135 ((rdev->family) == CHIP_RV630)) { 2136 tmp &= ~DONE_FIFO_HIWATER(0xff); 2137 tmp |= DONE_FIFO_HIWATER(0x4); 2138 } 2139 WREG32(SQ_MS_FIFO_SIZES, tmp); 2140 2141 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 2142 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 2143 */ 2144 sq_config = RREG32(SQ_CONFIG); 2145 sq_config &= ~(PS_PRIO(3) | 2146 VS_PRIO(3) | 2147 GS_PRIO(3) | 2148 ES_PRIO(3)); 2149 sq_config |= (DX9_CONSTS | 2150 VC_ENABLE | 2151 PS_PRIO(0) | 2152 VS_PRIO(1) | 2153 GS_PRIO(2) | 2154 ES_PRIO(3)); 2155 2156 if ((rdev->family) == CHIP_R600) { 2157 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | 2158 NUM_VS_GPRS(124) | 2159 NUM_CLAUSE_TEMP_GPRS(4)); 2160 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | 2161 NUM_ES_GPRS(0)); 2162 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | 2163 NUM_VS_THREADS(48) | 2164 NUM_GS_THREADS(4) | 2165 NUM_ES_THREADS(4)); 2166 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | 2167 NUM_VS_STACK_ENTRIES(128)); 2168 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | 2169 NUM_ES_STACK_ENTRIES(0)); 2170 } else if (((rdev->family) == CHIP_RV610) || 2171 ((rdev->family) == CHIP_RV620) || 2172 ((rdev->family) == CHIP_RS780) || 2173 ((rdev->family) == CHIP_RS880)) { 2174 /* no vertex cache */ 2175 sq_config &= ~VC_ENABLE; 2176 2177 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2178 NUM_VS_GPRS(44) | 2179 NUM_CLAUSE_TEMP_GPRS(2)); 2180 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 2181 NUM_ES_GPRS(17)); 2182 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2183 NUM_VS_THREADS(78) | 2184 NUM_GS_THREADS(4) | 2185 NUM_ES_THREADS(31)); 2186 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 2187 NUM_VS_STACK_ENTRIES(40)); 2188 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 2189 NUM_ES_STACK_ENTRIES(16)); 2190 } else if (((rdev->family) == CHIP_RV630) || 2191 ((rdev->family) == CHIP_RV635)) { 2192 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2193 NUM_VS_GPRS(44) | 2194 NUM_CLAUSE_TEMP_GPRS(2)); 2195 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | 2196 NUM_ES_GPRS(18)); 2197 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2198 NUM_VS_THREADS(78) | 2199 NUM_GS_THREADS(4) | 2200 NUM_ES_THREADS(31)); 2201 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 2202 NUM_VS_STACK_ENTRIES(40)); 2203 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 2204 NUM_ES_STACK_ENTRIES(16)); 2205 } else if ((rdev->family) == CHIP_RV670) { 2206 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 2207 NUM_VS_GPRS(44) | 2208 NUM_CLAUSE_TEMP_GPRS(2)); 2209 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 2210 NUM_ES_GPRS(17)); 2211 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 2212 NUM_VS_THREADS(78) | 2213 NUM_GS_THREADS(4) | 2214 NUM_ES_THREADS(31)); 2215 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | 2216 NUM_VS_STACK_ENTRIES(64)); 2217 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | 2218 NUM_ES_STACK_ENTRIES(64)); 2219 } 2220 2221 WREG32(SQ_CONFIG, sq_config); 2222 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 2223 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 2224 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 2225 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 2226 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 2227 2228 if (((rdev->family) == CHIP_RV610) || 2229 ((rdev->family) == CHIP_RV620) || 2230 ((rdev->family) == CHIP_RS780) || 2231 ((rdev->family) == CHIP_RS880)) { 2232 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); 2233 } else { 2234 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); 2235 } 2236 2237 /* More default values. 2D/3D driver should adjust as needed */ 2238 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | 2239 S1_X(0x4) | S1_Y(0xc))); 2240 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | 2241 S1_X(0x2) | S1_Y(0x2) | 2242 S2_X(0xa) | S2_Y(0x6) | 2243 S3_X(0x6) | S3_Y(0xa))); 2244 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | 2245 S1_X(0x4) | S1_Y(0xc) | 2246 S2_X(0x1) | S2_Y(0x6) | 2247 S3_X(0xa) | S3_Y(0xe))); 2248 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | 2249 S5_X(0x0) | S5_Y(0x0) | 2250 S6_X(0xb) | S6_Y(0x4) | 2251 S7_X(0x7) | S7_Y(0x8))); 2252 2253 WREG32(VGT_STRMOUT_EN, 0); 2254 tmp = rdev->config.r600.max_pipes * 16; 2255 switch (rdev->family) { 2256 case CHIP_RV610: 2257 case CHIP_RV620: 2258 case CHIP_RS780: 2259 case CHIP_RS880: 2260 tmp += 32; 2261 break; 2262 case CHIP_RV670: 2263 tmp += 128; 2264 break; 2265 default: 2266 break; 2267 } 2268 if (tmp > 256) { 2269 tmp = 256; 2270 } 2271 WREG32(VGT_ES_PER_GS, 128); 2272 WREG32(VGT_GS_PER_ES, tmp); 2273 WREG32(VGT_GS_PER_VS, 2); 2274 WREG32(VGT_GS_VERTEX_REUSE, 16); 2275 2276 /* more default values. 2D/3D driver should adjust as needed */ 2277 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 2278 WREG32(VGT_STRMOUT_EN, 0); 2279 WREG32(SX_MISC, 0); 2280 WREG32(PA_SC_MODE_CNTL, 0); 2281 WREG32(PA_SC_AA_CONFIG, 0); 2282 WREG32(PA_SC_LINE_STIPPLE, 0); 2283 WREG32(SPI_INPUT_Z, 0); 2284 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 2285 WREG32(CB_COLOR7_FRAG, 0); 2286 2287 /* Clear render buffer base addresses */ 2288 WREG32(CB_COLOR0_BASE, 0); 2289 WREG32(CB_COLOR1_BASE, 0); 2290 WREG32(CB_COLOR2_BASE, 0); 2291 WREG32(CB_COLOR3_BASE, 0); 2292 WREG32(CB_COLOR4_BASE, 0); 2293 WREG32(CB_COLOR5_BASE, 0); 2294 WREG32(CB_COLOR6_BASE, 0); 2295 WREG32(CB_COLOR7_BASE, 0); 2296 WREG32(CB_COLOR7_FRAG, 0); 2297 2298 switch (rdev->family) { 2299 case CHIP_RV610: 2300 case CHIP_RV620: 2301 case CHIP_RS780: 2302 case CHIP_RS880: 2303 tmp = TC_L2_SIZE(8); 2304 break; 2305 case CHIP_RV630: 2306 case CHIP_RV635: 2307 tmp = TC_L2_SIZE(4); 2308 break; 2309 case CHIP_R600: 2310 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; 2311 break; 2312 default: 2313 tmp = TC_L2_SIZE(0); 2314 break; 2315 } 2316 WREG32(TC_CNTL, tmp); 2317 2318 tmp = RREG32(HDP_HOST_PATH_CNTL); 2319 WREG32(HDP_HOST_PATH_CNTL, tmp); 2320 2321 tmp = RREG32(ARB_POP); 2322 tmp |= ENABLE_TC128; 2323 WREG32(ARB_POP, tmp); 2324 2325 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 2326 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 2327 NUM_CLIP_SEQ(3))); 2328 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); 2329 WREG32(VC_ENHANCE, 0); 2330 } 2331 2332 2333 /* 2334 * Indirect registers accessor 2335 */ 2336 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) 2337 { 2338 unsigned long flags; 2339 u32 r; 2340 2341 spin_lock_irqsave(&rdev->pciep_idx_lock, flags); 2342 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2343 (void)RREG32(PCIE_PORT_INDEX); 2344 r = RREG32(PCIE_PORT_DATA); 2345 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); 2346 return r; 2347 } 2348 2349 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2350 { 2351 unsigned long flags; 2352 2353 spin_lock_irqsave(&rdev->pciep_idx_lock, flags); 2354 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2355 (void)RREG32(PCIE_PORT_INDEX); 2356 WREG32(PCIE_PORT_DATA, (v)); 2357 (void)RREG32(PCIE_PORT_DATA); 2358 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); 2359 } 2360 2361 /* 2362 * CP & Ring 2363 */ 2364 void r600_cp_stop(struct radeon_device *rdev) 2365 { 2366 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 2367 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2368 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 2369 WREG32(SCRATCH_UMSK, 0); 2370 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 2371 } 2372 2373 int r600_init_microcode(struct radeon_device *rdev) 2374 { 2375 const char *chip_name; 2376 const char *rlc_chip_name; 2377 const char *smc_chip_name = "RV770"; 2378 size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0; 2379 char fw_name[30]; 2380 int err; 2381 2382 DRM_DEBUG("\n"); 2383 2384 switch (rdev->family) { 2385 case CHIP_R600: 2386 chip_name = "R600"; 2387 rlc_chip_name = "R600"; 2388 break; 2389 case CHIP_RV610: 2390 chip_name = "RV610"; 2391 rlc_chip_name = "R600"; 2392 break; 2393 case CHIP_RV630: 2394 chip_name = "RV630"; 2395 rlc_chip_name = "R600"; 2396 break; 2397 case CHIP_RV620: 2398 chip_name = "RV620"; 2399 rlc_chip_name = "R600"; 2400 break; 2401 case CHIP_RV635: 2402 chip_name = "RV635"; 2403 rlc_chip_name = "R600"; 2404 break; 2405 case CHIP_RV670: 2406 chip_name = "RV670"; 2407 rlc_chip_name = "R600"; 2408 break; 2409 case CHIP_RS780: 2410 case CHIP_RS880: 2411 chip_name = "RS780"; 2412 rlc_chip_name = "R600"; 2413 break; 2414 case CHIP_RV770: 2415 chip_name = "RV770"; 2416 rlc_chip_name = "R700"; 2417 smc_chip_name = "RV770"; 2418 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4); 2419 break; 2420 case CHIP_RV730: 2421 chip_name = "RV730"; 2422 rlc_chip_name = "R700"; 2423 smc_chip_name = "RV730"; 2424 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4); 2425 break; 2426 case CHIP_RV710: 2427 chip_name = "RV710"; 2428 rlc_chip_name = "R700"; 2429 smc_chip_name = "RV710"; 2430 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4); 2431 break; 2432 case CHIP_RV740: 2433 chip_name = "RV730"; 2434 rlc_chip_name = "R700"; 2435 smc_chip_name = "RV740"; 2436 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4); 2437 break; 2438 case CHIP_CEDAR: 2439 chip_name = "CEDAR"; 2440 rlc_chip_name = "CEDAR"; 2441 smc_chip_name = "CEDAR"; 2442 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4); 2443 break; 2444 case CHIP_REDWOOD: 2445 chip_name = "REDWOOD"; 2446 rlc_chip_name = "REDWOOD"; 2447 smc_chip_name = "REDWOOD"; 2448 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4); 2449 break; 2450 case CHIP_JUNIPER: 2451 chip_name = "JUNIPER"; 2452 rlc_chip_name = "JUNIPER"; 2453 smc_chip_name = "JUNIPER"; 2454 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4); 2455 break; 2456 case CHIP_CYPRESS: 2457 case CHIP_HEMLOCK: 2458 chip_name = "CYPRESS"; 2459 rlc_chip_name = "CYPRESS"; 2460 smc_chip_name = "CYPRESS"; 2461 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4); 2462 break; 2463 case CHIP_PALM: 2464 chip_name = "PALM"; 2465 rlc_chip_name = "SUMO"; 2466 break; 2467 case CHIP_SUMO: 2468 chip_name = "SUMO"; 2469 rlc_chip_name = "SUMO"; 2470 break; 2471 case CHIP_SUMO2: 2472 chip_name = "SUMO2"; 2473 rlc_chip_name = "SUMO"; 2474 break; 2475 default: BUG(); 2476 } 2477 2478 if (rdev->family >= CHIP_CEDAR) { 2479 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 2480 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 2481 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 2482 } else if (rdev->family >= CHIP_RV770) { 2483 pfp_req_size = R700_PFP_UCODE_SIZE * 4; 2484 me_req_size = R700_PM4_UCODE_SIZE * 4; 2485 rlc_req_size = R700_RLC_UCODE_SIZE * 4; 2486 } else { 2487 pfp_req_size = R600_PFP_UCODE_SIZE * 4; 2488 me_req_size = R600_PM4_UCODE_SIZE * 12; 2489 rlc_req_size = R600_RLC_UCODE_SIZE * 4; 2490 } 2491 2492 DRM_INFO("Loading %s Microcode\n", chip_name); 2493 2494 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 2495 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); 2496 if (err) 2497 goto out; 2498 if (rdev->pfp_fw->size != pfp_req_size) { 2499 printk(KERN_ERR 2500 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2501 rdev->pfp_fw->size, fw_name); 2502 err = -EINVAL; 2503 goto out; 2504 } 2505 2506 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 2507 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 2508 if (err) 2509 goto out; 2510 if (rdev->me_fw->size != me_req_size) { 2511 printk(KERN_ERR 2512 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2513 rdev->me_fw->size, fw_name); 2514 err = -EINVAL; 2515 } 2516 2517 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); 2518 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); 2519 if (err) 2520 goto out; 2521 if (rdev->rlc_fw->size != rlc_req_size) { 2522 printk(KERN_ERR 2523 "r600_rlc: Bogus length %zu in firmware \"%s\"\n", 2524 rdev->rlc_fw->size, fw_name); 2525 err = -EINVAL; 2526 } 2527 2528 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) { 2529 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", smc_chip_name); 2530 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); 2531 if (err) { 2532 printk(KERN_ERR 2533 "smc: error loading firmware \"%s\"\n", 2534 fw_name); 2535 release_firmware(rdev->smc_fw); 2536 rdev->smc_fw = NULL; 2537 err = 0; 2538 } else if (rdev->smc_fw->size != smc_req_size) { 2539 printk(KERN_ERR 2540 "smc: Bogus length %zu in firmware \"%s\"\n", 2541 rdev->smc_fw->size, fw_name); 2542 err = -EINVAL; 2543 } 2544 } 2545 2546 out: 2547 if (err) { 2548 if (err != -EINVAL) 2549 printk(KERN_ERR 2550 "r600_cp: Failed to load firmware \"%s\"\n", 2551 fw_name); 2552 release_firmware(rdev->pfp_fw); 2553 rdev->pfp_fw = NULL; 2554 release_firmware(rdev->me_fw); 2555 rdev->me_fw = NULL; 2556 release_firmware(rdev->rlc_fw); 2557 rdev->rlc_fw = NULL; 2558 release_firmware(rdev->smc_fw); 2559 rdev->smc_fw = NULL; 2560 } 2561 return err; 2562 } 2563 2564 u32 r600_gfx_get_rptr(struct radeon_device *rdev, 2565 struct radeon_ring *ring) 2566 { 2567 u32 rptr; 2568 2569 if (rdev->wb.enabled) 2570 rptr = rdev->wb.wb[ring->rptr_offs/4]; 2571 else 2572 rptr = RREG32(R600_CP_RB_RPTR); 2573 2574 return rptr; 2575 } 2576 2577 u32 r600_gfx_get_wptr(struct radeon_device *rdev, 2578 struct radeon_ring *ring) 2579 { 2580 u32 wptr; 2581 2582 wptr = RREG32(R600_CP_RB_WPTR); 2583 2584 return wptr; 2585 } 2586 2587 void r600_gfx_set_wptr(struct radeon_device *rdev, 2588 struct radeon_ring *ring) 2589 { 2590 WREG32(R600_CP_RB_WPTR, ring->wptr); 2591 (void)RREG32(R600_CP_RB_WPTR); 2592 } 2593 2594 static int r600_cp_load_microcode(struct radeon_device *rdev) 2595 { 2596 const __be32 *fw_data; 2597 int i; 2598 2599 if (!rdev->me_fw || !rdev->pfp_fw) 2600 return -EINVAL; 2601 2602 r600_cp_stop(rdev); 2603 2604 WREG32(CP_RB_CNTL, 2605 #ifdef __BIG_ENDIAN 2606 BUF_SWAP_32BIT | 2607 #endif 2608 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 2609 2610 /* Reset cp */ 2611 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2612 RREG32(GRBM_SOFT_RESET); 2613 mdelay(15); 2614 WREG32(GRBM_SOFT_RESET, 0); 2615 2616 WREG32(CP_ME_RAM_WADDR, 0); 2617 2618 fw_data = (const __be32 *)rdev->me_fw->data; 2619 WREG32(CP_ME_RAM_WADDR, 0); 2620 for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++) 2621 WREG32(CP_ME_RAM_DATA, 2622 be32_to_cpup(fw_data++)); 2623 2624 fw_data = (const __be32 *)rdev->pfp_fw->data; 2625 WREG32(CP_PFP_UCODE_ADDR, 0); 2626 for (i = 0; i < R600_PFP_UCODE_SIZE; i++) 2627 WREG32(CP_PFP_UCODE_DATA, 2628 be32_to_cpup(fw_data++)); 2629 2630 WREG32(CP_PFP_UCODE_ADDR, 0); 2631 WREG32(CP_ME_RAM_WADDR, 0); 2632 WREG32(CP_ME_RAM_RADDR, 0); 2633 return 0; 2634 } 2635 2636 int r600_cp_start(struct radeon_device *rdev) 2637 { 2638 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2639 int r; 2640 uint32_t cp_me; 2641 2642 r = radeon_ring_lock(rdev, ring, 7); 2643 if (r) { 2644 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 2645 return r; 2646 } 2647 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2648 radeon_ring_write(ring, 0x1); 2649 if (rdev->family >= CHIP_RV770) { 2650 radeon_ring_write(ring, 0x0); 2651 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); 2652 } else { 2653 radeon_ring_write(ring, 0x3); 2654 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); 2655 } 2656 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2657 radeon_ring_write(ring, 0); 2658 radeon_ring_write(ring, 0); 2659 radeon_ring_unlock_commit(rdev, ring, false); 2660 2661 cp_me = 0xff; 2662 WREG32(R_0086D8_CP_ME_CNTL, cp_me); 2663 return 0; 2664 } 2665 2666 int r600_cp_resume(struct radeon_device *rdev) 2667 { 2668 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2669 u32 tmp; 2670 u32 rb_bufsz; 2671 int r; 2672 2673 /* Reset cp */ 2674 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2675 RREG32(GRBM_SOFT_RESET); 2676 mdelay(15); 2677 WREG32(GRBM_SOFT_RESET, 0); 2678 2679 /* Set ring buffer size */ 2680 rb_bufsz = order_base_2(ring->ring_size / 8); 2681 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2682 #ifdef __BIG_ENDIAN 2683 tmp |= BUF_SWAP_32BIT; 2684 #endif 2685 WREG32(CP_RB_CNTL, tmp); 2686 WREG32(CP_SEM_WAIT_TIMER, 0x0); 2687 2688 /* Set the write pointer delay */ 2689 WREG32(CP_RB_WPTR_DELAY, 0); 2690 2691 /* Initialize the ring buffer's read and write pointers */ 2692 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 2693 WREG32(CP_RB_RPTR_WR, 0); 2694 ring->wptr = 0; 2695 WREG32(CP_RB_WPTR, ring->wptr); 2696 2697 /* set the wb address whether it's enabled or not */ 2698 WREG32(CP_RB_RPTR_ADDR, 2699 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); 2700 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 2701 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 2702 2703 if (rdev->wb.enabled) 2704 WREG32(SCRATCH_UMSK, 0xff); 2705 else { 2706 tmp |= RB_NO_UPDATE; 2707 WREG32(SCRATCH_UMSK, 0); 2708 } 2709 2710 mdelay(1); 2711 WREG32(CP_RB_CNTL, tmp); 2712 2713 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); 2714 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 2715 2716 r600_cp_start(rdev); 2717 ring->ready = true; 2718 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 2719 if (r) { 2720 ring->ready = false; 2721 return r; 2722 } 2723 2724 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) 2725 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 2726 2727 return 0; 2728 } 2729 2730 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) 2731 { 2732 u32 rb_bufsz; 2733 int r; 2734 2735 /* Align ring size */ 2736 rb_bufsz = order_base_2(ring_size / 8); 2737 ring_size = (1 << (rb_bufsz + 1)) * 4; 2738 ring->ring_size = ring_size; 2739 ring->align_mask = 16 - 1; 2740 2741 if (radeon_ring_supports_scratch_reg(rdev, ring)) { 2742 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 2743 if (r) { 2744 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 2745 ring->rptr_save_reg = 0; 2746 } 2747 } 2748 } 2749 2750 void r600_cp_fini(struct radeon_device *rdev) 2751 { 2752 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2753 r600_cp_stop(rdev); 2754 radeon_ring_fini(rdev, ring); 2755 radeon_scratch_free(rdev, ring->rptr_save_reg); 2756 } 2757 2758 /* 2759 * GPU scratch registers helpers function. 2760 */ 2761 void r600_scratch_init(struct radeon_device *rdev) 2762 { 2763 int i; 2764 2765 rdev->scratch.num_reg = 7; 2766 rdev->scratch.reg_base = SCRATCH_REG0; 2767 for (i = 0; i < rdev->scratch.num_reg; i++) { 2768 rdev->scratch.free[i] = true; 2769 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 2770 } 2771 } 2772 2773 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 2774 { 2775 uint32_t scratch; 2776 uint32_t tmp = 0; 2777 unsigned i; 2778 int r; 2779 2780 r = radeon_scratch_get(rdev, &scratch); 2781 if (r) { 2782 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 2783 return r; 2784 } 2785 WREG32(scratch, 0xCAFEDEAD); 2786 r = radeon_ring_lock(rdev, ring, 3); 2787 if (r) { 2788 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); 2789 radeon_scratch_free(rdev, scratch); 2790 return r; 2791 } 2792 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2793 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2794 radeon_ring_write(ring, 0xDEADBEEF); 2795 radeon_ring_unlock_commit(rdev, ring, false); 2796 for (i = 0; i < rdev->usec_timeout; i++) { 2797 tmp = RREG32(scratch); 2798 if (tmp == 0xDEADBEEF) 2799 break; 2800 DRM_UDELAY(1); 2801 } 2802 if (i < rdev->usec_timeout) { 2803 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2804 } else { 2805 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 2806 ring->idx, scratch, tmp); 2807 r = -EINVAL; 2808 } 2809 radeon_scratch_free(rdev, scratch); 2810 return r; 2811 } 2812 2813 /* 2814 * CP fences/semaphores 2815 */ 2816 2817 void r600_fence_ring_emit(struct radeon_device *rdev, 2818 struct radeon_fence *fence) 2819 { 2820 struct radeon_ring *ring = &rdev->ring[fence->ring]; 2821 u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA | 2822 PACKET3_SH_ACTION_ENA; 2823 2824 if (rdev->family >= CHIP_RV770) 2825 cp_coher_cntl |= PACKET3_FULL_CACHE_ENA; 2826 2827 if (rdev->wb.use_event) { 2828 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2829 /* flush read cache over gart */ 2830 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2831 radeon_ring_write(ring, cp_coher_cntl); 2832 radeon_ring_write(ring, 0xFFFFFFFF); 2833 radeon_ring_write(ring, 0); 2834 radeon_ring_write(ring, 10); /* poll interval */ 2835 /* EVENT_WRITE_EOP - flush caches, send int */ 2836 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2837 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 2838 radeon_ring_write(ring, lower_32_bits(addr)); 2839 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 2840 radeon_ring_write(ring, fence->seq); 2841 radeon_ring_write(ring, 0); 2842 } else { 2843 /* flush read cache over gart */ 2844 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2845 radeon_ring_write(ring, cp_coher_cntl); 2846 radeon_ring_write(ring, 0xFFFFFFFF); 2847 radeon_ring_write(ring, 0); 2848 radeon_ring_write(ring, 10); /* poll interval */ 2849 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2850 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); 2851 /* wait for 3D idle clean */ 2852 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2853 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2854 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); 2855 /* Emit fence sequence & fire IRQ */ 2856 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2857 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2858 radeon_ring_write(ring, fence->seq); 2859 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ 2860 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); 2861 radeon_ring_write(ring, RB_INT_STAT); 2862 } 2863 } 2864 2865 /** 2866 * r600_semaphore_ring_emit - emit a semaphore on the CP ring 2867 * 2868 * @rdev: radeon_device pointer 2869 * @ring: radeon ring buffer object 2870 * @semaphore: radeon semaphore object 2871 * @emit_wait: Is this a sempahore wait? 2872 * 2873 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP 2874 * from running ahead of semaphore waits. 2875 */ 2876 bool r600_semaphore_ring_emit(struct radeon_device *rdev, 2877 struct radeon_ring *ring, 2878 struct radeon_semaphore *semaphore, 2879 bool emit_wait) 2880 { 2881 uint64_t addr = semaphore->gpu_addr; 2882 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; 2883 2884 if (rdev->family < CHIP_CAYMAN) 2885 sel |= PACKET3_SEM_WAIT_ON_SIGNAL; 2886 2887 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); 2888 radeon_ring_write(ring, lower_32_bits(addr)); 2889 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); 2890 2891 /* PFP_SYNC_ME packet only exists on 7xx+, only enable it on eg+ */ 2892 if (emit_wait && (rdev->family >= CHIP_CEDAR)) { 2893 /* Prevent the PFP from running ahead of the semaphore wait */ 2894 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2895 radeon_ring_write(ring, 0x0); 2896 } 2897 2898 return true; 2899 } 2900 2901 /** 2902 * r600_copy_cpdma - copy pages using the CP DMA engine 2903 * 2904 * @rdev: radeon_device pointer 2905 * @src_offset: src GPU address 2906 * @dst_offset: dst GPU address 2907 * @num_gpu_pages: number of GPU pages to xfer 2908 * @fence: radeon fence object 2909 * 2910 * Copy GPU paging using the CP DMA engine (r6xx+). 2911 * Used by the radeon ttm implementation to move pages if 2912 * registered as the asic copy callback. 2913 */ 2914 struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev, 2915 uint64_t src_offset, uint64_t dst_offset, 2916 unsigned num_gpu_pages, 2917 struct reservation_object *resv) 2918 { 2919 struct radeon_fence *fence; 2920 struct radeon_sync sync; 2921 int ring_index = rdev->asic->copy.blit_ring_index; 2922 struct radeon_ring *ring = &rdev->ring[ring_index]; 2923 u32 size_in_bytes, cur_size_in_bytes, tmp; 2924 int i, num_loops; 2925 int r = 0; 2926 2927 radeon_sync_create(&sync); 2928 2929 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); 2930 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); 2931 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24); 2932 if (r) { 2933 DRM_ERROR("radeon: moving bo (%d).\n", r); 2934 radeon_sync_free(rdev, &sync, NULL); 2935 return ERR_PTR(r); 2936 } 2937 2938 radeon_sync_resv(rdev, &sync, resv, false); 2939 radeon_sync_rings(rdev, &sync, ring->idx); 2940 2941 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2942 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2943 radeon_ring_write(ring, WAIT_3D_IDLE_bit); 2944 for (i = 0; i < num_loops; i++) { 2945 cur_size_in_bytes = size_in_bytes; 2946 if (cur_size_in_bytes > 0x1fffff) 2947 cur_size_in_bytes = 0x1fffff; 2948 size_in_bytes -= cur_size_in_bytes; 2949 tmp = upper_32_bits(src_offset) & 0xff; 2950 if (size_in_bytes == 0) 2951 tmp |= PACKET3_CP_DMA_CP_SYNC; 2952 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)); 2953 radeon_ring_write(ring, lower_32_bits(src_offset)); 2954 radeon_ring_write(ring, tmp); 2955 radeon_ring_write(ring, lower_32_bits(dst_offset)); 2956 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); 2957 radeon_ring_write(ring, cur_size_in_bytes); 2958 src_offset += cur_size_in_bytes; 2959 dst_offset += cur_size_in_bytes; 2960 } 2961 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2962 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2963 radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit); 2964 2965 r = radeon_fence_emit(rdev, &fence, ring->idx); 2966 if (r) { 2967 radeon_ring_unlock_undo(rdev, ring); 2968 radeon_sync_free(rdev, &sync, NULL); 2969 return ERR_PTR(r); 2970 } 2971 2972 radeon_ring_unlock_commit(rdev, ring, false); 2973 radeon_sync_free(rdev, &sync, fence); 2974 2975 return fence; 2976 } 2977 2978 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 2979 uint32_t tiling_flags, uint32_t pitch, 2980 uint32_t offset, uint32_t obj_size) 2981 { 2982 /* FIXME: implement */ 2983 return 0; 2984 } 2985 2986 void r600_clear_surface_reg(struct radeon_device *rdev, int reg) 2987 { 2988 /* FIXME: implement */ 2989 } 2990 2991 static int r600_startup(struct radeon_device *rdev) 2992 { 2993 struct radeon_ring *ring; 2994 int r; 2995 2996 /* enable pcie gen2 link */ 2997 r600_pcie_gen2_enable(rdev); 2998 2999 /* scratch needs to be initialized before MC */ 3000 r = r600_vram_scratch_init(rdev); 3001 if (r) 3002 return r; 3003 3004 r600_mc_program(rdev); 3005 3006 if (rdev->flags & RADEON_IS_AGP) { 3007 r600_agp_enable(rdev); 3008 } else { 3009 r = r600_pcie_gart_enable(rdev); 3010 if (r) 3011 return r; 3012 } 3013 r600_gpu_init(rdev); 3014 3015 /* allocate wb buffer */ 3016 r = radeon_wb_init(rdev); 3017 if (r) 3018 return r; 3019 3020 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 3021 if (r) { 3022 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 3023 return r; 3024 } 3025 3026 if (rdev->has_uvd) { 3027 r = uvd_v1_0_resume(rdev); 3028 if (!r) { 3029 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX); 3030 if (r) { 3031 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); 3032 } 3033 } 3034 if (r) 3035 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; 3036 } 3037 3038 /* Enable IRQ */ 3039 if (!rdev->irq.installed) { 3040 r = radeon_irq_kms_init(rdev); 3041 if (r) 3042 return r; 3043 } 3044 3045 r = r600_irq_init(rdev); 3046 if (r) { 3047 DRM_ERROR("radeon: IH init failed (%d).\n", r); 3048 radeon_irq_kms_fini(rdev); 3049 return r; 3050 } 3051 r600_irq_set(rdev); 3052 3053 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3054 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 3055 RADEON_CP_PACKET2); 3056 if (r) 3057 return r; 3058 3059 r = r600_cp_load_microcode(rdev); 3060 if (r) 3061 return r; 3062 r = r600_cp_resume(rdev); 3063 if (r) 3064 return r; 3065 3066 if (rdev->has_uvd) { 3067 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 3068 if (ring->ring_size) { 3069 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 3070 RADEON_CP_PACKET2); 3071 if (!r) 3072 r = uvd_v1_0_init(rdev); 3073 if (r) 3074 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); 3075 } 3076 } 3077 3078 r = radeon_ib_pool_init(rdev); 3079 if (r) { 3080 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3081 return r; 3082 } 3083 3084 r = radeon_audio_init(rdev); 3085 if (r) { 3086 DRM_ERROR("radeon: audio init failed\n"); 3087 return r; 3088 } 3089 3090 return 0; 3091 } 3092 3093 void r600_vga_set_state(struct radeon_device *rdev, bool state) 3094 { 3095 uint32_t temp; 3096 3097 temp = RREG32(CONFIG_CNTL); 3098 if (state == false) { 3099 temp &= ~(1<<0); 3100 temp |= (1<<1); 3101 } else { 3102 temp &= ~(1<<1); 3103 } 3104 WREG32(CONFIG_CNTL, temp); 3105 } 3106 3107 int r600_resume(struct radeon_device *rdev) 3108 { 3109 int r; 3110 3111 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, 3112 * posting will perform necessary task to bring back GPU into good 3113 * shape. 3114 */ 3115 /* post card */ 3116 atom_asic_init(rdev->mode_info.atom_context); 3117 3118 if (rdev->pm.pm_method == PM_METHOD_DPM) 3119 radeon_pm_resume(rdev); 3120 3121 rdev->accel_working = true; 3122 r = r600_startup(rdev); 3123 if (r) { 3124 DRM_ERROR("r600 startup failed on resume\n"); 3125 rdev->accel_working = false; 3126 return r; 3127 } 3128 3129 return r; 3130 } 3131 3132 int r600_suspend(struct radeon_device *rdev) 3133 { 3134 radeon_pm_suspend(rdev); 3135 radeon_audio_fini(rdev); 3136 r600_cp_stop(rdev); 3137 if (rdev->has_uvd) { 3138 uvd_v1_0_fini(rdev); 3139 radeon_uvd_suspend(rdev); 3140 } 3141 r600_irq_suspend(rdev); 3142 radeon_wb_disable(rdev); 3143 r600_pcie_gart_disable(rdev); 3144 3145 return 0; 3146 } 3147 3148 /* Plan is to move initialization in that function and use 3149 * helper function so that radeon_device_init pretty much 3150 * do nothing more than calling asic specific function. This 3151 * should also allow to remove a bunch of callback function 3152 * like vram_info. 3153 */ 3154 int r600_init(struct radeon_device *rdev) 3155 { 3156 int r; 3157 3158 if (r600_debugfs_mc_info_init(rdev)) { 3159 DRM_ERROR("Failed to register debugfs file for mc !\n"); 3160 } 3161 /* Read BIOS */ 3162 if (!radeon_get_bios(rdev)) { 3163 if (ASIC_IS_AVIVO(rdev)) 3164 return -EINVAL; 3165 } 3166 /* Must be an ATOMBIOS */ 3167 if (!rdev->is_atom_bios) { 3168 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 3169 return -EINVAL; 3170 } 3171 r = radeon_atombios_init(rdev); 3172 if (r) 3173 return r; 3174 /* Post card if necessary */ 3175 if (!radeon_card_posted(rdev)) { 3176 if (!rdev->bios) { 3177 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 3178 return -EINVAL; 3179 } 3180 DRM_INFO("GPU not posted. posting now...\n"); 3181 atom_asic_init(rdev->mode_info.atom_context); 3182 } 3183 /* Initialize scratch registers */ 3184 r600_scratch_init(rdev); 3185 /* Initialize surface registers */ 3186 radeon_surface_init(rdev); 3187 /* Initialize clocks */ 3188 radeon_get_clock_info(rdev->ddev); 3189 /* Fence driver */ 3190 r = radeon_fence_driver_init(rdev); 3191 if (r) 3192 return r; 3193 if (rdev->flags & RADEON_IS_AGP) { 3194 r = radeon_agp_init(rdev); 3195 if (r) 3196 radeon_agp_disable(rdev); 3197 } 3198 r = r600_mc_init(rdev); 3199 if (r) 3200 return r; 3201 /* Memory manager */ 3202 r = radeon_bo_init(rdev); 3203 if (r) 3204 return r; 3205 3206 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 3207 r = r600_init_microcode(rdev); 3208 if (r) { 3209 DRM_ERROR("Failed to load firmware!\n"); 3210 return r; 3211 } 3212 } 3213 3214 /* Initialize power management */ 3215 radeon_pm_init(rdev); 3216 3217 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 3218 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 3219 3220 if (rdev->has_uvd) { 3221 r = radeon_uvd_init(rdev); 3222 if (!r) { 3223 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; 3224 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); 3225 } 3226 } 3227 3228 rdev->ih.ring_obj = NULL; 3229 r600_ih_ring_init(rdev, 64 * 1024); 3230 3231 r = r600_pcie_gart_init(rdev); 3232 if (r) 3233 return r; 3234 3235 rdev->accel_working = true; 3236 r = r600_startup(rdev); 3237 if (r) { 3238 dev_err(rdev->dev, "disabling GPU acceleration\n"); 3239 r600_cp_fini(rdev); 3240 r600_irq_fini(rdev); 3241 radeon_wb_fini(rdev); 3242 radeon_ib_pool_fini(rdev); 3243 radeon_irq_kms_fini(rdev); 3244 r600_pcie_gart_fini(rdev); 3245 rdev->accel_working = false; 3246 } 3247 3248 return 0; 3249 } 3250 3251 void r600_fini(struct radeon_device *rdev) 3252 { 3253 radeon_pm_fini(rdev); 3254 radeon_audio_fini(rdev); 3255 r600_cp_fini(rdev); 3256 r600_irq_fini(rdev); 3257 if (rdev->has_uvd) { 3258 uvd_v1_0_fini(rdev); 3259 radeon_uvd_fini(rdev); 3260 } 3261 radeon_wb_fini(rdev); 3262 radeon_ib_pool_fini(rdev); 3263 radeon_irq_kms_fini(rdev); 3264 r600_pcie_gart_fini(rdev); 3265 r600_vram_scratch_fini(rdev); 3266 radeon_agp_fini(rdev); 3267 radeon_gem_fini(rdev); 3268 radeon_fence_driver_fini(rdev); 3269 radeon_bo_fini(rdev); 3270 radeon_atombios_fini(rdev); 3271 kfree(rdev->bios); 3272 rdev->bios = NULL; 3273 } 3274 3275 3276 /* 3277 * CS stuff 3278 */ 3279 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3280 { 3281 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3282 u32 next_rptr; 3283 3284 if (ring->rptr_save_reg) { 3285 next_rptr = ring->wptr + 3 + 4; 3286 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3287 radeon_ring_write(ring, ((ring->rptr_save_reg - 3288 PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 3289 radeon_ring_write(ring, next_rptr); 3290 } else if (rdev->wb.enabled) { 3291 next_rptr = ring->wptr + 5 + 4; 3292 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); 3293 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3294 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); 3295 radeon_ring_write(ring, next_rptr); 3296 radeon_ring_write(ring, 0); 3297 } 3298 3299 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3300 radeon_ring_write(ring, 3301 #ifdef __BIG_ENDIAN 3302 (2 << 0) | 3303 #endif 3304 (ib->gpu_addr & 0xFFFFFFFC)); 3305 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); 3306 radeon_ring_write(ring, ib->length_dw); 3307 } 3308 3309 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3310 { 3311 struct radeon_ib ib; 3312 uint32_t scratch; 3313 uint32_t tmp = 0; 3314 unsigned i; 3315 int r; 3316 3317 r = radeon_scratch_get(rdev, &scratch); 3318 if (r) { 3319 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3320 return r; 3321 } 3322 WREG32(scratch, 0xCAFEDEAD); 3323 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3324 if (r) { 3325 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3326 goto free_scratch; 3327 } 3328 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 3329 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3330 ib.ptr[2] = 0xDEADBEEF; 3331 ib.length_dw = 3; 3332 r = radeon_ib_schedule(rdev, &ib, NULL, false); 3333 if (r) { 3334 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3335 goto free_ib; 3336 } 3337 r = radeon_fence_wait(ib.fence, false); 3338 if (r) { 3339 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3340 goto free_ib; 3341 } 3342 for (i = 0; i < rdev->usec_timeout; i++) { 3343 tmp = RREG32(scratch); 3344 if (tmp == 0xDEADBEEF) 3345 break; 3346 DRM_UDELAY(1); 3347 } 3348 if (i < rdev->usec_timeout) { 3349 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3350 } else { 3351 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3352 scratch, tmp); 3353 r = -EINVAL; 3354 } 3355 free_ib: 3356 radeon_ib_free(rdev, &ib); 3357 free_scratch: 3358 radeon_scratch_free(rdev, scratch); 3359 return r; 3360 } 3361 3362 /* 3363 * Interrupts 3364 * 3365 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty 3366 * the same as the CP ring buffer, but in reverse. Rather than the CPU 3367 * writing to the ring and the GPU consuming, the GPU writes to the ring 3368 * and host consumes. As the host irq handler processes interrupts, it 3369 * increments the rptr. When the rptr catches up with the wptr, all the 3370 * current interrupts have been processed. 3371 */ 3372 3373 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) 3374 { 3375 u32 rb_bufsz; 3376 3377 /* Align ring size */ 3378 rb_bufsz = order_base_2(ring_size / 4); 3379 ring_size = (1 << rb_bufsz) * 4; 3380 rdev->ih.ring_size = ring_size; 3381 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; 3382 rdev->ih.rptr = 0; 3383 } 3384 3385 int r600_ih_ring_alloc(struct radeon_device *rdev) 3386 { 3387 int r; 3388 3389 /* Allocate ring buffer */ 3390 if (rdev->ih.ring_obj == NULL) { 3391 r = radeon_bo_create(rdev, rdev->ih.ring_size, 3392 PAGE_SIZE, true, 3393 RADEON_GEM_DOMAIN_GTT, 0, 3394 NULL, NULL, &rdev->ih.ring_obj); 3395 if (r) { 3396 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); 3397 return r; 3398 } 3399 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3400 if (unlikely(r != 0)) 3401 return r; 3402 r = radeon_bo_pin(rdev->ih.ring_obj, 3403 RADEON_GEM_DOMAIN_GTT, 3404 &rdev->ih.gpu_addr); 3405 if (r) { 3406 radeon_bo_unreserve(rdev->ih.ring_obj); 3407 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); 3408 return r; 3409 } 3410 r = radeon_bo_kmap(rdev->ih.ring_obj, 3411 (void **)&rdev->ih.ring); 3412 radeon_bo_unreserve(rdev->ih.ring_obj); 3413 if (r) { 3414 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); 3415 return r; 3416 } 3417 } 3418 return 0; 3419 } 3420 3421 void r600_ih_ring_fini(struct radeon_device *rdev) 3422 { 3423 int r; 3424 if (rdev->ih.ring_obj) { 3425 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3426 if (likely(r == 0)) { 3427 radeon_bo_kunmap(rdev->ih.ring_obj); 3428 radeon_bo_unpin(rdev->ih.ring_obj); 3429 radeon_bo_unreserve(rdev->ih.ring_obj); 3430 } 3431 radeon_bo_unref(&rdev->ih.ring_obj); 3432 rdev->ih.ring = NULL; 3433 rdev->ih.ring_obj = NULL; 3434 } 3435 } 3436 3437 void r600_rlc_stop(struct radeon_device *rdev) 3438 { 3439 3440 if ((rdev->family >= CHIP_RV770) && 3441 (rdev->family <= CHIP_RV740)) { 3442 /* r7xx asics need to soft reset RLC before halting */ 3443 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); 3444 RREG32(SRBM_SOFT_RESET); 3445 mdelay(15); 3446 WREG32(SRBM_SOFT_RESET, 0); 3447 RREG32(SRBM_SOFT_RESET); 3448 } 3449 3450 WREG32(RLC_CNTL, 0); 3451 } 3452 3453 static void r600_rlc_start(struct radeon_device *rdev) 3454 { 3455 WREG32(RLC_CNTL, RLC_ENABLE); 3456 } 3457 3458 static int r600_rlc_resume(struct radeon_device *rdev) 3459 { 3460 u32 i; 3461 const __be32 *fw_data; 3462 3463 if (!rdev->rlc_fw) 3464 return -EINVAL; 3465 3466 r600_rlc_stop(rdev); 3467 3468 WREG32(RLC_HB_CNTL, 0); 3469 3470 WREG32(RLC_HB_BASE, 0); 3471 WREG32(RLC_HB_RPTR, 0); 3472 WREG32(RLC_HB_WPTR, 0); 3473 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); 3474 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); 3475 WREG32(RLC_MC_CNTL, 0); 3476 WREG32(RLC_UCODE_CNTL, 0); 3477 3478 fw_data = (const __be32 *)rdev->rlc_fw->data; 3479 if (rdev->family >= CHIP_RV770) { 3480 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { 3481 WREG32(RLC_UCODE_ADDR, i); 3482 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3483 } 3484 } else { 3485 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) { 3486 WREG32(RLC_UCODE_ADDR, i); 3487 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3488 } 3489 } 3490 WREG32(RLC_UCODE_ADDR, 0); 3491 3492 r600_rlc_start(rdev); 3493 3494 return 0; 3495 } 3496 3497 static void r600_enable_interrupts(struct radeon_device *rdev) 3498 { 3499 u32 ih_cntl = RREG32(IH_CNTL); 3500 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3501 3502 ih_cntl |= ENABLE_INTR; 3503 ih_rb_cntl |= IH_RB_ENABLE; 3504 WREG32(IH_CNTL, ih_cntl); 3505 WREG32(IH_RB_CNTL, ih_rb_cntl); 3506 rdev->ih.enabled = true; 3507 } 3508 3509 void r600_disable_interrupts(struct radeon_device *rdev) 3510 { 3511 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3512 u32 ih_cntl = RREG32(IH_CNTL); 3513 3514 ih_rb_cntl &= ~IH_RB_ENABLE; 3515 ih_cntl &= ~ENABLE_INTR; 3516 WREG32(IH_RB_CNTL, ih_rb_cntl); 3517 WREG32(IH_CNTL, ih_cntl); 3518 /* set rptr, wptr to 0 */ 3519 WREG32(IH_RB_RPTR, 0); 3520 WREG32(IH_RB_WPTR, 0); 3521 rdev->ih.enabled = false; 3522 rdev->ih.rptr = 0; 3523 } 3524 3525 static void r600_disable_interrupt_state(struct radeon_device *rdev) 3526 { 3527 u32 tmp; 3528 3529 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 3530 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3531 WREG32(DMA_CNTL, tmp); 3532 WREG32(GRBM_INT_CNTL, 0); 3533 WREG32(DxMODE_INT_MASK, 0); 3534 WREG32(D1GRPH_INTERRUPT_CONTROL, 0); 3535 WREG32(D2GRPH_INTERRUPT_CONTROL, 0); 3536 if (ASIC_IS_DCE3(rdev)) { 3537 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); 3538 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); 3539 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3540 WREG32(DC_HPD1_INT_CONTROL, tmp); 3541 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3542 WREG32(DC_HPD2_INT_CONTROL, tmp); 3543 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3544 WREG32(DC_HPD3_INT_CONTROL, tmp); 3545 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3546 WREG32(DC_HPD4_INT_CONTROL, tmp); 3547 if (ASIC_IS_DCE32(rdev)) { 3548 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3549 WREG32(DC_HPD5_INT_CONTROL, tmp); 3550 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3551 WREG32(DC_HPD6_INT_CONTROL, tmp); 3552 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3553 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3554 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3555 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3556 } else { 3557 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3558 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3559 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3560 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 3561 } 3562 } else { 3563 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 3564 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 3565 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3566 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3567 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3568 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3569 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3570 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3571 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3572 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3573 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3574 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 3575 } 3576 } 3577 3578 int r600_irq_init(struct radeon_device *rdev) 3579 { 3580 int ret = 0; 3581 int rb_bufsz; 3582 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 3583 3584 /* allocate ring */ 3585 ret = r600_ih_ring_alloc(rdev); 3586 if (ret) 3587 return ret; 3588 3589 /* disable irqs */ 3590 r600_disable_interrupts(rdev); 3591 3592 /* init rlc */ 3593 if (rdev->family >= CHIP_CEDAR) 3594 ret = evergreen_rlc_resume(rdev); 3595 else 3596 ret = r600_rlc_resume(rdev); 3597 if (ret) { 3598 r600_ih_ring_fini(rdev); 3599 return ret; 3600 } 3601 3602 /* setup interrupt control */ 3603 /* set dummy read address to ring address */ 3604 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); 3605 interrupt_cntl = RREG32(INTERRUPT_CNTL); 3606 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi 3607 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN 3608 */ 3609 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 3610 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ 3611 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 3612 WREG32(INTERRUPT_CNTL, interrupt_cntl); 3613 3614 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); 3615 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); 3616 3617 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | 3618 IH_WPTR_OVERFLOW_CLEAR | 3619 (rb_bufsz << 1)); 3620 3621 if (rdev->wb.enabled) 3622 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; 3623 3624 /* set the writeback address whether it's enabled or not */ 3625 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); 3626 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); 3627 3628 WREG32(IH_RB_CNTL, ih_rb_cntl); 3629 3630 /* set rptr, wptr to 0 */ 3631 WREG32(IH_RB_RPTR, 0); 3632 WREG32(IH_RB_WPTR, 0); 3633 3634 /* Default settings for IH_CNTL (disabled at first) */ 3635 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); 3636 /* RPTR_REARM only works if msi's are enabled */ 3637 if (rdev->msi_enabled) 3638 ih_cntl |= RPTR_REARM; 3639 WREG32(IH_CNTL, ih_cntl); 3640 3641 /* force the active interrupt state to all disabled */ 3642 if (rdev->family >= CHIP_CEDAR) 3643 evergreen_disable_interrupt_state(rdev); 3644 else 3645 r600_disable_interrupt_state(rdev); 3646 3647 /* at this point everything should be setup correctly to enable master */ 3648 pci_set_master(rdev->pdev); 3649 3650 /* enable irqs */ 3651 r600_enable_interrupts(rdev); 3652 3653 return ret; 3654 } 3655 3656 void r600_irq_suspend(struct radeon_device *rdev) 3657 { 3658 r600_irq_disable(rdev); 3659 r600_rlc_stop(rdev); 3660 } 3661 3662 void r600_irq_fini(struct radeon_device *rdev) 3663 { 3664 r600_irq_suspend(rdev); 3665 r600_ih_ring_fini(rdev); 3666 } 3667 3668 int r600_irq_set(struct radeon_device *rdev) 3669 { 3670 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 3671 u32 mode_int = 0; 3672 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 3673 u32 grbm_int_cntl = 0; 3674 u32 hdmi0, hdmi1; 3675 u32 dma_cntl; 3676 u32 thermal_int = 0; 3677 3678 if (!rdev->irq.installed) { 3679 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 3680 return -EINVAL; 3681 } 3682 /* don't enable anything if the ih is disabled */ 3683 if (!rdev->ih.enabled) { 3684 r600_disable_interrupts(rdev); 3685 /* force the active interrupt state to all disabled */ 3686 r600_disable_interrupt_state(rdev); 3687 return 0; 3688 } 3689 3690 if (ASIC_IS_DCE3(rdev)) { 3691 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3692 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3693 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3694 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 3695 if (ASIC_IS_DCE32(rdev)) { 3696 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 3697 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 3698 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3699 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3700 } else { 3701 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3702 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3703 } 3704 } else { 3705 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3706 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3707 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3708 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3709 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3710 } 3711 3712 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3713 3714 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { 3715 thermal_int = RREG32(CG_THERMAL_INT) & 3716 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 3717 } else if (rdev->family >= CHIP_RV770) { 3718 thermal_int = RREG32(RV770_CG_THERMAL_INT) & 3719 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 3720 } 3721 if (rdev->irq.dpm_thermal) { 3722 DRM_DEBUG("dpm thermal\n"); 3723 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 3724 } 3725 3726 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 3727 DRM_DEBUG("r600_irq_set: sw int\n"); 3728 cp_int_cntl |= RB_INT_ENABLE; 3729 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 3730 } 3731 3732 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { 3733 DRM_DEBUG("r600_irq_set: sw int dma\n"); 3734 dma_cntl |= TRAP_ENABLE; 3735 } 3736 3737 if (rdev->irq.crtc_vblank_int[0] || 3738 atomic_read(&rdev->irq.pflip[0])) { 3739 DRM_DEBUG("r600_irq_set: vblank 0\n"); 3740 mode_int |= D1MODE_VBLANK_INT_MASK; 3741 } 3742 if (rdev->irq.crtc_vblank_int[1] || 3743 atomic_read(&rdev->irq.pflip[1])) { 3744 DRM_DEBUG("r600_irq_set: vblank 1\n"); 3745 mode_int |= D2MODE_VBLANK_INT_MASK; 3746 } 3747 if (rdev->irq.hpd[0]) { 3748 DRM_DEBUG("r600_irq_set: hpd 1\n"); 3749 hpd1 |= DC_HPDx_INT_EN; 3750 } 3751 if (rdev->irq.hpd[1]) { 3752 DRM_DEBUG("r600_irq_set: hpd 2\n"); 3753 hpd2 |= DC_HPDx_INT_EN; 3754 } 3755 if (rdev->irq.hpd[2]) { 3756 DRM_DEBUG("r600_irq_set: hpd 3\n"); 3757 hpd3 |= DC_HPDx_INT_EN; 3758 } 3759 if (rdev->irq.hpd[3]) { 3760 DRM_DEBUG("r600_irq_set: hpd 4\n"); 3761 hpd4 |= DC_HPDx_INT_EN; 3762 } 3763 if (rdev->irq.hpd[4]) { 3764 DRM_DEBUG("r600_irq_set: hpd 5\n"); 3765 hpd5 |= DC_HPDx_INT_EN; 3766 } 3767 if (rdev->irq.hpd[5]) { 3768 DRM_DEBUG("r600_irq_set: hpd 6\n"); 3769 hpd6 |= DC_HPDx_INT_EN; 3770 } 3771 if (rdev->irq.afmt[0]) { 3772 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3773 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3774 } 3775 if (rdev->irq.afmt[1]) { 3776 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3777 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3778 } 3779 3780 WREG32(CP_INT_CNTL, cp_int_cntl); 3781 WREG32(DMA_CNTL, dma_cntl); 3782 WREG32(DxMODE_INT_MASK, mode_int); 3783 WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); 3784 WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); 3785 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 3786 if (ASIC_IS_DCE3(rdev)) { 3787 WREG32(DC_HPD1_INT_CONTROL, hpd1); 3788 WREG32(DC_HPD2_INT_CONTROL, hpd2); 3789 WREG32(DC_HPD3_INT_CONTROL, hpd3); 3790 WREG32(DC_HPD4_INT_CONTROL, hpd4); 3791 if (ASIC_IS_DCE32(rdev)) { 3792 WREG32(DC_HPD5_INT_CONTROL, hpd5); 3793 WREG32(DC_HPD6_INT_CONTROL, hpd6); 3794 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); 3795 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); 3796 } else { 3797 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3798 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3799 } 3800 } else { 3801 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 3802 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 3803 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); 3804 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3805 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3806 } 3807 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { 3808 WREG32(CG_THERMAL_INT, thermal_int); 3809 } else if (rdev->family >= CHIP_RV770) { 3810 WREG32(RV770_CG_THERMAL_INT, thermal_int); 3811 } 3812 3813 /* posting read */ 3814 RREG32(R_000E50_SRBM_STATUS); 3815 3816 return 0; 3817 } 3818 3819 static void r600_irq_ack(struct radeon_device *rdev) 3820 { 3821 u32 tmp; 3822 3823 if (ASIC_IS_DCE3(rdev)) { 3824 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); 3825 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); 3826 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); 3827 if (ASIC_IS_DCE32(rdev)) { 3828 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); 3829 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); 3830 } else { 3831 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3832 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); 3833 } 3834 } else { 3835 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); 3836 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 3837 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; 3838 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3839 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); 3840 } 3841 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); 3842 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); 3843 3844 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3845 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3846 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3847 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3848 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) 3849 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3850 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) 3851 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3852 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) 3853 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3854 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) 3855 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3856 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 3857 if (ASIC_IS_DCE3(rdev)) { 3858 tmp = RREG32(DC_HPD1_INT_CONTROL); 3859 tmp |= DC_HPDx_INT_ACK; 3860 WREG32(DC_HPD1_INT_CONTROL, tmp); 3861 } else { 3862 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 3863 tmp |= DC_HPDx_INT_ACK; 3864 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3865 } 3866 } 3867 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 3868 if (ASIC_IS_DCE3(rdev)) { 3869 tmp = RREG32(DC_HPD2_INT_CONTROL); 3870 tmp |= DC_HPDx_INT_ACK; 3871 WREG32(DC_HPD2_INT_CONTROL, tmp); 3872 } else { 3873 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 3874 tmp |= DC_HPDx_INT_ACK; 3875 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3876 } 3877 } 3878 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 3879 if (ASIC_IS_DCE3(rdev)) { 3880 tmp = RREG32(DC_HPD3_INT_CONTROL); 3881 tmp |= DC_HPDx_INT_ACK; 3882 WREG32(DC_HPD3_INT_CONTROL, tmp); 3883 } else { 3884 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 3885 tmp |= DC_HPDx_INT_ACK; 3886 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3887 } 3888 } 3889 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 3890 tmp = RREG32(DC_HPD4_INT_CONTROL); 3891 tmp |= DC_HPDx_INT_ACK; 3892 WREG32(DC_HPD4_INT_CONTROL, tmp); 3893 } 3894 if (ASIC_IS_DCE32(rdev)) { 3895 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 3896 tmp = RREG32(DC_HPD5_INT_CONTROL); 3897 tmp |= DC_HPDx_INT_ACK; 3898 WREG32(DC_HPD5_INT_CONTROL, tmp); 3899 } 3900 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 3901 tmp = RREG32(DC_HPD5_INT_CONTROL); 3902 tmp |= DC_HPDx_INT_ACK; 3903 WREG32(DC_HPD6_INT_CONTROL, tmp); 3904 } 3905 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { 3906 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); 3907 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 3908 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3909 } 3910 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { 3911 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); 3912 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 3913 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3914 } 3915 } else { 3916 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 3917 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); 3918 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3919 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3920 } 3921 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 3922 if (ASIC_IS_DCE3(rdev)) { 3923 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); 3924 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3925 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 3926 } else { 3927 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); 3928 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3929 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 3930 } 3931 } 3932 } 3933 } 3934 3935 void r600_irq_disable(struct radeon_device *rdev) 3936 { 3937 r600_disable_interrupts(rdev); 3938 /* Wait and acknowledge irq */ 3939 mdelay(1); 3940 r600_irq_ack(rdev); 3941 r600_disable_interrupt_state(rdev); 3942 } 3943 3944 static u32 r600_get_ih_wptr(struct radeon_device *rdev) 3945 { 3946 u32 wptr, tmp; 3947 3948 if (rdev->wb.enabled) 3949 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 3950 else 3951 wptr = RREG32(IH_RB_WPTR); 3952 3953 if (wptr & RB_OVERFLOW) { 3954 wptr &= ~RB_OVERFLOW; 3955 /* When a ring buffer overflow happen start parsing interrupt 3956 * from the last not overwritten vector (wptr + 16). Hopefully 3957 * this should allow us to catchup. 3958 */ 3959 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 3960 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); 3961 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 3962 tmp = RREG32(IH_RB_CNTL); 3963 tmp |= IH_WPTR_OVERFLOW_CLEAR; 3964 WREG32(IH_RB_CNTL, tmp); 3965 } 3966 return (wptr & rdev->ih.ptr_mask); 3967 } 3968 3969 /* r600 IV Ring 3970 * Each IV ring entry is 128 bits: 3971 * [7:0] - interrupt source id 3972 * [31:8] - reserved 3973 * [59:32] - interrupt source data 3974 * [127:60] - reserved 3975 * 3976 * The basic interrupt vector entries 3977 * are decoded as follows: 3978 * src_id src_data description 3979 * 1 0 D1 Vblank 3980 * 1 1 D1 Vline 3981 * 5 0 D2 Vblank 3982 * 5 1 D2 Vline 3983 * 19 0 FP Hot plug detection A 3984 * 19 1 FP Hot plug detection B 3985 * 19 2 DAC A auto-detection 3986 * 19 3 DAC B auto-detection 3987 * 21 4 HDMI block A 3988 * 21 5 HDMI block B 3989 * 176 - CP_INT RB 3990 * 177 - CP_INT IB1 3991 * 178 - CP_INT IB2 3992 * 181 - EOP Interrupt 3993 * 233 - GUI Idle 3994 * 3995 * Note, these are based on r600 and may need to be 3996 * adjusted or added to on newer asics 3997 */ 3998 3999 int r600_irq_process(struct radeon_device *rdev) 4000 { 4001 u32 wptr; 4002 u32 rptr; 4003 u32 src_id, src_data; 4004 u32 ring_index; 4005 bool queue_hotplug = false; 4006 bool queue_hdmi = false; 4007 bool queue_thermal = false; 4008 4009 if (!rdev->ih.enabled || rdev->shutdown) 4010 return IRQ_NONE; 4011 4012 /* No MSIs, need a dummy read to flush PCI DMAs */ 4013 if (!rdev->msi_enabled) 4014 RREG32(IH_RB_WPTR); 4015 4016 wptr = r600_get_ih_wptr(rdev); 4017 4018 restart_ih: 4019 /* is somebody else already processing irqs? */ 4020 if (atomic_xchg(&rdev->ih.lock, 1)) 4021 return IRQ_NONE; 4022 4023 rptr = rdev->ih.rptr; 4024 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 4025 4026 /* Order reading of wptr vs. reading of IH ring data */ 4027 rmb(); 4028 4029 /* display interrupts */ 4030 r600_irq_ack(rdev); 4031 4032 while (rptr != wptr) { 4033 /* wptr/rptr are in bytes! */ 4034 ring_index = rptr / 4; 4035 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 4036 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 4037 4038 switch (src_id) { 4039 case 1: /* D1 vblank/vline */ 4040 switch (src_data) { 4041 case 0: /* D1 vblank */ 4042 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) { 4043 if (rdev->irq.crtc_vblank_int[0]) { 4044 drm_handle_vblank(rdev->ddev, 0); 4045 rdev->pm.vblank_sync = true; 4046 wake_up(&rdev->irq.vblank_queue); 4047 } 4048 if (atomic_read(&rdev->irq.pflip[0])) 4049 radeon_crtc_handle_vblank(rdev, 0); 4050 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 4051 DRM_DEBUG("IH: D1 vblank\n"); 4052 } 4053 break; 4054 case 1: /* D1 vline */ 4055 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) { 4056 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; 4057 DRM_DEBUG("IH: D1 vline\n"); 4058 } 4059 break; 4060 default: 4061 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4062 break; 4063 } 4064 break; 4065 case 5: /* D2 vblank/vline */ 4066 switch (src_data) { 4067 case 0: /* D2 vblank */ 4068 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) { 4069 if (rdev->irq.crtc_vblank_int[1]) { 4070 drm_handle_vblank(rdev->ddev, 1); 4071 rdev->pm.vblank_sync = true; 4072 wake_up(&rdev->irq.vblank_queue); 4073 } 4074 if (atomic_read(&rdev->irq.pflip[1])) 4075 radeon_crtc_handle_vblank(rdev, 1); 4076 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; 4077 DRM_DEBUG("IH: D2 vblank\n"); 4078 } 4079 break; 4080 case 1: /* D1 vline */ 4081 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) { 4082 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; 4083 DRM_DEBUG("IH: D2 vline\n"); 4084 } 4085 break; 4086 default: 4087 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4088 break; 4089 } 4090 break; 4091 case 9: /* D1 pflip */ 4092 DRM_DEBUG("IH: D1 flip\n"); 4093 if (radeon_use_pflipirq > 0) 4094 radeon_crtc_handle_flip(rdev, 0); 4095 break; 4096 case 11: /* D2 pflip */ 4097 DRM_DEBUG("IH: D2 flip\n"); 4098 if (radeon_use_pflipirq > 0) 4099 radeon_crtc_handle_flip(rdev, 1); 4100 break; 4101 case 19: /* HPD/DAC hotplug */ 4102 switch (src_data) { 4103 case 0: 4104 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 4105 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; 4106 queue_hotplug = true; 4107 DRM_DEBUG("IH: HPD1\n"); 4108 } 4109 break; 4110 case 1: 4111 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 4112 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; 4113 queue_hotplug = true; 4114 DRM_DEBUG("IH: HPD2\n"); 4115 } 4116 break; 4117 case 4: 4118 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 4119 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; 4120 queue_hotplug = true; 4121 DRM_DEBUG("IH: HPD3\n"); 4122 } 4123 break; 4124 case 5: 4125 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 4126 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; 4127 queue_hotplug = true; 4128 DRM_DEBUG("IH: HPD4\n"); 4129 } 4130 break; 4131 case 10: 4132 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 4133 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; 4134 queue_hotplug = true; 4135 DRM_DEBUG("IH: HPD5\n"); 4136 } 4137 break; 4138 case 12: 4139 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 4140 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; 4141 queue_hotplug = true; 4142 DRM_DEBUG("IH: HPD6\n"); 4143 } 4144 break; 4145 default: 4146 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4147 break; 4148 } 4149 break; 4150 case 21: /* hdmi */ 4151 switch (src_data) { 4152 case 4: 4153 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 4154 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4155 queue_hdmi = true; 4156 DRM_DEBUG("IH: HDMI0\n"); 4157 } 4158 break; 4159 case 5: 4160 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 4161 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4162 queue_hdmi = true; 4163 DRM_DEBUG("IH: HDMI1\n"); 4164 } 4165 break; 4166 default: 4167 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 4168 break; 4169 } 4170 break; 4171 case 124: /* UVD */ 4172 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); 4173 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); 4174 break; 4175 case 176: /* CP_INT in ring buffer */ 4176 case 177: /* CP_INT in IB1 */ 4177 case 178: /* CP_INT in IB2 */ 4178 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); 4179 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4180 break; 4181 case 181: /* CP EOP event */ 4182 DRM_DEBUG("IH: CP EOP\n"); 4183 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4184 break; 4185 case 224: /* DMA trap event */ 4186 DRM_DEBUG("IH: DMA trap\n"); 4187 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); 4188 break; 4189 case 230: /* thermal low to high */ 4190 DRM_DEBUG("IH: thermal low to high\n"); 4191 rdev->pm.dpm.thermal.high_to_low = false; 4192 queue_thermal = true; 4193 break; 4194 case 231: /* thermal high to low */ 4195 DRM_DEBUG("IH: thermal high to low\n"); 4196 rdev->pm.dpm.thermal.high_to_low = true; 4197 queue_thermal = true; 4198 break; 4199 case 233: /* GUI IDLE */ 4200 DRM_DEBUG("IH: GUI idle\n"); 4201 break; 4202 default: 4203 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4204 break; 4205 } 4206 4207 /* wptr/rptr are in bytes! */ 4208 rptr += 16; 4209 rptr &= rdev->ih.ptr_mask; 4210 WREG32(IH_RB_RPTR, rptr); 4211 } 4212 if (queue_hotplug) 4213 schedule_work(&rdev->hotplug_work); 4214 if (queue_hdmi) 4215 schedule_work(&rdev->audio_work); 4216 if (queue_thermal && rdev->pm.dpm_enabled) 4217 schedule_work(&rdev->pm.dpm.thermal.work); 4218 rdev->ih.rptr = rptr; 4219 atomic_set(&rdev->ih.lock, 0); 4220 4221 /* make sure wptr hasn't changed while processing */ 4222 wptr = r600_get_ih_wptr(rdev); 4223 if (wptr != rptr) 4224 goto restart_ih; 4225 4226 return IRQ_HANDLED; 4227 } 4228 4229 /* 4230 * Debugfs info 4231 */ 4232 #if defined(CONFIG_DEBUG_FS) 4233 4234 static int r600_debugfs_mc_info(struct seq_file *m, void *data) 4235 { 4236 struct drm_info_node *node = (struct drm_info_node *) m->private; 4237 struct drm_device *dev = node->minor->dev; 4238 struct radeon_device *rdev = dev->dev_private; 4239 4240 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); 4241 DREG32_SYS(m, rdev, VM_L2_STATUS); 4242 return 0; 4243 } 4244 4245 static struct drm_info_list r600_mc_info_list[] = { 4246 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, 4247 }; 4248 #endif 4249 4250 int r600_debugfs_mc_info_init(struct radeon_device *rdev) 4251 { 4252 #if defined(CONFIG_DEBUG_FS) 4253 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); 4254 #else 4255 return 0; 4256 #endif 4257 } 4258 4259 /** 4260 * r600_mmio_hdp_flush - flush Host Data Path cache via MMIO 4261 * rdev: radeon device structure 4262 * 4263 * Some R6XX/R7XX don't seem to take into account HDP flushes performed 4264 * through the ring buffer. This leads to corruption in rendering, see 4265 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 . To avoid this, we 4266 * directly perform the HDP flush by writing the register through MMIO. 4267 */ 4268 void r600_mmio_hdp_flush(struct radeon_device *rdev) 4269 { 4270 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 4271 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL. 4272 * This seems to cause problems on some AGP cards. Just use the old 4273 * method for them. 4274 */ 4275 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 4276 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { 4277 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; 4278 u32 tmp; 4279 4280 WREG32(HDP_DEBUG1, 0); 4281 tmp = readl((void __iomem *)ptr); 4282 } else 4283 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 4284 } 4285 4286 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) 4287 { 4288 u32 link_width_cntl, mask; 4289 4290 if (rdev->flags & RADEON_IS_IGP) 4291 return; 4292 4293 if (!(rdev->flags & RADEON_IS_PCIE)) 4294 return; 4295 4296 /* x2 cards have a special sequence */ 4297 if (ASIC_IS_X2(rdev)) 4298 return; 4299 4300 radeon_gui_idle(rdev); 4301 4302 switch (lanes) { 4303 case 0: 4304 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 4305 break; 4306 case 1: 4307 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 4308 break; 4309 case 2: 4310 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 4311 break; 4312 case 4: 4313 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 4314 break; 4315 case 8: 4316 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 4317 break; 4318 case 12: 4319 /* not actually supported */ 4320 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 4321 break; 4322 case 16: 4323 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 4324 break; 4325 default: 4326 DRM_ERROR("invalid pcie lane request: %d\n", lanes); 4327 return; 4328 } 4329 4330 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4331 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK; 4332 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT; 4333 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW | 4334 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); 4335 4336 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4337 } 4338 4339 int r600_get_pcie_lanes(struct radeon_device *rdev) 4340 { 4341 u32 link_width_cntl; 4342 4343 if (rdev->flags & RADEON_IS_IGP) 4344 return 0; 4345 4346 if (!(rdev->flags & RADEON_IS_PCIE)) 4347 return 0; 4348 4349 /* x2 cards have a special sequence */ 4350 if (ASIC_IS_X2(rdev)) 4351 return 0; 4352 4353 radeon_gui_idle(rdev); 4354 4355 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4356 4357 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 4358 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4359 return 1; 4360 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4361 return 2; 4362 case RADEON_PCIE_LC_LINK_WIDTH_X4: 4363 return 4; 4364 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4365 return 8; 4366 case RADEON_PCIE_LC_LINK_WIDTH_X12: 4367 /* not actually supported */ 4368 return 12; 4369 case RADEON_PCIE_LC_LINK_WIDTH_X0: 4370 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4371 default: 4372 return 16; 4373 } 4374 } 4375 4376 static void r600_pcie_gen2_enable(struct radeon_device *rdev) 4377 { 4378 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; 4379 u16 link_cntl2; 4380 4381 if (radeon_pcie_gen2 == 0) 4382 return; 4383 4384 if (rdev->flags & RADEON_IS_IGP) 4385 return; 4386 4387 if (!(rdev->flags & RADEON_IS_PCIE)) 4388 return; 4389 4390 /* x2 cards have a special sequence */ 4391 if (ASIC_IS_X2(rdev)) 4392 return; 4393 4394 /* only RV6xx+ chips are supported */ 4395 if (rdev->family <= CHIP_R600) 4396 return; 4397 4398 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && 4399 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) 4400 return; 4401 4402 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4403 if (speed_cntl & LC_CURRENT_DATA_RATE) { 4404 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 4405 return; 4406 } 4407 4408 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 4409 4410 /* 55 nm r6xx asics */ 4411 if ((rdev->family == CHIP_RV670) || 4412 (rdev->family == CHIP_RV620) || 4413 (rdev->family == CHIP_RV635)) { 4414 /* advertise upconfig capability */ 4415 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4416 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4417 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4418 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4419 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 4420 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 4421 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 4422 LC_RECONFIG_ARC_MISSING_ESCAPE); 4423 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; 4424 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4425 } else { 4426 link_width_cntl |= LC_UPCONFIGURE_DIS; 4427 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4428 } 4429 } 4430 4431 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4432 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 4433 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 4434 4435 /* 55 nm r6xx asics */ 4436 if ((rdev->family == CHIP_RV670) || 4437 (rdev->family == CHIP_RV620) || 4438 (rdev->family == CHIP_RV635)) { 4439 WREG32(MM_CFGREGS_CNTL, 0x8); 4440 link_cntl2 = RREG32(0x4088); 4441 WREG32(MM_CFGREGS_CNTL, 0); 4442 /* not supported yet */ 4443 if (link_cntl2 & SELECTABLE_DEEMPHASIS) 4444 return; 4445 } 4446 4447 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; 4448 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); 4449 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; 4450 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; 4451 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; 4452 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4453 4454 tmp = RREG32(0x541c); 4455 WREG32(0x541c, tmp | 0x8); 4456 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); 4457 link_cntl2 = RREG16(0x4088); 4458 link_cntl2 &= ~TARGET_LINK_SPEED_MASK; 4459 link_cntl2 |= 0x2; 4460 WREG16(0x4088, link_cntl2); 4461 WREG32(MM_CFGREGS_CNTL, 0); 4462 4463 if ((rdev->family == CHIP_RV670) || 4464 (rdev->family == CHIP_RV620) || 4465 (rdev->family == CHIP_RV635)) { 4466 training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL); 4467 training_cntl &= ~LC_POINT_7_PLUS_EN; 4468 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl); 4469 } else { 4470 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4471 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 4472 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4473 } 4474 4475 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 4476 speed_cntl |= LC_GEN2_EN_STRAP; 4477 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 4478 4479 } else { 4480 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 4481 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 4482 if (1) 4483 link_width_cntl |= LC_UPCONFIGURE_DIS; 4484 else 4485 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4486 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4487 } 4488 } 4489 4490 /** 4491 * r600_get_gpu_clock_counter - return GPU clock counter snapshot 4492 * 4493 * @rdev: radeon_device pointer 4494 * 4495 * Fetches a GPU clock counter snapshot (R6xx-cayman). 4496 * Returns the 64 bit clock counter snapshot. 4497 */ 4498 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev) 4499 { 4500 uint64_t clock; 4501 4502 mutex_lock(&rdev->gpu_clock_mutex); 4503 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4504 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | 4505 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4506 mutex_unlock(&rdev->gpu_clock_mutex); 4507 return clock; 4508 } 4509