1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include <linux/slab.h> 30 #include <drm/drmP.h> 31 #include "radeon_reg.h" 32 #include "radeon.h" 33 #include "radeon_asic.h" 34 #include "atom.h" 35 #include "r100d.h" 36 #include "r420d.h" 37 #include "r420_reg_safe.h" 38 39 void r420_pm_init_profile(struct radeon_device *rdev) 40 { 41 /* default */ 42 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 43 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 44 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 45 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 46 /* low sh */ 47 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 48 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 49 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 50 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 51 /* mid sh */ 52 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 53 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 54 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 55 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 56 /* high sh */ 57 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 58 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 59 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 60 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 61 /* low mh */ 62 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 63 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 64 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 65 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 66 /* mid mh */ 67 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 68 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 69 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 70 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 71 /* high mh */ 72 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 73 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 74 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 75 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 76 } 77 78 static void r420_set_reg_safe(struct radeon_device *rdev) 79 { 80 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; 81 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); 82 } 83 84 void r420_pipes_init(struct radeon_device *rdev) 85 { 86 unsigned tmp; 87 unsigned gb_pipe_select; 88 unsigned num_pipes; 89 90 /* GA_ENHANCE workaround TCL deadlock issue */ 91 WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL | 92 (1 << 2) | (1 << 3)); 93 /* add idle wait as per freedesktop.org bug 24041 */ 94 if (r100_gui_wait_for_idle(rdev)) { 95 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 96 } 97 /* get max number of pipes */ 98 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 99 num_pipes = ((gb_pipe_select >> 12) & 3) + 1; 100 101 /* SE chips have 1 pipe */ 102 if ((rdev->pdev->device == 0x5e4c) || 103 (rdev->pdev->device == 0x5e4f)) 104 num_pipes = 1; 105 106 rdev->num_gb_pipes = num_pipes; 107 tmp = 0; 108 switch (num_pipes) { 109 default: 110 /* force to 1 pipe */ 111 num_pipes = 1; 112 case 1: 113 tmp = (0 << 1); 114 break; 115 case 2: 116 tmp = (3 << 1); 117 break; 118 case 3: 119 tmp = (6 << 1); 120 break; 121 case 4: 122 tmp = (7 << 1); 123 break; 124 } 125 WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); 126 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 127 tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING; 128 WREG32(R300_GB_TILE_CONFIG, tmp); 129 if (r100_gui_wait_for_idle(rdev)) { 130 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 131 } 132 133 tmp = RREG32(R300_DST_PIPE_CONFIG); 134 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); 135 136 WREG32(R300_RB2D_DSTCACHE_MODE, 137 RREG32(R300_RB2D_DSTCACHE_MODE) | 138 R300_DC_AUTOFLUSH_ENABLE | 139 R300_DC_DC_DISABLE_IGNORE_PE); 140 141 if (r100_gui_wait_for_idle(rdev)) { 142 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 143 } 144 145 if (rdev->family == CHIP_RV530) { 146 tmp = RREG32(RV530_GB_PIPE_SELECT2); 147 if ((tmp & 3) == 3) 148 rdev->num_z_pipes = 2; 149 else 150 rdev->num_z_pipes = 1; 151 } else 152 rdev->num_z_pipes = 1; 153 154 DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n", 155 rdev->num_gb_pipes, rdev->num_z_pipes); 156 } 157 158 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) 159 { 160 unsigned long flags; 161 u32 r; 162 163 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 164 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); 165 r = RREG32(R_0001FC_MC_IND_DATA); 166 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 167 return r; 168 } 169 170 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 171 { 172 unsigned long flags; 173 174 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 175 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | 176 S_0001F8_MC_IND_WR_EN(1)); 177 WREG32(R_0001FC_MC_IND_DATA, v); 178 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 179 } 180 181 static void r420_debugfs(struct radeon_device *rdev) 182 { 183 if (r100_debugfs_rbbm_init(rdev)) { 184 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 185 } 186 if (r420_debugfs_pipes_info_init(rdev)) { 187 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 188 } 189 } 190 191 static void r420_clock_resume(struct radeon_device *rdev) 192 { 193 u32 sclk_cntl; 194 195 if (radeon_dynclks != -1 && radeon_dynclks) 196 radeon_atom_set_clock_gating(rdev, 1); 197 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); 198 sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 199 if (rdev->family == CHIP_R420) 200 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1); 201 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); 202 } 203 204 static void r420_cp_errata_init(struct radeon_device *rdev) 205 { 206 int r; 207 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 208 209 /* RV410 and R420 can lock up if CP DMA to host memory happens 210 * while the 2D engine is busy. 211 * 212 * The proper workaround is to queue a RESYNC at the beginning 213 * of the CP init, apparently. 214 */ 215 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); 216 r = radeon_ring_lock(rdev, ring, 8); 217 WARN_ON(r); 218 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); 219 radeon_ring_write(ring, rdev->config.r300.resync_scratch); 220 radeon_ring_write(ring, 0xDEADBEEF); 221 radeon_ring_unlock_commit(rdev, ring, false); 222 } 223 224 static void r420_cp_errata_fini(struct radeon_device *rdev) 225 { 226 int r; 227 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 228 229 /* Catch the RESYNC we dispatched all the way back, 230 * at the very beginning of the CP init. 231 */ 232 r = radeon_ring_lock(rdev, ring, 8); 233 WARN_ON(r); 234 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 235 radeon_ring_write(ring, R300_RB3D_DC_FINISH); 236 radeon_ring_unlock_commit(rdev, ring, false); 237 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); 238 } 239 240 static int r420_startup(struct radeon_device *rdev) 241 { 242 int r; 243 244 /* set common regs */ 245 r100_set_common_regs(rdev); 246 /* program mc */ 247 r300_mc_program(rdev); 248 /* Resume clock */ 249 r420_clock_resume(rdev); 250 /* Initialize GART (initialize after TTM so we can allocate 251 * memory through TTM but finalize after TTM) */ 252 if (rdev->flags & RADEON_IS_PCIE) { 253 r = rv370_pcie_gart_enable(rdev); 254 if (r) 255 return r; 256 } 257 if (rdev->flags & RADEON_IS_PCI) { 258 r = r100_pci_gart_enable(rdev); 259 if (r) 260 return r; 261 } 262 r420_pipes_init(rdev); 263 264 /* allocate wb buffer */ 265 r = radeon_wb_init(rdev); 266 if (r) 267 return r; 268 269 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 270 if (r) { 271 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 272 return r; 273 } 274 275 /* Enable IRQ */ 276 if (!rdev->irq.installed) { 277 r = radeon_irq_kms_init(rdev); 278 if (r) 279 return r; 280 } 281 282 r100_irq_set(rdev); 283 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 284 /* 1M ring buffer */ 285 r = r100_cp_init(rdev, 1024 * 1024); 286 if (r) { 287 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 288 return r; 289 } 290 r420_cp_errata_init(rdev); 291 292 r = radeon_ib_pool_init(rdev); 293 if (r) { 294 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 295 return r; 296 } 297 298 return 0; 299 } 300 301 int r420_resume(struct radeon_device *rdev) 302 { 303 int r; 304 305 /* Make sur GART are not working */ 306 if (rdev->flags & RADEON_IS_PCIE) 307 rv370_pcie_gart_disable(rdev); 308 if (rdev->flags & RADEON_IS_PCI) 309 r100_pci_gart_disable(rdev); 310 /* Resume clock before doing reset */ 311 r420_clock_resume(rdev); 312 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 313 if (radeon_asic_reset(rdev)) { 314 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 315 RREG32(R_000E40_RBBM_STATUS), 316 RREG32(R_0007C0_CP_STAT)); 317 } 318 /* check if cards are posted or not */ 319 if (rdev->is_atom_bios) { 320 atom_asic_init(rdev->mode_info.atom_context); 321 } else { 322 radeon_combios_asic_init(rdev->ddev); 323 } 324 /* Resume clock after posting */ 325 r420_clock_resume(rdev); 326 /* Initialize surface registers */ 327 radeon_surface_init(rdev); 328 329 rdev->accel_working = true; 330 r = r420_startup(rdev); 331 if (r) { 332 rdev->accel_working = false; 333 } 334 return r; 335 } 336 337 int r420_suspend(struct radeon_device *rdev) 338 { 339 radeon_pm_suspend(rdev); 340 r420_cp_errata_fini(rdev); 341 r100_cp_disable(rdev); 342 radeon_wb_disable(rdev); 343 r100_irq_disable(rdev); 344 if (rdev->flags & RADEON_IS_PCIE) 345 rv370_pcie_gart_disable(rdev); 346 if (rdev->flags & RADEON_IS_PCI) 347 r100_pci_gart_disable(rdev); 348 return 0; 349 } 350 351 void r420_fini(struct radeon_device *rdev) 352 { 353 radeon_pm_fini(rdev); 354 r100_cp_fini(rdev); 355 radeon_wb_fini(rdev); 356 radeon_ib_pool_fini(rdev); 357 radeon_gem_fini(rdev); 358 if (rdev->flags & RADEON_IS_PCIE) 359 rv370_pcie_gart_fini(rdev); 360 if (rdev->flags & RADEON_IS_PCI) 361 r100_pci_gart_fini(rdev); 362 radeon_agp_fini(rdev); 363 radeon_irq_kms_fini(rdev); 364 radeon_fence_driver_fini(rdev); 365 radeon_bo_fini(rdev); 366 if (rdev->is_atom_bios) { 367 radeon_atombios_fini(rdev); 368 } else { 369 radeon_combios_fini(rdev); 370 } 371 kfree(rdev->bios); 372 rdev->bios = NULL; 373 } 374 375 int r420_init(struct radeon_device *rdev) 376 { 377 int r; 378 379 /* Initialize scratch registers */ 380 radeon_scratch_init(rdev); 381 /* Initialize surface registers */ 382 radeon_surface_init(rdev); 383 /* TODO: disable VGA need to use VGA request */ 384 /* restore some register to sane defaults */ 385 r100_restore_sanity(rdev); 386 /* BIOS*/ 387 if (!radeon_get_bios(rdev)) { 388 if (ASIC_IS_AVIVO(rdev)) 389 return -EINVAL; 390 } 391 if (rdev->is_atom_bios) { 392 r = radeon_atombios_init(rdev); 393 if (r) { 394 return r; 395 } 396 } else { 397 r = radeon_combios_init(rdev); 398 if (r) { 399 return r; 400 } 401 } 402 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 403 if (radeon_asic_reset(rdev)) { 404 dev_warn(rdev->dev, 405 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 406 RREG32(R_000E40_RBBM_STATUS), 407 RREG32(R_0007C0_CP_STAT)); 408 } 409 /* check if cards are posted or not */ 410 if (radeon_boot_test_post_card(rdev) == false) 411 return -EINVAL; 412 413 /* Initialize clocks */ 414 radeon_get_clock_info(rdev->ddev); 415 /* initialize AGP */ 416 if (rdev->flags & RADEON_IS_AGP) { 417 r = radeon_agp_init(rdev); 418 if (r) { 419 radeon_agp_disable(rdev); 420 } 421 } 422 /* initialize memory controller */ 423 r300_mc_init(rdev); 424 r420_debugfs(rdev); 425 /* Fence driver */ 426 r = radeon_fence_driver_init(rdev); 427 if (r) { 428 return r; 429 } 430 /* Memory manager */ 431 r = radeon_bo_init(rdev); 432 if (r) { 433 return r; 434 } 435 if (rdev->family == CHIP_R420) 436 r100_enable_bm(rdev); 437 438 if (rdev->flags & RADEON_IS_PCIE) { 439 r = rv370_pcie_gart_init(rdev); 440 if (r) 441 return r; 442 } 443 if (rdev->flags & RADEON_IS_PCI) { 444 r = r100_pci_gart_init(rdev); 445 if (r) 446 return r; 447 } 448 r420_set_reg_safe(rdev); 449 450 /* Initialize power management */ 451 radeon_pm_init(rdev); 452 453 rdev->accel_working = true; 454 r = r420_startup(rdev); 455 if (r) { 456 /* Somethings want wront with the accel init stop accel */ 457 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 458 r100_cp_fini(rdev); 459 radeon_wb_fini(rdev); 460 radeon_ib_pool_fini(rdev); 461 radeon_irq_kms_fini(rdev); 462 if (rdev->flags & RADEON_IS_PCIE) 463 rv370_pcie_gart_fini(rdev); 464 if (rdev->flags & RADEON_IS_PCI) 465 r100_pci_gart_fini(rdev); 466 radeon_agp_fini(rdev); 467 rdev->accel_working = false; 468 } 469 return 0; 470 } 471 472 /* 473 * Debugfs info 474 */ 475 #if defined(CONFIG_DEBUG_FS) 476 static int r420_debugfs_pipes_info(struct seq_file *m, void *data) 477 { 478 struct drm_info_node *node = (struct drm_info_node *) m->private; 479 struct drm_device *dev = node->minor->dev; 480 struct radeon_device *rdev = dev->dev_private; 481 uint32_t tmp; 482 483 tmp = RREG32(R400_GB_PIPE_SELECT); 484 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 485 tmp = RREG32(R300_GB_TILE_CONFIG); 486 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 487 tmp = RREG32(R300_DST_PIPE_CONFIG); 488 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 489 return 0; 490 } 491 492 static struct drm_info_list r420_pipes_info_list[] = { 493 {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL}, 494 }; 495 #endif 496 497 int r420_debugfs_pipes_info_init(struct radeon_device *rdev) 498 { 499 #if defined(CONFIG_DEBUG_FS) 500 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); 501 #else 502 return 0; 503 #endif 504 } 505