1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include "drmP.h" 30 #include "radeon_reg.h" 31 #include "radeon.h" 32 33 /* r420,r423,rv410 depends on : */ 34 void r100_pci_gart_disable(struct radeon_device *rdev); 35 void r100_hdp_reset(struct radeon_device *rdev); 36 void r100_mc_setup(struct radeon_device *rdev); 37 int r100_gui_wait_for_idle(struct radeon_device *rdev); 38 void r100_mc_disable_clients(struct radeon_device *rdev); 39 void r300_vram_info(struct radeon_device *rdev); 40 int r300_mc_wait_for_idle(struct radeon_device *rdev); 41 int rv370_pcie_gart_enable(struct radeon_device *rdev); 42 void rv370_pcie_gart_disable(struct radeon_device *rdev); 43 44 /* This files gather functions specifics to : 45 * r420,r423,rv410 46 * 47 * Some of these functions might be used by newer ASICs. 48 */ 49 void r420_gpu_init(struct radeon_device *rdev); 50 int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 51 52 53 /* 54 * MC 55 */ 56 int r420_mc_init(struct radeon_device *rdev) 57 { 58 int r; 59 60 if (r100_debugfs_rbbm_init(rdev)) { 61 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 62 } 63 if (r420_debugfs_pipes_info_init(rdev)) { 64 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 65 } 66 67 r420_gpu_init(rdev); 68 r100_pci_gart_disable(rdev); 69 if (rdev->flags & RADEON_IS_PCIE) { 70 rv370_pcie_gart_disable(rdev); 71 } 72 73 /* Setup GPU memory space */ 74 rdev->mc.vram_location = 0xFFFFFFFFUL; 75 rdev->mc.gtt_location = 0xFFFFFFFFUL; 76 if (rdev->flags & RADEON_IS_AGP) { 77 r = radeon_agp_init(rdev); 78 if (r) { 79 printk(KERN_WARNING "[drm] Disabling AGP\n"); 80 rdev->flags &= ~RADEON_IS_AGP; 81 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 82 } else { 83 rdev->mc.gtt_location = rdev->mc.agp_base; 84 } 85 } 86 r = radeon_mc_setup(rdev); 87 if (r) { 88 return r; 89 } 90 91 /* Program GPU memory space */ 92 r100_mc_disable_clients(rdev); 93 if (r300_mc_wait_for_idle(rdev)) { 94 printk(KERN_WARNING "Failed to wait MC idle while " 95 "programming pipes. Bad things might happen.\n"); 96 } 97 r100_mc_setup(rdev); 98 return 0; 99 } 100 101 void r420_mc_fini(struct radeon_device *rdev) 102 { 103 rv370_pcie_gart_disable(rdev); 104 radeon_gart_table_vram_free(rdev); 105 radeon_gart_fini(rdev); 106 } 107 108 109 /* 110 * Global GPU functions 111 */ 112 void r420_errata(struct radeon_device *rdev) 113 { 114 rdev->pll_errata = 0; 115 } 116 117 void r420_pipes_init(struct radeon_device *rdev) 118 { 119 unsigned tmp; 120 unsigned gb_pipe_select; 121 unsigned num_pipes; 122 123 /* GA_ENHANCE workaround TCL deadlock issue */ 124 WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)); 125 /* get max number of pipes */ 126 gb_pipe_select = RREG32(0x402C); 127 num_pipes = ((gb_pipe_select >> 12) & 3) + 1; 128 rdev->num_gb_pipes = num_pipes; 129 tmp = 0; 130 switch (num_pipes) { 131 default: 132 /* force to 1 pipe */ 133 num_pipes = 1; 134 case 1: 135 tmp = (0 << 1); 136 break; 137 case 2: 138 tmp = (3 << 1); 139 break; 140 case 3: 141 tmp = (6 << 1); 142 break; 143 case 4: 144 tmp = (7 << 1); 145 break; 146 } 147 WREG32(0x42C8, (1 << num_pipes) - 1); 148 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 149 tmp |= (1 << 4) | (1 << 0); 150 WREG32(0x4018, tmp); 151 if (r100_gui_wait_for_idle(rdev)) { 152 printk(KERN_WARNING "Failed to wait GUI idle while " 153 "programming pipes. Bad things might happen.\n"); 154 } 155 156 tmp = RREG32(0x170C); 157 WREG32(0x170C, tmp | (1 << 31)); 158 159 WREG32(R300_RB2D_DSTCACHE_MODE, 160 RREG32(R300_RB2D_DSTCACHE_MODE) | 161 R300_DC_AUTOFLUSH_ENABLE | 162 R300_DC_DC_DISABLE_IGNORE_PE); 163 164 if (r100_gui_wait_for_idle(rdev)) { 165 printk(KERN_WARNING "Failed to wait GUI idle while " 166 "programming pipes. Bad things might happen.\n"); 167 } 168 169 if (rdev->family == CHIP_RV530) { 170 tmp = RREG32(RV530_GB_PIPE_SELECT2); 171 if ((tmp & 3) == 3) 172 rdev->num_z_pipes = 2; 173 else 174 rdev->num_z_pipes = 1; 175 } else 176 rdev->num_z_pipes = 1; 177 178 DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n", 179 rdev->num_gb_pipes, rdev->num_z_pipes); 180 } 181 182 void r420_gpu_init(struct radeon_device *rdev) 183 { 184 r100_hdp_reset(rdev); 185 r420_pipes_init(rdev); 186 if (r300_mc_wait_for_idle(rdev)) { 187 printk(KERN_WARNING "Failed to wait MC idle while " 188 "programming pipes. Bad things might happen.\n"); 189 } 190 } 191 192 193 /* 194 * r420,r423,rv410 VRAM info 195 */ 196 void r420_vram_info(struct radeon_device *rdev) 197 { 198 r300_vram_info(rdev); 199 } 200 201 202 /* 203 * Debugfs info 204 */ 205 #if defined(CONFIG_DEBUG_FS) 206 static int r420_debugfs_pipes_info(struct seq_file *m, void *data) 207 { 208 struct drm_info_node *node = (struct drm_info_node *) m->private; 209 struct drm_device *dev = node->minor->dev; 210 struct radeon_device *rdev = dev->dev_private; 211 uint32_t tmp; 212 213 tmp = RREG32(R400_GB_PIPE_SELECT); 214 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 215 tmp = RREG32(R300_GB_TILE_CONFIG); 216 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 217 tmp = RREG32(R300_DST_PIPE_CONFIG); 218 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 219 return 0; 220 } 221 222 static struct drm_info_list r420_pipes_info_list[] = { 223 {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL}, 224 }; 225 #endif 226 227 int r420_debugfs_pipes_info_init(struct radeon_device *rdev) 228 { 229 #if defined(CONFIG_DEBUG_FS) 230 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); 231 #else 232 return 0; 233 #endif 234 } 235