1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include <linux/slab.h> 30 #include <drm/drmP.h> 31 #include "radeon_reg.h" 32 #include "radeon.h" 33 #include "radeon_asic.h" 34 #include "atom.h" 35 #include "r100d.h" 36 #include "r420d.h" 37 #include "r420_reg_safe.h" 38 39 void r420_pm_init_profile(struct radeon_device *rdev) 40 { 41 /* default */ 42 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 43 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 44 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 45 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 46 /* low sh */ 47 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 48 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 49 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 50 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 51 /* mid sh */ 52 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 53 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 54 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 55 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 56 /* high sh */ 57 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 58 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 59 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 60 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 61 /* low mh */ 62 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 63 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 64 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 65 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 66 /* mid mh */ 67 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 68 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 69 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 70 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 71 /* high mh */ 72 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 73 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 74 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 75 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 76 } 77 78 static void r420_set_reg_safe(struct radeon_device *rdev) 79 { 80 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; 81 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); 82 } 83 84 void r420_pipes_init(struct radeon_device *rdev) 85 { 86 unsigned tmp; 87 unsigned gb_pipe_select; 88 unsigned num_pipes; 89 90 /* GA_ENHANCE workaround TCL deadlock issue */ 91 WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL | 92 (1 << 2) | (1 << 3)); 93 /* add idle wait as per freedesktop.org bug 24041 */ 94 if (r100_gui_wait_for_idle(rdev)) { 95 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 96 } 97 /* get max number of pipes */ 98 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 99 num_pipes = ((gb_pipe_select >> 12) & 3) + 1; 100 101 /* SE chips have 1 pipe */ 102 if ((rdev->pdev->device == 0x5e4c) || 103 (rdev->pdev->device == 0x5e4f)) 104 num_pipes = 1; 105 106 rdev->num_gb_pipes = num_pipes; 107 tmp = 0; 108 switch (num_pipes) { 109 default: 110 /* force to 1 pipe */ 111 num_pipes = 1; 112 /* fall through */ 113 case 1: 114 tmp = (0 << 1); 115 break; 116 case 2: 117 tmp = (3 << 1); 118 break; 119 case 3: 120 tmp = (6 << 1); 121 break; 122 case 4: 123 tmp = (7 << 1); 124 break; 125 } 126 WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); 127 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 128 tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING; 129 WREG32(R300_GB_TILE_CONFIG, tmp); 130 if (r100_gui_wait_for_idle(rdev)) { 131 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 132 } 133 134 tmp = RREG32(R300_DST_PIPE_CONFIG); 135 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); 136 137 WREG32(R300_RB2D_DSTCACHE_MODE, 138 RREG32(R300_RB2D_DSTCACHE_MODE) | 139 R300_DC_AUTOFLUSH_ENABLE | 140 R300_DC_DC_DISABLE_IGNORE_PE); 141 142 if (r100_gui_wait_for_idle(rdev)) { 143 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 144 } 145 146 if (rdev->family == CHIP_RV530) { 147 tmp = RREG32(RV530_GB_PIPE_SELECT2); 148 if ((tmp & 3) == 3) 149 rdev->num_z_pipes = 2; 150 else 151 rdev->num_z_pipes = 1; 152 } else 153 rdev->num_z_pipes = 1; 154 155 DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n", 156 rdev->num_gb_pipes, rdev->num_z_pipes); 157 } 158 159 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) 160 { 161 unsigned long flags; 162 u32 r; 163 164 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 165 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); 166 r = RREG32(R_0001FC_MC_IND_DATA); 167 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 168 return r; 169 } 170 171 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 172 { 173 unsigned long flags; 174 175 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 176 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | 177 S_0001F8_MC_IND_WR_EN(1)); 178 WREG32(R_0001FC_MC_IND_DATA, v); 179 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 180 } 181 182 static void r420_debugfs(struct radeon_device *rdev) 183 { 184 if (r100_debugfs_rbbm_init(rdev)) { 185 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 186 } 187 if (r420_debugfs_pipes_info_init(rdev)) { 188 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 189 } 190 } 191 192 static void r420_clock_resume(struct radeon_device *rdev) 193 { 194 u32 sclk_cntl; 195 196 if (radeon_dynclks != -1 && radeon_dynclks) 197 radeon_atom_set_clock_gating(rdev, 1); 198 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); 199 sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 200 if (rdev->family == CHIP_R420) 201 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1); 202 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); 203 } 204 205 static void r420_cp_errata_init(struct radeon_device *rdev) 206 { 207 int r; 208 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 209 210 /* RV410 and R420 can lock up if CP DMA to host memory happens 211 * while the 2D engine is busy. 212 * 213 * The proper workaround is to queue a RESYNC at the beginning 214 * of the CP init, apparently. 215 */ 216 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); 217 r = radeon_ring_lock(rdev, ring, 8); 218 WARN_ON(r); 219 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); 220 radeon_ring_write(ring, rdev->config.r300.resync_scratch); 221 radeon_ring_write(ring, 0xDEADBEEF); 222 radeon_ring_unlock_commit(rdev, ring, false); 223 } 224 225 static void r420_cp_errata_fini(struct radeon_device *rdev) 226 { 227 int r; 228 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 229 230 /* Catch the RESYNC we dispatched all the way back, 231 * at the very beginning of the CP init. 232 */ 233 r = radeon_ring_lock(rdev, ring, 8); 234 WARN_ON(r); 235 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 236 radeon_ring_write(ring, R300_RB3D_DC_FINISH); 237 radeon_ring_unlock_commit(rdev, ring, false); 238 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); 239 } 240 241 static int r420_startup(struct radeon_device *rdev) 242 { 243 int r; 244 245 /* set common regs */ 246 r100_set_common_regs(rdev); 247 /* program mc */ 248 r300_mc_program(rdev); 249 /* Resume clock */ 250 r420_clock_resume(rdev); 251 /* Initialize GART (initialize after TTM so we can allocate 252 * memory through TTM but finalize after TTM) */ 253 if (rdev->flags & RADEON_IS_PCIE) { 254 r = rv370_pcie_gart_enable(rdev); 255 if (r) 256 return r; 257 } 258 if (rdev->flags & RADEON_IS_PCI) { 259 r = r100_pci_gart_enable(rdev); 260 if (r) 261 return r; 262 } 263 r420_pipes_init(rdev); 264 265 /* allocate wb buffer */ 266 r = radeon_wb_init(rdev); 267 if (r) 268 return r; 269 270 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 271 if (r) { 272 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 273 return r; 274 } 275 276 /* Enable IRQ */ 277 if (!rdev->irq.installed) { 278 r = radeon_irq_kms_init(rdev); 279 if (r) 280 return r; 281 } 282 283 r100_irq_set(rdev); 284 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 285 /* 1M ring buffer */ 286 r = r100_cp_init(rdev, 1024 * 1024); 287 if (r) { 288 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 289 return r; 290 } 291 r420_cp_errata_init(rdev); 292 293 r = radeon_ib_pool_init(rdev); 294 if (r) { 295 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 296 return r; 297 } 298 299 return 0; 300 } 301 302 int r420_resume(struct radeon_device *rdev) 303 { 304 int r; 305 306 /* Make sur GART are not working */ 307 if (rdev->flags & RADEON_IS_PCIE) 308 rv370_pcie_gart_disable(rdev); 309 if (rdev->flags & RADEON_IS_PCI) 310 r100_pci_gart_disable(rdev); 311 /* Resume clock before doing reset */ 312 r420_clock_resume(rdev); 313 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 314 if (radeon_asic_reset(rdev)) { 315 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 316 RREG32(R_000E40_RBBM_STATUS), 317 RREG32(R_0007C0_CP_STAT)); 318 } 319 /* check if cards are posted or not */ 320 if (rdev->is_atom_bios) { 321 atom_asic_init(rdev->mode_info.atom_context); 322 } else { 323 radeon_combios_asic_init(rdev->ddev); 324 } 325 /* Resume clock after posting */ 326 r420_clock_resume(rdev); 327 /* Initialize surface registers */ 328 radeon_surface_init(rdev); 329 330 rdev->accel_working = true; 331 r = r420_startup(rdev); 332 if (r) { 333 rdev->accel_working = false; 334 } 335 return r; 336 } 337 338 int r420_suspend(struct radeon_device *rdev) 339 { 340 radeon_pm_suspend(rdev); 341 r420_cp_errata_fini(rdev); 342 r100_cp_disable(rdev); 343 radeon_wb_disable(rdev); 344 r100_irq_disable(rdev); 345 if (rdev->flags & RADEON_IS_PCIE) 346 rv370_pcie_gart_disable(rdev); 347 if (rdev->flags & RADEON_IS_PCI) 348 r100_pci_gart_disable(rdev); 349 return 0; 350 } 351 352 void r420_fini(struct radeon_device *rdev) 353 { 354 radeon_pm_fini(rdev); 355 r100_cp_fini(rdev); 356 radeon_wb_fini(rdev); 357 radeon_ib_pool_fini(rdev); 358 radeon_gem_fini(rdev); 359 if (rdev->flags & RADEON_IS_PCIE) 360 rv370_pcie_gart_fini(rdev); 361 if (rdev->flags & RADEON_IS_PCI) 362 r100_pci_gart_fini(rdev); 363 radeon_agp_fini(rdev); 364 radeon_irq_kms_fini(rdev); 365 radeon_fence_driver_fini(rdev); 366 radeon_bo_fini(rdev); 367 if (rdev->is_atom_bios) { 368 radeon_atombios_fini(rdev); 369 } else { 370 radeon_combios_fini(rdev); 371 } 372 kfree(rdev->bios); 373 rdev->bios = NULL; 374 } 375 376 int r420_init(struct radeon_device *rdev) 377 { 378 int r; 379 380 /* Initialize scratch registers */ 381 radeon_scratch_init(rdev); 382 /* Initialize surface registers */ 383 radeon_surface_init(rdev); 384 /* TODO: disable VGA need to use VGA request */ 385 /* restore some register to sane defaults */ 386 r100_restore_sanity(rdev); 387 /* BIOS*/ 388 if (!radeon_get_bios(rdev)) { 389 if (ASIC_IS_AVIVO(rdev)) 390 return -EINVAL; 391 } 392 if (rdev->is_atom_bios) { 393 r = radeon_atombios_init(rdev); 394 if (r) { 395 return r; 396 } 397 } else { 398 r = radeon_combios_init(rdev); 399 if (r) { 400 return r; 401 } 402 } 403 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 404 if (radeon_asic_reset(rdev)) { 405 dev_warn(rdev->dev, 406 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 407 RREG32(R_000E40_RBBM_STATUS), 408 RREG32(R_0007C0_CP_STAT)); 409 } 410 /* check if cards are posted or not */ 411 if (radeon_boot_test_post_card(rdev) == false) 412 return -EINVAL; 413 414 /* Initialize clocks */ 415 radeon_get_clock_info(rdev->ddev); 416 /* initialize AGP */ 417 if (rdev->flags & RADEON_IS_AGP) { 418 r = radeon_agp_init(rdev); 419 if (r) { 420 radeon_agp_disable(rdev); 421 } 422 } 423 /* initialize memory controller */ 424 r300_mc_init(rdev); 425 r420_debugfs(rdev); 426 /* Fence driver */ 427 r = radeon_fence_driver_init(rdev); 428 if (r) { 429 return r; 430 } 431 /* Memory manager */ 432 r = radeon_bo_init(rdev); 433 if (r) { 434 return r; 435 } 436 if (rdev->family == CHIP_R420) 437 r100_enable_bm(rdev); 438 439 if (rdev->flags & RADEON_IS_PCIE) { 440 r = rv370_pcie_gart_init(rdev); 441 if (r) 442 return r; 443 } 444 if (rdev->flags & RADEON_IS_PCI) { 445 r = r100_pci_gart_init(rdev); 446 if (r) 447 return r; 448 } 449 r420_set_reg_safe(rdev); 450 451 /* Initialize power management */ 452 radeon_pm_init(rdev); 453 454 rdev->accel_working = true; 455 r = r420_startup(rdev); 456 if (r) { 457 /* Somethings want wront with the accel init stop accel */ 458 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 459 r100_cp_fini(rdev); 460 radeon_wb_fini(rdev); 461 radeon_ib_pool_fini(rdev); 462 radeon_irq_kms_fini(rdev); 463 if (rdev->flags & RADEON_IS_PCIE) 464 rv370_pcie_gart_fini(rdev); 465 if (rdev->flags & RADEON_IS_PCI) 466 r100_pci_gart_fini(rdev); 467 radeon_agp_fini(rdev); 468 rdev->accel_working = false; 469 } 470 return 0; 471 } 472 473 /* 474 * Debugfs info 475 */ 476 #if defined(CONFIG_DEBUG_FS) 477 static int r420_debugfs_pipes_info(struct seq_file *m, void *data) 478 { 479 struct drm_info_node *node = (struct drm_info_node *) m->private; 480 struct drm_device *dev = node->minor->dev; 481 struct radeon_device *rdev = dev->dev_private; 482 uint32_t tmp; 483 484 tmp = RREG32(R400_GB_PIPE_SELECT); 485 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 486 tmp = RREG32(R300_GB_TILE_CONFIG); 487 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 488 tmp = RREG32(R300_DST_PIPE_CONFIG); 489 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 490 return 0; 491 } 492 493 static struct drm_info_list r420_pipes_info_list[] = { 494 {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL}, 495 }; 496 #endif 497 498 int r420_debugfs_pipes_info_init(struct radeon_device *rdev) 499 { 500 #if defined(CONFIG_DEBUG_FS) 501 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); 502 #else 503 return 0; 504 #endif 505 } 506