1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include <linux/slab.h> 30 #include <drm/drmP.h> 31 #include <drm/drm.h> 32 #include <drm/drm_crtc_helper.h> 33 #include "radeon_reg.h" 34 #include "radeon.h" 35 #include "radeon_asic.h" 36 #include "radeon_drm.h" 37 #include "r100_track.h" 38 #include "r300d.h" 39 #include "rv350d.h" 40 #include "r300_reg_safe.h" 41 42 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 43 * 44 * GPU Errata: 45 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL 46 * using MMIO to flush host path read cache, this lead to HARDLOCKUP. 47 * However, scheduling such write to the ring seems harmless, i suspect 48 * the CP read collide with the flush somehow, or maybe the MC, hard to 49 * tell. (Jerome Glisse) 50 */ 51 52 /* 53 * rv370,rv380 PCIE GART 54 */ 55 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 56 57 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) 58 { 59 uint32_t tmp; 60 int i; 61 62 /* Workaround HW bug do flush 2 times */ 63 for (i = 0; i < 2; i++) { 64 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 65 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); 66 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 67 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 68 } 69 mb(); 70 } 71 72 #define R300_PTE_WRITEABLE (1 << 2) 73 #define R300_PTE_READABLE (1 << 3) 74 75 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 76 { 77 void __iomem *ptr = rdev->gart.ptr; 78 79 if (i < 0 || i > rdev->gart.num_gpu_pages) { 80 return -EINVAL; 81 } 82 addr = (lower_32_bits(addr) >> 8) | 83 ((upper_32_bits(addr) & 0xff) << 24) | 84 R300_PTE_WRITEABLE | R300_PTE_READABLE; 85 /* on x86 we want this to be CPU endian, on powerpc 86 * on powerpc without HW swappers, it'll get swapped on way 87 * into VRAM - so no need for cpu_to_le32 on VRAM tables */ 88 writel(addr, ((void __iomem *)ptr) + (i * 4)); 89 return 0; 90 } 91 92 int rv370_pcie_gart_init(struct radeon_device *rdev) 93 { 94 int r; 95 96 if (rdev->gart.robj) { 97 WARN(1, "RV370 PCIE GART already initialized\n"); 98 return 0; 99 } 100 /* Initialize common gart structure */ 101 r = radeon_gart_init(rdev); 102 if (r) 103 return r; 104 r = rv370_debugfs_pcie_gart_info_init(rdev); 105 if (r) 106 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); 107 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 108 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 109 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 110 return radeon_gart_table_vram_alloc(rdev); 111 } 112 113 int rv370_pcie_gart_enable(struct radeon_device *rdev) 114 { 115 uint32_t table_addr; 116 uint32_t tmp; 117 int r; 118 119 if (rdev->gart.robj == NULL) { 120 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 121 return -EINVAL; 122 } 123 r = radeon_gart_table_vram_pin(rdev); 124 if (r) 125 return r; 126 radeon_gart_restore(rdev); 127 /* discard memory request outside of configured range */ 128 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 129 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 130 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); 131 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK; 132 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); 133 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 134 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 135 table_addr = rdev->gart.table_addr; 136 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); 137 /* FIXME: setup default page */ 138 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); 139 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); 140 /* Clear error */ 141 WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); 142 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 143 tmp |= RADEON_PCIE_TX_GART_EN; 144 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 145 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 146 rv370_pcie_gart_tlb_flush(rdev); 147 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 148 (unsigned)(rdev->mc.gtt_size >> 20), 149 (unsigned long long)table_addr); 150 rdev->gart.ready = true; 151 return 0; 152 } 153 154 void rv370_pcie_gart_disable(struct radeon_device *rdev) 155 { 156 u32 tmp; 157 158 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0); 159 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0); 160 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 161 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 162 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 163 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 164 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); 165 radeon_gart_table_vram_unpin(rdev); 166 } 167 168 void rv370_pcie_gart_fini(struct radeon_device *rdev) 169 { 170 radeon_gart_fini(rdev); 171 rv370_pcie_gart_disable(rdev); 172 radeon_gart_table_vram_free(rdev); 173 } 174 175 void r300_fence_ring_emit(struct radeon_device *rdev, 176 struct radeon_fence *fence) 177 { 178 struct radeon_ring *ring = &rdev->ring[fence->ring]; 179 180 /* Who ever call radeon_fence_emit should call ring_lock and ask 181 * for enough space (today caller are ib schedule and buffer move) */ 182 /* Write SC register so SC & US assert idle */ 183 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0)); 184 radeon_ring_write(ring, 0); 185 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0)); 186 radeon_ring_write(ring, 0); 187 /* Flush 3D cache */ 188 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 189 radeon_ring_write(ring, R300_RB3D_DC_FLUSH); 190 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 191 radeon_ring_write(ring, R300_ZC_FLUSH); 192 /* Wait until IDLE & CLEAN */ 193 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 194 radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN | 195 RADEON_WAIT_2D_IDLECLEAN | 196 RADEON_WAIT_DMA_GUI_IDLE)); 197 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 198 radeon_ring_write(ring, rdev->config.r300.hdp_cntl | 199 RADEON_HDP_READ_BUFFER_INVALIDATE); 200 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 201 radeon_ring_write(ring, rdev->config.r300.hdp_cntl); 202 /* Emit fence sequence & fire IRQ */ 203 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); 204 radeon_ring_write(ring, fence->seq); 205 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); 206 radeon_ring_write(ring, RADEON_SW_INT_FIRE); 207 } 208 209 void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 210 { 211 unsigned gb_tile_config; 212 int r; 213 214 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 215 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 216 switch(rdev->num_gb_pipes) { 217 case 2: 218 gb_tile_config |= R300_PIPE_COUNT_R300; 219 break; 220 case 3: 221 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 222 break; 223 case 4: 224 gb_tile_config |= R300_PIPE_COUNT_R420; 225 break; 226 case 1: 227 default: 228 gb_tile_config |= R300_PIPE_COUNT_RV350; 229 break; 230 } 231 232 r = radeon_ring_lock(rdev, ring, 64); 233 if (r) { 234 return; 235 } 236 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); 237 radeon_ring_write(ring, 238 RADEON_ISYNC_ANY2D_IDLE3D | 239 RADEON_ISYNC_ANY3D_IDLE2D | 240 RADEON_ISYNC_WAIT_IDLEGUI | 241 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 242 radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0)); 243 radeon_ring_write(ring, gb_tile_config); 244 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 245 radeon_ring_write(ring, 246 RADEON_WAIT_2D_IDLECLEAN | 247 RADEON_WAIT_3D_IDLECLEAN); 248 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); 249 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); 250 radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0)); 251 radeon_ring_write(ring, 0); 252 radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0)); 253 radeon_ring_write(ring, 0); 254 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 255 radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 256 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 257 radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); 258 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 259 radeon_ring_write(ring, 260 RADEON_WAIT_2D_IDLECLEAN | 261 RADEON_WAIT_3D_IDLECLEAN); 262 radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0)); 263 radeon_ring_write(ring, 0); 264 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 265 radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 266 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 267 radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); 268 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0)); 269 radeon_ring_write(ring, 270 ((6 << R300_MS_X0_SHIFT) | 271 (6 << R300_MS_Y0_SHIFT) | 272 (6 << R300_MS_X1_SHIFT) | 273 (6 << R300_MS_Y1_SHIFT) | 274 (6 << R300_MS_X2_SHIFT) | 275 (6 << R300_MS_Y2_SHIFT) | 276 (6 << R300_MSBD0_Y_SHIFT) | 277 (6 << R300_MSBD0_X_SHIFT))); 278 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0)); 279 radeon_ring_write(ring, 280 ((6 << R300_MS_X3_SHIFT) | 281 (6 << R300_MS_Y3_SHIFT) | 282 (6 << R300_MS_X4_SHIFT) | 283 (6 << R300_MS_Y4_SHIFT) | 284 (6 << R300_MS_X5_SHIFT) | 285 (6 << R300_MS_Y5_SHIFT) | 286 (6 << R300_MSBD1_SHIFT))); 287 radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0)); 288 radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); 289 radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0)); 290 radeon_ring_write(ring, 291 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); 292 radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0)); 293 radeon_ring_write(ring, 294 R300_GEOMETRY_ROUND_NEAREST | 295 R300_COLOR_ROUND_NEAREST); 296 radeon_ring_unlock_commit(rdev, ring); 297 } 298 299 void r300_errata(struct radeon_device *rdev) 300 { 301 rdev->pll_errata = 0; 302 303 if (rdev->family == CHIP_R300 && 304 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { 305 rdev->pll_errata |= CHIP_ERRATA_R300_CG; 306 } 307 } 308 309 int r300_mc_wait_for_idle(struct radeon_device *rdev) 310 { 311 unsigned i; 312 uint32_t tmp; 313 314 for (i = 0; i < rdev->usec_timeout; i++) { 315 /* read MC_STATUS */ 316 tmp = RREG32(RADEON_MC_STATUS); 317 if (tmp & R300_MC_IDLE) { 318 return 0; 319 } 320 DRM_UDELAY(1); 321 } 322 return -1; 323 } 324 325 void r300_gpu_init(struct radeon_device *rdev) 326 { 327 uint32_t gb_tile_config, tmp; 328 329 if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) || 330 (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) { 331 /* r300,r350 */ 332 rdev->num_gb_pipes = 2; 333 } else { 334 /* rv350,rv370,rv380,r300 AD, r350 AH */ 335 rdev->num_gb_pipes = 1; 336 } 337 rdev->num_z_pipes = 1; 338 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 339 switch (rdev->num_gb_pipes) { 340 case 2: 341 gb_tile_config |= R300_PIPE_COUNT_R300; 342 break; 343 case 3: 344 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 345 break; 346 case 4: 347 gb_tile_config |= R300_PIPE_COUNT_R420; 348 break; 349 default: 350 case 1: 351 gb_tile_config |= R300_PIPE_COUNT_RV350; 352 break; 353 } 354 WREG32(R300_GB_TILE_CONFIG, gb_tile_config); 355 356 if (r100_gui_wait_for_idle(rdev)) { 357 printk(KERN_WARNING "Failed to wait GUI idle while " 358 "programming pipes. Bad things might happen.\n"); 359 } 360 361 tmp = RREG32(R300_DST_PIPE_CONFIG); 362 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); 363 364 WREG32(R300_RB2D_DSTCACHE_MODE, 365 R300_DC_AUTOFLUSH_ENABLE | 366 R300_DC_DC_DISABLE_IGNORE_PE); 367 368 if (r100_gui_wait_for_idle(rdev)) { 369 printk(KERN_WARNING "Failed to wait GUI idle while " 370 "programming pipes. Bad things might happen.\n"); 371 } 372 if (r300_mc_wait_for_idle(rdev)) { 373 printk(KERN_WARNING "Failed to wait MC idle while " 374 "programming pipes. Bad things might happen.\n"); 375 } 376 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n", 377 rdev->num_gb_pipes, rdev->num_z_pipes); 378 } 379 380 bool r300_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 381 { 382 u32 rbbm_status; 383 int r; 384 385 rbbm_status = RREG32(R_000E40_RBBM_STATUS); 386 if (!G_000E40_GUI_ACTIVE(rbbm_status)) { 387 r100_gpu_lockup_update(&rdev->config.r300.lockup, ring); 388 return false; 389 } 390 /* force CP activities */ 391 r = radeon_ring_lock(rdev, ring, 2); 392 if (!r) { 393 /* PACKET2 NOP */ 394 radeon_ring_write(ring, 0x80000000); 395 radeon_ring_write(ring, 0x80000000); 396 radeon_ring_unlock_commit(rdev, ring); 397 } 398 ring->rptr = RREG32(RADEON_CP_RB_RPTR); 399 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, ring); 400 } 401 402 int r300_asic_reset(struct radeon_device *rdev) 403 { 404 struct r100_mc_save save; 405 u32 status, tmp; 406 int ret = 0; 407 408 status = RREG32(R_000E40_RBBM_STATUS); 409 if (!G_000E40_GUI_ACTIVE(status)) { 410 return 0; 411 } 412 r100_mc_stop(rdev, &save); 413 status = RREG32(R_000E40_RBBM_STATUS); 414 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 415 /* stop CP */ 416 WREG32(RADEON_CP_CSQ_CNTL, 0); 417 tmp = RREG32(RADEON_CP_RB_CNTL); 418 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 419 WREG32(RADEON_CP_RB_RPTR_WR, 0); 420 WREG32(RADEON_CP_RB_WPTR, 0); 421 WREG32(RADEON_CP_RB_CNTL, tmp); 422 /* save PCI state */ 423 pci_save_state(rdev->pdev); 424 /* disable bus mastering */ 425 r100_bm_disable(rdev); 426 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | 427 S_0000F0_SOFT_RESET_GA(1)); 428 RREG32(R_0000F0_RBBM_SOFT_RESET); 429 mdelay(500); 430 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 431 mdelay(1); 432 status = RREG32(R_000E40_RBBM_STATUS); 433 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 434 /* resetting the CP seems to be problematic sometimes it end up 435 * hard locking the computer, but it's necessary for successful 436 * reset more test & playing is needed on R3XX/R4XX to find a 437 * reliable (if any solution) 438 */ 439 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 440 RREG32(R_0000F0_RBBM_SOFT_RESET); 441 mdelay(500); 442 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 443 mdelay(1); 444 status = RREG32(R_000E40_RBBM_STATUS); 445 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 446 /* restore PCI & busmastering */ 447 pci_restore_state(rdev->pdev); 448 r100_enable_bm(rdev); 449 /* Check if GPU is idle */ 450 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { 451 dev_err(rdev->dev, "failed to reset GPU\n"); 452 rdev->gpu_lockup = true; 453 ret = -1; 454 } else 455 dev_info(rdev->dev, "GPU reset succeed\n"); 456 r100_mc_resume(rdev, &save); 457 return ret; 458 } 459 460 /* 461 * r300,r350,rv350,rv380 VRAM info 462 */ 463 void r300_mc_init(struct radeon_device *rdev) 464 { 465 u64 base; 466 u32 tmp; 467 468 /* DDR for all card after R300 & IGP */ 469 rdev->mc.vram_is_ddr = true; 470 tmp = RREG32(RADEON_MEM_CNTL); 471 tmp &= R300_MEM_NUM_CHANNELS_MASK; 472 switch (tmp) { 473 case 0: rdev->mc.vram_width = 64; break; 474 case 1: rdev->mc.vram_width = 128; break; 475 case 2: rdev->mc.vram_width = 256; break; 476 default: rdev->mc.vram_width = 128; break; 477 } 478 r100_vram_init_sizes(rdev); 479 base = rdev->mc.aper_base; 480 if (rdev->flags & RADEON_IS_IGP) 481 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 482 radeon_vram_location(rdev, &rdev->mc, base); 483 rdev->mc.gtt_base_align = 0; 484 if (!(rdev->flags & RADEON_IS_AGP)) 485 radeon_gtt_location(rdev, &rdev->mc); 486 radeon_update_bandwidth_info(rdev); 487 } 488 489 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) 490 { 491 uint32_t link_width_cntl, mask; 492 493 if (rdev->flags & RADEON_IS_IGP) 494 return; 495 496 if (!(rdev->flags & RADEON_IS_PCIE)) 497 return; 498 499 /* FIXME wait for idle */ 500 501 switch (lanes) { 502 case 0: 503 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 504 break; 505 case 1: 506 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 507 break; 508 case 2: 509 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 510 break; 511 case 4: 512 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 513 break; 514 case 8: 515 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 516 break; 517 case 12: 518 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 519 break; 520 case 16: 521 default: 522 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 523 break; 524 } 525 526 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 527 528 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == 529 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) 530 return; 531 532 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | 533 RADEON_PCIE_LC_RECONFIG_NOW | 534 RADEON_PCIE_LC_RECONFIG_LATER | 535 RADEON_PCIE_LC_SHORT_RECONFIG_EN); 536 link_width_cntl |= mask; 537 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 538 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | 539 RADEON_PCIE_LC_RECONFIG_NOW)); 540 541 /* wait for lane set to complete */ 542 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 543 while (link_width_cntl == 0xffffffff) 544 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 545 546 } 547 548 int rv370_get_pcie_lanes(struct radeon_device *rdev) 549 { 550 u32 link_width_cntl; 551 552 if (rdev->flags & RADEON_IS_IGP) 553 return 0; 554 555 if (!(rdev->flags & RADEON_IS_PCIE)) 556 return 0; 557 558 /* FIXME wait for idle */ 559 560 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 561 562 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 563 case RADEON_PCIE_LC_LINK_WIDTH_X0: 564 return 0; 565 case RADEON_PCIE_LC_LINK_WIDTH_X1: 566 return 1; 567 case RADEON_PCIE_LC_LINK_WIDTH_X2: 568 return 2; 569 case RADEON_PCIE_LC_LINK_WIDTH_X4: 570 return 4; 571 case RADEON_PCIE_LC_LINK_WIDTH_X8: 572 return 8; 573 case RADEON_PCIE_LC_LINK_WIDTH_X16: 574 default: 575 return 16; 576 } 577 } 578 579 #if defined(CONFIG_DEBUG_FS) 580 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) 581 { 582 struct drm_info_node *node = (struct drm_info_node *) m->private; 583 struct drm_device *dev = node->minor->dev; 584 struct radeon_device *rdev = dev->dev_private; 585 uint32_t tmp; 586 587 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 588 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); 589 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); 590 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); 591 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); 592 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); 593 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); 594 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); 595 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); 596 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); 597 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); 598 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); 599 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); 600 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); 601 return 0; 602 } 603 604 static struct drm_info_list rv370_pcie_gart_info_list[] = { 605 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL}, 606 }; 607 #endif 608 609 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 610 { 611 #if defined(CONFIG_DEBUG_FS) 612 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); 613 #else 614 return 0; 615 #endif 616 } 617 618 static int r300_packet0_check(struct radeon_cs_parser *p, 619 struct radeon_cs_packet *pkt, 620 unsigned idx, unsigned reg) 621 { 622 struct radeon_cs_reloc *reloc; 623 struct r100_cs_track *track; 624 volatile uint32_t *ib; 625 uint32_t tmp, tile_flags = 0; 626 unsigned i; 627 int r; 628 u32 idx_value; 629 630 ib = p->ib->ptr; 631 track = (struct r100_cs_track *)p->track; 632 idx_value = radeon_get_ib_value(p, idx); 633 634 switch(reg) { 635 case AVIVO_D1MODE_VLINE_START_END: 636 case RADEON_CRTC_GUI_TRIG_VLINE: 637 r = r100_cs_packet_parse_vline(p); 638 if (r) { 639 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 640 idx, reg); 641 r100_cs_dump_packet(p, pkt); 642 return r; 643 } 644 break; 645 case RADEON_DST_PITCH_OFFSET: 646 case RADEON_SRC_PITCH_OFFSET: 647 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 648 if (r) 649 return r; 650 break; 651 case R300_RB3D_COLOROFFSET0: 652 case R300_RB3D_COLOROFFSET1: 653 case R300_RB3D_COLOROFFSET2: 654 case R300_RB3D_COLOROFFSET3: 655 i = (reg - R300_RB3D_COLOROFFSET0) >> 2; 656 r = r100_cs_packet_next_reloc(p, &reloc); 657 if (r) { 658 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 659 idx, reg); 660 r100_cs_dump_packet(p, pkt); 661 return r; 662 } 663 track->cb[i].robj = reloc->robj; 664 track->cb[i].offset = idx_value; 665 track->cb_dirty = true; 666 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 667 break; 668 case R300_ZB_DEPTHOFFSET: 669 r = r100_cs_packet_next_reloc(p, &reloc); 670 if (r) { 671 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 672 idx, reg); 673 r100_cs_dump_packet(p, pkt); 674 return r; 675 } 676 track->zb.robj = reloc->robj; 677 track->zb.offset = idx_value; 678 track->zb_dirty = true; 679 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 680 break; 681 case R300_TX_OFFSET_0: 682 case R300_TX_OFFSET_0+4: 683 case R300_TX_OFFSET_0+8: 684 case R300_TX_OFFSET_0+12: 685 case R300_TX_OFFSET_0+16: 686 case R300_TX_OFFSET_0+20: 687 case R300_TX_OFFSET_0+24: 688 case R300_TX_OFFSET_0+28: 689 case R300_TX_OFFSET_0+32: 690 case R300_TX_OFFSET_0+36: 691 case R300_TX_OFFSET_0+40: 692 case R300_TX_OFFSET_0+44: 693 case R300_TX_OFFSET_0+48: 694 case R300_TX_OFFSET_0+52: 695 case R300_TX_OFFSET_0+56: 696 case R300_TX_OFFSET_0+60: 697 i = (reg - R300_TX_OFFSET_0) >> 2; 698 r = r100_cs_packet_next_reloc(p, &reloc); 699 if (r) { 700 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 701 idx, reg); 702 r100_cs_dump_packet(p, pkt); 703 return r; 704 } 705 706 if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) { 707 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ 708 ((idx_value & ~31) + (u32)reloc->lobj.gpu_offset); 709 } else { 710 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 711 tile_flags |= R300_TXO_MACRO_TILE; 712 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 713 tile_flags |= R300_TXO_MICRO_TILE; 714 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) 715 tile_flags |= R300_TXO_MICRO_TILE_SQUARE; 716 717 tmp = idx_value + ((u32)reloc->lobj.gpu_offset); 718 tmp |= tile_flags; 719 ib[idx] = tmp; 720 } 721 track->textures[i].robj = reloc->robj; 722 track->tex_dirty = true; 723 break; 724 /* Tracked registers */ 725 case 0x2084: 726 /* VAP_VF_CNTL */ 727 track->vap_vf_cntl = idx_value; 728 break; 729 case 0x20B4: 730 /* VAP_VTX_SIZE */ 731 track->vtx_size = idx_value & 0x7F; 732 break; 733 case 0x2134: 734 /* VAP_VF_MAX_VTX_INDX */ 735 track->max_indx = idx_value & 0x00FFFFFFUL; 736 break; 737 case 0x2088: 738 /* VAP_ALT_NUM_VERTICES - only valid on r500 */ 739 if (p->rdev->family < CHIP_RV515) 740 goto fail; 741 track->vap_alt_nverts = idx_value & 0xFFFFFF; 742 break; 743 case 0x43E4: 744 /* SC_SCISSOR1 */ 745 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; 746 if (p->rdev->family < CHIP_RV515) { 747 track->maxy -= 1440; 748 } 749 track->cb_dirty = true; 750 track->zb_dirty = true; 751 break; 752 case 0x4E00: 753 /* RB3D_CCTL */ 754 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */ 755 p->rdev->cmask_filp != p->filp) { 756 DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n"); 757 return -EINVAL; 758 } 759 track->num_cb = ((idx_value >> 5) & 0x3) + 1; 760 track->cb_dirty = true; 761 break; 762 case 0x4E38: 763 case 0x4E3C: 764 case 0x4E40: 765 case 0x4E44: 766 /* RB3D_COLORPITCH0 */ 767 /* RB3D_COLORPITCH1 */ 768 /* RB3D_COLORPITCH2 */ 769 /* RB3D_COLORPITCH3 */ 770 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 771 r = r100_cs_packet_next_reloc(p, &reloc); 772 if (r) { 773 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 774 idx, reg); 775 r100_cs_dump_packet(p, pkt); 776 return r; 777 } 778 779 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 780 tile_flags |= R300_COLOR_TILE_ENABLE; 781 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 782 tile_flags |= R300_COLOR_MICROTILE_ENABLE; 783 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) 784 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; 785 786 tmp = idx_value & ~(0x7 << 16); 787 tmp |= tile_flags; 788 ib[idx] = tmp; 789 } 790 i = (reg - 0x4E38) >> 2; 791 track->cb[i].pitch = idx_value & 0x3FFE; 792 switch (((idx_value >> 21) & 0xF)) { 793 case 9: 794 case 11: 795 case 12: 796 track->cb[i].cpp = 1; 797 break; 798 case 3: 799 case 4: 800 case 13: 801 case 15: 802 track->cb[i].cpp = 2; 803 break; 804 case 5: 805 if (p->rdev->family < CHIP_RV515) { 806 DRM_ERROR("Invalid color buffer format (%d)!\n", 807 ((idx_value >> 21) & 0xF)); 808 return -EINVAL; 809 } 810 /* Pass through. */ 811 case 6: 812 track->cb[i].cpp = 4; 813 break; 814 case 10: 815 track->cb[i].cpp = 8; 816 break; 817 case 7: 818 track->cb[i].cpp = 16; 819 break; 820 default: 821 DRM_ERROR("Invalid color buffer format (%d) !\n", 822 ((idx_value >> 21) & 0xF)); 823 return -EINVAL; 824 } 825 track->cb_dirty = true; 826 break; 827 case 0x4F00: 828 /* ZB_CNTL */ 829 if (idx_value & 2) { 830 track->z_enabled = true; 831 } else { 832 track->z_enabled = false; 833 } 834 track->zb_dirty = true; 835 break; 836 case 0x4F10: 837 /* ZB_FORMAT */ 838 switch ((idx_value & 0xF)) { 839 case 0: 840 case 1: 841 track->zb.cpp = 2; 842 break; 843 case 2: 844 track->zb.cpp = 4; 845 break; 846 default: 847 DRM_ERROR("Invalid z buffer format (%d) !\n", 848 (idx_value & 0xF)); 849 return -EINVAL; 850 } 851 track->zb_dirty = true; 852 break; 853 case 0x4F24: 854 /* ZB_DEPTHPITCH */ 855 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 856 r = r100_cs_packet_next_reloc(p, &reloc); 857 if (r) { 858 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 859 idx, reg); 860 r100_cs_dump_packet(p, pkt); 861 return r; 862 } 863 864 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 865 tile_flags |= R300_DEPTHMACROTILE_ENABLE; 866 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 867 tile_flags |= R300_DEPTHMICROTILE_TILED; 868 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) 869 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE; 870 871 tmp = idx_value & ~(0x7 << 16); 872 tmp |= tile_flags; 873 ib[idx] = tmp; 874 } 875 track->zb.pitch = idx_value & 0x3FFC; 876 track->zb_dirty = true; 877 break; 878 case 0x4104: 879 /* TX_ENABLE */ 880 for (i = 0; i < 16; i++) { 881 bool enabled; 882 883 enabled = !!(idx_value & (1 << i)); 884 track->textures[i].enabled = enabled; 885 } 886 track->tex_dirty = true; 887 break; 888 case 0x44C0: 889 case 0x44C4: 890 case 0x44C8: 891 case 0x44CC: 892 case 0x44D0: 893 case 0x44D4: 894 case 0x44D8: 895 case 0x44DC: 896 case 0x44E0: 897 case 0x44E4: 898 case 0x44E8: 899 case 0x44EC: 900 case 0x44F0: 901 case 0x44F4: 902 case 0x44F8: 903 case 0x44FC: 904 /* TX_FORMAT1_[0-15] */ 905 i = (reg - 0x44C0) >> 2; 906 tmp = (idx_value >> 25) & 0x3; 907 track->textures[i].tex_coord_type = tmp; 908 switch ((idx_value & 0x1F)) { 909 case R300_TX_FORMAT_X8: 910 case R300_TX_FORMAT_Y4X4: 911 case R300_TX_FORMAT_Z3Y3X2: 912 track->textures[i].cpp = 1; 913 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 914 break; 915 case R300_TX_FORMAT_X16: 916 case R300_TX_FORMAT_FL_I16: 917 case R300_TX_FORMAT_Y8X8: 918 case R300_TX_FORMAT_Z5Y6X5: 919 case R300_TX_FORMAT_Z6Y5X5: 920 case R300_TX_FORMAT_W4Z4Y4X4: 921 case R300_TX_FORMAT_W1Z5Y5X5: 922 case R300_TX_FORMAT_D3DMFT_CxV8U8: 923 case R300_TX_FORMAT_B8G8_B8G8: 924 case R300_TX_FORMAT_G8R8_G8B8: 925 track->textures[i].cpp = 2; 926 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 927 break; 928 case R300_TX_FORMAT_Y16X16: 929 case R300_TX_FORMAT_FL_I16A16: 930 case R300_TX_FORMAT_Z11Y11X10: 931 case R300_TX_FORMAT_Z10Y11X11: 932 case R300_TX_FORMAT_W8Z8Y8X8: 933 case R300_TX_FORMAT_W2Z10Y10X10: 934 case 0x17: 935 case R300_TX_FORMAT_FL_I32: 936 case 0x1e: 937 track->textures[i].cpp = 4; 938 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 939 break; 940 case R300_TX_FORMAT_W16Z16Y16X16: 941 case R300_TX_FORMAT_FL_R16G16B16A16: 942 case R300_TX_FORMAT_FL_I32A32: 943 track->textures[i].cpp = 8; 944 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 945 break; 946 case R300_TX_FORMAT_FL_R32G32B32A32: 947 track->textures[i].cpp = 16; 948 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 949 break; 950 case R300_TX_FORMAT_DXT1: 951 track->textures[i].cpp = 1; 952 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 953 break; 954 case R300_TX_FORMAT_ATI2N: 955 if (p->rdev->family < CHIP_R420) { 956 DRM_ERROR("Invalid texture format %u\n", 957 (idx_value & 0x1F)); 958 return -EINVAL; 959 } 960 /* The same rules apply as for DXT3/5. */ 961 /* Pass through. */ 962 case R300_TX_FORMAT_DXT3: 963 case R300_TX_FORMAT_DXT5: 964 track->textures[i].cpp = 1; 965 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 966 break; 967 default: 968 DRM_ERROR("Invalid texture format %u\n", 969 (idx_value & 0x1F)); 970 return -EINVAL; 971 } 972 track->tex_dirty = true; 973 break; 974 case 0x4400: 975 case 0x4404: 976 case 0x4408: 977 case 0x440C: 978 case 0x4410: 979 case 0x4414: 980 case 0x4418: 981 case 0x441C: 982 case 0x4420: 983 case 0x4424: 984 case 0x4428: 985 case 0x442C: 986 case 0x4430: 987 case 0x4434: 988 case 0x4438: 989 case 0x443C: 990 /* TX_FILTER0_[0-15] */ 991 i = (reg - 0x4400) >> 2; 992 tmp = idx_value & 0x7; 993 if (tmp == 2 || tmp == 4 || tmp == 6) { 994 track->textures[i].roundup_w = false; 995 } 996 tmp = (idx_value >> 3) & 0x7; 997 if (tmp == 2 || tmp == 4 || tmp == 6) { 998 track->textures[i].roundup_h = false; 999 } 1000 track->tex_dirty = true; 1001 break; 1002 case 0x4500: 1003 case 0x4504: 1004 case 0x4508: 1005 case 0x450C: 1006 case 0x4510: 1007 case 0x4514: 1008 case 0x4518: 1009 case 0x451C: 1010 case 0x4520: 1011 case 0x4524: 1012 case 0x4528: 1013 case 0x452C: 1014 case 0x4530: 1015 case 0x4534: 1016 case 0x4538: 1017 case 0x453C: 1018 /* TX_FORMAT2_[0-15] */ 1019 i = (reg - 0x4500) >> 2; 1020 tmp = idx_value & 0x3FFF; 1021 track->textures[i].pitch = tmp + 1; 1022 if (p->rdev->family >= CHIP_RV515) { 1023 tmp = ((idx_value >> 15) & 1) << 11; 1024 track->textures[i].width_11 = tmp; 1025 tmp = ((idx_value >> 16) & 1) << 11; 1026 track->textures[i].height_11 = tmp; 1027 1028 /* ATI1N */ 1029 if (idx_value & (1 << 14)) { 1030 /* The same rules apply as for DXT1. */ 1031 track->textures[i].compress_format = 1032 R100_TRACK_COMP_DXT1; 1033 } 1034 } else if (idx_value & (1 << 14)) { 1035 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); 1036 return -EINVAL; 1037 } 1038 track->tex_dirty = true; 1039 break; 1040 case 0x4480: 1041 case 0x4484: 1042 case 0x4488: 1043 case 0x448C: 1044 case 0x4490: 1045 case 0x4494: 1046 case 0x4498: 1047 case 0x449C: 1048 case 0x44A0: 1049 case 0x44A4: 1050 case 0x44A8: 1051 case 0x44AC: 1052 case 0x44B0: 1053 case 0x44B4: 1054 case 0x44B8: 1055 case 0x44BC: 1056 /* TX_FORMAT0_[0-15] */ 1057 i = (reg - 0x4480) >> 2; 1058 tmp = idx_value & 0x7FF; 1059 track->textures[i].width = tmp + 1; 1060 tmp = (idx_value >> 11) & 0x7FF; 1061 track->textures[i].height = tmp + 1; 1062 tmp = (idx_value >> 26) & 0xF; 1063 track->textures[i].num_levels = tmp; 1064 tmp = idx_value & (1 << 31); 1065 track->textures[i].use_pitch = !!tmp; 1066 tmp = (idx_value >> 22) & 0xF; 1067 track->textures[i].txdepth = tmp; 1068 track->tex_dirty = true; 1069 break; 1070 case R300_ZB_ZPASS_ADDR: 1071 r = r100_cs_packet_next_reloc(p, &reloc); 1072 if (r) { 1073 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1074 idx, reg); 1075 r100_cs_dump_packet(p, pkt); 1076 return r; 1077 } 1078 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1079 break; 1080 case 0x4e0c: 1081 /* RB3D_COLOR_CHANNEL_MASK */ 1082 track->color_channel_mask = idx_value; 1083 track->cb_dirty = true; 1084 break; 1085 case 0x43a4: 1086 /* SC_HYPERZ_EN */ 1087 /* r300c emits this register - we need to disable hyperz for it 1088 * without complaining */ 1089 if (p->rdev->hyperz_filp != p->filp) { 1090 if (idx_value & 0x1) 1091 ib[idx] = idx_value & ~1; 1092 } 1093 break; 1094 case 0x4f1c: 1095 /* ZB_BW_CNTL */ 1096 track->zb_cb_clear = !!(idx_value & (1 << 5)); 1097 track->cb_dirty = true; 1098 track->zb_dirty = true; 1099 if (p->rdev->hyperz_filp != p->filp) { 1100 if (idx_value & (R300_HIZ_ENABLE | 1101 R300_RD_COMP_ENABLE | 1102 R300_WR_COMP_ENABLE | 1103 R300_FAST_FILL_ENABLE)) 1104 goto fail; 1105 } 1106 break; 1107 case 0x4e04: 1108 /* RB3D_BLENDCNTL */ 1109 track->blend_read_enable = !!(idx_value & (1 << 2)); 1110 track->cb_dirty = true; 1111 break; 1112 case R300_RB3D_AARESOLVE_OFFSET: 1113 r = r100_cs_packet_next_reloc(p, &reloc); 1114 if (r) { 1115 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1116 idx, reg); 1117 r100_cs_dump_packet(p, pkt); 1118 return r; 1119 } 1120 track->aa.robj = reloc->robj; 1121 track->aa.offset = idx_value; 1122 track->aa_dirty = true; 1123 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1124 break; 1125 case R300_RB3D_AARESOLVE_PITCH: 1126 track->aa.pitch = idx_value & 0x3FFE; 1127 track->aa_dirty = true; 1128 break; 1129 case R300_RB3D_AARESOLVE_CTL: 1130 track->aaresolve = idx_value & 0x1; 1131 track->aa_dirty = true; 1132 break; 1133 case 0x4f30: /* ZB_MASK_OFFSET */ 1134 case 0x4f34: /* ZB_ZMASK_PITCH */ 1135 case 0x4f44: /* ZB_HIZ_OFFSET */ 1136 case 0x4f54: /* ZB_HIZ_PITCH */ 1137 if (idx_value && (p->rdev->hyperz_filp != p->filp)) 1138 goto fail; 1139 break; 1140 case 0x4028: 1141 if (idx_value && (p->rdev->hyperz_filp != p->filp)) 1142 goto fail; 1143 /* GB_Z_PEQ_CONFIG */ 1144 if (p->rdev->family >= CHIP_RV350) 1145 break; 1146 goto fail; 1147 break; 1148 case 0x4be8: 1149 /* valid register only on RV530 */ 1150 if (p->rdev->family == CHIP_RV530) 1151 break; 1152 /* fallthrough do not move */ 1153 default: 1154 goto fail; 1155 } 1156 return 0; 1157 fail: 1158 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n", 1159 reg, idx, idx_value); 1160 return -EINVAL; 1161 } 1162 1163 static int r300_packet3_check(struct radeon_cs_parser *p, 1164 struct radeon_cs_packet *pkt) 1165 { 1166 struct radeon_cs_reloc *reloc; 1167 struct r100_cs_track *track; 1168 volatile uint32_t *ib; 1169 unsigned idx; 1170 int r; 1171 1172 ib = p->ib->ptr; 1173 idx = pkt->idx + 1; 1174 track = (struct r100_cs_track *)p->track; 1175 switch(pkt->opcode) { 1176 case PACKET3_3D_LOAD_VBPNTR: 1177 r = r100_packet3_load_vbpntr(p, pkt, idx); 1178 if (r) 1179 return r; 1180 break; 1181 case PACKET3_INDX_BUFFER: 1182 r = r100_cs_packet_next_reloc(p, &reloc); 1183 if (r) { 1184 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1185 r100_cs_dump_packet(p, pkt); 1186 return r; 1187 } 1188 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 1189 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1190 if (r) { 1191 return r; 1192 } 1193 break; 1194 /* Draw packet */ 1195 case PACKET3_3D_DRAW_IMMD: 1196 /* Number of dwords is vtx_size * (num_vertices - 1) 1197 * PRIM_WALK must be equal to 3 vertex data in embedded 1198 * in cmd stream */ 1199 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1200 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1201 return -EINVAL; 1202 } 1203 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1204 track->immd_dwords = pkt->count - 1; 1205 r = r100_cs_track_check(p->rdev, track); 1206 if (r) { 1207 return r; 1208 } 1209 break; 1210 case PACKET3_3D_DRAW_IMMD_2: 1211 /* Number of dwords is vtx_size * (num_vertices - 1) 1212 * PRIM_WALK must be equal to 3 vertex data in embedded 1213 * in cmd stream */ 1214 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1215 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1216 return -EINVAL; 1217 } 1218 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1219 track->immd_dwords = pkt->count; 1220 r = r100_cs_track_check(p->rdev, track); 1221 if (r) { 1222 return r; 1223 } 1224 break; 1225 case PACKET3_3D_DRAW_VBUF: 1226 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1227 r = r100_cs_track_check(p->rdev, track); 1228 if (r) { 1229 return r; 1230 } 1231 break; 1232 case PACKET3_3D_DRAW_VBUF_2: 1233 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1234 r = r100_cs_track_check(p->rdev, track); 1235 if (r) { 1236 return r; 1237 } 1238 break; 1239 case PACKET3_3D_DRAW_INDX: 1240 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1241 r = r100_cs_track_check(p->rdev, track); 1242 if (r) { 1243 return r; 1244 } 1245 break; 1246 case PACKET3_3D_DRAW_INDX_2: 1247 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1248 r = r100_cs_track_check(p->rdev, track); 1249 if (r) { 1250 return r; 1251 } 1252 break; 1253 case PACKET3_3D_CLEAR_HIZ: 1254 case PACKET3_3D_CLEAR_ZMASK: 1255 if (p->rdev->hyperz_filp != p->filp) 1256 return -EINVAL; 1257 break; 1258 case PACKET3_3D_CLEAR_CMASK: 1259 if (p->rdev->cmask_filp != p->filp) 1260 return -EINVAL; 1261 break; 1262 case PACKET3_NOP: 1263 break; 1264 default: 1265 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 1266 return -EINVAL; 1267 } 1268 return 0; 1269 } 1270 1271 int r300_cs_parse(struct radeon_cs_parser *p) 1272 { 1273 struct radeon_cs_packet pkt; 1274 struct r100_cs_track *track; 1275 int r; 1276 1277 track = kzalloc(sizeof(*track), GFP_KERNEL); 1278 if (track == NULL) 1279 return -ENOMEM; 1280 r100_cs_track_clear(p->rdev, track); 1281 p->track = track; 1282 do { 1283 r = r100_cs_packet_parse(p, &pkt, p->idx); 1284 if (r) { 1285 return r; 1286 } 1287 p->idx += pkt.count + 2; 1288 switch (pkt.type) { 1289 case PACKET_TYPE0: 1290 r = r100_cs_parse_packet0(p, &pkt, 1291 p->rdev->config.r300.reg_safe_bm, 1292 p->rdev->config.r300.reg_safe_bm_size, 1293 &r300_packet0_check); 1294 break; 1295 case PACKET_TYPE2: 1296 break; 1297 case PACKET_TYPE3: 1298 r = r300_packet3_check(p, &pkt); 1299 break; 1300 default: 1301 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 1302 return -EINVAL; 1303 } 1304 if (r) { 1305 return r; 1306 } 1307 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 1308 return 0; 1309 } 1310 1311 void r300_set_reg_safe(struct radeon_device *rdev) 1312 { 1313 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; 1314 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); 1315 } 1316 1317 void r300_mc_program(struct radeon_device *rdev) 1318 { 1319 struct r100_mc_save save; 1320 int r; 1321 1322 r = r100_debugfs_mc_info_init(rdev); 1323 if (r) { 1324 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 1325 } 1326 1327 /* Stops all mc clients */ 1328 r100_mc_stop(rdev, &save); 1329 if (rdev->flags & RADEON_IS_AGP) { 1330 WREG32(R_00014C_MC_AGP_LOCATION, 1331 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 1332 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 1333 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 1334 WREG32(R_00015C_AGP_BASE_2, 1335 upper_32_bits(rdev->mc.agp_base) & 0xff); 1336 } else { 1337 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 1338 WREG32(R_000170_AGP_BASE, 0); 1339 WREG32(R_00015C_AGP_BASE_2, 0); 1340 } 1341 /* Wait for mc idle */ 1342 if (r300_mc_wait_for_idle(rdev)) 1343 DRM_INFO("Failed to wait MC idle before programming MC.\n"); 1344 /* Program MC, should be a 32bits limited address space */ 1345 WREG32(R_000148_MC_FB_LOCATION, 1346 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 1347 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 1348 r100_mc_resume(rdev, &save); 1349 } 1350 1351 void r300_clock_startup(struct radeon_device *rdev) 1352 { 1353 u32 tmp; 1354 1355 if (radeon_dynclks != -1 && radeon_dynclks) 1356 radeon_legacy_set_clock_gating(rdev, 1); 1357 /* We need to force on some of the block */ 1358 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 1359 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 1360 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380)) 1361 tmp |= S_00000D_FORCE_VAP(1); 1362 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 1363 } 1364 1365 static int r300_startup(struct radeon_device *rdev) 1366 { 1367 int r; 1368 1369 /* set common regs */ 1370 r100_set_common_regs(rdev); 1371 /* program mc */ 1372 r300_mc_program(rdev); 1373 /* Resume clock */ 1374 r300_clock_startup(rdev); 1375 /* Initialize GPU configuration (# pipes, ...) */ 1376 r300_gpu_init(rdev); 1377 /* Initialize GART (initialize after TTM so we can allocate 1378 * memory through TTM but finalize after TTM) */ 1379 if (rdev->flags & RADEON_IS_PCIE) { 1380 r = rv370_pcie_gart_enable(rdev); 1381 if (r) 1382 return r; 1383 } 1384 1385 if (rdev->family == CHIP_R300 || 1386 rdev->family == CHIP_R350 || 1387 rdev->family == CHIP_RV350) 1388 r100_enable_bm(rdev); 1389 1390 if (rdev->flags & RADEON_IS_PCI) { 1391 r = r100_pci_gart_enable(rdev); 1392 if (r) 1393 return r; 1394 } 1395 1396 /* allocate wb buffer */ 1397 r = radeon_wb_init(rdev); 1398 if (r) 1399 return r; 1400 1401 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 1402 if (r) { 1403 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 1404 return r; 1405 } 1406 1407 /* Enable IRQ */ 1408 r100_irq_set(rdev); 1409 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 1410 /* 1M ring buffer */ 1411 r = r100_cp_init(rdev, 1024 * 1024); 1412 if (r) { 1413 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 1414 return r; 1415 } 1416 1417 r = radeon_ib_pool_start(rdev); 1418 if (r) 1419 return r; 1420 1421 r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1422 if (r) { 1423 dev_err(rdev->dev, "failed testing IB (%d).\n", r); 1424 rdev->accel_working = false; 1425 return r; 1426 } 1427 1428 return 0; 1429 } 1430 1431 int r300_resume(struct radeon_device *rdev) 1432 { 1433 int r; 1434 1435 /* Make sur GART are not working */ 1436 if (rdev->flags & RADEON_IS_PCIE) 1437 rv370_pcie_gart_disable(rdev); 1438 if (rdev->flags & RADEON_IS_PCI) 1439 r100_pci_gart_disable(rdev); 1440 /* Resume clock before doing reset */ 1441 r300_clock_startup(rdev); 1442 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1443 if (radeon_asic_reset(rdev)) { 1444 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1445 RREG32(R_000E40_RBBM_STATUS), 1446 RREG32(R_0007C0_CP_STAT)); 1447 } 1448 /* post */ 1449 radeon_combios_asic_init(rdev->ddev); 1450 /* Resume clock after posting */ 1451 r300_clock_startup(rdev); 1452 /* Initialize surface registers */ 1453 radeon_surface_init(rdev); 1454 1455 rdev->accel_working = true; 1456 r = r300_startup(rdev); 1457 if (r) { 1458 rdev->accel_working = false; 1459 } 1460 return r; 1461 } 1462 1463 int r300_suspend(struct radeon_device *rdev) 1464 { 1465 radeon_ib_pool_suspend(rdev); 1466 r100_cp_disable(rdev); 1467 radeon_wb_disable(rdev); 1468 r100_irq_disable(rdev); 1469 if (rdev->flags & RADEON_IS_PCIE) 1470 rv370_pcie_gart_disable(rdev); 1471 if (rdev->flags & RADEON_IS_PCI) 1472 r100_pci_gart_disable(rdev); 1473 return 0; 1474 } 1475 1476 void r300_fini(struct radeon_device *rdev) 1477 { 1478 r100_cp_fini(rdev); 1479 radeon_wb_fini(rdev); 1480 r100_ib_fini(rdev); 1481 radeon_gem_fini(rdev); 1482 if (rdev->flags & RADEON_IS_PCIE) 1483 rv370_pcie_gart_fini(rdev); 1484 if (rdev->flags & RADEON_IS_PCI) 1485 r100_pci_gart_fini(rdev); 1486 radeon_agp_fini(rdev); 1487 radeon_irq_kms_fini(rdev); 1488 radeon_fence_driver_fini(rdev); 1489 radeon_bo_fini(rdev); 1490 radeon_atombios_fini(rdev); 1491 kfree(rdev->bios); 1492 rdev->bios = NULL; 1493 } 1494 1495 int r300_init(struct radeon_device *rdev) 1496 { 1497 int r; 1498 1499 /* Disable VGA */ 1500 r100_vga_render_disable(rdev); 1501 /* Initialize scratch registers */ 1502 radeon_scratch_init(rdev); 1503 /* Initialize surface registers */ 1504 radeon_surface_init(rdev); 1505 /* TODO: disable VGA need to use VGA request */ 1506 /* restore some register to sane defaults */ 1507 r100_restore_sanity(rdev); 1508 /* BIOS*/ 1509 if (!radeon_get_bios(rdev)) { 1510 if (ASIC_IS_AVIVO(rdev)) 1511 return -EINVAL; 1512 } 1513 if (rdev->is_atom_bios) { 1514 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 1515 return -EINVAL; 1516 } else { 1517 r = radeon_combios_init(rdev); 1518 if (r) 1519 return r; 1520 } 1521 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1522 if (radeon_asic_reset(rdev)) { 1523 dev_warn(rdev->dev, 1524 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1525 RREG32(R_000E40_RBBM_STATUS), 1526 RREG32(R_0007C0_CP_STAT)); 1527 } 1528 /* check if cards are posted or not */ 1529 if (radeon_boot_test_post_card(rdev) == false) 1530 return -EINVAL; 1531 /* Set asic errata */ 1532 r300_errata(rdev); 1533 /* Initialize clocks */ 1534 radeon_get_clock_info(rdev->ddev); 1535 /* initialize AGP */ 1536 if (rdev->flags & RADEON_IS_AGP) { 1537 r = radeon_agp_init(rdev); 1538 if (r) { 1539 radeon_agp_disable(rdev); 1540 } 1541 } 1542 /* initialize memory controller */ 1543 r300_mc_init(rdev); 1544 /* Fence driver */ 1545 r = radeon_fence_driver_init(rdev); 1546 if (r) 1547 return r; 1548 r = radeon_irq_kms_init(rdev); 1549 if (r) 1550 return r; 1551 /* Memory manager */ 1552 r = radeon_bo_init(rdev); 1553 if (r) 1554 return r; 1555 if (rdev->flags & RADEON_IS_PCIE) { 1556 r = rv370_pcie_gart_init(rdev); 1557 if (r) 1558 return r; 1559 } 1560 if (rdev->flags & RADEON_IS_PCI) { 1561 r = r100_pci_gart_init(rdev); 1562 if (r) 1563 return r; 1564 } 1565 r300_set_reg_safe(rdev); 1566 1567 r = radeon_ib_pool_init(rdev); 1568 rdev->accel_working = true; 1569 if (r) { 1570 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1571 rdev->accel_working = false; 1572 } 1573 1574 r = r300_startup(rdev); 1575 if (r) { 1576 /* Somethings want wront with the accel init stop accel */ 1577 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 1578 r100_cp_fini(rdev); 1579 radeon_wb_fini(rdev); 1580 r100_ib_fini(rdev); 1581 radeon_irq_kms_fini(rdev); 1582 if (rdev->flags & RADEON_IS_PCIE) 1583 rv370_pcie_gart_fini(rdev); 1584 if (rdev->flags & RADEON_IS_PCI) 1585 r100_pci_gart_fini(rdev); 1586 radeon_agp_fini(rdev); 1587 rdev->accel_working = false; 1588 } 1589 return 0; 1590 } 1591