xref: /openbmc/linux/drivers/gpu/drm/radeon/r300.c (revision b6dcefde)
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/seq_file.h>
29 #include "drmP.h"
30 #include "drm.h"
31 #include "radeon_reg.h"
32 #include "radeon.h"
33 #include "radeon_drm.h"
34 #include "r100_track.h"
35 #include "r300d.h"
36 #include "rv350d.h"
37 #include "r300_reg_safe.h"
38 
39 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
40  *
41  * GPU Errata:
42  * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
43  *   using MMIO to flush host path read cache, this lead to HARDLOCKUP.
44  *   However, scheduling such write to the ring seems harmless, i suspect
45  *   the CP read collide with the flush somehow, or maybe the MC, hard to
46  *   tell. (Jerome Glisse)
47  */
48 
49 /*
50  * rv370,rv380 PCIE GART
51  */
52 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
53 
54 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
55 {
56 	uint32_t tmp;
57 	int i;
58 
59 	/* Workaround HW bug do flush 2 times */
60 	for (i = 0; i < 2; i++) {
61 		tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
62 		WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
63 		(void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
64 		WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
65 	}
66 	mb();
67 }
68 
69 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
70 {
71 	void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
72 
73 	if (i < 0 || i > rdev->gart.num_gpu_pages) {
74 		return -EINVAL;
75 	}
76 	addr = (lower_32_bits(addr) >> 8) |
77 	       ((upper_32_bits(addr) & 0xff) << 24) |
78 	       0xc;
79 	/* on x86 we want this to be CPU endian, on powerpc
80 	 * on powerpc without HW swappers, it'll get swapped on way
81 	 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
82 	writel(addr, ((void __iomem *)ptr) + (i * 4));
83 	return 0;
84 }
85 
86 int rv370_pcie_gart_init(struct radeon_device *rdev)
87 {
88 	int r;
89 
90 	if (rdev->gart.table.vram.robj) {
91 		WARN(1, "RV370 PCIE GART already initialized.\n");
92 		return 0;
93 	}
94 	/* Initialize common gart structure */
95 	r = radeon_gart_init(rdev);
96 	if (r)
97 		return r;
98 	r = rv370_debugfs_pcie_gart_info_init(rdev);
99 	if (r)
100 		DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
101 	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
102 	rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
103 	rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
104 	return radeon_gart_table_vram_alloc(rdev);
105 }
106 
107 int rv370_pcie_gart_enable(struct radeon_device *rdev)
108 {
109 	uint32_t table_addr;
110 	uint32_t tmp;
111 	int r;
112 
113 	if (rdev->gart.table.vram.robj == NULL) {
114 		dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
115 		return -EINVAL;
116 	}
117 	r = radeon_gart_table_vram_pin(rdev);
118 	if (r)
119 		return r;
120 	/* discard memory request outside of configured range */
121 	tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
122 	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
123 	WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location);
124 	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - RADEON_GPU_PAGE_SIZE;
125 	WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
126 	WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
127 	WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
128 	table_addr = rdev->gart.table_addr;
129 	WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
130 	/* FIXME: setup default page */
131 	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location);
132 	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
133 	/* Clear error */
134 	WREG32_PCIE(0x18, 0);
135 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
136 	tmp |= RADEON_PCIE_TX_GART_EN;
137 	tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
138 	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
139 	rv370_pcie_gart_tlb_flush(rdev);
140 	DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
141 		 (unsigned)(rdev->mc.gtt_size >> 20), table_addr);
142 	rdev->gart.ready = true;
143 	return 0;
144 }
145 
146 void rv370_pcie_gart_disable(struct radeon_device *rdev)
147 {
148 	u32 tmp;
149 	int r;
150 
151 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
152 	tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
153 	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
154 	if (rdev->gart.table.vram.robj) {
155 		r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
156 		if (likely(r == 0)) {
157 			radeon_bo_kunmap(rdev->gart.table.vram.robj);
158 			radeon_bo_unpin(rdev->gart.table.vram.robj);
159 			radeon_bo_unreserve(rdev->gart.table.vram.robj);
160 		}
161 	}
162 }
163 
164 void rv370_pcie_gart_fini(struct radeon_device *rdev)
165 {
166 	rv370_pcie_gart_disable(rdev);
167 	radeon_gart_table_vram_free(rdev);
168 	radeon_gart_fini(rdev);
169 }
170 
171 void r300_fence_ring_emit(struct radeon_device *rdev,
172 			  struct radeon_fence *fence)
173 {
174 	/* Who ever call radeon_fence_emit should call ring_lock and ask
175 	 * for enough space (today caller are ib schedule and buffer move) */
176 	/* Write SC register so SC & US assert idle */
177 	radeon_ring_write(rdev, PACKET0(0x43E0, 0));
178 	radeon_ring_write(rdev, 0);
179 	radeon_ring_write(rdev, PACKET0(0x43E4, 0));
180 	radeon_ring_write(rdev, 0);
181 	/* Flush 3D cache */
182 	radeon_ring_write(rdev, PACKET0(0x4E4C, 0));
183 	radeon_ring_write(rdev, (2 << 0));
184 	radeon_ring_write(rdev, PACKET0(0x4F18, 0));
185 	radeon_ring_write(rdev, (1 << 0));
186 	/* Wait until IDLE & CLEAN */
187 	radeon_ring_write(rdev, PACKET0(0x1720, 0));
188 	radeon_ring_write(rdev, (1 << 17) | (1 << 16)  | (1 << 9));
189 	radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
190 	radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
191 				RADEON_HDP_READ_BUFFER_INVALIDATE);
192 	radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
193 	radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
194 	/* Emit fence sequence & fire IRQ */
195 	radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
196 	radeon_ring_write(rdev, fence->seq);
197 	radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
198 	radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
199 }
200 
201 int r300_copy_dma(struct radeon_device *rdev,
202 		  uint64_t src_offset,
203 		  uint64_t dst_offset,
204 		  unsigned num_pages,
205 		  struct radeon_fence *fence)
206 {
207 	uint32_t size;
208 	uint32_t cur_size;
209 	int i, num_loops;
210 	int r = 0;
211 
212 	/* radeon pitch is /64 */
213 	size = num_pages << PAGE_SHIFT;
214 	num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
215 	r = radeon_ring_lock(rdev, num_loops * 4 + 64);
216 	if (r) {
217 		DRM_ERROR("radeon: moving bo (%d).\n", r);
218 		return r;
219 	}
220 	/* Must wait for 2D idle & clean before DMA or hangs might happen */
221 	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0 ));
222 	radeon_ring_write(rdev, (1 << 16));
223 	for (i = 0; i < num_loops; i++) {
224 		cur_size = size;
225 		if (cur_size > 0x1FFFFF) {
226 			cur_size = 0x1FFFFF;
227 		}
228 		size -= cur_size;
229 		radeon_ring_write(rdev, PACKET0(0x720, 2));
230 		radeon_ring_write(rdev, src_offset);
231 		radeon_ring_write(rdev, dst_offset);
232 		radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30));
233 		src_offset += cur_size;
234 		dst_offset += cur_size;
235 	}
236 	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
237 	radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE);
238 	if (fence) {
239 		r = radeon_fence_emit(rdev, fence);
240 	}
241 	radeon_ring_unlock_commit(rdev);
242 	return r;
243 }
244 
245 void r300_ring_start(struct radeon_device *rdev)
246 {
247 	unsigned gb_tile_config;
248 	int r;
249 
250 	/* Sub pixel 1/12 so we can have 4K rendering according to doc */
251 	gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
252 	switch(rdev->num_gb_pipes) {
253 	case 2:
254 		gb_tile_config |= R300_PIPE_COUNT_R300;
255 		break;
256 	case 3:
257 		gb_tile_config |= R300_PIPE_COUNT_R420_3P;
258 		break;
259 	case 4:
260 		gb_tile_config |= R300_PIPE_COUNT_R420;
261 		break;
262 	case 1:
263 	default:
264 		gb_tile_config |= R300_PIPE_COUNT_RV350;
265 		break;
266 	}
267 
268 	r = radeon_ring_lock(rdev, 64);
269 	if (r) {
270 		return;
271 	}
272 	radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
273 	radeon_ring_write(rdev,
274 			  RADEON_ISYNC_ANY2D_IDLE3D |
275 			  RADEON_ISYNC_ANY3D_IDLE2D |
276 			  RADEON_ISYNC_WAIT_IDLEGUI |
277 			  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
278 	radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
279 	radeon_ring_write(rdev, gb_tile_config);
280 	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
281 	radeon_ring_write(rdev,
282 			  RADEON_WAIT_2D_IDLECLEAN |
283 			  RADEON_WAIT_3D_IDLECLEAN);
284 	radeon_ring_write(rdev, PACKET0(0x170C, 0));
285 	radeon_ring_write(rdev, 1 << 31);
286 	radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
287 	radeon_ring_write(rdev, 0);
288 	radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
289 	radeon_ring_write(rdev, 0);
290 	radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
291 	radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
292 	radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
293 	radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
294 	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
295 	radeon_ring_write(rdev,
296 			  RADEON_WAIT_2D_IDLECLEAN |
297 			  RADEON_WAIT_3D_IDLECLEAN);
298 	radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
299 	radeon_ring_write(rdev, 0);
300 	radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
301 	radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
302 	radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
303 	radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
304 	radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
305 	radeon_ring_write(rdev,
306 			  ((6 << R300_MS_X0_SHIFT) |
307 			   (6 << R300_MS_Y0_SHIFT) |
308 			   (6 << R300_MS_X1_SHIFT) |
309 			   (6 << R300_MS_Y1_SHIFT) |
310 			   (6 << R300_MS_X2_SHIFT) |
311 			   (6 << R300_MS_Y2_SHIFT) |
312 			   (6 << R300_MSBD0_Y_SHIFT) |
313 			   (6 << R300_MSBD0_X_SHIFT)));
314 	radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
315 	radeon_ring_write(rdev,
316 			  ((6 << R300_MS_X3_SHIFT) |
317 			   (6 << R300_MS_Y3_SHIFT) |
318 			   (6 << R300_MS_X4_SHIFT) |
319 			   (6 << R300_MS_Y4_SHIFT) |
320 			   (6 << R300_MS_X5_SHIFT) |
321 			   (6 << R300_MS_Y5_SHIFT) |
322 			   (6 << R300_MSBD1_SHIFT)));
323 	radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
324 	radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
325 	radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
326 	radeon_ring_write(rdev,
327 			  R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
328 	radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
329 	radeon_ring_write(rdev,
330 			  R300_GEOMETRY_ROUND_NEAREST |
331 			  R300_COLOR_ROUND_NEAREST);
332 	radeon_ring_unlock_commit(rdev);
333 }
334 
335 void r300_errata(struct radeon_device *rdev)
336 {
337 	rdev->pll_errata = 0;
338 
339 	if (rdev->family == CHIP_R300 &&
340 	    (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
341 		rdev->pll_errata |= CHIP_ERRATA_R300_CG;
342 	}
343 }
344 
345 int r300_mc_wait_for_idle(struct radeon_device *rdev)
346 {
347 	unsigned i;
348 	uint32_t tmp;
349 
350 	for (i = 0; i < rdev->usec_timeout; i++) {
351 		/* read MC_STATUS */
352 		tmp = RREG32(0x0150);
353 		if (tmp & (1 << 4)) {
354 			return 0;
355 		}
356 		DRM_UDELAY(1);
357 	}
358 	return -1;
359 }
360 
361 void r300_gpu_init(struct radeon_device *rdev)
362 {
363 	uint32_t gb_tile_config, tmp;
364 
365 	r100_hdp_reset(rdev);
366 	/* FIXME: rv380 one pipes ? */
367 	if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) {
368 		/* r300,r350 */
369 		rdev->num_gb_pipes = 2;
370 	} else {
371 		/* rv350,rv370,rv380 */
372 		rdev->num_gb_pipes = 1;
373 	}
374 	rdev->num_z_pipes = 1;
375 	gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
376 	switch (rdev->num_gb_pipes) {
377 	case 2:
378 		gb_tile_config |= R300_PIPE_COUNT_R300;
379 		break;
380 	case 3:
381 		gb_tile_config |= R300_PIPE_COUNT_R420_3P;
382 		break;
383 	case 4:
384 		gb_tile_config |= R300_PIPE_COUNT_R420;
385 		break;
386 	default:
387 	case 1:
388 		gb_tile_config |= R300_PIPE_COUNT_RV350;
389 		break;
390 	}
391 	WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
392 
393 	if (r100_gui_wait_for_idle(rdev)) {
394 		printk(KERN_WARNING "Failed to wait GUI idle while "
395 		       "programming pipes. Bad things might happen.\n");
396 	}
397 
398 	tmp = RREG32(0x170C);
399 	WREG32(0x170C, tmp | (1 << 31));
400 
401 	WREG32(R300_RB2D_DSTCACHE_MODE,
402 	       R300_DC_AUTOFLUSH_ENABLE |
403 	       R300_DC_DC_DISABLE_IGNORE_PE);
404 
405 	if (r100_gui_wait_for_idle(rdev)) {
406 		printk(KERN_WARNING "Failed to wait GUI idle while "
407 		       "programming pipes. Bad things might happen.\n");
408 	}
409 	if (r300_mc_wait_for_idle(rdev)) {
410 		printk(KERN_WARNING "Failed to wait MC idle while "
411 		       "programming pipes. Bad things might happen.\n");
412 	}
413 	DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
414 		 rdev->num_gb_pipes, rdev->num_z_pipes);
415 }
416 
417 int r300_ga_reset(struct radeon_device *rdev)
418 {
419 	uint32_t tmp;
420 	bool reinit_cp;
421 	int i;
422 
423 	reinit_cp = rdev->cp.ready;
424 	rdev->cp.ready = false;
425 	for (i = 0; i < rdev->usec_timeout; i++) {
426 		WREG32(RADEON_CP_CSQ_MODE, 0);
427 		WREG32(RADEON_CP_CSQ_CNTL, 0);
428 		WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
429 		(void)RREG32(RADEON_RBBM_SOFT_RESET);
430 		udelay(200);
431 		WREG32(RADEON_RBBM_SOFT_RESET, 0);
432 		/* Wait to prevent race in RBBM_STATUS */
433 		mdelay(1);
434 		tmp = RREG32(RADEON_RBBM_STATUS);
435 		if (tmp & ((1 << 20) | (1 << 26))) {
436 			DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
437 			/* GA still busy soft reset it */
438 			WREG32(0x429C, 0x200);
439 			WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
440 			WREG32(0x43E0, 0);
441 			WREG32(0x43E4, 0);
442 			WREG32(0x24AC, 0);
443 		}
444 		/* Wait to prevent race in RBBM_STATUS */
445 		mdelay(1);
446 		tmp = RREG32(RADEON_RBBM_STATUS);
447 		if (!(tmp & ((1 << 20) | (1 << 26)))) {
448 			break;
449 		}
450 	}
451 	for (i = 0; i < rdev->usec_timeout; i++) {
452 		tmp = RREG32(RADEON_RBBM_STATUS);
453 		if (!(tmp & ((1 << 20) | (1 << 26)))) {
454 			DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
455 				 tmp);
456 			if (reinit_cp) {
457 				return r100_cp_init(rdev, rdev->cp.ring_size);
458 			}
459 			return 0;
460 		}
461 		DRM_UDELAY(1);
462 	}
463 	tmp = RREG32(RADEON_RBBM_STATUS);
464 	DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
465 	return -1;
466 }
467 
468 int r300_gpu_reset(struct radeon_device *rdev)
469 {
470 	uint32_t status;
471 
472 	/* reset order likely matter */
473 	status = RREG32(RADEON_RBBM_STATUS);
474 	/* reset HDP */
475 	r100_hdp_reset(rdev);
476 	/* reset rb2d */
477 	if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
478 		r100_rb2d_reset(rdev);
479 	}
480 	/* reset GA */
481 	if (status & ((1 << 20) | (1 << 26))) {
482 		r300_ga_reset(rdev);
483 	}
484 	/* reset CP */
485 	status = RREG32(RADEON_RBBM_STATUS);
486 	if (status & (1 << 16)) {
487 		r100_cp_reset(rdev);
488 	}
489 	/* Check if GPU is idle */
490 	status = RREG32(RADEON_RBBM_STATUS);
491 	if (status & (1 << 31)) {
492 		DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
493 		return -1;
494 	}
495 	DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
496 	return 0;
497 }
498 
499 
500 /*
501  * r300,r350,rv350,rv380 VRAM info
502  */
503 void r300_vram_info(struct radeon_device *rdev)
504 {
505 	uint32_t tmp;
506 
507 	/* DDR for all card after R300 & IGP */
508 	rdev->mc.vram_is_ddr = true;
509 
510 	tmp = RREG32(RADEON_MEM_CNTL);
511 	tmp &= R300_MEM_NUM_CHANNELS_MASK;
512 	switch (tmp) {
513 	case 0: rdev->mc.vram_width = 64; break;
514 	case 1: rdev->mc.vram_width = 128; break;
515 	case 2: rdev->mc.vram_width = 256; break;
516 	default:  rdev->mc.vram_width = 128; break;
517 	}
518 
519 	r100_vram_init_sizes(rdev);
520 }
521 
522 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
523 {
524 	uint32_t link_width_cntl, mask;
525 
526 	if (rdev->flags & RADEON_IS_IGP)
527 		return;
528 
529 	if (!(rdev->flags & RADEON_IS_PCIE))
530 		return;
531 
532 	/* FIXME wait for idle */
533 
534 	switch (lanes) {
535 	case 0:
536 		mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
537 		break;
538 	case 1:
539 		mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
540 		break;
541 	case 2:
542 		mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
543 		break;
544 	case 4:
545 		mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
546 		break;
547 	case 8:
548 		mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
549 		break;
550 	case 12:
551 		mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
552 		break;
553 	case 16:
554 	default:
555 		mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
556 		break;
557 	}
558 
559 	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
560 
561 	if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
562 	    (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
563 		return;
564 
565 	link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
566 			     RADEON_PCIE_LC_RECONFIG_NOW |
567 			     RADEON_PCIE_LC_RECONFIG_LATER |
568 			     RADEON_PCIE_LC_SHORT_RECONFIG_EN);
569 	link_width_cntl |= mask;
570 	WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
571 	WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
572 						     RADEON_PCIE_LC_RECONFIG_NOW));
573 
574 	/* wait for lane set to complete */
575 	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
576 	while (link_width_cntl == 0xffffffff)
577 		link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
578 
579 }
580 
581 #if defined(CONFIG_DEBUG_FS)
582 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
583 {
584 	struct drm_info_node *node = (struct drm_info_node *) m->private;
585 	struct drm_device *dev = node->minor->dev;
586 	struct radeon_device *rdev = dev->dev_private;
587 	uint32_t tmp;
588 
589 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
590 	seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
591 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
592 	seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
593 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
594 	seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
595 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
596 	seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
597 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
598 	seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
599 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
600 	seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
601 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
602 	seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
603 	return 0;
604 }
605 
606 static struct drm_info_list rv370_pcie_gart_info_list[] = {
607 	{"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
608 };
609 #endif
610 
611 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
612 {
613 #if defined(CONFIG_DEBUG_FS)
614 	return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
615 #else
616 	return 0;
617 #endif
618 }
619 
620 static int r300_packet0_check(struct radeon_cs_parser *p,
621 		struct radeon_cs_packet *pkt,
622 		unsigned idx, unsigned reg)
623 {
624 	struct radeon_cs_reloc *reloc;
625 	struct r100_cs_track *track;
626 	volatile uint32_t *ib;
627 	uint32_t tmp, tile_flags = 0;
628 	unsigned i;
629 	int r;
630 	u32 idx_value;
631 
632 	ib = p->ib->ptr;
633 	track = (struct r100_cs_track *)p->track;
634 	idx_value = radeon_get_ib_value(p, idx);
635 
636 	switch(reg) {
637 	case AVIVO_D1MODE_VLINE_START_END:
638 	case RADEON_CRTC_GUI_TRIG_VLINE:
639 		r = r100_cs_packet_parse_vline(p);
640 		if (r) {
641 			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
642 					idx, reg);
643 			r100_cs_dump_packet(p, pkt);
644 			return r;
645 		}
646 		break;
647 	case RADEON_DST_PITCH_OFFSET:
648 	case RADEON_SRC_PITCH_OFFSET:
649 		r = r100_reloc_pitch_offset(p, pkt, idx, reg);
650 		if (r)
651 			return r;
652 		break;
653 	case R300_RB3D_COLOROFFSET0:
654 	case R300_RB3D_COLOROFFSET1:
655 	case R300_RB3D_COLOROFFSET2:
656 	case R300_RB3D_COLOROFFSET3:
657 		i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
658 		r = r100_cs_packet_next_reloc(p, &reloc);
659 		if (r) {
660 			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
661 					idx, reg);
662 			r100_cs_dump_packet(p, pkt);
663 			return r;
664 		}
665 		track->cb[i].robj = reloc->robj;
666 		track->cb[i].offset = idx_value;
667 		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
668 		break;
669 	case R300_ZB_DEPTHOFFSET:
670 		r = r100_cs_packet_next_reloc(p, &reloc);
671 		if (r) {
672 			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
673 					idx, reg);
674 			r100_cs_dump_packet(p, pkt);
675 			return r;
676 		}
677 		track->zb.robj = reloc->robj;
678 		track->zb.offset = idx_value;
679 		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
680 		break;
681 	case R300_TX_OFFSET_0:
682 	case R300_TX_OFFSET_0+4:
683 	case R300_TX_OFFSET_0+8:
684 	case R300_TX_OFFSET_0+12:
685 	case R300_TX_OFFSET_0+16:
686 	case R300_TX_OFFSET_0+20:
687 	case R300_TX_OFFSET_0+24:
688 	case R300_TX_OFFSET_0+28:
689 	case R300_TX_OFFSET_0+32:
690 	case R300_TX_OFFSET_0+36:
691 	case R300_TX_OFFSET_0+40:
692 	case R300_TX_OFFSET_0+44:
693 	case R300_TX_OFFSET_0+48:
694 	case R300_TX_OFFSET_0+52:
695 	case R300_TX_OFFSET_0+56:
696 	case R300_TX_OFFSET_0+60:
697 		i = (reg - R300_TX_OFFSET_0) >> 2;
698 		r = r100_cs_packet_next_reloc(p, &reloc);
699 		if (r) {
700 			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
701 					idx, reg);
702 			r100_cs_dump_packet(p, pkt);
703 			return r;
704 		}
705 
706 		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
707 			tile_flags |= R300_TXO_MACRO_TILE;
708 		if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
709 			tile_flags |= R300_TXO_MICRO_TILE;
710 
711 		tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
712 		tmp |= tile_flags;
713 		ib[idx] = tmp;
714 		track->textures[i].robj = reloc->robj;
715 		break;
716 	/* Tracked registers */
717 	case 0x2084:
718 		/* VAP_VF_CNTL */
719 		track->vap_vf_cntl = idx_value;
720 		break;
721 	case 0x20B4:
722 		/* VAP_VTX_SIZE */
723 		track->vtx_size = idx_value & 0x7F;
724 		break;
725 	case 0x2134:
726 		/* VAP_VF_MAX_VTX_INDX */
727 		track->max_indx = idx_value & 0x00FFFFFFUL;
728 		break;
729 	case 0x43E4:
730 		/* SC_SCISSOR1 */
731 		track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
732 		if (p->rdev->family < CHIP_RV515) {
733 			track->maxy -= 1440;
734 		}
735 		break;
736 	case 0x4E00:
737 		/* RB3D_CCTL */
738 		track->num_cb = ((idx_value >> 5) & 0x3) + 1;
739 		break;
740 	case 0x4E38:
741 	case 0x4E3C:
742 	case 0x4E40:
743 	case 0x4E44:
744 		/* RB3D_COLORPITCH0 */
745 		/* RB3D_COLORPITCH1 */
746 		/* RB3D_COLORPITCH2 */
747 		/* RB3D_COLORPITCH3 */
748 		r = r100_cs_packet_next_reloc(p, &reloc);
749 		if (r) {
750 			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
751 				  idx, reg);
752 			r100_cs_dump_packet(p, pkt);
753 			return r;
754 		}
755 
756 		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
757 			tile_flags |= R300_COLOR_TILE_ENABLE;
758 		if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
759 			tile_flags |= R300_COLOR_MICROTILE_ENABLE;
760 
761 		tmp = idx_value & ~(0x7 << 16);
762 		tmp |= tile_flags;
763 		ib[idx] = tmp;
764 
765 		i = (reg - 0x4E38) >> 2;
766 		track->cb[i].pitch = idx_value & 0x3FFE;
767 		switch (((idx_value >> 21) & 0xF)) {
768 		case 9:
769 		case 11:
770 		case 12:
771 			track->cb[i].cpp = 1;
772 			break;
773 		case 3:
774 		case 4:
775 		case 13:
776 		case 15:
777 			track->cb[i].cpp = 2;
778 			break;
779 		case 6:
780 			track->cb[i].cpp = 4;
781 			break;
782 		case 10:
783 			track->cb[i].cpp = 8;
784 			break;
785 		case 7:
786 			track->cb[i].cpp = 16;
787 			break;
788 		default:
789 			DRM_ERROR("Invalid color buffer format (%d) !\n",
790 				  ((idx_value >> 21) & 0xF));
791 			return -EINVAL;
792 		}
793 		break;
794 	case 0x4F00:
795 		/* ZB_CNTL */
796 		if (idx_value & 2) {
797 			track->z_enabled = true;
798 		} else {
799 			track->z_enabled = false;
800 		}
801 		break;
802 	case 0x4F10:
803 		/* ZB_FORMAT */
804 		switch ((idx_value & 0xF)) {
805 		case 0:
806 		case 1:
807 			track->zb.cpp = 2;
808 			break;
809 		case 2:
810 			track->zb.cpp = 4;
811 			break;
812 		default:
813 			DRM_ERROR("Invalid z buffer format (%d) !\n",
814 				  (idx_value & 0xF));
815 			return -EINVAL;
816 		}
817 		break;
818 	case 0x4F24:
819 		/* ZB_DEPTHPITCH */
820 		r = r100_cs_packet_next_reloc(p, &reloc);
821 		if (r) {
822 			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
823 				  idx, reg);
824 			r100_cs_dump_packet(p, pkt);
825 			return r;
826 		}
827 
828 		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
829 			tile_flags |= R300_DEPTHMACROTILE_ENABLE;
830 		if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
831 			tile_flags |= R300_DEPTHMICROTILE_TILED;;
832 
833 		tmp = idx_value & ~(0x7 << 16);
834 		tmp |= tile_flags;
835 		ib[idx] = tmp;
836 
837 		track->zb.pitch = idx_value & 0x3FFC;
838 		break;
839 	case 0x4104:
840 		for (i = 0; i < 16; i++) {
841 			bool enabled;
842 
843 			enabled = !!(idx_value & (1 << i));
844 			track->textures[i].enabled = enabled;
845 		}
846 		break;
847 	case 0x44C0:
848 	case 0x44C4:
849 	case 0x44C8:
850 	case 0x44CC:
851 	case 0x44D0:
852 	case 0x44D4:
853 	case 0x44D8:
854 	case 0x44DC:
855 	case 0x44E0:
856 	case 0x44E4:
857 	case 0x44E8:
858 	case 0x44EC:
859 	case 0x44F0:
860 	case 0x44F4:
861 	case 0x44F8:
862 	case 0x44FC:
863 		/* TX_FORMAT1_[0-15] */
864 		i = (reg - 0x44C0) >> 2;
865 		tmp = (idx_value >> 25) & 0x3;
866 		track->textures[i].tex_coord_type = tmp;
867 		switch ((idx_value & 0x1F)) {
868 		case R300_TX_FORMAT_X8:
869 		case R300_TX_FORMAT_Y4X4:
870 		case R300_TX_FORMAT_Z3Y3X2:
871 			track->textures[i].cpp = 1;
872 			break;
873 		case R300_TX_FORMAT_X16:
874 		case R300_TX_FORMAT_Y8X8:
875 		case R300_TX_FORMAT_Z5Y6X5:
876 		case R300_TX_FORMAT_Z6Y5X5:
877 		case R300_TX_FORMAT_W4Z4Y4X4:
878 		case R300_TX_FORMAT_W1Z5Y5X5:
879 		case R300_TX_FORMAT_D3DMFT_CxV8U8:
880 		case R300_TX_FORMAT_B8G8_B8G8:
881 		case R300_TX_FORMAT_G8R8_G8B8:
882 			track->textures[i].cpp = 2;
883 			break;
884 		case R300_TX_FORMAT_Y16X16:
885 		case R300_TX_FORMAT_Z11Y11X10:
886 		case R300_TX_FORMAT_Z10Y11X11:
887 		case R300_TX_FORMAT_W8Z8Y8X8:
888 		case R300_TX_FORMAT_W2Z10Y10X10:
889 		case 0x17:
890 		case R300_TX_FORMAT_FL_I32:
891 		case 0x1e:
892 			track->textures[i].cpp = 4;
893 			break;
894 		case R300_TX_FORMAT_W16Z16Y16X16:
895 		case R300_TX_FORMAT_FL_R16G16B16A16:
896 		case R300_TX_FORMAT_FL_I32A32:
897 			track->textures[i].cpp = 8;
898 			break;
899 		case R300_TX_FORMAT_FL_R32G32B32A32:
900 			track->textures[i].cpp = 16;
901 			break;
902 		case R300_TX_FORMAT_DXT1:
903 			track->textures[i].cpp = 1;
904 			track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
905 			break;
906 		case R300_TX_FORMAT_ATI2N:
907 			if (p->rdev->family < CHIP_R420) {
908 				DRM_ERROR("Invalid texture format %u\n",
909 					  (idx_value & 0x1F));
910 				return -EINVAL;
911 			}
912 			/* The same rules apply as for DXT3/5. */
913 			/* Pass through. */
914 		case R300_TX_FORMAT_DXT3:
915 		case R300_TX_FORMAT_DXT5:
916 			track->textures[i].cpp = 1;
917 			track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
918 			break;
919 		default:
920 			DRM_ERROR("Invalid texture format %u\n",
921 				  (idx_value & 0x1F));
922 			return -EINVAL;
923 			break;
924 		}
925 		break;
926 	case 0x4400:
927 	case 0x4404:
928 	case 0x4408:
929 	case 0x440C:
930 	case 0x4410:
931 	case 0x4414:
932 	case 0x4418:
933 	case 0x441C:
934 	case 0x4420:
935 	case 0x4424:
936 	case 0x4428:
937 	case 0x442C:
938 	case 0x4430:
939 	case 0x4434:
940 	case 0x4438:
941 	case 0x443C:
942 		/* TX_FILTER0_[0-15] */
943 		i = (reg - 0x4400) >> 2;
944 		tmp = idx_value & 0x7;
945 		if (tmp == 2 || tmp == 4 || tmp == 6) {
946 			track->textures[i].roundup_w = false;
947 		}
948 		tmp = (idx_value >> 3) & 0x7;
949 		if (tmp == 2 || tmp == 4 || tmp == 6) {
950 			track->textures[i].roundup_h = false;
951 		}
952 		break;
953 	case 0x4500:
954 	case 0x4504:
955 	case 0x4508:
956 	case 0x450C:
957 	case 0x4510:
958 	case 0x4514:
959 	case 0x4518:
960 	case 0x451C:
961 	case 0x4520:
962 	case 0x4524:
963 	case 0x4528:
964 	case 0x452C:
965 	case 0x4530:
966 	case 0x4534:
967 	case 0x4538:
968 	case 0x453C:
969 		/* TX_FORMAT2_[0-15] */
970 		i = (reg - 0x4500) >> 2;
971 		tmp = idx_value & 0x3FFF;
972 		track->textures[i].pitch = tmp + 1;
973 		if (p->rdev->family >= CHIP_RV515) {
974 			tmp = ((idx_value >> 15) & 1) << 11;
975 			track->textures[i].width_11 = tmp;
976 			tmp = ((idx_value >> 16) & 1) << 11;
977 			track->textures[i].height_11 = tmp;
978 
979 			/* ATI1N */
980 			if (idx_value & (1 << 14)) {
981 				/* The same rules apply as for DXT1. */
982 				track->textures[i].compress_format =
983 					R100_TRACK_COMP_DXT1;
984 			}
985 		} else if (idx_value & (1 << 14)) {
986 			DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
987 			return -EINVAL;
988 		}
989 		break;
990 	case 0x4480:
991 	case 0x4484:
992 	case 0x4488:
993 	case 0x448C:
994 	case 0x4490:
995 	case 0x4494:
996 	case 0x4498:
997 	case 0x449C:
998 	case 0x44A0:
999 	case 0x44A4:
1000 	case 0x44A8:
1001 	case 0x44AC:
1002 	case 0x44B0:
1003 	case 0x44B4:
1004 	case 0x44B8:
1005 	case 0x44BC:
1006 		/* TX_FORMAT0_[0-15] */
1007 		i = (reg - 0x4480) >> 2;
1008 		tmp = idx_value & 0x7FF;
1009 		track->textures[i].width = tmp + 1;
1010 		tmp = (idx_value >> 11) & 0x7FF;
1011 		track->textures[i].height = tmp + 1;
1012 		tmp = (idx_value >> 26) & 0xF;
1013 		track->textures[i].num_levels = tmp;
1014 		tmp = idx_value & (1 << 31);
1015 		track->textures[i].use_pitch = !!tmp;
1016 		tmp = (idx_value >> 22) & 0xF;
1017 		track->textures[i].txdepth = tmp;
1018 		break;
1019 	case R300_ZB_ZPASS_ADDR:
1020 		r = r100_cs_packet_next_reloc(p, &reloc);
1021 		if (r) {
1022 			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1023 					idx, reg);
1024 			r100_cs_dump_packet(p, pkt);
1025 			return r;
1026 		}
1027 		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1028 		break;
1029 	case 0x4e0c:
1030 		/* RB3D_COLOR_CHANNEL_MASK */
1031 		track->color_channel_mask = idx_value;
1032 		break;
1033 	case 0x4d1c:
1034 		/* ZB_BW_CNTL */
1035 		track->fastfill = !!(idx_value & (1 << 2));
1036 		break;
1037 	case 0x4e04:
1038 		/* RB3D_BLENDCNTL */
1039 		track->blend_read_enable = !!(idx_value & (1 << 2));
1040 		break;
1041 	case 0x4be8:
1042 		/* valid register only on RV530 */
1043 		if (p->rdev->family == CHIP_RV530)
1044 			break;
1045 		/* fallthrough do not move */
1046 	default:
1047 		printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1048 		       reg, idx);
1049 		return -EINVAL;
1050 	}
1051 	return 0;
1052 }
1053 
1054 static int r300_packet3_check(struct radeon_cs_parser *p,
1055 			      struct radeon_cs_packet *pkt)
1056 {
1057 	struct radeon_cs_reloc *reloc;
1058 	struct r100_cs_track *track;
1059 	volatile uint32_t *ib;
1060 	unsigned idx;
1061 	int r;
1062 
1063 	ib = p->ib->ptr;
1064 	idx = pkt->idx + 1;
1065 	track = (struct r100_cs_track *)p->track;
1066 	switch(pkt->opcode) {
1067 	case PACKET3_3D_LOAD_VBPNTR:
1068 		r = r100_packet3_load_vbpntr(p, pkt, idx);
1069 		if (r)
1070 			return r;
1071 		break;
1072 	case PACKET3_INDX_BUFFER:
1073 		r = r100_cs_packet_next_reloc(p, &reloc);
1074 		if (r) {
1075 			DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1076 			r100_cs_dump_packet(p, pkt);
1077 			return r;
1078 		}
1079 		ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1080 		r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1081 		if (r) {
1082 			return r;
1083 		}
1084 		break;
1085 	/* Draw packet */
1086 	case PACKET3_3D_DRAW_IMMD:
1087 		/* Number of dwords is vtx_size * (num_vertices - 1)
1088 		 * PRIM_WALK must be equal to 3 vertex data in embedded
1089 		 * in cmd stream */
1090 		if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1091 			DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1092 			return -EINVAL;
1093 		}
1094 		track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1095 		track->immd_dwords = pkt->count - 1;
1096 		r = r100_cs_track_check(p->rdev, track);
1097 		if (r) {
1098 			return r;
1099 		}
1100 		break;
1101 	case PACKET3_3D_DRAW_IMMD_2:
1102 		/* Number of dwords is vtx_size * (num_vertices - 1)
1103 		 * PRIM_WALK must be equal to 3 vertex data in embedded
1104 		 * in cmd stream */
1105 		if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1106 			DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1107 			return -EINVAL;
1108 		}
1109 		track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1110 		track->immd_dwords = pkt->count;
1111 		r = r100_cs_track_check(p->rdev, track);
1112 		if (r) {
1113 			return r;
1114 		}
1115 		break;
1116 	case PACKET3_3D_DRAW_VBUF:
1117 		track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1118 		r = r100_cs_track_check(p->rdev, track);
1119 		if (r) {
1120 			return r;
1121 		}
1122 		break;
1123 	case PACKET3_3D_DRAW_VBUF_2:
1124 		track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1125 		r = r100_cs_track_check(p->rdev, track);
1126 		if (r) {
1127 			return r;
1128 		}
1129 		break;
1130 	case PACKET3_3D_DRAW_INDX:
1131 		track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1132 		r = r100_cs_track_check(p->rdev, track);
1133 		if (r) {
1134 			return r;
1135 		}
1136 		break;
1137 	case PACKET3_3D_DRAW_INDX_2:
1138 		track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1139 		r = r100_cs_track_check(p->rdev, track);
1140 		if (r) {
1141 			return r;
1142 		}
1143 		break;
1144 	case PACKET3_NOP:
1145 		break;
1146 	default:
1147 		DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1148 		return -EINVAL;
1149 	}
1150 	return 0;
1151 }
1152 
1153 int r300_cs_parse(struct radeon_cs_parser *p)
1154 {
1155 	struct radeon_cs_packet pkt;
1156 	struct r100_cs_track *track;
1157 	int r;
1158 
1159 	track = kzalloc(sizeof(*track), GFP_KERNEL);
1160 	r100_cs_track_clear(p->rdev, track);
1161 	p->track = track;
1162 	do {
1163 		r = r100_cs_packet_parse(p, &pkt, p->idx);
1164 		if (r) {
1165 			return r;
1166 		}
1167 		p->idx += pkt.count + 2;
1168 		switch (pkt.type) {
1169 		case PACKET_TYPE0:
1170 			r = r100_cs_parse_packet0(p, &pkt,
1171 						  p->rdev->config.r300.reg_safe_bm,
1172 						  p->rdev->config.r300.reg_safe_bm_size,
1173 						  &r300_packet0_check);
1174 			break;
1175 		case PACKET_TYPE2:
1176 			break;
1177 		case PACKET_TYPE3:
1178 			r = r300_packet3_check(p, &pkt);
1179 			break;
1180 		default:
1181 			DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1182 			return -EINVAL;
1183 		}
1184 		if (r) {
1185 			return r;
1186 		}
1187 	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1188 	return 0;
1189 }
1190 
1191 void r300_set_reg_safe(struct radeon_device *rdev)
1192 {
1193 	rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1194 	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1195 }
1196 
1197 void r300_mc_program(struct radeon_device *rdev)
1198 {
1199 	struct r100_mc_save save;
1200 	int r;
1201 
1202 	r = r100_debugfs_mc_info_init(rdev);
1203 	if (r) {
1204 		dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1205 	}
1206 
1207 	/* Stops all mc clients */
1208 	r100_mc_stop(rdev, &save);
1209 	if (rdev->flags & RADEON_IS_AGP) {
1210 		WREG32(R_00014C_MC_AGP_LOCATION,
1211 			S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1212 			S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1213 		WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1214 		WREG32(R_00015C_AGP_BASE_2,
1215 			upper_32_bits(rdev->mc.agp_base) & 0xff);
1216 	} else {
1217 		WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1218 		WREG32(R_000170_AGP_BASE, 0);
1219 		WREG32(R_00015C_AGP_BASE_2, 0);
1220 	}
1221 	/* Wait for mc idle */
1222 	if (r300_mc_wait_for_idle(rdev))
1223 		DRM_INFO("Failed to wait MC idle before programming MC.\n");
1224 	/* Program MC, should be a 32bits limited address space */
1225 	WREG32(R_000148_MC_FB_LOCATION,
1226 		S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1227 		S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1228 	r100_mc_resume(rdev, &save);
1229 }
1230 
1231 void r300_clock_startup(struct radeon_device *rdev)
1232 {
1233 	u32 tmp;
1234 
1235 	if (radeon_dynclks != -1 && radeon_dynclks)
1236 		radeon_legacy_set_clock_gating(rdev, 1);
1237 	/* We need to force on some of the block */
1238 	tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1239 	tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1240 	if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1241 		tmp |= S_00000D_FORCE_VAP(1);
1242 	WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1243 }
1244 
1245 static int r300_startup(struct radeon_device *rdev)
1246 {
1247 	int r;
1248 
1249 	/* set common regs */
1250 	r100_set_common_regs(rdev);
1251 	/* program mc */
1252 	r300_mc_program(rdev);
1253 	/* Resume clock */
1254 	r300_clock_startup(rdev);
1255 	/* Initialize GPU configuration (# pipes, ...) */
1256 	r300_gpu_init(rdev);
1257 	/* Initialize GART (initialize after TTM so we can allocate
1258 	 * memory through TTM but finalize after TTM) */
1259 	if (rdev->flags & RADEON_IS_PCIE) {
1260 		r = rv370_pcie_gart_enable(rdev);
1261 		if (r)
1262 			return r;
1263 	}
1264 
1265 	if (rdev->family == CHIP_R300 ||
1266 	    rdev->family == CHIP_R350 ||
1267 	    rdev->family == CHIP_RV350)
1268 		r100_enable_bm(rdev);
1269 
1270 	if (rdev->flags & RADEON_IS_PCI) {
1271 		r = r100_pci_gart_enable(rdev);
1272 		if (r)
1273 			return r;
1274 	}
1275 	/* Enable IRQ */
1276 	r100_irq_set(rdev);
1277 	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1278 	/* 1M ring buffer */
1279 	r = r100_cp_init(rdev, 1024 * 1024);
1280 	if (r) {
1281 		dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
1282 		return r;
1283 	}
1284 	r = r100_wb_init(rdev);
1285 	if (r)
1286 		dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
1287 	r = r100_ib_init(rdev);
1288 	if (r) {
1289 		dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
1290 		return r;
1291 	}
1292 	return 0;
1293 }
1294 
1295 int r300_resume(struct radeon_device *rdev)
1296 {
1297 	/* Make sur GART are not working */
1298 	if (rdev->flags & RADEON_IS_PCIE)
1299 		rv370_pcie_gart_disable(rdev);
1300 	if (rdev->flags & RADEON_IS_PCI)
1301 		r100_pci_gart_disable(rdev);
1302 	/* Resume clock before doing reset */
1303 	r300_clock_startup(rdev);
1304 	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
1305 	if (radeon_gpu_reset(rdev)) {
1306 		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1307 			RREG32(R_000E40_RBBM_STATUS),
1308 			RREG32(R_0007C0_CP_STAT));
1309 	}
1310 	/* post */
1311 	radeon_combios_asic_init(rdev->ddev);
1312 	/* Resume clock after posting */
1313 	r300_clock_startup(rdev);
1314 	/* Initialize surface registers */
1315 	radeon_surface_init(rdev);
1316 	return r300_startup(rdev);
1317 }
1318 
1319 int r300_suspend(struct radeon_device *rdev)
1320 {
1321 	r100_cp_disable(rdev);
1322 	r100_wb_disable(rdev);
1323 	r100_irq_disable(rdev);
1324 	if (rdev->flags & RADEON_IS_PCIE)
1325 		rv370_pcie_gart_disable(rdev);
1326 	if (rdev->flags & RADEON_IS_PCI)
1327 		r100_pci_gart_disable(rdev);
1328 	return 0;
1329 }
1330 
1331 void r300_fini(struct radeon_device *rdev)
1332 {
1333 	r100_cp_fini(rdev);
1334 	r100_wb_fini(rdev);
1335 	r100_ib_fini(rdev);
1336 	radeon_gem_fini(rdev);
1337 	if (rdev->flags & RADEON_IS_PCIE)
1338 		rv370_pcie_gart_fini(rdev);
1339 	if (rdev->flags & RADEON_IS_PCI)
1340 		r100_pci_gart_fini(rdev);
1341 	radeon_agp_fini(rdev);
1342 	radeon_irq_kms_fini(rdev);
1343 	radeon_fence_driver_fini(rdev);
1344 	radeon_bo_fini(rdev);
1345 	radeon_atombios_fini(rdev);
1346 	kfree(rdev->bios);
1347 	rdev->bios = NULL;
1348 }
1349 
1350 int r300_init(struct radeon_device *rdev)
1351 {
1352 	int r;
1353 
1354 	/* Disable VGA */
1355 	r100_vga_render_disable(rdev);
1356 	/* Initialize scratch registers */
1357 	radeon_scratch_init(rdev);
1358 	/* Initialize surface registers */
1359 	radeon_surface_init(rdev);
1360 	/* TODO: disable VGA need to use VGA request */
1361 	/* BIOS*/
1362 	if (!radeon_get_bios(rdev)) {
1363 		if (ASIC_IS_AVIVO(rdev))
1364 			return -EINVAL;
1365 	}
1366 	if (rdev->is_atom_bios) {
1367 		dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1368 		return -EINVAL;
1369 	} else {
1370 		r = radeon_combios_init(rdev);
1371 		if (r)
1372 			return r;
1373 	}
1374 	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
1375 	if (radeon_gpu_reset(rdev)) {
1376 		dev_warn(rdev->dev,
1377 			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1378 			RREG32(R_000E40_RBBM_STATUS),
1379 			RREG32(R_0007C0_CP_STAT));
1380 	}
1381 	/* check if cards are posted or not */
1382 	if (radeon_boot_test_post_card(rdev) == false)
1383 		return -EINVAL;
1384 	/* Set asic errata */
1385 	r300_errata(rdev);
1386 	/* Initialize clocks */
1387 	radeon_get_clock_info(rdev->ddev);
1388 	/* Initialize power management */
1389 	radeon_pm_init(rdev);
1390 	/* Get vram informations */
1391 	r300_vram_info(rdev);
1392 	/* Initialize memory controller (also test AGP) */
1393 	r = r420_mc_init(rdev);
1394 	if (r)
1395 		return r;
1396 	/* Fence driver */
1397 	r = radeon_fence_driver_init(rdev);
1398 	if (r)
1399 		return r;
1400 	r = radeon_irq_kms_init(rdev);
1401 	if (r)
1402 		return r;
1403 	/* Memory manager */
1404 	r = radeon_bo_init(rdev);
1405 	if (r)
1406 		return r;
1407 	if (rdev->flags & RADEON_IS_PCIE) {
1408 		r = rv370_pcie_gart_init(rdev);
1409 		if (r)
1410 			return r;
1411 	}
1412 	if (rdev->flags & RADEON_IS_PCI) {
1413 		r = r100_pci_gart_init(rdev);
1414 		if (r)
1415 			return r;
1416 	}
1417 	r300_set_reg_safe(rdev);
1418 	rdev->accel_working = true;
1419 	r = r300_startup(rdev);
1420 	if (r) {
1421 		/* Somethings want wront with the accel init stop accel */
1422 		dev_err(rdev->dev, "Disabling GPU acceleration\n");
1423 		r100_cp_fini(rdev);
1424 		r100_wb_fini(rdev);
1425 		r100_ib_fini(rdev);
1426 		radeon_irq_kms_fini(rdev);
1427 		if (rdev->flags & RADEON_IS_PCIE)
1428 			rv370_pcie_gart_fini(rdev);
1429 		if (rdev->flags & RADEON_IS_PCI)
1430 			r100_pci_gart_fini(rdev);
1431 		radeon_agp_fini(rdev);
1432 		rdev->accel_working = false;
1433 	}
1434 	return 0;
1435 }
1436