1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include "drmP.h" 30 #include "drm.h" 31 #include "radeon_reg.h" 32 #include "radeon.h" 33 #include "radeon_drm.h" 34 #include "r100_track.h" 35 #include "r300d.h" 36 #include "rv350d.h" 37 #include "r300_reg_safe.h" 38 39 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 40 * 41 * GPU Errata: 42 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL 43 * using MMIO to flush host path read cache, this lead to HARDLOCKUP. 44 * However, scheduling such write to the ring seems harmless, i suspect 45 * the CP read collide with the flush somehow, or maybe the MC, hard to 46 * tell. (Jerome Glisse) 47 */ 48 49 /* 50 * rv370,rv380 PCIE GART 51 */ 52 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 53 54 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) 55 { 56 uint32_t tmp; 57 int i; 58 59 /* Workaround HW bug do flush 2 times */ 60 for (i = 0; i < 2; i++) { 61 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 62 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); 63 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 64 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 65 } 66 mb(); 67 } 68 69 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 70 { 71 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; 72 73 if (i < 0 || i > rdev->gart.num_gpu_pages) { 74 return -EINVAL; 75 } 76 addr = (lower_32_bits(addr) >> 8) | 77 ((upper_32_bits(addr) & 0xff) << 24) | 78 0xc; 79 /* on x86 we want this to be CPU endian, on powerpc 80 * on powerpc without HW swappers, it'll get swapped on way 81 * into VRAM - so no need for cpu_to_le32 on VRAM tables */ 82 writel(addr, ((void __iomem *)ptr) + (i * 4)); 83 return 0; 84 } 85 86 int rv370_pcie_gart_init(struct radeon_device *rdev) 87 { 88 int r; 89 90 if (rdev->gart.table.vram.robj) { 91 WARN(1, "RV370 PCIE GART already initialized.\n"); 92 return 0; 93 } 94 /* Initialize common gart structure */ 95 r = radeon_gart_init(rdev); 96 if (r) 97 return r; 98 r = rv370_debugfs_pcie_gart_info_init(rdev); 99 if (r) 100 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); 101 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 102 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; 103 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; 104 return radeon_gart_table_vram_alloc(rdev); 105 } 106 107 int rv370_pcie_gart_enable(struct radeon_device *rdev) 108 { 109 uint32_t table_addr; 110 uint32_t tmp; 111 int r; 112 113 if (rdev->gart.table.vram.robj == NULL) { 114 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 115 return -EINVAL; 116 } 117 r = radeon_gart_table_vram_pin(rdev); 118 if (r) 119 return r; 120 /* discard memory request outside of configured range */ 121 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 122 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 123 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location); 124 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - RADEON_GPU_PAGE_SIZE; 125 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); 126 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 127 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 128 table_addr = rdev->gart.table_addr; 129 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); 130 /* FIXME: setup default page */ 131 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location); 132 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); 133 /* Clear error */ 134 WREG32_PCIE(0x18, 0); 135 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 136 tmp |= RADEON_PCIE_TX_GART_EN; 137 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 138 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 139 rv370_pcie_gart_tlb_flush(rdev); 140 DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n", 141 (unsigned)(rdev->mc.gtt_size >> 20), table_addr); 142 rdev->gart.ready = true; 143 return 0; 144 } 145 146 void rv370_pcie_gart_disable(struct radeon_device *rdev) 147 { 148 u32 tmp; 149 int r; 150 151 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 152 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 153 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); 154 if (rdev->gart.table.vram.robj) { 155 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); 156 if (likely(r == 0)) { 157 radeon_bo_kunmap(rdev->gart.table.vram.robj); 158 radeon_bo_unpin(rdev->gart.table.vram.robj); 159 radeon_bo_unreserve(rdev->gart.table.vram.robj); 160 } 161 } 162 } 163 164 void rv370_pcie_gart_fini(struct radeon_device *rdev) 165 { 166 rv370_pcie_gart_disable(rdev); 167 radeon_gart_table_vram_free(rdev); 168 radeon_gart_fini(rdev); 169 } 170 171 void r300_fence_ring_emit(struct radeon_device *rdev, 172 struct radeon_fence *fence) 173 { 174 /* Who ever call radeon_fence_emit should call ring_lock and ask 175 * for enough space (today caller are ib schedule and buffer move) */ 176 /* Write SC register so SC & US assert idle */ 177 radeon_ring_write(rdev, PACKET0(0x43E0, 0)); 178 radeon_ring_write(rdev, 0); 179 radeon_ring_write(rdev, PACKET0(0x43E4, 0)); 180 radeon_ring_write(rdev, 0); 181 /* Flush 3D cache */ 182 radeon_ring_write(rdev, PACKET0(0x4E4C, 0)); 183 radeon_ring_write(rdev, (2 << 0)); 184 radeon_ring_write(rdev, PACKET0(0x4F18, 0)); 185 radeon_ring_write(rdev, (1 << 0)); 186 /* Wait until IDLE & CLEAN */ 187 radeon_ring_write(rdev, PACKET0(0x1720, 0)); 188 radeon_ring_write(rdev, (1 << 17) | (1 << 16) | (1 << 9)); 189 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 190 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl | 191 RADEON_HDP_READ_BUFFER_INVALIDATE); 192 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 193 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl); 194 /* Emit fence sequence & fire IRQ */ 195 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); 196 radeon_ring_write(rdev, fence->seq); 197 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); 198 radeon_ring_write(rdev, RADEON_SW_INT_FIRE); 199 } 200 201 int r300_copy_dma(struct radeon_device *rdev, 202 uint64_t src_offset, 203 uint64_t dst_offset, 204 unsigned num_pages, 205 struct radeon_fence *fence) 206 { 207 uint32_t size; 208 uint32_t cur_size; 209 int i, num_loops; 210 int r = 0; 211 212 /* radeon pitch is /64 */ 213 size = num_pages << PAGE_SHIFT; 214 num_loops = DIV_ROUND_UP(size, 0x1FFFFF); 215 r = radeon_ring_lock(rdev, num_loops * 4 + 64); 216 if (r) { 217 DRM_ERROR("radeon: moving bo (%d).\n", r); 218 return r; 219 } 220 /* Must wait for 2D idle & clean before DMA or hangs might happen */ 221 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0 )); 222 radeon_ring_write(rdev, (1 << 16)); 223 for (i = 0; i < num_loops; i++) { 224 cur_size = size; 225 if (cur_size > 0x1FFFFF) { 226 cur_size = 0x1FFFFF; 227 } 228 size -= cur_size; 229 radeon_ring_write(rdev, PACKET0(0x720, 2)); 230 radeon_ring_write(rdev, src_offset); 231 radeon_ring_write(rdev, dst_offset); 232 radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30)); 233 src_offset += cur_size; 234 dst_offset += cur_size; 235 } 236 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 237 radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE); 238 if (fence) { 239 r = radeon_fence_emit(rdev, fence); 240 } 241 radeon_ring_unlock_commit(rdev); 242 return r; 243 } 244 245 void r300_ring_start(struct radeon_device *rdev) 246 { 247 unsigned gb_tile_config; 248 int r; 249 250 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 251 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 252 switch(rdev->num_gb_pipes) { 253 case 2: 254 gb_tile_config |= R300_PIPE_COUNT_R300; 255 break; 256 case 3: 257 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 258 break; 259 case 4: 260 gb_tile_config |= R300_PIPE_COUNT_R420; 261 break; 262 case 1: 263 default: 264 gb_tile_config |= R300_PIPE_COUNT_RV350; 265 break; 266 } 267 268 r = radeon_ring_lock(rdev, 64); 269 if (r) { 270 return; 271 } 272 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); 273 radeon_ring_write(rdev, 274 RADEON_ISYNC_ANY2D_IDLE3D | 275 RADEON_ISYNC_ANY3D_IDLE2D | 276 RADEON_ISYNC_WAIT_IDLEGUI | 277 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 278 radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0)); 279 radeon_ring_write(rdev, gb_tile_config); 280 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 281 radeon_ring_write(rdev, 282 RADEON_WAIT_2D_IDLECLEAN | 283 RADEON_WAIT_3D_IDLECLEAN); 284 radeon_ring_write(rdev, PACKET0(0x170C, 0)); 285 radeon_ring_write(rdev, 1 << 31); 286 radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0)); 287 radeon_ring_write(rdev, 0); 288 radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0)); 289 radeon_ring_write(rdev, 0); 290 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 291 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 292 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 293 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); 294 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 295 radeon_ring_write(rdev, 296 RADEON_WAIT_2D_IDLECLEAN | 297 RADEON_WAIT_3D_IDLECLEAN); 298 radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0)); 299 radeon_ring_write(rdev, 0); 300 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 301 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 302 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 303 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); 304 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0)); 305 radeon_ring_write(rdev, 306 ((6 << R300_MS_X0_SHIFT) | 307 (6 << R300_MS_Y0_SHIFT) | 308 (6 << R300_MS_X1_SHIFT) | 309 (6 << R300_MS_Y1_SHIFT) | 310 (6 << R300_MS_X2_SHIFT) | 311 (6 << R300_MS_Y2_SHIFT) | 312 (6 << R300_MSBD0_Y_SHIFT) | 313 (6 << R300_MSBD0_X_SHIFT))); 314 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0)); 315 radeon_ring_write(rdev, 316 ((6 << R300_MS_X3_SHIFT) | 317 (6 << R300_MS_Y3_SHIFT) | 318 (6 << R300_MS_X4_SHIFT) | 319 (6 << R300_MS_Y4_SHIFT) | 320 (6 << R300_MS_X5_SHIFT) | 321 (6 << R300_MS_Y5_SHIFT) | 322 (6 << R300_MSBD1_SHIFT))); 323 radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0)); 324 radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); 325 radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0)); 326 radeon_ring_write(rdev, 327 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); 328 radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0)); 329 radeon_ring_write(rdev, 330 R300_GEOMETRY_ROUND_NEAREST | 331 R300_COLOR_ROUND_NEAREST); 332 radeon_ring_unlock_commit(rdev); 333 } 334 335 void r300_errata(struct radeon_device *rdev) 336 { 337 rdev->pll_errata = 0; 338 339 if (rdev->family == CHIP_R300 && 340 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { 341 rdev->pll_errata |= CHIP_ERRATA_R300_CG; 342 } 343 } 344 345 int r300_mc_wait_for_idle(struct radeon_device *rdev) 346 { 347 unsigned i; 348 uint32_t tmp; 349 350 for (i = 0; i < rdev->usec_timeout; i++) { 351 /* read MC_STATUS */ 352 tmp = RREG32(0x0150); 353 if (tmp & (1 << 4)) { 354 return 0; 355 } 356 DRM_UDELAY(1); 357 } 358 return -1; 359 } 360 361 void r300_gpu_init(struct radeon_device *rdev) 362 { 363 uint32_t gb_tile_config, tmp; 364 365 r100_hdp_reset(rdev); 366 /* FIXME: rv380 one pipes ? */ 367 if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) { 368 /* r300,r350 */ 369 rdev->num_gb_pipes = 2; 370 } else { 371 /* rv350,rv370,rv380 */ 372 rdev->num_gb_pipes = 1; 373 } 374 rdev->num_z_pipes = 1; 375 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 376 switch (rdev->num_gb_pipes) { 377 case 2: 378 gb_tile_config |= R300_PIPE_COUNT_R300; 379 break; 380 case 3: 381 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 382 break; 383 case 4: 384 gb_tile_config |= R300_PIPE_COUNT_R420; 385 break; 386 default: 387 case 1: 388 gb_tile_config |= R300_PIPE_COUNT_RV350; 389 break; 390 } 391 WREG32(R300_GB_TILE_CONFIG, gb_tile_config); 392 393 if (r100_gui_wait_for_idle(rdev)) { 394 printk(KERN_WARNING "Failed to wait GUI idle while " 395 "programming pipes. Bad things might happen.\n"); 396 } 397 398 tmp = RREG32(0x170C); 399 WREG32(0x170C, tmp | (1 << 31)); 400 401 WREG32(R300_RB2D_DSTCACHE_MODE, 402 R300_DC_AUTOFLUSH_ENABLE | 403 R300_DC_DC_DISABLE_IGNORE_PE); 404 405 if (r100_gui_wait_for_idle(rdev)) { 406 printk(KERN_WARNING "Failed to wait GUI idle while " 407 "programming pipes. Bad things might happen.\n"); 408 } 409 if (r300_mc_wait_for_idle(rdev)) { 410 printk(KERN_WARNING "Failed to wait MC idle while " 411 "programming pipes. Bad things might happen.\n"); 412 } 413 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n", 414 rdev->num_gb_pipes, rdev->num_z_pipes); 415 } 416 417 int r300_ga_reset(struct radeon_device *rdev) 418 { 419 uint32_t tmp; 420 bool reinit_cp; 421 int i; 422 423 reinit_cp = rdev->cp.ready; 424 rdev->cp.ready = false; 425 for (i = 0; i < rdev->usec_timeout; i++) { 426 WREG32(RADEON_CP_CSQ_MODE, 0); 427 WREG32(RADEON_CP_CSQ_CNTL, 0); 428 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005); 429 (void)RREG32(RADEON_RBBM_SOFT_RESET); 430 udelay(200); 431 WREG32(RADEON_RBBM_SOFT_RESET, 0); 432 /* Wait to prevent race in RBBM_STATUS */ 433 mdelay(1); 434 tmp = RREG32(RADEON_RBBM_STATUS); 435 if (tmp & ((1 << 20) | (1 << 26))) { 436 DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp); 437 /* GA still busy soft reset it */ 438 WREG32(0x429C, 0x200); 439 WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0); 440 WREG32(0x43E0, 0); 441 WREG32(0x43E4, 0); 442 WREG32(0x24AC, 0); 443 } 444 /* Wait to prevent race in RBBM_STATUS */ 445 mdelay(1); 446 tmp = RREG32(RADEON_RBBM_STATUS); 447 if (!(tmp & ((1 << 20) | (1 << 26)))) { 448 break; 449 } 450 } 451 for (i = 0; i < rdev->usec_timeout; i++) { 452 tmp = RREG32(RADEON_RBBM_STATUS); 453 if (!(tmp & ((1 << 20) | (1 << 26)))) { 454 DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n", 455 tmp); 456 if (reinit_cp) { 457 return r100_cp_init(rdev, rdev->cp.ring_size); 458 } 459 return 0; 460 } 461 DRM_UDELAY(1); 462 } 463 tmp = RREG32(RADEON_RBBM_STATUS); 464 DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp); 465 return -1; 466 } 467 468 int r300_gpu_reset(struct radeon_device *rdev) 469 { 470 uint32_t status; 471 472 /* reset order likely matter */ 473 status = RREG32(RADEON_RBBM_STATUS); 474 /* reset HDP */ 475 r100_hdp_reset(rdev); 476 /* reset rb2d */ 477 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) { 478 r100_rb2d_reset(rdev); 479 } 480 /* reset GA */ 481 if (status & ((1 << 20) | (1 << 26))) { 482 r300_ga_reset(rdev); 483 } 484 /* reset CP */ 485 status = RREG32(RADEON_RBBM_STATUS); 486 if (status & (1 << 16)) { 487 r100_cp_reset(rdev); 488 } 489 /* Check if GPU is idle */ 490 status = RREG32(RADEON_RBBM_STATUS); 491 if (status & (1 << 31)) { 492 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); 493 return -1; 494 } 495 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status); 496 return 0; 497 } 498 499 500 /* 501 * r300,r350,rv350,rv380 VRAM info 502 */ 503 void r300_vram_info(struct radeon_device *rdev) 504 { 505 uint32_t tmp; 506 507 /* DDR for all card after R300 & IGP */ 508 rdev->mc.vram_is_ddr = true; 509 tmp = RREG32(RADEON_MEM_CNTL); 510 if (tmp & R300_MEM_NUM_CHANNELS_MASK) { 511 rdev->mc.vram_width = 128; 512 } else { 513 rdev->mc.vram_width = 64; 514 } 515 516 r100_vram_init_sizes(rdev); 517 } 518 519 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) 520 { 521 uint32_t link_width_cntl, mask; 522 523 if (rdev->flags & RADEON_IS_IGP) 524 return; 525 526 if (!(rdev->flags & RADEON_IS_PCIE)) 527 return; 528 529 /* FIXME wait for idle */ 530 531 switch (lanes) { 532 case 0: 533 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 534 break; 535 case 1: 536 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 537 break; 538 case 2: 539 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 540 break; 541 case 4: 542 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 543 break; 544 case 8: 545 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 546 break; 547 case 12: 548 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 549 break; 550 case 16: 551 default: 552 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 553 break; 554 } 555 556 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 557 558 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == 559 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) 560 return; 561 562 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | 563 RADEON_PCIE_LC_RECONFIG_NOW | 564 RADEON_PCIE_LC_RECONFIG_LATER | 565 RADEON_PCIE_LC_SHORT_RECONFIG_EN); 566 link_width_cntl |= mask; 567 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 568 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | 569 RADEON_PCIE_LC_RECONFIG_NOW)); 570 571 /* wait for lane set to complete */ 572 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 573 while (link_width_cntl == 0xffffffff) 574 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 575 576 } 577 578 #if defined(CONFIG_DEBUG_FS) 579 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) 580 { 581 struct drm_info_node *node = (struct drm_info_node *) m->private; 582 struct drm_device *dev = node->minor->dev; 583 struct radeon_device *rdev = dev->dev_private; 584 uint32_t tmp; 585 586 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 587 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); 588 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); 589 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); 590 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); 591 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); 592 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); 593 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); 594 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); 595 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); 596 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); 597 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); 598 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); 599 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); 600 return 0; 601 } 602 603 static struct drm_info_list rv370_pcie_gart_info_list[] = { 604 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL}, 605 }; 606 #endif 607 608 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 609 { 610 #if defined(CONFIG_DEBUG_FS) 611 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); 612 #else 613 return 0; 614 #endif 615 } 616 617 static int r300_packet0_check(struct radeon_cs_parser *p, 618 struct radeon_cs_packet *pkt, 619 unsigned idx, unsigned reg) 620 { 621 struct radeon_cs_reloc *reloc; 622 struct r100_cs_track *track; 623 volatile uint32_t *ib; 624 uint32_t tmp, tile_flags = 0; 625 unsigned i; 626 int r; 627 u32 idx_value; 628 629 ib = p->ib->ptr; 630 track = (struct r100_cs_track *)p->track; 631 idx_value = radeon_get_ib_value(p, idx); 632 633 switch(reg) { 634 case AVIVO_D1MODE_VLINE_START_END: 635 case RADEON_CRTC_GUI_TRIG_VLINE: 636 r = r100_cs_packet_parse_vline(p); 637 if (r) { 638 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 639 idx, reg); 640 r100_cs_dump_packet(p, pkt); 641 return r; 642 } 643 break; 644 case RADEON_DST_PITCH_OFFSET: 645 case RADEON_SRC_PITCH_OFFSET: 646 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 647 if (r) 648 return r; 649 break; 650 case R300_RB3D_COLOROFFSET0: 651 case R300_RB3D_COLOROFFSET1: 652 case R300_RB3D_COLOROFFSET2: 653 case R300_RB3D_COLOROFFSET3: 654 i = (reg - R300_RB3D_COLOROFFSET0) >> 2; 655 r = r100_cs_packet_next_reloc(p, &reloc); 656 if (r) { 657 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 658 idx, reg); 659 r100_cs_dump_packet(p, pkt); 660 return r; 661 } 662 track->cb[i].robj = reloc->robj; 663 track->cb[i].offset = idx_value; 664 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 665 break; 666 case R300_ZB_DEPTHOFFSET: 667 r = r100_cs_packet_next_reloc(p, &reloc); 668 if (r) { 669 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 670 idx, reg); 671 r100_cs_dump_packet(p, pkt); 672 return r; 673 } 674 track->zb.robj = reloc->robj; 675 track->zb.offset = idx_value; 676 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 677 break; 678 case R300_TX_OFFSET_0: 679 case R300_TX_OFFSET_0+4: 680 case R300_TX_OFFSET_0+8: 681 case R300_TX_OFFSET_0+12: 682 case R300_TX_OFFSET_0+16: 683 case R300_TX_OFFSET_0+20: 684 case R300_TX_OFFSET_0+24: 685 case R300_TX_OFFSET_0+28: 686 case R300_TX_OFFSET_0+32: 687 case R300_TX_OFFSET_0+36: 688 case R300_TX_OFFSET_0+40: 689 case R300_TX_OFFSET_0+44: 690 case R300_TX_OFFSET_0+48: 691 case R300_TX_OFFSET_0+52: 692 case R300_TX_OFFSET_0+56: 693 case R300_TX_OFFSET_0+60: 694 i = (reg - R300_TX_OFFSET_0) >> 2; 695 r = r100_cs_packet_next_reloc(p, &reloc); 696 if (r) { 697 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 698 idx, reg); 699 r100_cs_dump_packet(p, pkt); 700 return r; 701 } 702 703 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 704 tile_flags |= R300_TXO_MACRO_TILE; 705 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 706 tile_flags |= R300_TXO_MICRO_TILE; 707 708 tmp = idx_value + ((u32)reloc->lobj.gpu_offset); 709 tmp |= tile_flags; 710 ib[idx] = tmp; 711 track->textures[i].robj = reloc->robj; 712 break; 713 /* Tracked registers */ 714 case 0x2084: 715 /* VAP_VF_CNTL */ 716 track->vap_vf_cntl = idx_value; 717 break; 718 case 0x20B4: 719 /* VAP_VTX_SIZE */ 720 track->vtx_size = idx_value & 0x7F; 721 break; 722 case 0x2134: 723 /* VAP_VF_MAX_VTX_INDX */ 724 track->max_indx = idx_value & 0x00FFFFFFUL; 725 break; 726 case 0x43E4: 727 /* SC_SCISSOR1 */ 728 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; 729 if (p->rdev->family < CHIP_RV515) { 730 track->maxy -= 1440; 731 } 732 break; 733 case 0x4E00: 734 /* RB3D_CCTL */ 735 track->num_cb = ((idx_value >> 5) & 0x3) + 1; 736 break; 737 case 0x4E38: 738 case 0x4E3C: 739 case 0x4E40: 740 case 0x4E44: 741 /* RB3D_COLORPITCH0 */ 742 /* RB3D_COLORPITCH1 */ 743 /* RB3D_COLORPITCH2 */ 744 /* RB3D_COLORPITCH3 */ 745 r = r100_cs_packet_next_reloc(p, &reloc); 746 if (r) { 747 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 748 idx, reg); 749 r100_cs_dump_packet(p, pkt); 750 return r; 751 } 752 753 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 754 tile_flags |= R300_COLOR_TILE_ENABLE; 755 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 756 tile_flags |= R300_COLOR_MICROTILE_ENABLE; 757 758 tmp = idx_value & ~(0x7 << 16); 759 tmp |= tile_flags; 760 ib[idx] = tmp; 761 762 i = (reg - 0x4E38) >> 2; 763 track->cb[i].pitch = idx_value & 0x3FFE; 764 switch (((idx_value >> 21) & 0xF)) { 765 case 9: 766 case 11: 767 case 12: 768 track->cb[i].cpp = 1; 769 break; 770 case 3: 771 case 4: 772 case 13: 773 case 15: 774 track->cb[i].cpp = 2; 775 break; 776 case 6: 777 track->cb[i].cpp = 4; 778 break; 779 case 10: 780 track->cb[i].cpp = 8; 781 break; 782 case 7: 783 track->cb[i].cpp = 16; 784 break; 785 default: 786 DRM_ERROR("Invalid color buffer format (%d) !\n", 787 ((idx_value >> 21) & 0xF)); 788 return -EINVAL; 789 } 790 break; 791 case 0x4F00: 792 /* ZB_CNTL */ 793 if (idx_value & 2) { 794 track->z_enabled = true; 795 } else { 796 track->z_enabled = false; 797 } 798 break; 799 case 0x4F10: 800 /* ZB_FORMAT */ 801 switch ((idx_value & 0xF)) { 802 case 0: 803 case 1: 804 track->zb.cpp = 2; 805 break; 806 case 2: 807 track->zb.cpp = 4; 808 break; 809 default: 810 DRM_ERROR("Invalid z buffer format (%d) !\n", 811 (idx_value & 0xF)); 812 return -EINVAL; 813 } 814 break; 815 case 0x4F24: 816 /* ZB_DEPTHPITCH */ 817 r = r100_cs_packet_next_reloc(p, &reloc); 818 if (r) { 819 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 820 idx, reg); 821 r100_cs_dump_packet(p, pkt); 822 return r; 823 } 824 825 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 826 tile_flags |= R300_DEPTHMACROTILE_ENABLE; 827 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 828 tile_flags |= R300_DEPTHMICROTILE_TILED;; 829 830 tmp = idx_value & ~(0x7 << 16); 831 tmp |= tile_flags; 832 ib[idx] = tmp; 833 834 track->zb.pitch = idx_value & 0x3FFC; 835 break; 836 case 0x4104: 837 for (i = 0; i < 16; i++) { 838 bool enabled; 839 840 enabled = !!(idx_value & (1 << i)); 841 track->textures[i].enabled = enabled; 842 } 843 break; 844 case 0x44C0: 845 case 0x44C4: 846 case 0x44C8: 847 case 0x44CC: 848 case 0x44D0: 849 case 0x44D4: 850 case 0x44D8: 851 case 0x44DC: 852 case 0x44E0: 853 case 0x44E4: 854 case 0x44E8: 855 case 0x44EC: 856 case 0x44F0: 857 case 0x44F4: 858 case 0x44F8: 859 case 0x44FC: 860 /* TX_FORMAT1_[0-15] */ 861 i = (reg - 0x44C0) >> 2; 862 tmp = (idx_value >> 25) & 0x3; 863 track->textures[i].tex_coord_type = tmp; 864 switch ((idx_value & 0x1F)) { 865 case R300_TX_FORMAT_X8: 866 case R300_TX_FORMAT_Y4X4: 867 case R300_TX_FORMAT_Z3Y3X2: 868 track->textures[i].cpp = 1; 869 break; 870 case R300_TX_FORMAT_X16: 871 case R300_TX_FORMAT_Y8X8: 872 case R300_TX_FORMAT_Z5Y6X5: 873 case R300_TX_FORMAT_Z6Y5X5: 874 case R300_TX_FORMAT_W4Z4Y4X4: 875 case R300_TX_FORMAT_W1Z5Y5X5: 876 case R300_TX_FORMAT_D3DMFT_CxV8U8: 877 case R300_TX_FORMAT_B8G8_B8G8: 878 case R300_TX_FORMAT_G8R8_G8B8: 879 track->textures[i].cpp = 2; 880 break; 881 case R300_TX_FORMAT_Y16X16: 882 case R300_TX_FORMAT_Z11Y11X10: 883 case R300_TX_FORMAT_Z10Y11X11: 884 case R300_TX_FORMAT_W8Z8Y8X8: 885 case R300_TX_FORMAT_W2Z10Y10X10: 886 case 0x17: 887 case R300_TX_FORMAT_FL_I32: 888 case 0x1e: 889 track->textures[i].cpp = 4; 890 break; 891 case R300_TX_FORMAT_W16Z16Y16X16: 892 case R300_TX_FORMAT_FL_R16G16B16A16: 893 case R300_TX_FORMAT_FL_I32A32: 894 track->textures[i].cpp = 8; 895 break; 896 case R300_TX_FORMAT_FL_R32G32B32A32: 897 track->textures[i].cpp = 16; 898 break; 899 case R300_TX_FORMAT_DXT1: 900 track->textures[i].cpp = 1; 901 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 902 break; 903 case R300_TX_FORMAT_ATI2N: 904 if (p->rdev->family < CHIP_R420) { 905 DRM_ERROR("Invalid texture format %u\n", 906 (idx_value & 0x1F)); 907 return -EINVAL; 908 } 909 /* The same rules apply as for DXT3/5. */ 910 /* Pass through. */ 911 case R300_TX_FORMAT_DXT3: 912 case R300_TX_FORMAT_DXT5: 913 track->textures[i].cpp = 1; 914 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 915 break; 916 default: 917 DRM_ERROR("Invalid texture format %u\n", 918 (idx_value & 0x1F)); 919 return -EINVAL; 920 break; 921 } 922 break; 923 case 0x4400: 924 case 0x4404: 925 case 0x4408: 926 case 0x440C: 927 case 0x4410: 928 case 0x4414: 929 case 0x4418: 930 case 0x441C: 931 case 0x4420: 932 case 0x4424: 933 case 0x4428: 934 case 0x442C: 935 case 0x4430: 936 case 0x4434: 937 case 0x4438: 938 case 0x443C: 939 /* TX_FILTER0_[0-15] */ 940 i = (reg - 0x4400) >> 2; 941 tmp = idx_value & 0x7; 942 if (tmp == 2 || tmp == 4 || tmp == 6) { 943 track->textures[i].roundup_w = false; 944 } 945 tmp = (idx_value >> 3) & 0x7; 946 if (tmp == 2 || tmp == 4 || tmp == 6) { 947 track->textures[i].roundup_h = false; 948 } 949 break; 950 case 0x4500: 951 case 0x4504: 952 case 0x4508: 953 case 0x450C: 954 case 0x4510: 955 case 0x4514: 956 case 0x4518: 957 case 0x451C: 958 case 0x4520: 959 case 0x4524: 960 case 0x4528: 961 case 0x452C: 962 case 0x4530: 963 case 0x4534: 964 case 0x4538: 965 case 0x453C: 966 /* TX_FORMAT2_[0-15] */ 967 i = (reg - 0x4500) >> 2; 968 tmp = idx_value & 0x3FFF; 969 track->textures[i].pitch = tmp + 1; 970 if (p->rdev->family >= CHIP_RV515) { 971 tmp = ((idx_value >> 15) & 1) << 11; 972 track->textures[i].width_11 = tmp; 973 tmp = ((idx_value >> 16) & 1) << 11; 974 track->textures[i].height_11 = tmp; 975 976 /* ATI1N */ 977 if (idx_value & (1 << 14)) { 978 /* The same rules apply as for DXT1. */ 979 track->textures[i].compress_format = 980 R100_TRACK_COMP_DXT1; 981 } 982 } else if (idx_value & (1 << 14)) { 983 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); 984 return -EINVAL; 985 } 986 break; 987 case 0x4480: 988 case 0x4484: 989 case 0x4488: 990 case 0x448C: 991 case 0x4490: 992 case 0x4494: 993 case 0x4498: 994 case 0x449C: 995 case 0x44A0: 996 case 0x44A4: 997 case 0x44A8: 998 case 0x44AC: 999 case 0x44B0: 1000 case 0x44B4: 1001 case 0x44B8: 1002 case 0x44BC: 1003 /* TX_FORMAT0_[0-15] */ 1004 i = (reg - 0x4480) >> 2; 1005 tmp = idx_value & 0x7FF; 1006 track->textures[i].width = tmp + 1; 1007 tmp = (idx_value >> 11) & 0x7FF; 1008 track->textures[i].height = tmp + 1; 1009 tmp = (idx_value >> 26) & 0xF; 1010 track->textures[i].num_levels = tmp; 1011 tmp = idx_value & (1 << 31); 1012 track->textures[i].use_pitch = !!tmp; 1013 tmp = (idx_value >> 22) & 0xF; 1014 track->textures[i].txdepth = tmp; 1015 break; 1016 case R300_ZB_ZPASS_ADDR: 1017 r = r100_cs_packet_next_reloc(p, &reloc); 1018 if (r) { 1019 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1020 idx, reg); 1021 r100_cs_dump_packet(p, pkt); 1022 return r; 1023 } 1024 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1025 break; 1026 case 0x4e0c: 1027 /* RB3D_COLOR_CHANNEL_MASK */ 1028 track->color_channel_mask = idx_value; 1029 break; 1030 case 0x4d1c: 1031 /* ZB_BW_CNTL */ 1032 track->fastfill = !!(idx_value & (1 << 2)); 1033 break; 1034 case 0x4e04: 1035 /* RB3D_BLENDCNTL */ 1036 track->blend_read_enable = !!(idx_value & (1 << 2)); 1037 break; 1038 case 0x4be8: 1039 /* valid register only on RV530 */ 1040 if (p->rdev->family == CHIP_RV530) 1041 break; 1042 /* fallthrough do not move */ 1043 default: 1044 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", 1045 reg, idx); 1046 return -EINVAL; 1047 } 1048 return 0; 1049 } 1050 1051 static int r300_packet3_check(struct radeon_cs_parser *p, 1052 struct radeon_cs_packet *pkt) 1053 { 1054 struct radeon_cs_reloc *reloc; 1055 struct r100_cs_track *track; 1056 volatile uint32_t *ib; 1057 unsigned idx; 1058 int r; 1059 1060 ib = p->ib->ptr; 1061 idx = pkt->idx + 1; 1062 track = (struct r100_cs_track *)p->track; 1063 switch(pkt->opcode) { 1064 case PACKET3_3D_LOAD_VBPNTR: 1065 r = r100_packet3_load_vbpntr(p, pkt, idx); 1066 if (r) 1067 return r; 1068 break; 1069 case PACKET3_INDX_BUFFER: 1070 r = r100_cs_packet_next_reloc(p, &reloc); 1071 if (r) { 1072 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1073 r100_cs_dump_packet(p, pkt); 1074 return r; 1075 } 1076 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 1077 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1078 if (r) { 1079 return r; 1080 } 1081 break; 1082 /* Draw packet */ 1083 case PACKET3_3D_DRAW_IMMD: 1084 /* Number of dwords is vtx_size * (num_vertices - 1) 1085 * PRIM_WALK must be equal to 3 vertex data in embedded 1086 * in cmd stream */ 1087 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1088 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1089 return -EINVAL; 1090 } 1091 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1092 track->immd_dwords = pkt->count - 1; 1093 r = r100_cs_track_check(p->rdev, track); 1094 if (r) { 1095 return r; 1096 } 1097 break; 1098 case PACKET3_3D_DRAW_IMMD_2: 1099 /* Number of dwords is vtx_size * (num_vertices - 1) 1100 * PRIM_WALK must be equal to 3 vertex data in embedded 1101 * in cmd stream */ 1102 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1103 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1104 return -EINVAL; 1105 } 1106 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1107 track->immd_dwords = pkt->count; 1108 r = r100_cs_track_check(p->rdev, track); 1109 if (r) { 1110 return r; 1111 } 1112 break; 1113 case PACKET3_3D_DRAW_VBUF: 1114 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1115 r = r100_cs_track_check(p->rdev, track); 1116 if (r) { 1117 return r; 1118 } 1119 break; 1120 case PACKET3_3D_DRAW_VBUF_2: 1121 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1122 r = r100_cs_track_check(p->rdev, track); 1123 if (r) { 1124 return r; 1125 } 1126 break; 1127 case PACKET3_3D_DRAW_INDX: 1128 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1129 r = r100_cs_track_check(p->rdev, track); 1130 if (r) { 1131 return r; 1132 } 1133 break; 1134 case PACKET3_3D_DRAW_INDX_2: 1135 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1136 r = r100_cs_track_check(p->rdev, track); 1137 if (r) { 1138 return r; 1139 } 1140 break; 1141 case PACKET3_NOP: 1142 break; 1143 default: 1144 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 1145 return -EINVAL; 1146 } 1147 return 0; 1148 } 1149 1150 int r300_cs_parse(struct radeon_cs_parser *p) 1151 { 1152 struct radeon_cs_packet pkt; 1153 struct r100_cs_track *track; 1154 int r; 1155 1156 track = kzalloc(sizeof(*track), GFP_KERNEL); 1157 r100_cs_track_clear(p->rdev, track); 1158 p->track = track; 1159 do { 1160 r = r100_cs_packet_parse(p, &pkt, p->idx); 1161 if (r) { 1162 return r; 1163 } 1164 p->idx += pkt.count + 2; 1165 switch (pkt.type) { 1166 case PACKET_TYPE0: 1167 r = r100_cs_parse_packet0(p, &pkt, 1168 p->rdev->config.r300.reg_safe_bm, 1169 p->rdev->config.r300.reg_safe_bm_size, 1170 &r300_packet0_check); 1171 break; 1172 case PACKET_TYPE2: 1173 break; 1174 case PACKET_TYPE3: 1175 r = r300_packet3_check(p, &pkt); 1176 break; 1177 default: 1178 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 1179 return -EINVAL; 1180 } 1181 if (r) { 1182 return r; 1183 } 1184 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 1185 return 0; 1186 } 1187 1188 void r300_set_reg_safe(struct radeon_device *rdev) 1189 { 1190 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; 1191 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); 1192 } 1193 1194 void r300_mc_program(struct radeon_device *rdev) 1195 { 1196 struct r100_mc_save save; 1197 int r; 1198 1199 r = r100_debugfs_mc_info_init(rdev); 1200 if (r) { 1201 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 1202 } 1203 1204 /* Stops all mc clients */ 1205 r100_mc_stop(rdev, &save); 1206 if (rdev->flags & RADEON_IS_AGP) { 1207 WREG32(R_00014C_MC_AGP_LOCATION, 1208 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 1209 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 1210 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 1211 WREG32(R_00015C_AGP_BASE_2, 1212 upper_32_bits(rdev->mc.agp_base) & 0xff); 1213 } else { 1214 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 1215 WREG32(R_000170_AGP_BASE, 0); 1216 WREG32(R_00015C_AGP_BASE_2, 0); 1217 } 1218 /* Wait for mc idle */ 1219 if (r300_mc_wait_for_idle(rdev)) 1220 DRM_INFO("Failed to wait MC idle before programming MC.\n"); 1221 /* Program MC, should be a 32bits limited address space */ 1222 WREG32(R_000148_MC_FB_LOCATION, 1223 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 1224 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 1225 r100_mc_resume(rdev, &save); 1226 } 1227 1228 void r300_clock_startup(struct radeon_device *rdev) 1229 { 1230 u32 tmp; 1231 1232 if (radeon_dynclks != -1 && radeon_dynclks) 1233 radeon_legacy_set_clock_gating(rdev, 1); 1234 /* We need to force on some of the block */ 1235 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 1236 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 1237 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380)) 1238 tmp |= S_00000D_FORCE_VAP(1); 1239 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 1240 } 1241 1242 static int r300_startup(struct radeon_device *rdev) 1243 { 1244 int r; 1245 1246 /* set common regs */ 1247 r100_set_common_regs(rdev); 1248 /* program mc */ 1249 r300_mc_program(rdev); 1250 /* Resume clock */ 1251 r300_clock_startup(rdev); 1252 /* Initialize GPU configuration (# pipes, ...) */ 1253 r300_gpu_init(rdev); 1254 /* Initialize GART (initialize after TTM so we can allocate 1255 * memory through TTM but finalize after TTM) */ 1256 if (rdev->flags & RADEON_IS_PCIE) { 1257 r = rv370_pcie_gart_enable(rdev); 1258 if (r) 1259 return r; 1260 } 1261 1262 if (rdev->family == CHIP_R300 || 1263 rdev->family == CHIP_R350 || 1264 rdev->family == CHIP_RV350) 1265 r100_enable_bm(rdev); 1266 1267 if (rdev->flags & RADEON_IS_PCI) { 1268 r = r100_pci_gart_enable(rdev); 1269 if (r) 1270 return r; 1271 } 1272 /* Enable IRQ */ 1273 r100_irq_set(rdev); 1274 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 1275 /* 1M ring buffer */ 1276 r = r100_cp_init(rdev, 1024 * 1024); 1277 if (r) { 1278 dev_err(rdev->dev, "failled initializing CP (%d).\n", r); 1279 return r; 1280 } 1281 r = r100_wb_init(rdev); 1282 if (r) 1283 dev_err(rdev->dev, "failled initializing WB (%d).\n", r); 1284 r = r100_ib_init(rdev); 1285 if (r) { 1286 dev_err(rdev->dev, "failled initializing IB (%d).\n", r); 1287 return r; 1288 } 1289 return 0; 1290 } 1291 1292 int r300_resume(struct radeon_device *rdev) 1293 { 1294 /* Make sur GART are not working */ 1295 if (rdev->flags & RADEON_IS_PCIE) 1296 rv370_pcie_gart_disable(rdev); 1297 if (rdev->flags & RADEON_IS_PCI) 1298 r100_pci_gart_disable(rdev); 1299 /* Resume clock before doing reset */ 1300 r300_clock_startup(rdev); 1301 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1302 if (radeon_gpu_reset(rdev)) { 1303 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1304 RREG32(R_000E40_RBBM_STATUS), 1305 RREG32(R_0007C0_CP_STAT)); 1306 } 1307 /* post */ 1308 radeon_combios_asic_init(rdev->ddev); 1309 /* Resume clock after posting */ 1310 r300_clock_startup(rdev); 1311 /* Initialize surface registers */ 1312 radeon_surface_init(rdev); 1313 return r300_startup(rdev); 1314 } 1315 1316 int r300_suspend(struct radeon_device *rdev) 1317 { 1318 r100_cp_disable(rdev); 1319 r100_wb_disable(rdev); 1320 r100_irq_disable(rdev); 1321 if (rdev->flags & RADEON_IS_PCIE) 1322 rv370_pcie_gart_disable(rdev); 1323 if (rdev->flags & RADEON_IS_PCI) 1324 r100_pci_gart_disable(rdev); 1325 return 0; 1326 } 1327 1328 void r300_fini(struct radeon_device *rdev) 1329 { 1330 r300_suspend(rdev); 1331 r100_cp_fini(rdev); 1332 r100_wb_fini(rdev); 1333 r100_ib_fini(rdev); 1334 radeon_gem_fini(rdev); 1335 if (rdev->flags & RADEON_IS_PCIE) 1336 rv370_pcie_gart_fini(rdev); 1337 if (rdev->flags & RADEON_IS_PCI) 1338 r100_pci_gart_fini(rdev); 1339 radeon_agp_fini(rdev); 1340 radeon_irq_kms_fini(rdev); 1341 radeon_fence_driver_fini(rdev); 1342 radeon_bo_fini(rdev); 1343 radeon_atombios_fini(rdev); 1344 kfree(rdev->bios); 1345 rdev->bios = NULL; 1346 } 1347 1348 int r300_init(struct radeon_device *rdev) 1349 { 1350 int r; 1351 1352 /* Disable VGA */ 1353 r100_vga_render_disable(rdev); 1354 /* Initialize scratch registers */ 1355 radeon_scratch_init(rdev); 1356 /* Initialize surface registers */ 1357 radeon_surface_init(rdev); 1358 /* TODO: disable VGA need to use VGA request */ 1359 /* BIOS*/ 1360 if (!radeon_get_bios(rdev)) { 1361 if (ASIC_IS_AVIVO(rdev)) 1362 return -EINVAL; 1363 } 1364 if (rdev->is_atom_bios) { 1365 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 1366 return -EINVAL; 1367 } else { 1368 r = radeon_combios_init(rdev); 1369 if (r) 1370 return r; 1371 } 1372 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1373 if (radeon_gpu_reset(rdev)) { 1374 dev_warn(rdev->dev, 1375 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1376 RREG32(R_000E40_RBBM_STATUS), 1377 RREG32(R_0007C0_CP_STAT)); 1378 } 1379 /* check if cards are posted or not */ 1380 if (radeon_boot_test_post_card(rdev) == false) 1381 return -EINVAL; 1382 /* Set asic errata */ 1383 r300_errata(rdev); 1384 /* Initialize clocks */ 1385 radeon_get_clock_info(rdev->ddev); 1386 /* Initialize power management */ 1387 radeon_pm_init(rdev); 1388 /* Get vram informations */ 1389 r300_vram_info(rdev); 1390 /* Initialize memory controller (also test AGP) */ 1391 r = r420_mc_init(rdev); 1392 if (r) 1393 return r; 1394 /* Fence driver */ 1395 r = radeon_fence_driver_init(rdev); 1396 if (r) 1397 return r; 1398 r = radeon_irq_kms_init(rdev); 1399 if (r) 1400 return r; 1401 /* Memory manager */ 1402 r = radeon_bo_init(rdev); 1403 if (r) 1404 return r; 1405 if (rdev->flags & RADEON_IS_PCIE) { 1406 r = rv370_pcie_gart_init(rdev); 1407 if (r) 1408 return r; 1409 } 1410 if (rdev->flags & RADEON_IS_PCI) { 1411 r = r100_pci_gart_init(rdev); 1412 if (r) 1413 return r; 1414 } 1415 r300_set_reg_safe(rdev); 1416 rdev->accel_working = true; 1417 r = r300_startup(rdev); 1418 if (r) { 1419 /* Somethings want wront with the accel init stop accel */ 1420 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 1421 r300_suspend(rdev); 1422 r100_cp_fini(rdev); 1423 r100_wb_fini(rdev); 1424 r100_ib_fini(rdev); 1425 if (rdev->flags & RADEON_IS_PCIE) 1426 rv370_pcie_gart_fini(rdev); 1427 if (rdev->flags & RADEON_IS_PCI) 1428 r100_pci_gart_fini(rdev); 1429 radeon_irq_kms_fini(rdev); 1430 rdev->accel_working = false; 1431 } 1432 return 0; 1433 } 1434