1 2 #define R100_TRACK_MAX_TEXTURE 3 3 #define R200_TRACK_MAX_TEXTURE 6 4 #define R300_TRACK_MAX_TEXTURE 16 5 6 #define R100_MAX_CB 1 7 #define R300_MAX_CB 4 8 9 /* 10 * CS functions 11 */ 12 struct r100_cs_track_cb { 13 struct radeon_bo *robj; 14 unsigned pitch; 15 unsigned cpp; 16 unsigned offset; 17 }; 18 19 struct r100_cs_track_array { 20 struct radeon_bo *robj; 21 unsigned esize; 22 }; 23 24 struct r100_cs_cube_info { 25 struct radeon_bo *robj; 26 unsigned offset; 27 unsigned width; 28 unsigned height; 29 }; 30 31 #define R100_TRACK_COMP_NONE 0 32 #define R100_TRACK_COMP_DXT1 1 33 #define R100_TRACK_COMP_DXT35 2 34 35 struct r100_cs_track_texture { 36 struct radeon_bo *robj; 37 struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */ 38 unsigned pitch; 39 unsigned width; 40 unsigned height; 41 unsigned num_levels; 42 unsigned cpp; 43 unsigned tex_coord_type; 44 unsigned txdepth; 45 unsigned width_11; 46 unsigned height_11; 47 bool use_pitch; 48 bool enabled; 49 bool roundup_w; 50 bool roundup_h; 51 unsigned compress_format; 52 }; 53 54 struct r100_cs_track_limits { 55 unsigned num_cb; 56 unsigned num_texture; 57 unsigned max_levels; 58 }; 59 60 struct r100_cs_track { 61 struct radeon_device *rdev; 62 unsigned num_cb; 63 unsigned num_texture; 64 unsigned maxy; 65 unsigned vtx_size; 66 unsigned vap_vf_cntl; 67 unsigned immd_dwords; 68 unsigned num_arrays; 69 unsigned max_indx; 70 unsigned color_channel_mask; 71 struct r100_cs_track_array arrays[11]; 72 struct r100_cs_track_cb cb[R300_MAX_CB]; 73 struct r100_cs_track_cb zb; 74 struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE]; 75 bool z_enabled; 76 bool separate_cube; 77 bool fastfill; 78 bool blend_read_enable; 79 }; 80 81 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track); 82 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track); 83 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, 84 struct radeon_cs_reloc **cs_reloc); 85 void r100_cs_dump_packet(struct radeon_cs_parser *p, 86 struct radeon_cs_packet *pkt); 87 88 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p); 89 90 int r200_packet0_check(struct radeon_cs_parser *p, 91 struct radeon_cs_packet *pkt, 92 unsigned idx, unsigned reg); 93 94 95 96 static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p, 97 struct radeon_cs_packet *pkt, 98 unsigned idx, 99 unsigned reg) 100 { 101 int r; 102 u32 tile_flags = 0; 103 u32 tmp; 104 struct radeon_cs_reloc *reloc; 105 u32 value; 106 107 r = r100_cs_packet_next_reloc(p, &reloc); 108 if (r) { 109 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 110 idx, reg); 111 r100_cs_dump_packet(p, pkt); 112 return r; 113 } 114 value = radeon_get_ib_value(p, idx); 115 tmp = value & 0x003fffff; 116 tmp += (((u32)reloc->lobj.gpu_offset) >> 10); 117 118 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 119 tile_flags |= RADEON_DST_TILE_MACRO; 120 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { 121 if (reg == RADEON_SRC_PITCH_OFFSET) { 122 DRM_ERROR("Cannot src blit from microtiled surface\n"); 123 r100_cs_dump_packet(p, pkt); 124 return -EINVAL; 125 } 126 tile_flags |= RADEON_DST_TILE_MICRO; 127 } 128 129 tmp |= tile_flags; 130 p->ib->ptr[idx] = (value & 0x3fc00000) | tmp; 131 return 0; 132 } 133 134 static inline int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, 135 struct radeon_cs_packet *pkt, 136 int idx) 137 { 138 unsigned c, i; 139 struct radeon_cs_reloc *reloc; 140 struct r100_cs_track *track; 141 int r = 0; 142 volatile uint32_t *ib; 143 u32 idx_value; 144 145 ib = p->ib->ptr; 146 track = (struct r100_cs_track *)p->track; 147 c = radeon_get_ib_value(p, idx++) & 0x1F; 148 track->num_arrays = c; 149 for (i = 0; i < (c - 1); i+=2, idx+=3) { 150 r = r100_cs_packet_next_reloc(p, &reloc); 151 if (r) { 152 DRM_ERROR("No reloc for packet3 %d\n", 153 pkt->opcode); 154 r100_cs_dump_packet(p, pkt); 155 return r; 156 } 157 idx_value = radeon_get_ib_value(p, idx); 158 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 159 160 track->arrays[i + 0].esize = idx_value >> 8; 161 track->arrays[i + 0].robj = reloc->robj; 162 track->arrays[i + 0].esize &= 0x7F; 163 r = r100_cs_packet_next_reloc(p, &reloc); 164 if (r) { 165 DRM_ERROR("No reloc for packet3 %d\n", 166 pkt->opcode); 167 r100_cs_dump_packet(p, pkt); 168 return r; 169 } 170 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset); 171 track->arrays[i + 1].robj = reloc->robj; 172 track->arrays[i + 1].esize = idx_value >> 24; 173 track->arrays[i + 1].esize &= 0x7F; 174 } 175 if (c & 1) { 176 r = r100_cs_packet_next_reloc(p, &reloc); 177 if (r) { 178 DRM_ERROR("No reloc for packet3 %d\n", 179 pkt->opcode); 180 r100_cs_dump_packet(p, pkt); 181 return r; 182 } 183 idx_value = radeon_get_ib_value(p, idx); 184 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 185 track->arrays[i + 0].robj = reloc->robj; 186 track->arrays[i + 0].esize = idx_value >> 8; 187 track->arrays[i + 0].esize &= 0x7F; 188 } 189 return r; 190 } 191