1 2 #define R100_TRACK_MAX_TEXTURE 3 3 #define R200_TRACK_MAX_TEXTURE 6 4 #define R300_TRACK_MAX_TEXTURE 16 5 6 #define R100_MAX_CB 1 7 #define R300_MAX_CB 4 8 9 /* 10 * CS functions 11 */ 12 struct r100_cs_track_cb { 13 struct radeon_object *robj; 14 unsigned pitch; 15 unsigned cpp; 16 unsigned offset; 17 }; 18 19 struct r100_cs_track_array { 20 struct radeon_object *robj; 21 unsigned esize; 22 }; 23 24 struct r100_cs_cube_info { 25 struct radeon_object *robj; 26 unsigned offset; 27 unsigned width; 28 unsigned height; 29 }; 30 31 struct r100_cs_track_texture { 32 struct radeon_object *robj; 33 struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */ 34 unsigned pitch; 35 unsigned width; 36 unsigned height; 37 unsigned num_levels; 38 unsigned cpp; 39 unsigned tex_coord_type; 40 unsigned txdepth; 41 unsigned width_11; 42 unsigned height_11; 43 bool use_pitch; 44 bool enabled; 45 bool roundup_w; 46 bool roundup_h; 47 }; 48 49 struct r100_cs_track_limits { 50 unsigned num_cb; 51 unsigned num_texture; 52 unsigned max_levels; 53 }; 54 55 struct r100_cs_track { 56 struct radeon_device *rdev; 57 unsigned num_cb; 58 unsigned num_texture; 59 unsigned maxy; 60 unsigned vtx_size; 61 unsigned vap_vf_cntl; 62 unsigned immd_dwords; 63 unsigned num_arrays; 64 unsigned max_indx; 65 struct r100_cs_track_array arrays[11]; 66 struct r100_cs_track_cb cb[R300_MAX_CB]; 67 struct r100_cs_track_cb zb; 68 struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE]; 69 bool z_enabled; 70 bool separate_cube; 71 72 }; 73 74 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track); 75 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track); 76 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, 77 struct radeon_cs_reloc **cs_reloc); 78 void r100_cs_dump_packet(struct radeon_cs_parser *p, 79 struct radeon_cs_packet *pkt); 80 81 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p); 82 83 int r200_packet0_check(struct radeon_cs_parser *p, 84 struct radeon_cs_packet *pkt, 85 unsigned idx, unsigned reg); 86 87 static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p, 88 struct radeon_cs_packet *pkt, 89 unsigned idx, 90 unsigned reg) 91 { 92 int r; 93 u32 tile_flags = 0; 94 u32 tmp; 95 struct radeon_cs_reloc *reloc; 96 struct radeon_cs_chunk *ib_chunk; 97 98 ib_chunk = &p->chunks[p->chunk_ib_idx]; 99 100 r = r100_cs_packet_next_reloc(p, &reloc); 101 if (r) { 102 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 103 idx, reg); 104 r100_cs_dump_packet(p, pkt); 105 return r; 106 } 107 tmp = ib_chunk->kdata[idx] & 0x003fffff; 108 tmp += (((u32)reloc->lobj.gpu_offset) >> 10); 109 110 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 111 tile_flags |= RADEON_DST_TILE_MACRO; 112 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { 113 if (reg == RADEON_SRC_PITCH_OFFSET) { 114 DRM_ERROR("Cannot src blit from microtiled surface\n"); 115 r100_cs_dump_packet(p, pkt); 116 return -EINVAL; 117 } 118 tile_flags |= RADEON_DST_TILE_MICRO; 119 } 120 121 tmp |= tile_flags; 122 p->ib->ptr[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp; 123 return 0; 124 } 125