1551ebd83SDave Airlie 2551ebd83SDave Airlie #define R100_TRACK_MAX_TEXTURE 3 3551ebd83SDave Airlie #define R200_TRACK_MAX_TEXTURE 6 4551ebd83SDave Airlie #define R300_TRACK_MAX_TEXTURE 16 5551ebd83SDave Airlie 6551ebd83SDave Airlie #define R100_MAX_CB 1 7551ebd83SDave Airlie #define R300_MAX_CB 4 8551ebd83SDave Airlie 9551ebd83SDave Airlie /* 10551ebd83SDave Airlie * CS functions 11551ebd83SDave Airlie */ 12551ebd83SDave Airlie struct r100_cs_track_cb { 13551ebd83SDave Airlie struct radeon_object *robj; 14551ebd83SDave Airlie unsigned pitch; 15551ebd83SDave Airlie unsigned cpp; 16551ebd83SDave Airlie unsigned offset; 17551ebd83SDave Airlie }; 18551ebd83SDave Airlie 19551ebd83SDave Airlie struct r100_cs_track_array { 20551ebd83SDave Airlie struct radeon_object *robj; 21551ebd83SDave Airlie unsigned esize; 22551ebd83SDave Airlie }; 23551ebd83SDave Airlie 24551ebd83SDave Airlie struct r100_cs_cube_info { 25551ebd83SDave Airlie struct radeon_object *robj; 26551ebd83SDave Airlie unsigned offset; 27551ebd83SDave Airlie unsigned width; 28551ebd83SDave Airlie unsigned height; 29551ebd83SDave Airlie }; 30551ebd83SDave Airlie 31551ebd83SDave Airlie struct r100_cs_track_texture { 32551ebd83SDave Airlie struct radeon_object *robj; 33551ebd83SDave Airlie struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */ 34551ebd83SDave Airlie unsigned pitch; 35551ebd83SDave Airlie unsigned width; 36551ebd83SDave Airlie unsigned height; 37551ebd83SDave Airlie unsigned num_levels; 38551ebd83SDave Airlie unsigned cpp; 39551ebd83SDave Airlie unsigned tex_coord_type; 40551ebd83SDave Airlie unsigned txdepth; 41551ebd83SDave Airlie unsigned width_11; 42551ebd83SDave Airlie unsigned height_11; 43551ebd83SDave Airlie bool use_pitch; 44551ebd83SDave Airlie bool enabled; 45551ebd83SDave Airlie bool roundup_w; 46551ebd83SDave Airlie bool roundup_h; 47551ebd83SDave Airlie }; 48551ebd83SDave Airlie 49551ebd83SDave Airlie struct r100_cs_track_limits { 50551ebd83SDave Airlie unsigned num_cb; 51551ebd83SDave Airlie unsigned num_texture; 52551ebd83SDave Airlie unsigned max_levels; 53551ebd83SDave Airlie }; 54551ebd83SDave Airlie 55551ebd83SDave Airlie struct r100_cs_track { 56551ebd83SDave Airlie struct radeon_device *rdev; 57551ebd83SDave Airlie unsigned num_cb; 58551ebd83SDave Airlie unsigned num_texture; 59551ebd83SDave Airlie unsigned maxy; 60551ebd83SDave Airlie unsigned vtx_size; 61551ebd83SDave Airlie unsigned vap_vf_cntl; 62551ebd83SDave Airlie unsigned immd_dwords; 63551ebd83SDave Airlie unsigned num_arrays; 64551ebd83SDave Airlie unsigned max_indx; 65551ebd83SDave Airlie struct r100_cs_track_array arrays[11]; 66551ebd83SDave Airlie struct r100_cs_track_cb cb[R300_MAX_CB]; 67551ebd83SDave Airlie struct r100_cs_track_cb zb; 68551ebd83SDave Airlie struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE]; 69551ebd83SDave Airlie bool z_enabled; 70551ebd83SDave Airlie bool separate_cube; 71551ebd83SDave Airlie 72551ebd83SDave Airlie }; 73551ebd83SDave Airlie 74551ebd83SDave Airlie int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track); 75551ebd83SDave Airlie void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track); 76551ebd83SDave Airlie int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, 77551ebd83SDave Airlie struct radeon_cs_reloc **cs_reloc); 78551ebd83SDave Airlie void r100_cs_dump_packet(struct radeon_cs_parser *p, 79551ebd83SDave Airlie struct radeon_cs_packet *pkt); 80551ebd83SDave Airlie 81551ebd83SDave Airlie int r100_cs_packet_parse_vline(struct radeon_cs_parser *p); 82551ebd83SDave Airlie 83551ebd83SDave Airlie int r200_packet0_check(struct radeon_cs_parser *p, 84551ebd83SDave Airlie struct radeon_cs_packet *pkt, 85551ebd83SDave Airlie unsigned idx, unsigned reg); 86551ebd83SDave Airlie 87551ebd83SDave Airlie static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p, 88551ebd83SDave Airlie struct radeon_cs_packet *pkt, 89551ebd83SDave Airlie unsigned idx, 90551ebd83SDave Airlie unsigned reg) 91551ebd83SDave Airlie { 92551ebd83SDave Airlie int r; 93551ebd83SDave Airlie u32 tile_flags = 0; 94551ebd83SDave Airlie u32 tmp; 95551ebd83SDave Airlie struct radeon_cs_reloc *reloc; 96551ebd83SDave Airlie struct radeon_cs_chunk *ib_chunk; 97551ebd83SDave Airlie 98551ebd83SDave Airlie ib_chunk = &p->chunks[p->chunk_ib_idx]; 99551ebd83SDave Airlie 100551ebd83SDave Airlie r = r100_cs_packet_next_reloc(p, &reloc); 101551ebd83SDave Airlie if (r) { 102551ebd83SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 103551ebd83SDave Airlie idx, reg); 104551ebd83SDave Airlie r100_cs_dump_packet(p, pkt); 105551ebd83SDave Airlie return r; 106551ebd83SDave Airlie } 107551ebd83SDave Airlie tmp = ib_chunk->kdata[idx] & 0x003fffff; 108551ebd83SDave Airlie tmp += (((u32)reloc->lobj.gpu_offset) >> 10); 109551ebd83SDave Airlie 110551ebd83SDave Airlie if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 111551ebd83SDave Airlie tile_flags |= RADEON_DST_TILE_MACRO; 112551ebd83SDave Airlie if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { 113551ebd83SDave Airlie if (reg == RADEON_SRC_PITCH_OFFSET) { 114551ebd83SDave Airlie DRM_ERROR("Cannot src blit from microtiled surface\n"); 115551ebd83SDave Airlie r100_cs_dump_packet(p, pkt); 116551ebd83SDave Airlie return -EINVAL; 117551ebd83SDave Airlie } 118551ebd83SDave Airlie tile_flags |= RADEON_DST_TILE_MICRO; 119551ebd83SDave Airlie } 120551ebd83SDave Airlie 121551ebd83SDave Airlie tmp |= tile_flags; 122551ebd83SDave Airlie p->ib->ptr[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp; 123551ebd83SDave Airlie return 0; 124551ebd83SDave Airlie } 125