1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include <linux/slab.h> 30 #include "drmP.h" 31 #include "drm.h" 32 #include "radeon_drm.h" 33 #include "radeon_reg.h" 34 #include "radeon.h" 35 #include "radeon_asic.h" 36 #include "r100d.h" 37 #include "rs100d.h" 38 #include "rv200d.h" 39 #include "rv250d.h" 40 #include "atom.h" 41 42 #include <linux/firmware.h> 43 #include <linux/platform_device.h> 44 45 #include "r100_reg_safe.h" 46 #include "rn50_reg_safe.h" 47 48 /* Firmware Names */ 49 #define FIRMWARE_R100 "radeon/R100_cp.bin" 50 #define FIRMWARE_R200 "radeon/R200_cp.bin" 51 #define FIRMWARE_R300 "radeon/R300_cp.bin" 52 #define FIRMWARE_R420 "radeon/R420_cp.bin" 53 #define FIRMWARE_RS690 "radeon/RS690_cp.bin" 54 #define FIRMWARE_RS600 "radeon/RS600_cp.bin" 55 #define FIRMWARE_R520 "radeon/R520_cp.bin" 56 57 MODULE_FIRMWARE(FIRMWARE_R100); 58 MODULE_FIRMWARE(FIRMWARE_R200); 59 MODULE_FIRMWARE(FIRMWARE_R300); 60 MODULE_FIRMWARE(FIRMWARE_R420); 61 MODULE_FIRMWARE(FIRMWARE_RS690); 62 MODULE_FIRMWARE(FIRMWARE_RS600); 63 MODULE_FIRMWARE(FIRMWARE_R520); 64 65 #include "r100_track.h" 66 67 /* This files gather functions specifics to: 68 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 69 */ 70 71 void r100_pre_page_flip(struct radeon_device *rdev, int crtc) 72 { 73 /* enable the pflip int */ 74 radeon_irq_kms_pflip_irq_get(rdev, crtc); 75 } 76 77 void r100_post_page_flip(struct radeon_device *rdev, int crtc) 78 { 79 /* disable the pflip int */ 80 radeon_irq_kms_pflip_irq_put(rdev, crtc); 81 } 82 83 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 84 { 85 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 86 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; 87 88 /* Lock the graphics update lock */ 89 /* update the scanout addresses */ 90 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 91 92 /* Wait for update_pending to go high. */ 93 while (!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)); 94 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 95 96 /* Unlock the lock, so double-buffering can take place inside vblank */ 97 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK; 98 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 99 100 /* Return current update_pending status: */ 101 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET; 102 } 103 104 void r100_pm_get_dynpm_state(struct radeon_device *rdev) 105 { 106 int i; 107 rdev->pm.dynpm_can_upclock = true; 108 rdev->pm.dynpm_can_downclock = true; 109 110 switch (rdev->pm.dynpm_planned_action) { 111 case DYNPM_ACTION_MINIMUM: 112 rdev->pm.requested_power_state_index = 0; 113 rdev->pm.dynpm_can_downclock = false; 114 break; 115 case DYNPM_ACTION_DOWNCLOCK: 116 if (rdev->pm.current_power_state_index == 0) { 117 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 118 rdev->pm.dynpm_can_downclock = false; 119 } else { 120 if (rdev->pm.active_crtc_count > 1) { 121 for (i = 0; i < rdev->pm.num_power_states; i++) { 122 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 123 continue; 124 else if (i >= rdev->pm.current_power_state_index) { 125 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 126 break; 127 } else { 128 rdev->pm.requested_power_state_index = i; 129 break; 130 } 131 } 132 } else 133 rdev->pm.requested_power_state_index = 134 rdev->pm.current_power_state_index - 1; 135 } 136 /* don't use the power state if crtcs are active and no display flag is set */ 137 if ((rdev->pm.active_crtc_count > 0) && 138 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & 139 RADEON_PM_MODE_NO_DISPLAY)) { 140 rdev->pm.requested_power_state_index++; 141 } 142 break; 143 case DYNPM_ACTION_UPCLOCK: 144 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 145 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 146 rdev->pm.dynpm_can_upclock = false; 147 } else { 148 if (rdev->pm.active_crtc_count > 1) { 149 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 150 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 151 continue; 152 else if (i <= rdev->pm.current_power_state_index) { 153 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 154 break; 155 } else { 156 rdev->pm.requested_power_state_index = i; 157 break; 158 } 159 } 160 } else 161 rdev->pm.requested_power_state_index = 162 rdev->pm.current_power_state_index + 1; 163 } 164 break; 165 case DYNPM_ACTION_DEFAULT: 166 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 167 rdev->pm.dynpm_can_upclock = false; 168 break; 169 case DYNPM_ACTION_NONE: 170 default: 171 DRM_ERROR("Requested mode for not defined action\n"); 172 return; 173 } 174 /* only one clock mode per power state */ 175 rdev->pm.requested_clock_mode_index = 0; 176 177 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 178 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 179 clock_info[rdev->pm.requested_clock_mode_index].sclk, 180 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 181 clock_info[rdev->pm.requested_clock_mode_index].mclk, 182 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 183 pcie_lanes); 184 } 185 186 void r100_pm_init_profile(struct radeon_device *rdev) 187 { 188 /* default */ 189 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 190 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 191 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 192 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 193 /* low sh */ 194 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 195 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 196 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 197 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 198 /* mid sh */ 199 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 200 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 201 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 202 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 203 /* high sh */ 204 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 205 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 206 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 207 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 208 /* low mh */ 209 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 210 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 211 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 212 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 213 /* mid mh */ 214 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 215 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 216 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 217 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 218 /* high mh */ 219 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 220 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 221 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 222 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 223 } 224 225 void r100_pm_misc(struct radeon_device *rdev) 226 { 227 int requested_index = rdev->pm.requested_power_state_index; 228 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 229 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 230 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl; 231 232 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 233 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 234 tmp = RREG32(voltage->gpio.reg); 235 if (voltage->active_high) 236 tmp |= voltage->gpio.mask; 237 else 238 tmp &= ~(voltage->gpio.mask); 239 WREG32(voltage->gpio.reg, tmp); 240 if (voltage->delay) 241 udelay(voltage->delay); 242 } else { 243 tmp = RREG32(voltage->gpio.reg); 244 if (voltage->active_high) 245 tmp &= ~voltage->gpio.mask; 246 else 247 tmp |= voltage->gpio.mask; 248 WREG32(voltage->gpio.reg, tmp); 249 if (voltage->delay) 250 udelay(voltage->delay); 251 } 252 } 253 254 sclk_cntl = RREG32_PLL(SCLK_CNTL); 255 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); 256 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3); 257 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); 258 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3); 259 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 260 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN; 261 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE) 262 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE; 263 else 264 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE; 265 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) 266 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0); 267 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) 268 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2); 269 } else 270 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN; 271 272 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 273 sclk_more_cntl |= IO_CG_VOLTAGE_DROP; 274 if (voltage->delay) { 275 sclk_more_cntl |= VOLTAGE_DROP_SYNC; 276 switch (voltage->delay) { 277 case 33: 278 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0); 279 break; 280 case 66: 281 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1); 282 break; 283 case 99: 284 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2); 285 break; 286 case 132: 287 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3); 288 break; 289 } 290 } else 291 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC; 292 } else 293 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP; 294 295 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 296 sclk_cntl &= ~FORCE_HDP; 297 else 298 sclk_cntl |= FORCE_HDP; 299 300 WREG32_PLL(SCLK_CNTL, sclk_cntl); 301 WREG32_PLL(SCLK_CNTL2, sclk_cntl2); 302 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl); 303 304 /* set pcie lanes */ 305 if ((rdev->flags & RADEON_IS_PCIE) && 306 !(rdev->flags & RADEON_IS_IGP) && 307 rdev->asic->set_pcie_lanes && 308 (ps->pcie_lanes != 309 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 310 radeon_set_pcie_lanes(rdev, 311 ps->pcie_lanes); 312 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes); 313 } 314 } 315 316 void r100_pm_prepare(struct radeon_device *rdev) 317 { 318 struct drm_device *ddev = rdev->ddev; 319 struct drm_crtc *crtc; 320 struct radeon_crtc *radeon_crtc; 321 u32 tmp; 322 323 /* disable any active CRTCs */ 324 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 325 radeon_crtc = to_radeon_crtc(crtc); 326 if (radeon_crtc->enabled) { 327 if (radeon_crtc->crtc_id) { 328 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 329 tmp |= RADEON_CRTC2_DISP_REQ_EN_B; 330 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 331 } else { 332 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 333 tmp |= RADEON_CRTC_DISP_REQ_EN_B; 334 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 335 } 336 } 337 } 338 } 339 340 void r100_pm_finish(struct radeon_device *rdev) 341 { 342 struct drm_device *ddev = rdev->ddev; 343 struct drm_crtc *crtc; 344 struct radeon_crtc *radeon_crtc; 345 u32 tmp; 346 347 /* enable any active CRTCs */ 348 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 349 radeon_crtc = to_radeon_crtc(crtc); 350 if (radeon_crtc->enabled) { 351 if (radeon_crtc->crtc_id) { 352 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 353 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B; 354 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 355 } else { 356 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 357 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B; 358 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 359 } 360 } 361 } 362 } 363 364 bool r100_gui_idle(struct radeon_device *rdev) 365 { 366 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) 367 return false; 368 else 369 return true; 370 } 371 372 /* hpd for digital panel detect/disconnect */ 373 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 374 { 375 bool connected = false; 376 377 switch (hpd) { 378 case RADEON_HPD_1: 379 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) 380 connected = true; 381 break; 382 case RADEON_HPD_2: 383 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) 384 connected = true; 385 break; 386 default: 387 break; 388 } 389 return connected; 390 } 391 392 void r100_hpd_set_polarity(struct radeon_device *rdev, 393 enum radeon_hpd_id hpd) 394 { 395 u32 tmp; 396 bool connected = r100_hpd_sense(rdev, hpd); 397 398 switch (hpd) { 399 case RADEON_HPD_1: 400 tmp = RREG32(RADEON_FP_GEN_CNTL); 401 if (connected) 402 tmp &= ~RADEON_FP_DETECT_INT_POL; 403 else 404 tmp |= RADEON_FP_DETECT_INT_POL; 405 WREG32(RADEON_FP_GEN_CNTL, tmp); 406 break; 407 case RADEON_HPD_2: 408 tmp = RREG32(RADEON_FP2_GEN_CNTL); 409 if (connected) 410 tmp &= ~RADEON_FP2_DETECT_INT_POL; 411 else 412 tmp |= RADEON_FP2_DETECT_INT_POL; 413 WREG32(RADEON_FP2_GEN_CNTL, tmp); 414 break; 415 default: 416 break; 417 } 418 } 419 420 void r100_hpd_init(struct radeon_device *rdev) 421 { 422 struct drm_device *dev = rdev->ddev; 423 struct drm_connector *connector; 424 425 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 426 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 427 switch (radeon_connector->hpd.hpd) { 428 case RADEON_HPD_1: 429 rdev->irq.hpd[0] = true; 430 break; 431 case RADEON_HPD_2: 432 rdev->irq.hpd[1] = true; 433 break; 434 default: 435 break; 436 } 437 } 438 if (rdev->irq.installed) 439 r100_irq_set(rdev); 440 } 441 442 void r100_hpd_fini(struct radeon_device *rdev) 443 { 444 struct drm_device *dev = rdev->ddev; 445 struct drm_connector *connector; 446 447 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 448 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 449 switch (radeon_connector->hpd.hpd) { 450 case RADEON_HPD_1: 451 rdev->irq.hpd[0] = false; 452 break; 453 case RADEON_HPD_2: 454 rdev->irq.hpd[1] = false; 455 break; 456 default: 457 break; 458 } 459 } 460 } 461 462 /* 463 * PCI GART 464 */ 465 void r100_pci_gart_tlb_flush(struct radeon_device *rdev) 466 { 467 /* TODO: can we do somethings here ? */ 468 /* It seems hw only cache one entry so we should discard this 469 * entry otherwise if first GPU GART read hit this entry it 470 * could end up in wrong address. */ 471 } 472 473 int r100_pci_gart_init(struct radeon_device *rdev) 474 { 475 int r; 476 477 if (rdev->gart.table.ram.ptr) { 478 WARN(1, "R100 PCI GART already initialized\n"); 479 return 0; 480 } 481 /* Initialize common gart structure */ 482 r = radeon_gart_init(rdev); 483 if (r) 484 return r; 485 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 486 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; 487 rdev->asic->gart_set_page = &r100_pci_gart_set_page; 488 return radeon_gart_table_ram_alloc(rdev); 489 } 490 491 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 492 void r100_enable_bm(struct radeon_device *rdev) 493 { 494 uint32_t tmp; 495 /* Enable bus mastering */ 496 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 497 WREG32(RADEON_BUS_CNTL, tmp); 498 } 499 500 int r100_pci_gart_enable(struct radeon_device *rdev) 501 { 502 uint32_t tmp; 503 504 radeon_gart_restore(rdev); 505 /* discard memory request outside of configured range */ 506 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 507 WREG32(RADEON_AIC_CNTL, tmp); 508 /* set address range for PCI address translate */ 509 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); 510 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); 511 /* set PCI GART page-table base address */ 512 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); 513 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; 514 WREG32(RADEON_AIC_CNTL, tmp); 515 r100_pci_gart_tlb_flush(rdev); 516 rdev->gart.ready = true; 517 return 0; 518 } 519 520 void r100_pci_gart_disable(struct radeon_device *rdev) 521 { 522 uint32_t tmp; 523 524 /* discard memory request outside of configured range */ 525 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 526 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); 527 WREG32(RADEON_AIC_LO_ADDR, 0); 528 WREG32(RADEON_AIC_HI_ADDR, 0); 529 } 530 531 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 532 { 533 if (i < 0 || i > rdev->gart.num_gpu_pages) { 534 return -EINVAL; 535 } 536 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr)); 537 return 0; 538 } 539 540 void r100_pci_gart_fini(struct radeon_device *rdev) 541 { 542 radeon_gart_fini(rdev); 543 r100_pci_gart_disable(rdev); 544 radeon_gart_table_ram_free(rdev); 545 } 546 547 int r100_irq_set(struct radeon_device *rdev) 548 { 549 uint32_t tmp = 0; 550 551 if (!rdev->irq.installed) { 552 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 553 WREG32(R_000040_GEN_INT_CNTL, 0); 554 return -EINVAL; 555 } 556 if (rdev->irq.sw_int) { 557 tmp |= RADEON_SW_INT_ENABLE; 558 } 559 if (rdev->irq.gui_idle) { 560 tmp |= RADEON_GUI_IDLE_MASK; 561 } 562 if (rdev->irq.crtc_vblank_int[0] || 563 rdev->irq.pflip[0]) { 564 tmp |= RADEON_CRTC_VBLANK_MASK; 565 } 566 if (rdev->irq.crtc_vblank_int[1] || 567 rdev->irq.pflip[1]) { 568 tmp |= RADEON_CRTC2_VBLANK_MASK; 569 } 570 if (rdev->irq.hpd[0]) { 571 tmp |= RADEON_FP_DETECT_MASK; 572 } 573 if (rdev->irq.hpd[1]) { 574 tmp |= RADEON_FP2_DETECT_MASK; 575 } 576 WREG32(RADEON_GEN_INT_CNTL, tmp); 577 return 0; 578 } 579 580 void r100_irq_disable(struct radeon_device *rdev) 581 { 582 u32 tmp; 583 584 WREG32(R_000040_GEN_INT_CNTL, 0); 585 /* Wait and acknowledge irq */ 586 mdelay(1); 587 tmp = RREG32(R_000044_GEN_INT_STATUS); 588 WREG32(R_000044_GEN_INT_STATUS, tmp); 589 } 590 591 static inline uint32_t r100_irq_ack(struct radeon_device *rdev) 592 { 593 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); 594 uint32_t irq_mask = RADEON_SW_INT_TEST | 595 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | 596 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; 597 598 /* the interrupt works, but the status bit is permanently asserted */ 599 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) { 600 if (!rdev->irq.gui_idle_acked) 601 irq_mask |= RADEON_GUI_IDLE_STAT; 602 } 603 604 if (irqs) { 605 WREG32(RADEON_GEN_INT_STATUS, irqs); 606 } 607 return irqs & irq_mask; 608 } 609 610 int r100_irq_process(struct radeon_device *rdev) 611 { 612 uint32_t status, msi_rearm; 613 bool queue_hotplug = false; 614 615 /* reset gui idle ack. the status bit is broken */ 616 rdev->irq.gui_idle_acked = false; 617 618 status = r100_irq_ack(rdev); 619 if (!status) { 620 return IRQ_NONE; 621 } 622 if (rdev->shutdown) { 623 return IRQ_NONE; 624 } 625 while (status) { 626 /* SW interrupt */ 627 if (status & RADEON_SW_INT_TEST) { 628 radeon_fence_process(rdev); 629 } 630 /* gui idle interrupt */ 631 if (status & RADEON_GUI_IDLE_STAT) { 632 rdev->irq.gui_idle_acked = true; 633 rdev->pm.gui_idle = true; 634 wake_up(&rdev->irq.idle_queue); 635 } 636 /* Vertical blank interrupts */ 637 if (status & RADEON_CRTC_VBLANK_STAT) { 638 if (rdev->irq.crtc_vblank_int[0]) { 639 drm_handle_vblank(rdev->ddev, 0); 640 rdev->pm.vblank_sync = true; 641 wake_up(&rdev->irq.vblank_queue); 642 } 643 if (rdev->irq.pflip[0]) 644 radeon_crtc_handle_flip(rdev, 0); 645 } 646 if (status & RADEON_CRTC2_VBLANK_STAT) { 647 if (rdev->irq.crtc_vblank_int[1]) { 648 drm_handle_vblank(rdev->ddev, 1); 649 rdev->pm.vblank_sync = true; 650 wake_up(&rdev->irq.vblank_queue); 651 } 652 if (rdev->irq.pflip[1]) 653 radeon_crtc_handle_flip(rdev, 1); 654 } 655 if (status & RADEON_FP_DETECT_STAT) { 656 queue_hotplug = true; 657 DRM_DEBUG("HPD1\n"); 658 } 659 if (status & RADEON_FP2_DETECT_STAT) { 660 queue_hotplug = true; 661 DRM_DEBUG("HPD2\n"); 662 } 663 status = r100_irq_ack(rdev); 664 } 665 /* reset gui idle ack. the status bit is broken */ 666 rdev->irq.gui_idle_acked = false; 667 if (queue_hotplug) 668 schedule_work(&rdev->hotplug_work); 669 if (rdev->msi_enabled) { 670 switch (rdev->family) { 671 case CHIP_RS400: 672 case CHIP_RS480: 673 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; 674 WREG32(RADEON_AIC_CNTL, msi_rearm); 675 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); 676 break; 677 default: 678 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN; 679 WREG32(RADEON_MSI_REARM_EN, msi_rearm); 680 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN); 681 break; 682 } 683 } 684 return IRQ_HANDLED; 685 } 686 687 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) 688 { 689 if (crtc == 0) 690 return RREG32(RADEON_CRTC_CRNT_FRAME); 691 else 692 return RREG32(RADEON_CRTC2_CRNT_FRAME); 693 } 694 695 /* Who ever call radeon_fence_emit should call ring_lock and ask 696 * for enough space (today caller are ib schedule and buffer move) */ 697 void r100_fence_ring_emit(struct radeon_device *rdev, 698 struct radeon_fence *fence) 699 { 700 /* We have to make sure that caches are flushed before 701 * CPU might read something from VRAM. */ 702 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); 703 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL); 704 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); 705 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL); 706 /* Wait until IDLE & CLEAN */ 707 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 708 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 709 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 710 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl | 711 RADEON_HDP_READ_BUFFER_INVALIDATE); 712 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 713 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl); 714 /* Emit fence sequence & fire IRQ */ 715 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); 716 radeon_ring_write(rdev, fence->seq); 717 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); 718 radeon_ring_write(rdev, RADEON_SW_INT_FIRE); 719 } 720 721 int r100_copy_blit(struct radeon_device *rdev, 722 uint64_t src_offset, 723 uint64_t dst_offset, 724 unsigned num_gpu_pages, 725 struct radeon_fence *fence) 726 { 727 uint32_t cur_pages; 728 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; 729 uint32_t pitch; 730 uint32_t stride_pixels; 731 unsigned ndw; 732 int num_loops; 733 int r = 0; 734 735 /* radeon limited to 16k stride */ 736 stride_bytes &= 0x3fff; 737 /* radeon pitch is /64 */ 738 pitch = stride_bytes / 64; 739 stride_pixels = stride_bytes / 4; 740 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191); 741 742 /* Ask for enough room for blit + flush + fence */ 743 ndw = 64 + (10 * num_loops); 744 r = radeon_ring_lock(rdev, ndw); 745 if (r) { 746 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); 747 return -EINVAL; 748 } 749 while (num_gpu_pages > 0) { 750 cur_pages = num_gpu_pages; 751 if (cur_pages > 8191) { 752 cur_pages = 8191; 753 } 754 num_gpu_pages -= cur_pages; 755 756 /* pages are in Y direction - height 757 page width in X direction - width */ 758 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8)); 759 radeon_ring_write(rdev, 760 RADEON_GMC_SRC_PITCH_OFFSET_CNTL | 761 RADEON_GMC_DST_PITCH_OFFSET_CNTL | 762 RADEON_GMC_SRC_CLIPPING | 763 RADEON_GMC_DST_CLIPPING | 764 RADEON_GMC_BRUSH_NONE | 765 (RADEON_COLOR_FORMAT_ARGB8888 << 8) | 766 RADEON_GMC_SRC_DATATYPE_COLOR | 767 RADEON_ROP3_S | 768 RADEON_DP_SRC_SOURCE_MEMORY | 769 RADEON_GMC_CLR_CMP_CNTL_DIS | 770 RADEON_GMC_WR_MSK_DIS); 771 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10)); 772 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10)); 773 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16)); 774 radeon_ring_write(rdev, 0); 775 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16)); 776 radeon_ring_write(rdev, cur_pages); 777 radeon_ring_write(rdev, cur_pages); 778 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16)); 779 } 780 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); 781 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL); 782 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 783 radeon_ring_write(rdev, 784 RADEON_WAIT_2D_IDLECLEAN | 785 RADEON_WAIT_HOST_IDLECLEAN | 786 RADEON_WAIT_DMA_GUI_IDLE); 787 if (fence) { 788 r = radeon_fence_emit(rdev, fence); 789 } 790 radeon_ring_unlock_commit(rdev); 791 return r; 792 } 793 794 static int r100_cp_wait_for_idle(struct radeon_device *rdev) 795 { 796 unsigned i; 797 u32 tmp; 798 799 for (i = 0; i < rdev->usec_timeout; i++) { 800 tmp = RREG32(R_000E40_RBBM_STATUS); 801 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { 802 return 0; 803 } 804 udelay(1); 805 } 806 return -1; 807 } 808 809 void r100_ring_start(struct radeon_device *rdev) 810 { 811 int r; 812 813 r = radeon_ring_lock(rdev, 2); 814 if (r) { 815 return; 816 } 817 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); 818 radeon_ring_write(rdev, 819 RADEON_ISYNC_ANY2D_IDLE3D | 820 RADEON_ISYNC_ANY3D_IDLE2D | 821 RADEON_ISYNC_WAIT_IDLEGUI | 822 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 823 radeon_ring_unlock_commit(rdev); 824 } 825 826 827 /* Load the microcode for the CP */ 828 static int r100_cp_init_microcode(struct radeon_device *rdev) 829 { 830 struct platform_device *pdev; 831 const char *fw_name = NULL; 832 int err; 833 834 DRM_DEBUG_KMS("\n"); 835 836 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); 837 err = IS_ERR(pdev); 838 if (err) { 839 printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); 840 return -EINVAL; 841 } 842 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || 843 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || 844 (rdev->family == CHIP_RS200)) { 845 DRM_INFO("Loading R100 Microcode\n"); 846 fw_name = FIRMWARE_R100; 847 } else if ((rdev->family == CHIP_R200) || 848 (rdev->family == CHIP_RV250) || 849 (rdev->family == CHIP_RV280) || 850 (rdev->family == CHIP_RS300)) { 851 DRM_INFO("Loading R200 Microcode\n"); 852 fw_name = FIRMWARE_R200; 853 } else if ((rdev->family == CHIP_R300) || 854 (rdev->family == CHIP_R350) || 855 (rdev->family == CHIP_RV350) || 856 (rdev->family == CHIP_RV380) || 857 (rdev->family == CHIP_RS400) || 858 (rdev->family == CHIP_RS480)) { 859 DRM_INFO("Loading R300 Microcode\n"); 860 fw_name = FIRMWARE_R300; 861 } else if ((rdev->family == CHIP_R420) || 862 (rdev->family == CHIP_R423) || 863 (rdev->family == CHIP_RV410)) { 864 DRM_INFO("Loading R400 Microcode\n"); 865 fw_name = FIRMWARE_R420; 866 } else if ((rdev->family == CHIP_RS690) || 867 (rdev->family == CHIP_RS740)) { 868 DRM_INFO("Loading RS690/RS740 Microcode\n"); 869 fw_name = FIRMWARE_RS690; 870 } else if (rdev->family == CHIP_RS600) { 871 DRM_INFO("Loading RS600 Microcode\n"); 872 fw_name = FIRMWARE_RS600; 873 } else if ((rdev->family == CHIP_RV515) || 874 (rdev->family == CHIP_R520) || 875 (rdev->family == CHIP_RV530) || 876 (rdev->family == CHIP_R580) || 877 (rdev->family == CHIP_RV560) || 878 (rdev->family == CHIP_RV570)) { 879 DRM_INFO("Loading R500 Microcode\n"); 880 fw_name = FIRMWARE_R520; 881 } 882 883 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); 884 platform_device_unregister(pdev); 885 if (err) { 886 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", 887 fw_name); 888 } else if (rdev->me_fw->size % 8) { 889 printk(KERN_ERR 890 "radeon_cp: Bogus length %zu in firmware \"%s\"\n", 891 rdev->me_fw->size, fw_name); 892 err = -EINVAL; 893 release_firmware(rdev->me_fw); 894 rdev->me_fw = NULL; 895 } 896 return err; 897 } 898 899 static void r100_cp_load_microcode(struct radeon_device *rdev) 900 { 901 const __be32 *fw_data; 902 int i, size; 903 904 if (r100_gui_wait_for_idle(rdev)) { 905 printk(KERN_WARNING "Failed to wait GUI idle while " 906 "programming pipes. Bad things might happen.\n"); 907 } 908 909 if (rdev->me_fw) { 910 size = rdev->me_fw->size / 4; 911 fw_data = (const __be32 *)&rdev->me_fw->data[0]; 912 WREG32(RADEON_CP_ME_RAM_ADDR, 0); 913 for (i = 0; i < size; i += 2) { 914 WREG32(RADEON_CP_ME_RAM_DATAH, 915 be32_to_cpup(&fw_data[i])); 916 WREG32(RADEON_CP_ME_RAM_DATAL, 917 be32_to_cpup(&fw_data[i + 1])); 918 } 919 } 920 } 921 922 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 923 { 924 unsigned rb_bufsz; 925 unsigned rb_blksz; 926 unsigned max_fetch; 927 unsigned pre_write_timer; 928 unsigned pre_write_limit; 929 unsigned indirect2_start; 930 unsigned indirect1_start; 931 uint32_t tmp; 932 int r; 933 934 if (r100_debugfs_cp_init(rdev)) { 935 DRM_ERROR("Failed to register debugfs file for CP !\n"); 936 } 937 if (!rdev->me_fw) { 938 r = r100_cp_init_microcode(rdev); 939 if (r) { 940 DRM_ERROR("Failed to load firmware!\n"); 941 return r; 942 } 943 } 944 945 /* Align ring size */ 946 rb_bufsz = drm_order(ring_size / 8); 947 ring_size = (1 << (rb_bufsz + 1)) * 4; 948 r100_cp_load_microcode(rdev); 949 r = radeon_ring_init(rdev, ring_size); 950 if (r) { 951 return r; 952 } 953 /* Each time the cp read 1024 bytes (16 dword/quadword) update 954 * the rptr copy in system ram */ 955 rb_blksz = 9; 956 /* cp will read 128bytes at a time (4 dwords) */ 957 max_fetch = 1; 958 rdev->cp.align_mask = 16 - 1; 959 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ 960 pre_write_timer = 64; 961 /* Force CP_RB_WPTR write if written more than one time before the 962 * delay expire 963 */ 964 pre_write_limit = 0; 965 /* Setup the cp cache like this (cache size is 96 dwords) : 966 * RING 0 to 15 967 * INDIRECT1 16 to 79 968 * INDIRECT2 80 to 95 969 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 970 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) 971 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 972 * Idea being that most of the gpu cmd will be through indirect1 buffer 973 * so it gets the bigger cache. 974 */ 975 indirect2_start = 80; 976 indirect1_start = 16; 977 /* cp setup */ 978 WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); 979 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | 980 REG_SET(RADEON_RB_BLKSZ, rb_blksz) | 981 REG_SET(RADEON_MAX_FETCH, max_fetch)); 982 #ifdef __BIG_ENDIAN 983 tmp |= RADEON_BUF_SWAP_32BIT; 984 #endif 985 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); 986 987 /* Set ring address */ 988 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr); 989 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr); 990 /* Force read & write ptr to 0 */ 991 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); 992 WREG32(RADEON_CP_RB_RPTR_WR, 0); 993 rdev->cp.wptr = 0; 994 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr); 995 996 /* set the wb address whether it's enabled or not */ 997 WREG32(R_00070C_CP_RB_RPTR_ADDR, 998 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); 999 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); 1000 1001 if (rdev->wb.enabled) 1002 WREG32(R_000770_SCRATCH_UMSK, 0xff); 1003 else { 1004 tmp |= RADEON_RB_NO_UPDATE; 1005 WREG32(R_000770_SCRATCH_UMSK, 0); 1006 } 1007 1008 WREG32(RADEON_CP_RB_CNTL, tmp); 1009 udelay(10); 1010 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); 1011 /* Set cp mode to bus mastering & enable cp*/ 1012 WREG32(RADEON_CP_CSQ_MODE, 1013 REG_SET(RADEON_INDIRECT2_START, indirect2_start) | 1014 REG_SET(RADEON_INDIRECT1_START, indirect1_start)); 1015 WREG32(RADEON_CP_RB_WPTR_DELAY, 0); 1016 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); 1017 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); 1018 radeon_ring_start(rdev); 1019 r = radeon_ring_test(rdev); 1020 if (r) { 1021 DRM_ERROR("radeon: cp isn't working (%d).\n", r); 1022 return r; 1023 } 1024 rdev->cp.ready = true; 1025 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 1026 return 0; 1027 } 1028 1029 void r100_cp_fini(struct radeon_device *rdev) 1030 { 1031 if (r100_cp_wait_for_idle(rdev)) { 1032 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); 1033 } 1034 /* Disable ring */ 1035 r100_cp_disable(rdev); 1036 radeon_ring_fini(rdev); 1037 DRM_INFO("radeon: cp finalized\n"); 1038 } 1039 1040 void r100_cp_disable(struct radeon_device *rdev) 1041 { 1042 /* Disable ring */ 1043 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1044 rdev->cp.ready = false; 1045 WREG32(RADEON_CP_CSQ_MODE, 0); 1046 WREG32(RADEON_CP_CSQ_CNTL, 0); 1047 WREG32(R_000770_SCRATCH_UMSK, 0); 1048 if (r100_gui_wait_for_idle(rdev)) { 1049 printk(KERN_WARNING "Failed to wait GUI idle while " 1050 "programming pipes. Bad things might happen.\n"); 1051 } 1052 } 1053 1054 void r100_cp_commit(struct radeon_device *rdev) 1055 { 1056 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr); 1057 (void)RREG32(RADEON_CP_RB_WPTR); 1058 } 1059 1060 1061 /* 1062 * CS functions 1063 */ 1064 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 1065 struct radeon_cs_packet *pkt, 1066 const unsigned *auth, unsigned n, 1067 radeon_packet0_check_t check) 1068 { 1069 unsigned reg; 1070 unsigned i, j, m; 1071 unsigned idx; 1072 int r; 1073 1074 idx = pkt->idx + 1; 1075 reg = pkt->reg; 1076 /* Check that register fall into register range 1077 * determined by the number of entry (n) in the 1078 * safe register bitmap. 1079 */ 1080 if (pkt->one_reg_wr) { 1081 if ((reg >> 7) > n) { 1082 return -EINVAL; 1083 } 1084 } else { 1085 if (((reg + (pkt->count << 2)) >> 7) > n) { 1086 return -EINVAL; 1087 } 1088 } 1089 for (i = 0; i <= pkt->count; i++, idx++) { 1090 j = (reg >> 7); 1091 m = 1 << ((reg >> 2) & 31); 1092 if (auth[j] & m) { 1093 r = check(p, pkt, idx, reg); 1094 if (r) { 1095 return r; 1096 } 1097 } 1098 if (pkt->one_reg_wr) { 1099 if (!(auth[j] & m)) { 1100 break; 1101 } 1102 } else { 1103 reg += 4; 1104 } 1105 } 1106 return 0; 1107 } 1108 1109 void r100_cs_dump_packet(struct radeon_cs_parser *p, 1110 struct radeon_cs_packet *pkt) 1111 { 1112 volatile uint32_t *ib; 1113 unsigned i; 1114 unsigned idx; 1115 1116 ib = p->ib->ptr; 1117 idx = pkt->idx; 1118 for (i = 0; i <= (pkt->count + 1); i++, idx++) { 1119 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); 1120 } 1121 } 1122 1123 /** 1124 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet 1125 * @parser: parser structure holding parsing context. 1126 * @pkt: where to store packet informations 1127 * 1128 * Assume that chunk_ib_index is properly set. Will return -EINVAL 1129 * if packet is bigger than remaining ib size. or if packets is unknown. 1130 **/ 1131 int r100_cs_packet_parse(struct radeon_cs_parser *p, 1132 struct radeon_cs_packet *pkt, 1133 unsigned idx) 1134 { 1135 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; 1136 uint32_t header; 1137 1138 if (idx >= ib_chunk->length_dw) { 1139 DRM_ERROR("Can not parse packet at %d after CS end %d !\n", 1140 idx, ib_chunk->length_dw); 1141 return -EINVAL; 1142 } 1143 header = radeon_get_ib_value(p, idx); 1144 pkt->idx = idx; 1145 pkt->type = CP_PACKET_GET_TYPE(header); 1146 pkt->count = CP_PACKET_GET_COUNT(header); 1147 switch (pkt->type) { 1148 case PACKET_TYPE0: 1149 pkt->reg = CP_PACKET0_GET_REG(header); 1150 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header); 1151 break; 1152 case PACKET_TYPE3: 1153 pkt->opcode = CP_PACKET3_GET_OPCODE(header); 1154 break; 1155 case PACKET_TYPE2: 1156 pkt->count = -1; 1157 break; 1158 default: 1159 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); 1160 return -EINVAL; 1161 } 1162 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { 1163 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", 1164 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); 1165 return -EINVAL; 1166 } 1167 return 0; 1168 } 1169 1170 /** 1171 * r100_cs_packet_next_vline() - parse userspace VLINE packet 1172 * @parser: parser structure holding parsing context. 1173 * 1174 * Userspace sends a special sequence for VLINE waits. 1175 * PACKET0 - VLINE_START_END + value 1176 * PACKET0 - WAIT_UNTIL +_value 1177 * RELOC (P3) - crtc_id in reloc. 1178 * 1179 * This function parses this and relocates the VLINE START END 1180 * and WAIT UNTIL packets to the correct crtc. 1181 * It also detects a switched off crtc and nulls out the 1182 * wait in that case. 1183 */ 1184 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) 1185 { 1186 struct drm_mode_object *obj; 1187 struct drm_crtc *crtc; 1188 struct radeon_crtc *radeon_crtc; 1189 struct radeon_cs_packet p3reloc, waitreloc; 1190 int crtc_id; 1191 int r; 1192 uint32_t header, h_idx, reg; 1193 volatile uint32_t *ib; 1194 1195 ib = p->ib->ptr; 1196 1197 /* parse the wait until */ 1198 r = r100_cs_packet_parse(p, &waitreloc, p->idx); 1199 if (r) 1200 return r; 1201 1202 /* check its a wait until and only 1 count */ 1203 if (waitreloc.reg != RADEON_WAIT_UNTIL || 1204 waitreloc.count != 0) { 1205 DRM_ERROR("vline wait had illegal wait until segment\n"); 1206 return -EINVAL; 1207 } 1208 1209 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { 1210 DRM_ERROR("vline wait had illegal wait until\n"); 1211 return -EINVAL; 1212 } 1213 1214 /* jump over the NOP */ 1215 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); 1216 if (r) 1217 return r; 1218 1219 h_idx = p->idx - 2; 1220 p->idx += waitreloc.count + 2; 1221 p->idx += p3reloc.count + 2; 1222 1223 header = radeon_get_ib_value(p, h_idx); 1224 crtc_id = radeon_get_ib_value(p, h_idx + 5); 1225 reg = CP_PACKET0_GET_REG(header); 1226 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 1227 if (!obj) { 1228 DRM_ERROR("cannot find crtc %d\n", crtc_id); 1229 return -EINVAL; 1230 } 1231 crtc = obj_to_crtc(obj); 1232 radeon_crtc = to_radeon_crtc(crtc); 1233 crtc_id = radeon_crtc->crtc_id; 1234 1235 if (!crtc->enabled) { 1236 /* if the CRTC isn't enabled - we need to nop out the wait until */ 1237 ib[h_idx + 2] = PACKET2(0); 1238 ib[h_idx + 3] = PACKET2(0); 1239 } else if (crtc_id == 1) { 1240 switch (reg) { 1241 case AVIVO_D1MODE_VLINE_START_END: 1242 header &= ~R300_CP_PACKET0_REG_MASK; 1243 header |= AVIVO_D2MODE_VLINE_START_END >> 2; 1244 break; 1245 case RADEON_CRTC_GUI_TRIG_VLINE: 1246 header &= ~R300_CP_PACKET0_REG_MASK; 1247 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; 1248 break; 1249 default: 1250 DRM_ERROR("unknown crtc reloc\n"); 1251 return -EINVAL; 1252 } 1253 ib[h_idx] = header; 1254 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; 1255 } 1256 1257 return 0; 1258 } 1259 1260 /** 1261 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3 1262 * @parser: parser structure holding parsing context. 1263 * @data: pointer to relocation data 1264 * @offset_start: starting offset 1265 * @offset_mask: offset mask (to align start offset on) 1266 * @reloc: reloc informations 1267 * 1268 * Check next packet is relocation packet3, do bo validation and compute 1269 * GPU offset using the provided start. 1270 **/ 1271 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, 1272 struct radeon_cs_reloc **cs_reloc) 1273 { 1274 struct radeon_cs_chunk *relocs_chunk; 1275 struct radeon_cs_packet p3reloc; 1276 unsigned idx; 1277 int r; 1278 1279 if (p->chunk_relocs_idx == -1) { 1280 DRM_ERROR("No relocation chunk !\n"); 1281 return -EINVAL; 1282 } 1283 *cs_reloc = NULL; 1284 relocs_chunk = &p->chunks[p->chunk_relocs_idx]; 1285 r = r100_cs_packet_parse(p, &p3reloc, p->idx); 1286 if (r) { 1287 return r; 1288 } 1289 p->idx += p3reloc.count + 2; 1290 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { 1291 DRM_ERROR("No packet3 for relocation for packet at %d.\n", 1292 p3reloc.idx); 1293 r100_cs_dump_packet(p, &p3reloc); 1294 return -EINVAL; 1295 } 1296 idx = radeon_get_ib_value(p, p3reloc.idx + 1); 1297 if (idx >= relocs_chunk->length_dw) { 1298 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 1299 idx, relocs_chunk->length_dw); 1300 r100_cs_dump_packet(p, &p3reloc); 1301 return -EINVAL; 1302 } 1303 /* FIXME: we assume reloc size is 4 dwords */ 1304 *cs_reloc = p->relocs_ptr[(idx / 4)]; 1305 return 0; 1306 } 1307 1308 static int r100_get_vtx_size(uint32_t vtx_fmt) 1309 { 1310 int vtx_size; 1311 vtx_size = 2; 1312 /* ordered according to bits in spec */ 1313 if (vtx_fmt & RADEON_SE_VTX_FMT_W0) 1314 vtx_size++; 1315 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) 1316 vtx_size += 3; 1317 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) 1318 vtx_size++; 1319 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) 1320 vtx_size++; 1321 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) 1322 vtx_size += 3; 1323 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) 1324 vtx_size++; 1325 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) 1326 vtx_size++; 1327 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) 1328 vtx_size += 2; 1329 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) 1330 vtx_size += 2; 1331 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) 1332 vtx_size++; 1333 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) 1334 vtx_size += 2; 1335 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) 1336 vtx_size++; 1337 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) 1338 vtx_size += 2; 1339 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) 1340 vtx_size++; 1341 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) 1342 vtx_size++; 1343 /* blend weight */ 1344 if (vtx_fmt & (0x7 << 15)) 1345 vtx_size += (vtx_fmt >> 15) & 0x7; 1346 if (vtx_fmt & RADEON_SE_VTX_FMT_N0) 1347 vtx_size += 3; 1348 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) 1349 vtx_size += 2; 1350 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) 1351 vtx_size++; 1352 if (vtx_fmt & RADEON_SE_VTX_FMT_W1) 1353 vtx_size++; 1354 if (vtx_fmt & RADEON_SE_VTX_FMT_N1) 1355 vtx_size++; 1356 if (vtx_fmt & RADEON_SE_VTX_FMT_Z) 1357 vtx_size++; 1358 return vtx_size; 1359 } 1360 1361 static int r100_packet0_check(struct radeon_cs_parser *p, 1362 struct radeon_cs_packet *pkt, 1363 unsigned idx, unsigned reg) 1364 { 1365 struct radeon_cs_reloc *reloc; 1366 struct r100_cs_track *track; 1367 volatile uint32_t *ib; 1368 uint32_t tmp; 1369 int r; 1370 int i, face; 1371 u32 tile_flags = 0; 1372 u32 idx_value; 1373 1374 ib = p->ib->ptr; 1375 track = (struct r100_cs_track *)p->track; 1376 1377 idx_value = radeon_get_ib_value(p, idx); 1378 1379 switch (reg) { 1380 case RADEON_CRTC_GUI_TRIG_VLINE: 1381 r = r100_cs_packet_parse_vline(p); 1382 if (r) { 1383 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1384 idx, reg); 1385 r100_cs_dump_packet(p, pkt); 1386 return r; 1387 } 1388 break; 1389 /* FIXME: only allow PACKET3 blit? easier to check for out of 1390 * range access */ 1391 case RADEON_DST_PITCH_OFFSET: 1392 case RADEON_SRC_PITCH_OFFSET: 1393 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 1394 if (r) 1395 return r; 1396 break; 1397 case RADEON_RB3D_DEPTHOFFSET: 1398 r = r100_cs_packet_next_reloc(p, &reloc); 1399 if (r) { 1400 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1401 idx, reg); 1402 r100_cs_dump_packet(p, pkt); 1403 return r; 1404 } 1405 track->zb.robj = reloc->robj; 1406 track->zb.offset = idx_value; 1407 track->zb_dirty = true; 1408 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1409 break; 1410 case RADEON_RB3D_COLOROFFSET: 1411 r = r100_cs_packet_next_reloc(p, &reloc); 1412 if (r) { 1413 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1414 idx, reg); 1415 r100_cs_dump_packet(p, pkt); 1416 return r; 1417 } 1418 track->cb[0].robj = reloc->robj; 1419 track->cb[0].offset = idx_value; 1420 track->cb_dirty = true; 1421 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1422 break; 1423 case RADEON_PP_TXOFFSET_0: 1424 case RADEON_PP_TXOFFSET_1: 1425 case RADEON_PP_TXOFFSET_2: 1426 i = (reg - RADEON_PP_TXOFFSET_0) / 24; 1427 r = r100_cs_packet_next_reloc(p, &reloc); 1428 if (r) { 1429 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1430 idx, reg); 1431 r100_cs_dump_packet(p, pkt); 1432 return r; 1433 } 1434 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1435 track->textures[i].robj = reloc->robj; 1436 track->tex_dirty = true; 1437 break; 1438 case RADEON_PP_CUBIC_OFFSET_T0_0: 1439 case RADEON_PP_CUBIC_OFFSET_T0_1: 1440 case RADEON_PP_CUBIC_OFFSET_T0_2: 1441 case RADEON_PP_CUBIC_OFFSET_T0_3: 1442 case RADEON_PP_CUBIC_OFFSET_T0_4: 1443 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; 1444 r = r100_cs_packet_next_reloc(p, &reloc); 1445 if (r) { 1446 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1447 idx, reg); 1448 r100_cs_dump_packet(p, pkt); 1449 return r; 1450 } 1451 track->textures[0].cube_info[i].offset = idx_value; 1452 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1453 track->textures[0].cube_info[i].robj = reloc->robj; 1454 track->tex_dirty = true; 1455 break; 1456 case RADEON_PP_CUBIC_OFFSET_T1_0: 1457 case RADEON_PP_CUBIC_OFFSET_T1_1: 1458 case RADEON_PP_CUBIC_OFFSET_T1_2: 1459 case RADEON_PP_CUBIC_OFFSET_T1_3: 1460 case RADEON_PP_CUBIC_OFFSET_T1_4: 1461 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; 1462 r = r100_cs_packet_next_reloc(p, &reloc); 1463 if (r) { 1464 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1465 idx, reg); 1466 r100_cs_dump_packet(p, pkt); 1467 return r; 1468 } 1469 track->textures[1].cube_info[i].offset = idx_value; 1470 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1471 track->textures[1].cube_info[i].robj = reloc->robj; 1472 track->tex_dirty = true; 1473 break; 1474 case RADEON_PP_CUBIC_OFFSET_T2_0: 1475 case RADEON_PP_CUBIC_OFFSET_T2_1: 1476 case RADEON_PP_CUBIC_OFFSET_T2_2: 1477 case RADEON_PP_CUBIC_OFFSET_T2_3: 1478 case RADEON_PP_CUBIC_OFFSET_T2_4: 1479 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; 1480 r = r100_cs_packet_next_reloc(p, &reloc); 1481 if (r) { 1482 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1483 idx, reg); 1484 r100_cs_dump_packet(p, pkt); 1485 return r; 1486 } 1487 track->textures[2].cube_info[i].offset = idx_value; 1488 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1489 track->textures[2].cube_info[i].robj = reloc->robj; 1490 track->tex_dirty = true; 1491 break; 1492 case RADEON_RE_WIDTH_HEIGHT: 1493 track->maxy = ((idx_value >> 16) & 0x7FF); 1494 track->cb_dirty = true; 1495 track->zb_dirty = true; 1496 break; 1497 case RADEON_RB3D_COLORPITCH: 1498 r = r100_cs_packet_next_reloc(p, &reloc); 1499 if (r) { 1500 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1501 idx, reg); 1502 r100_cs_dump_packet(p, pkt); 1503 return r; 1504 } 1505 1506 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1507 tile_flags |= RADEON_COLOR_TILE_ENABLE; 1508 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1509 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; 1510 1511 tmp = idx_value & ~(0x7 << 16); 1512 tmp |= tile_flags; 1513 ib[idx] = tmp; 1514 1515 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; 1516 track->cb_dirty = true; 1517 break; 1518 case RADEON_RB3D_DEPTHPITCH: 1519 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; 1520 track->zb_dirty = true; 1521 break; 1522 case RADEON_RB3D_CNTL: 1523 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { 1524 case 7: 1525 case 8: 1526 case 9: 1527 case 11: 1528 case 12: 1529 track->cb[0].cpp = 1; 1530 break; 1531 case 3: 1532 case 4: 1533 case 15: 1534 track->cb[0].cpp = 2; 1535 break; 1536 case 6: 1537 track->cb[0].cpp = 4; 1538 break; 1539 default: 1540 DRM_ERROR("Invalid color buffer format (%d) !\n", 1541 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); 1542 return -EINVAL; 1543 } 1544 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); 1545 track->cb_dirty = true; 1546 track->zb_dirty = true; 1547 break; 1548 case RADEON_RB3D_ZSTENCILCNTL: 1549 switch (idx_value & 0xf) { 1550 case 0: 1551 track->zb.cpp = 2; 1552 break; 1553 case 2: 1554 case 3: 1555 case 4: 1556 case 5: 1557 case 9: 1558 case 11: 1559 track->zb.cpp = 4; 1560 break; 1561 default: 1562 break; 1563 } 1564 track->zb_dirty = true; 1565 break; 1566 case RADEON_RB3D_ZPASS_ADDR: 1567 r = r100_cs_packet_next_reloc(p, &reloc); 1568 if (r) { 1569 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1570 idx, reg); 1571 r100_cs_dump_packet(p, pkt); 1572 return r; 1573 } 1574 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1575 break; 1576 case RADEON_PP_CNTL: 1577 { 1578 uint32_t temp = idx_value >> 4; 1579 for (i = 0; i < track->num_texture; i++) 1580 track->textures[i].enabled = !!(temp & (1 << i)); 1581 track->tex_dirty = true; 1582 } 1583 break; 1584 case RADEON_SE_VF_CNTL: 1585 track->vap_vf_cntl = idx_value; 1586 break; 1587 case RADEON_SE_VTX_FMT: 1588 track->vtx_size = r100_get_vtx_size(idx_value); 1589 break; 1590 case RADEON_PP_TEX_SIZE_0: 1591 case RADEON_PP_TEX_SIZE_1: 1592 case RADEON_PP_TEX_SIZE_2: 1593 i = (reg - RADEON_PP_TEX_SIZE_0) / 8; 1594 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; 1595 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; 1596 track->tex_dirty = true; 1597 break; 1598 case RADEON_PP_TEX_PITCH_0: 1599 case RADEON_PP_TEX_PITCH_1: 1600 case RADEON_PP_TEX_PITCH_2: 1601 i = (reg - RADEON_PP_TEX_PITCH_0) / 8; 1602 track->textures[i].pitch = idx_value + 32; 1603 track->tex_dirty = true; 1604 break; 1605 case RADEON_PP_TXFILTER_0: 1606 case RADEON_PP_TXFILTER_1: 1607 case RADEON_PP_TXFILTER_2: 1608 i = (reg - RADEON_PP_TXFILTER_0) / 24; 1609 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) 1610 >> RADEON_MAX_MIP_LEVEL_SHIFT); 1611 tmp = (idx_value >> 23) & 0x7; 1612 if (tmp == 2 || tmp == 6) 1613 track->textures[i].roundup_w = false; 1614 tmp = (idx_value >> 27) & 0x7; 1615 if (tmp == 2 || tmp == 6) 1616 track->textures[i].roundup_h = false; 1617 track->tex_dirty = true; 1618 break; 1619 case RADEON_PP_TXFORMAT_0: 1620 case RADEON_PP_TXFORMAT_1: 1621 case RADEON_PP_TXFORMAT_2: 1622 i = (reg - RADEON_PP_TXFORMAT_0) / 24; 1623 if (idx_value & RADEON_TXFORMAT_NON_POWER2) { 1624 track->textures[i].use_pitch = 1; 1625 } else { 1626 track->textures[i].use_pitch = 0; 1627 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); 1628 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); 1629 } 1630 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) 1631 track->textures[i].tex_coord_type = 2; 1632 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { 1633 case RADEON_TXFORMAT_I8: 1634 case RADEON_TXFORMAT_RGB332: 1635 case RADEON_TXFORMAT_Y8: 1636 track->textures[i].cpp = 1; 1637 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1638 break; 1639 case RADEON_TXFORMAT_AI88: 1640 case RADEON_TXFORMAT_ARGB1555: 1641 case RADEON_TXFORMAT_RGB565: 1642 case RADEON_TXFORMAT_ARGB4444: 1643 case RADEON_TXFORMAT_VYUY422: 1644 case RADEON_TXFORMAT_YVYU422: 1645 case RADEON_TXFORMAT_SHADOW16: 1646 case RADEON_TXFORMAT_LDUDV655: 1647 case RADEON_TXFORMAT_DUDV88: 1648 track->textures[i].cpp = 2; 1649 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1650 break; 1651 case RADEON_TXFORMAT_ARGB8888: 1652 case RADEON_TXFORMAT_RGBA8888: 1653 case RADEON_TXFORMAT_SHADOW32: 1654 case RADEON_TXFORMAT_LDUDUV8888: 1655 track->textures[i].cpp = 4; 1656 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1657 break; 1658 case RADEON_TXFORMAT_DXT1: 1659 track->textures[i].cpp = 1; 1660 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 1661 break; 1662 case RADEON_TXFORMAT_DXT23: 1663 case RADEON_TXFORMAT_DXT45: 1664 track->textures[i].cpp = 1; 1665 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 1666 break; 1667 } 1668 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); 1669 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); 1670 track->tex_dirty = true; 1671 break; 1672 case RADEON_PP_CUBIC_FACES_0: 1673 case RADEON_PP_CUBIC_FACES_1: 1674 case RADEON_PP_CUBIC_FACES_2: 1675 tmp = idx_value; 1676 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; 1677 for (face = 0; face < 4; face++) { 1678 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); 1679 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); 1680 } 1681 track->tex_dirty = true; 1682 break; 1683 default: 1684 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", 1685 reg, idx); 1686 return -EINVAL; 1687 } 1688 return 0; 1689 } 1690 1691 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 1692 struct radeon_cs_packet *pkt, 1693 struct radeon_bo *robj) 1694 { 1695 unsigned idx; 1696 u32 value; 1697 idx = pkt->idx + 1; 1698 value = radeon_get_ib_value(p, idx + 2); 1699 if ((value + 1) > radeon_bo_size(robj)) { 1700 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " 1701 "(need %u have %lu) !\n", 1702 value + 1, 1703 radeon_bo_size(robj)); 1704 return -EINVAL; 1705 } 1706 return 0; 1707 } 1708 1709 static int r100_packet3_check(struct radeon_cs_parser *p, 1710 struct radeon_cs_packet *pkt) 1711 { 1712 struct radeon_cs_reloc *reloc; 1713 struct r100_cs_track *track; 1714 unsigned idx; 1715 volatile uint32_t *ib; 1716 int r; 1717 1718 ib = p->ib->ptr; 1719 idx = pkt->idx + 1; 1720 track = (struct r100_cs_track *)p->track; 1721 switch (pkt->opcode) { 1722 case PACKET3_3D_LOAD_VBPNTR: 1723 r = r100_packet3_load_vbpntr(p, pkt, idx); 1724 if (r) 1725 return r; 1726 break; 1727 case PACKET3_INDX_BUFFER: 1728 r = r100_cs_packet_next_reloc(p, &reloc); 1729 if (r) { 1730 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1731 r100_cs_dump_packet(p, pkt); 1732 return r; 1733 } 1734 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); 1735 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1736 if (r) { 1737 return r; 1738 } 1739 break; 1740 case 0x23: 1741 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ 1742 r = r100_cs_packet_next_reloc(p, &reloc); 1743 if (r) { 1744 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1745 r100_cs_dump_packet(p, pkt); 1746 return r; 1747 } 1748 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); 1749 track->num_arrays = 1; 1750 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); 1751 1752 track->arrays[0].robj = reloc->robj; 1753 track->arrays[0].esize = track->vtx_size; 1754 1755 track->max_indx = radeon_get_ib_value(p, idx+1); 1756 1757 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); 1758 track->immd_dwords = pkt->count - 1; 1759 r = r100_cs_track_check(p->rdev, track); 1760 if (r) 1761 return r; 1762 break; 1763 case PACKET3_3D_DRAW_IMMD: 1764 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1765 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1766 return -EINVAL; 1767 } 1768 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); 1769 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1770 track->immd_dwords = pkt->count - 1; 1771 r = r100_cs_track_check(p->rdev, track); 1772 if (r) 1773 return r; 1774 break; 1775 /* triggers drawing using in-packet vertex data */ 1776 case PACKET3_3D_DRAW_IMMD_2: 1777 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1778 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1779 return -EINVAL; 1780 } 1781 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1782 track->immd_dwords = pkt->count; 1783 r = r100_cs_track_check(p->rdev, track); 1784 if (r) 1785 return r; 1786 break; 1787 /* triggers drawing using in-packet vertex data */ 1788 case PACKET3_3D_DRAW_VBUF_2: 1789 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1790 r = r100_cs_track_check(p->rdev, track); 1791 if (r) 1792 return r; 1793 break; 1794 /* triggers drawing of vertex buffers setup elsewhere */ 1795 case PACKET3_3D_DRAW_INDX_2: 1796 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1797 r = r100_cs_track_check(p->rdev, track); 1798 if (r) 1799 return r; 1800 break; 1801 /* triggers drawing using indices to vertex buffer */ 1802 case PACKET3_3D_DRAW_VBUF: 1803 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1804 r = r100_cs_track_check(p->rdev, track); 1805 if (r) 1806 return r; 1807 break; 1808 /* triggers drawing of vertex buffers setup elsewhere */ 1809 case PACKET3_3D_DRAW_INDX: 1810 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1811 r = r100_cs_track_check(p->rdev, track); 1812 if (r) 1813 return r; 1814 break; 1815 /* triggers drawing using indices to vertex buffer */ 1816 case PACKET3_3D_CLEAR_HIZ: 1817 case PACKET3_3D_CLEAR_ZMASK: 1818 if (p->rdev->hyperz_filp != p->filp) 1819 return -EINVAL; 1820 break; 1821 case PACKET3_NOP: 1822 break; 1823 default: 1824 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 1825 return -EINVAL; 1826 } 1827 return 0; 1828 } 1829 1830 int r100_cs_parse(struct radeon_cs_parser *p) 1831 { 1832 struct radeon_cs_packet pkt; 1833 struct r100_cs_track *track; 1834 int r; 1835 1836 track = kzalloc(sizeof(*track), GFP_KERNEL); 1837 r100_cs_track_clear(p->rdev, track); 1838 p->track = track; 1839 do { 1840 r = r100_cs_packet_parse(p, &pkt, p->idx); 1841 if (r) { 1842 return r; 1843 } 1844 p->idx += pkt.count + 2; 1845 switch (pkt.type) { 1846 case PACKET_TYPE0: 1847 if (p->rdev->family >= CHIP_R200) 1848 r = r100_cs_parse_packet0(p, &pkt, 1849 p->rdev->config.r100.reg_safe_bm, 1850 p->rdev->config.r100.reg_safe_bm_size, 1851 &r200_packet0_check); 1852 else 1853 r = r100_cs_parse_packet0(p, &pkt, 1854 p->rdev->config.r100.reg_safe_bm, 1855 p->rdev->config.r100.reg_safe_bm_size, 1856 &r100_packet0_check); 1857 break; 1858 case PACKET_TYPE2: 1859 break; 1860 case PACKET_TYPE3: 1861 r = r100_packet3_check(p, &pkt); 1862 break; 1863 default: 1864 DRM_ERROR("Unknown packet type %d !\n", 1865 pkt.type); 1866 return -EINVAL; 1867 } 1868 if (r) { 1869 return r; 1870 } 1871 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 1872 return 0; 1873 } 1874 1875 1876 /* 1877 * Global GPU functions 1878 */ 1879 void r100_errata(struct radeon_device *rdev) 1880 { 1881 rdev->pll_errata = 0; 1882 1883 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { 1884 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; 1885 } 1886 1887 if (rdev->family == CHIP_RV100 || 1888 rdev->family == CHIP_RS100 || 1889 rdev->family == CHIP_RS200) { 1890 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; 1891 } 1892 } 1893 1894 /* Wait for vertical sync on primary CRTC */ 1895 void r100_gpu_wait_for_vsync(struct radeon_device *rdev) 1896 { 1897 uint32_t crtc_gen_cntl, tmp; 1898 int i; 1899 1900 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 1901 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) || 1902 !(crtc_gen_cntl & RADEON_CRTC_EN)) { 1903 return; 1904 } 1905 /* Clear the CRTC_VBLANK_SAVE bit */ 1906 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR); 1907 for (i = 0; i < rdev->usec_timeout; i++) { 1908 tmp = RREG32(RADEON_CRTC_STATUS); 1909 if (tmp & RADEON_CRTC_VBLANK_SAVE) { 1910 return; 1911 } 1912 DRM_UDELAY(1); 1913 } 1914 } 1915 1916 /* Wait for vertical sync on secondary CRTC */ 1917 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev) 1918 { 1919 uint32_t crtc2_gen_cntl, tmp; 1920 int i; 1921 1922 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 1923 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) || 1924 !(crtc2_gen_cntl & RADEON_CRTC2_EN)) 1925 return; 1926 1927 /* Clear the CRTC_VBLANK_SAVE bit */ 1928 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR); 1929 for (i = 0; i < rdev->usec_timeout; i++) { 1930 tmp = RREG32(RADEON_CRTC2_STATUS); 1931 if (tmp & RADEON_CRTC2_VBLANK_SAVE) { 1932 return; 1933 } 1934 DRM_UDELAY(1); 1935 } 1936 } 1937 1938 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) 1939 { 1940 unsigned i; 1941 uint32_t tmp; 1942 1943 for (i = 0; i < rdev->usec_timeout; i++) { 1944 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; 1945 if (tmp >= n) { 1946 return 0; 1947 } 1948 DRM_UDELAY(1); 1949 } 1950 return -1; 1951 } 1952 1953 int r100_gui_wait_for_idle(struct radeon_device *rdev) 1954 { 1955 unsigned i; 1956 uint32_t tmp; 1957 1958 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { 1959 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !" 1960 " Bad things might happen.\n"); 1961 } 1962 for (i = 0; i < rdev->usec_timeout; i++) { 1963 tmp = RREG32(RADEON_RBBM_STATUS); 1964 if (!(tmp & RADEON_RBBM_ACTIVE)) { 1965 return 0; 1966 } 1967 DRM_UDELAY(1); 1968 } 1969 return -1; 1970 } 1971 1972 int r100_mc_wait_for_idle(struct radeon_device *rdev) 1973 { 1974 unsigned i; 1975 uint32_t tmp; 1976 1977 for (i = 0; i < rdev->usec_timeout; i++) { 1978 /* read MC_STATUS */ 1979 tmp = RREG32(RADEON_MC_STATUS); 1980 if (tmp & RADEON_MC_IDLE) { 1981 return 0; 1982 } 1983 DRM_UDELAY(1); 1984 } 1985 return -1; 1986 } 1987 1988 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp) 1989 { 1990 lockup->last_cp_rptr = cp->rptr; 1991 lockup->last_jiffies = jiffies; 1992 } 1993 1994 /** 1995 * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information 1996 * @rdev: radeon device structure 1997 * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations 1998 * @cp: radeon_cp structure holding CP information 1999 * 2000 * We don't need to initialize the lockup tracking information as we will either 2001 * have CP rptr to a different value of jiffies wrap around which will force 2002 * initialization of the lockup tracking informations. 2003 * 2004 * A possible false positivie is if we get call after while and last_cp_rptr == 2005 * the current CP rptr, even if it's unlikely it might happen. To avoid this 2006 * if the elapsed time since last call is bigger than 2 second than we return 2007 * false and update the tracking information. Due to this the caller must call 2008 * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported 2009 * the fencing code should be cautious about that. 2010 * 2011 * Caller should write to the ring to force CP to do something so we don't get 2012 * false positive when CP is just gived nothing to do. 2013 * 2014 **/ 2015 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp) 2016 { 2017 unsigned long cjiffies, elapsed; 2018 2019 cjiffies = jiffies; 2020 if (!time_after(cjiffies, lockup->last_jiffies)) { 2021 /* likely a wrap around */ 2022 lockup->last_cp_rptr = cp->rptr; 2023 lockup->last_jiffies = jiffies; 2024 return false; 2025 } 2026 if (cp->rptr != lockup->last_cp_rptr) { 2027 /* CP is still working no lockup */ 2028 lockup->last_cp_rptr = cp->rptr; 2029 lockup->last_jiffies = jiffies; 2030 return false; 2031 } 2032 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies); 2033 if (elapsed >= 10000) { 2034 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); 2035 return true; 2036 } 2037 /* give a chance to the GPU ... */ 2038 return false; 2039 } 2040 2041 bool r100_gpu_is_lockup(struct radeon_device *rdev) 2042 { 2043 u32 rbbm_status; 2044 int r; 2045 2046 rbbm_status = RREG32(R_000E40_RBBM_STATUS); 2047 if (!G_000E40_GUI_ACTIVE(rbbm_status)) { 2048 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp); 2049 return false; 2050 } 2051 /* force CP activities */ 2052 r = radeon_ring_lock(rdev, 2); 2053 if (!r) { 2054 /* PACKET2 NOP */ 2055 radeon_ring_write(rdev, 0x80000000); 2056 radeon_ring_write(rdev, 0x80000000); 2057 radeon_ring_unlock_commit(rdev); 2058 } 2059 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); 2060 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp); 2061 } 2062 2063 void r100_bm_disable(struct radeon_device *rdev) 2064 { 2065 u32 tmp; 2066 2067 /* disable bus mastering */ 2068 tmp = RREG32(R_000030_BUS_CNTL); 2069 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); 2070 mdelay(1); 2071 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); 2072 mdelay(1); 2073 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); 2074 tmp = RREG32(RADEON_BUS_CNTL); 2075 mdelay(1); 2076 pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp); 2077 pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB); 2078 mdelay(1); 2079 } 2080 2081 int r100_asic_reset(struct radeon_device *rdev) 2082 { 2083 struct r100_mc_save save; 2084 u32 status, tmp; 2085 int ret = 0; 2086 2087 status = RREG32(R_000E40_RBBM_STATUS); 2088 if (!G_000E40_GUI_ACTIVE(status)) { 2089 return 0; 2090 } 2091 r100_mc_stop(rdev, &save); 2092 status = RREG32(R_000E40_RBBM_STATUS); 2093 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2094 /* stop CP */ 2095 WREG32(RADEON_CP_CSQ_CNTL, 0); 2096 tmp = RREG32(RADEON_CP_RB_CNTL); 2097 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 2098 WREG32(RADEON_CP_RB_RPTR_WR, 0); 2099 WREG32(RADEON_CP_RB_WPTR, 0); 2100 WREG32(RADEON_CP_RB_CNTL, tmp); 2101 /* save PCI state */ 2102 pci_save_state(rdev->pdev); 2103 /* disable bus mastering */ 2104 r100_bm_disable(rdev); 2105 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | 2106 S_0000F0_SOFT_RESET_RE(1) | 2107 S_0000F0_SOFT_RESET_PP(1) | 2108 S_0000F0_SOFT_RESET_RB(1)); 2109 RREG32(R_0000F0_RBBM_SOFT_RESET); 2110 mdelay(500); 2111 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2112 mdelay(1); 2113 status = RREG32(R_000E40_RBBM_STATUS); 2114 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2115 /* reset CP */ 2116 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 2117 RREG32(R_0000F0_RBBM_SOFT_RESET); 2118 mdelay(500); 2119 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2120 mdelay(1); 2121 status = RREG32(R_000E40_RBBM_STATUS); 2122 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2123 /* restore PCI & busmastering */ 2124 pci_restore_state(rdev->pdev); 2125 r100_enable_bm(rdev); 2126 /* Check if GPU is idle */ 2127 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || 2128 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { 2129 dev_err(rdev->dev, "failed to reset GPU\n"); 2130 rdev->gpu_lockup = true; 2131 ret = -1; 2132 } else 2133 dev_info(rdev->dev, "GPU reset succeed\n"); 2134 r100_mc_resume(rdev, &save); 2135 return ret; 2136 } 2137 2138 void r100_set_common_regs(struct radeon_device *rdev) 2139 { 2140 struct drm_device *dev = rdev->ddev; 2141 bool force_dac2 = false; 2142 u32 tmp; 2143 2144 /* set these so they don't interfere with anything */ 2145 WREG32(RADEON_OV0_SCALE_CNTL, 0); 2146 WREG32(RADEON_SUBPIC_CNTL, 0); 2147 WREG32(RADEON_VIPH_CONTROL, 0); 2148 WREG32(RADEON_I2C_CNTL_1, 0); 2149 WREG32(RADEON_DVI_I2C_CNTL_1, 0); 2150 WREG32(RADEON_CAP0_TRIG_CNTL, 0); 2151 WREG32(RADEON_CAP1_TRIG_CNTL, 0); 2152 2153 /* always set up dac2 on rn50 and some rv100 as lots 2154 * of servers seem to wire it up to a VGA port but 2155 * don't report it in the bios connector 2156 * table. 2157 */ 2158 switch (dev->pdev->device) { 2159 /* RN50 */ 2160 case 0x515e: 2161 case 0x5969: 2162 force_dac2 = true; 2163 break; 2164 /* RV100*/ 2165 case 0x5159: 2166 case 0x515a: 2167 /* DELL triple head servers */ 2168 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) && 2169 ((dev->pdev->subsystem_device == 0x016c) || 2170 (dev->pdev->subsystem_device == 0x016d) || 2171 (dev->pdev->subsystem_device == 0x016e) || 2172 (dev->pdev->subsystem_device == 0x016f) || 2173 (dev->pdev->subsystem_device == 0x0170) || 2174 (dev->pdev->subsystem_device == 0x017d) || 2175 (dev->pdev->subsystem_device == 0x017e) || 2176 (dev->pdev->subsystem_device == 0x0183) || 2177 (dev->pdev->subsystem_device == 0x018a) || 2178 (dev->pdev->subsystem_device == 0x019a))) 2179 force_dac2 = true; 2180 break; 2181 } 2182 2183 if (force_dac2) { 2184 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 2185 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 2186 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 2187 2188 /* For CRT on DAC2, don't turn it on if BIOS didn't 2189 enable it, even it's detected. 2190 */ 2191 2192 /* force it to crtc0 */ 2193 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; 2194 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; 2195 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 2196 2197 /* set up the TV DAC */ 2198 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | 2199 RADEON_TV_DAC_STD_MASK | 2200 RADEON_TV_DAC_RDACPD | 2201 RADEON_TV_DAC_GDACPD | 2202 RADEON_TV_DAC_BDACPD | 2203 RADEON_TV_DAC_BGADJ_MASK | 2204 RADEON_TV_DAC_DACADJ_MASK); 2205 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | 2206 RADEON_TV_DAC_NHOLD | 2207 RADEON_TV_DAC_STD_PS2 | 2208 (0x58 << 16)); 2209 2210 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 2211 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 2212 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 2213 } 2214 2215 /* switch PM block to ACPI mode */ 2216 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); 2217 tmp &= ~RADEON_PM_MODE_SEL; 2218 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); 2219 2220 } 2221 2222 /* 2223 * VRAM info 2224 */ 2225 static void r100_vram_get_type(struct radeon_device *rdev) 2226 { 2227 uint32_t tmp; 2228 2229 rdev->mc.vram_is_ddr = false; 2230 if (rdev->flags & RADEON_IS_IGP) 2231 rdev->mc.vram_is_ddr = true; 2232 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) 2233 rdev->mc.vram_is_ddr = true; 2234 if ((rdev->family == CHIP_RV100) || 2235 (rdev->family == CHIP_RS100) || 2236 (rdev->family == CHIP_RS200)) { 2237 tmp = RREG32(RADEON_MEM_CNTL); 2238 if (tmp & RV100_HALF_MODE) { 2239 rdev->mc.vram_width = 32; 2240 } else { 2241 rdev->mc.vram_width = 64; 2242 } 2243 if (rdev->flags & RADEON_SINGLE_CRTC) { 2244 rdev->mc.vram_width /= 4; 2245 rdev->mc.vram_is_ddr = true; 2246 } 2247 } else if (rdev->family <= CHIP_RV280) { 2248 tmp = RREG32(RADEON_MEM_CNTL); 2249 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { 2250 rdev->mc.vram_width = 128; 2251 } else { 2252 rdev->mc.vram_width = 64; 2253 } 2254 } else { 2255 /* newer IGPs */ 2256 rdev->mc.vram_width = 128; 2257 } 2258 } 2259 2260 static u32 r100_get_accessible_vram(struct radeon_device *rdev) 2261 { 2262 u32 aper_size; 2263 u8 byte; 2264 2265 aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2266 2267 /* Set HDP_APER_CNTL only on cards that are known not to be broken, 2268 * that is has the 2nd generation multifunction PCI interface 2269 */ 2270 if (rdev->family == CHIP_RV280 || 2271 rdev->family >= CHIP_RV350) { 2272 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, 2273 ~RADEON_HDP_APER_CNTL); 2274 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); 2275 return aper_size * 2; 2276 } 2277 2278 /* Older cards have all sorts of funny issues to deal with. First 2279 * check if it's a multifunction card by reading the PCI config 2280 * header type... Limit those to one aperture size 2281 */ 2282 pci_read_config_byte(rdev->pdev, 0xe, &byte); 2283 if (byte & 0x80) { 2284 DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); 2285 DRM_INFO("Limiting VRAM to one aperture\n"); 2286 return aper_size; 2287 } 2288 2289 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS 2290 * have set it up. We don't write this as it's broken on some ASICs but 2291 * we expect the BIOS to have done the right thing (might be too optimistic...) 2292 */ 2293 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) 2294 return aper_size * 2; 2295 return aper_size; 2296 } 2297 2298 void r100_vram_init_sizes(struct radeon_device *rdev) 2299 { 2300 u64 config_aper_size; 2301 2302 /* work out accessible VRAM */ 2303 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 2304 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 2305 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); 2306 /* FIXME we don't use the second aperture yet when we could use it */ 2307 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) 2308 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2309 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2310 if (rdev->flags & RADEON_IS_IGP) { 2311 uint32_t tom; 2312 /* read NB_TOM to get the amount of ram stolen for the GPU */ 2313 tom = RREG32(RADEON_NB_TOM); 2314 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); 2315 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2316 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2317 } else { 2318 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 2319 /* Some production boards of m6 will report 0 2320 * if it's 8 MB 2321 */ 2322 if (rdev->mc.real_vram_size == 0) { 2323 rdev->mc.real_vram_size = 8192 * 1024; 2324 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2325 } 2326 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 2327 * Novell bug 204882 + along with lots of ubuntu ones 2328 */ 2329 if (rdev->mc.aper_size > config_aper_size) 2330 config_aper_size = rdev->mc.aper_size; 2331 2332 if (config_aper_size > rdev->mc.real_vram_size) 2333 rdev->mc.mc_vram_size = config_aper_size; 2334 else 2335 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2336 } 2337 } 2338 2339 void r100_vga_set_state(struct radeon_device *rdev, bool state) 2340 { 2341 uint32_t temp; 2342 2343 temp = RREG32(RADEON_CONFIG_CNTL); 2344 if (state == false) { 2345 temp &= ~RADEON_CFG_VGA_RAM_EN; 2346 temp |= RADEON_CFG_VGA_IO_DIS; 2347 } else { 2348 temp &= ~RADEON_CFG_VGA_IO_DIS; 2349 } 2350 WREG32(RADEON_CONFIG_CNTL, temp); 2351 } 2352 2353 void r100_mc_init(struct radeon_device *rdev) 2354 { 2355 u64 base; 2356 2357 r100_vram_get_type(rdev); 2358 r100_vram_init_sizes(rdev); 2359 base = rdev->mc.aper_base; 2360 if (rdev->flags & RADEON_IS_IGP) 2361 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 2362 radeon_vram_location(rdev, &rdev->mc, base); 2363 rdev->mc.gtt_base_align = 0; 2364 if (!(rdev->flags & RADEON_IS_AGP)) 2365 radeon_gtt_location(rdev, &rdev->mc); 2366 radeon_update_bandwidth_info(rdev); 2367 } 2368 2369 2370 /* 2371 * Indirect registers accessor 2372 */ 2373 void r100_pll_errata_after_index(struct radeon_device *rdev) 2374 { 2375 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { 2376 (void)RREG32(RADEON_CLOCK_CNTL_DATA); 2377 (void)RREG32(RADEON_CRTC_GEN_CNTL); 2378 } 2379 } 2380 2381 static void r100_pll_errata_after_data(struct radeon_device *rdev) 2382 { 2383 /* This workarounds is necessary on RV100, RS100 and RS200 chips 2384 * or the chip could hang on a subsequent access 2385 */ 2386 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { 2387 udelay(5000); 2388 } 2389 2390 /* This function is required to workaround a hardware bug in some (all?) 2391 * revisions of the R300. This workaround should be called after every 2392 * CLOCK_CNTL_INDEX register access. If not, register reads afterward 2393 * may not be correct. 2394 */ 2395 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { 2396 uint32_t save, tmp; 2397 2398 save = RREG32(RADEON_CLOCK_CNTL_INDEX); 2399 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2400 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); 2401 tmp = RREG32(RADEON_CLOCK_CNTL_DATA); 2402 WREG32(RADEON_CLOCK_CNTL_INDEX, save); 2403 } 2404 } 2405 2406 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) 2407 { 2408 uint32_t data; 2409 2410 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); 2411 r100_pll_errata_after_index(rdev); 2412 data = RREG32(RADEON_CLOCK_CNTL_DATA); 2413 r100_pll_errata_after_data(rdev); 2414 return data; 2415 } 2416 2417 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2418 { 2419 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); 2420 r100_pll_errata_after_index(rdev); 2421 WREG32(RADEON_CLOCK_CNTL_DATA, v); 2422 r100_pll_errata_after_data(rdev); 2423 } 2424 2425 void r100_set_safe_registers(struct radeon_device *rdev) 2426 { 2427 if (ASIC_IS_RN50(rdev)) { 2428 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; 2429 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); 2430 } else if (rdev->family < CHIP_R200) { 2431 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; 2432 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); 2433 } else { 2434 r200_set_safe_registers(rdev); 2435 } 2436 } 2437 2438 /* 2439 * Debugfs info 2440 */ 2441 #if defined(CONFIG_DEBUG_FS) 2442 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data) 2443 { 2444 struct drm_info_node *node = (struct drm_info_node *) m->private; 2445 struct drm_device *dev = node->minor->dev; 2446 struct radeon_device *rdev = dev->dev_private; 2447 uint32_t reg, value; 2448 unsigned i; 2449 2450 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); 2451 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); 2452 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2453 for (i = 0; i < 64; i++) { 2454 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); 2455 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; 2456 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); 2457 value = RREG32(RADEON_RBBM_CMDFIFO_DATA); 2458 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); 2459 } 2460 return 0; 2461 } 2462 2463 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) 2464 { 2465 struct drm_info_node *node = (struct drm_info_node *) m->private; 2466 struct drm_device *dev = node->minor->dev; 2467 struct radeon_device *rdev = dev->dev_private; 2468 uint32_t rdp, wdp; 2469 unsigned count, i, j; 2470 2471 radeon_ring_free_size(rdev); 2472 rdp = RREG32(RADEON_CP_RB_RPTR); 2473 wdp = RREG32(RADEON_CP_RB_WPTR); 2474 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask; 2475 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2476 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); 2477 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); 2478 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); 2479 seq_printf(m, "%u dwords in ring\n", count); 2480 for (j = 0; j <= count; j++) { 2481 i = (rdp + j) & rdev->cp.ptr_mask; 2482 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); 2483 } 2484 return 0; 2485 } 2486 2487 2488 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data) 2489 { 2490 struct drm_info_node *node = (struct drm_info_node *) m->private; 2491 struct drm_device *dev = node->minor->dev; 2492 struct radeon_device *rdev = dev->dev_private; 2493 uint32_t csq_stat, csq2_stat, tmp; 2494 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; 2495 unsigned i; 2496 2497 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2498 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); 2499 csq_stat = RREG32(RADEON_CP_CSQ_STAT); 2500 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); 2501 r_rptr = (csq_stat >> 0) & 0x3ff; 2502 r_wptr = (csq_stat >> 10) & 0x3ff; 2503 ib1_rptr = (csq_stat >> 20) & 0x3ff; 2504 ib1_wptr = (csq2_stat >> 0) & 0x3ff; 2505 ib2_rptr = (csq2_stat >> 10) & 0x3ff; 2506 ib2_wptr = (csq2_stat >> 20) & 0x3ff; 2507 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); 2508 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); 2509 seq_printf(m, "Ring rptr %u\n", r_rptr); 2510 seq_printf(m, "Ring wptr %u\n", r_wptr); 2511 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); 2512 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); 2513 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); 2514 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); 2515 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms 2516 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ 2517 seq_printf(m, "Ring fifo:\n"); 2518 for (i = 0; i < 256; i++) { 2519 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2520 tmp = RREG32(RADEON_CP_CSQ_DATA); 2521 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); 2522 } 2523 seq_printf(m, "Indirect1 fifo:\n"); 2524 for (i = 256; i <= 512; i++) { 2525 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2526 tmp = RREG32(RADEON_CP_CSQ_DATA); 2527 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); 2528 } 2529 seq_printf(m, "Indirect2 fifo:\n"); 2530 for (i = 640; i < ib1_wptr; i++) { 2531 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2532 tmp = RREG32(RADEON_CP_CSQ_DATA); 2533 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); 2534 } 2535 return 0; 2536 } 2537 2538 static int r100_debugfs_mc_info(struct seq_file *m, void *data) 2539 { 2540 struct drm_info_node *node = (struct drm_info_node *) m->private; 2541 struct drm_device *dev = node->minor->dev; 2542 struct radeon_device *rdev = dev->dev_private; 2543 uint32_t tmp; 2544 2545 tmp = RREG32(RADEON_CONFIG_MEMSIZE); 2546 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); 2547 tmp = RREG32(RADEON_MC_FB_LOCATION); 2548 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); 2549 tmp = RREG32(RADEON_BUS_CNTL); 2550 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 2551 tmp = RREG32(RADEON_MC_AGP_LOCATION); 2552 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 2553 tmp = RREG32(RADEON_AGP_BASE); 2554 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 2555 tmp = RREG32(RADEON_HOST_PATH_CNTL); 2556 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 2557 tmp = RREG32(0x01D0); 2558 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); 2559 tmp = RREG32(RADEON_AIC_LO_ADDR); 2560 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); 2561 tmp = RREG32(RADEON_AIC_HI_ADDR); 2562 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); 2563 tmp = RREG32(0x01E4); 2564 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); 2565 return 0; 2566 } 2567 2568 static struct drm_info_list r100_debugfs_rbbm_list[] = { 2569 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL}, 2570 }; 2571 2572 static struct drm_info_list r100_debugfs_cp_list[] = { 2573 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL}, 2574 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL}, 2575 }; 2576 2577 static struct drm_info_list r100_debugfs_mc_info_list[] = { 2578 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL}, 2579 }; 2580 #endif 2581 2582 int r100_debugfs_rbbm_init(struct radeon_device *rdev) 2583 { 2584 #if defined(CONFIG_DEBUG_FS) 2585 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); 2586 #else 2587 return 0; 2588 #endif 2589 } 2590 2591 int r100_debugfs_cp_init(struct radeon_device *rdev) 2592 { 2593 #if defined(CONFIG_DEBUG_FS) 2594 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); 2595 #else 2596 return 0; 2597 #endif 2598 } 2599 2600 int r100_debugfs_mc_info_init(struct radeon_device *rdev) 2601 { 2602 #if defined(CONFIG_DEBUG_FS) 2603 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); 2604 #else 2605 return 0; 2606 #endif 2607 } 2608 2609 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 2610 uint32_t tiling_flags, uint32_t pitch, 2611 uint32_t offset, uint32_t obj_size) 2612 { 2613 int surf_index = reg * 16; 2614 int flags = 0; 2615 2616 if (rdev->family <= CHIP_RS200) { 2617 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 2618 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 2619 flags |= RADEON_SURF_TILE_COLOR_BOTH; 2620 if (tiling_flags & RADEON_TILING_MACRO) 2621 flags |= RADEON_SURF_TILE_COLOR_MACRO; 2622 } else if (rdev->family <= CHIP_RV280) { 2623 if (tiling_flags & (RADEON_TILING_MACRO)) 2624 flags |= R200_SURF_TILE_COLOR_MACRO; 2625 if (tiling_flags & RADEON_TILING_MICRO) 2626 flags |= R200_SURF_TILE_COLOR_MICRO; 2627 } else { 2628 if (tiling_flags & RADEON_TILING_MACRO) 2629 flags |= R300_SURF_TILE_MACRO; 2630 if (tiling_flags & RADEON_TILING_MICRO) 2631 flags |= R300_SURF_TILE_MICRO; 2632 } 2633 2634 if (tiling_flags & RADEON_TILING_SWAP_16BIT) 2635 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; 2636 if (tiling_flags & RADEON_TILING_SWAP_32BIT) 2637 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; 2638 2639 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */ 2640 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) { 2641 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) 2642 if (ASIC_IS_RN50(rdev)) 2643 pitch /= 16; 2644 } 2645 2646 /* r100/r200 divide by 16 */ 2647 if (rdev->family < CHIP_R300) 2648 flags |= pitch / 16; 2649 else 2650 flags |= pitch / 8; 2651 2652 2653 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); 2654 WREG32(RADEON_SURFACE0_INFO + surf_index, flags); 2655 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); 2656 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); 2657 return 0; 2658 } 2659 2660 void r100_clear_surface_reg(struct radeon_device *rdev, int reg) 2661 { 2662 int surf_index = reg * 16; 2663 WREG32(RADEON_SURFACE0_INFO + surf_index, 0); 2664 } 2665 2666 void r100_bandwidth_update(struct radeon_device *rdev) 2667 { 2668 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; 2669 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; 2670 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; 2671 uint32_t temp, data, mem_trcd, mem_trp, mem_tras; 2672 fixed20_12 memtcas_ff[8] = { 2673 dfixed_init(1), 2674 dfixed_init(2), 2675 dfixed_init(3), 2676 dfixed_init(0), 2677 dfixed_init_half(1), 2678 dfixed_init_half(2), 2679 dfixed_init(0), 2680 }; 2681 fixed20_12 memtcas_rs480_ff[8] = { 2682 dfixed_init(0), 2683 dfixed_init(1), 2684 dfixed_init(2), 2685 dfixed_init(3), 2686 dfixed_init(0), 2687 dfixed_init_half(1), 2688 dfixed_init_half(2), 2689 dfixed_init_half(3), 2690 }; 2691 fixed20_12 memtcas2_ff[8] = { 2692 dfixed_init(0), 2693 dfixed_init(1), 2694 dfixed_init(2), 2695 dfixed_init(3), 2696 dfixed_init(4), 2697 dfixed_init(5), 2698 dfixed_init(6), 2699 dfixed_init(7), 2700 }; 2701 fixed20_12 memtrbs[8] = { 2702 dfixed_init(1), 2703 dfixed_init_half(1), 2704 dfixed_init(2), 2705 dfixed_init_half(2), 2706 dfixed_init(3), 2707 dfixed_init_half(3), 2708 dfixed_init(4), 2709 dfixed_init_half(4) 2710 }; 2711 fixed20_12 memtrbs_r4xx[8] = { 2712 dfixed_init(4), 2713 dfixed_init(5), 2714 dfixed_init(6), 2715 dfixed_init(7), 2716 dfixed_init(8), 2717 dfixed_init(9), 2718 dfixed_init(10), 2719 dfixed_init(11) 2720 }; 2721 fixed20_12 min_mem_eff; 2722 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; 2723 fixed20_12 cur_latency_mclk, cur_latency_sclk; 2724 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, 2725 disp_drain_rate2, read_return_rate; 2726 fixed20_12 time_disp1_drop_priority; 2727 int c; 2728 int cur_size = 16; /* in octawords */ 2729 int critical_point = 0, critical_point2; 2730 /* uint32_t read_return_rate, time_disp1_drop_priority; */ 2731 int stop_req, max_stop_req; 2732 struct drm_display_mode *mode1 = NULL; 2733 struct drm_display_mode *mode2 = NULL; 2734 uint32_t pixel_bytes1 = 0; 2735 uint32_t pixel_bytes2 = 0; 2736 2737 radeon_update_display_priority(rdev); 2738 2739 if (rdev->mode_info.crtcs[0]->base.enabled) { 2740 mode1 = &rdev->mode_info.crtcs[0]->base.mode; 2741 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8; 2742 } 2743 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 2744 if (rdev->mode_info.crtcs[1]->base.enabled) { 2745 mode2 = &rdev->mode_info.crtcs[1]->base.mode; 2746 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8; 2747 } 2748 } 2749 2750 min_mem_eff.full = dfixed_const_8(0); 2751 /* get modes */ 2752 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { 2753 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); 2754 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); 2755 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); 2756 /* check crtc enables */ 2757 if (mode2) 2758 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); 2759 if (mode1) 2760 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); 2761 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); 2762 } 2763 2764 /* 2765 * determine is there is enough bw for current mode 2766 */ 2767 sclk_ff = rdev->pm.sclk; 2768 mclk_ff = rdev->pm.mclk; 2769 2770 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); 2771 temp_ff.full = dfixed_const(temp); 2772 mem_bw.full = dfixed_mul(mclk_ff, temp_ff); 2773 2774 pix_clk.full = 0; 2775 pix_clk2.full = 0; 2776 peak_disp_bw.full = 0; 2777 if (mode1) { 2778 temp_ff.full = dfixed_const(1000); 2779 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ 2780 pix_clk.full = dfixed_div(pix_clk, temp_ff); 2781 temp_ff.full = dfixed_const(pixel_bytes1); 2782 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); 2783 } 2784 if (mode2) { 2785 temp_ff.full = dfixed_const(1000); 2786 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ 2787 pix_clk2.full = dfixed_div(pix_clk2, temp_ff); 2788 temp_ff.full = dfixed_const(pixel_bytes2); 2789 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); 2790 } 2791 2792 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); 2793 if (peak_disp_bw.full >= mem_bw.full) { 2794 DRM_ERROR("You may not have enough display bandwidth for current mode\n" 2795 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); 2796 } 2797 2798 /* Get values from the EXT_MEM_CNTL register...converting its contents. */ 2799 temp = RREG32(RADEON_MEM_TIMING_CNTL); 2800 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ 2801 mem_trcd = ((temp >> 2) & 0x3) + 1; 2802 mem_trp = ((temp & 0x3)) + 1; 2803 mem_tras = ((temp & 0x70) >> 4) + 1; 2804 } else if (rdev->family == CHIP_R300 || 2805 rdev->family == CHIP_R350) { /* r300, r350 */ 2806 mem_trcd = (temp & 0x7) + 1; 2807 mem_trp = ((temp >> 8) & 0x7) + 1; 2808 mem_tras = ((temp >> 11) & 0xf) + 4; 2809 } else if (rdev->family == CHIP_RV350 || 2810 rdev->family <= CHIP_RV380) { 2811 /* rv3x0 */ 2812 mem_trcd = (temp & 0x7) + 3; 2813 mem_trp = ((temp >> 8) & 0x7) + 3; 2814 mem_tras = ((temp >> 11) & 0xf) + 6; 2815 } else if (rdev->family == CHIP_R420 || 2816 rdev->family == CHIP_R423 || 2817 rdev->family == CHIP_RV410) { 2818 /* r4xx */ 2819 mem_trcd = (temp & 0xf) + 3; 2820 if (mem_trcd > 15) 2821 mem_trcd = 15; 2822 mem_trp = ((temp >> 8) & 0xf) + 3; 2823 if (mem_trp > 15) 2824 mem_trp = 15; 2825 mem_tras = ((temp >> 12) & 0x1f) + 6; 2826 if (mem_tras > 31) 2827 mem_tras = 31; 2828 } else { /* RV200, R200 */ 2829 mem_trcd = (temp & 0x7) + 1; 2830 mem_trp = ((temp >> 8) & 0x7) + 1; 2831 mem_tras = ((temp >> 12) & 0xf) + 4; 2832 } 2833 /* convert to FF */ 2834 trcd_ff.full = dfixed_const(mem_trcd); 2835 trp_ff.full = dfixed_const(mem_trp); 2836 tras_ff.full = dfixed_const(mem_tras); 2837 2838 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ 2839 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 2840 data = (temp & (7 << 20)) >> 20; 2841 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { 2842 if (rdev->family == CHIP_RS480) /* don't think rs400 */ 2843 tcas_ff = memtcas_rs480_ff[data]; 2844 else 2845 tcas_ff = memtcas_ff[data]; 2846 } else 2847 tcas_ff = memtcas2_ff[data]; 2848 2849 if (rdev->family == CHIP_RS400 || 2850 rdev->family == CHIP_RS480) { 2851 /* extra cas latency stored in bits 23-25 0-4 clocks */ 2852 data = (temp >> 23) & 0x7; 2853 if (data < 5) 2854 tcas_ff.full += dfixed_const(data); 2855 } 2856 2857 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { 2858 /* on the R300, Tcas is included in Trbs. 2859 */ 2860 temp = RREG32(RADEON_MEM_CNTL); 2861 data = (R300_MEM_NUM_CHANNELS_MASK & temp); 2862 if (data == 1) { 2863 if (R300_MEM_USE_CD_CH_ONLY & temp) { 2864 temp = RREG32(R300_MC_IND_INDEX); 2865 temp &= ~R300_MC_IND_ADDR_MASK; 2866 temp |= R300_MC_READ_CNTL_CD_mcind; 2867 WREG32(R300_MC_IND_INDEX, temp); 2868 temp = RREG32(R300_MC_IND_DATA); 2869 data = (R300_MEM_RBS_POSITION_C_MASK & temp); 2870 } else { 2871 temp = RREG32(R300_MC_READ_CNTL_AB); 2872 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 2873 } 2874 } else { 2875 temp = RREG32(R300_MC_READ_CNTL_AB); 2876 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 2877 } 2878 if (rdev->family == CHIP_RV410 || 2879 rdev->family == CHIP_R420 || 2880 rdev->family == CHIP_R423) 2881 trbs_ff = memtrbs_r4xx[data]; 2882 else 2883 trbs_ff = memtrbs[data]; 2884 tcas_ff.full += trbs_ff.full; 2885 } 2886 2887 sclk_eff_ff.full = sclk_ff.full; 2888 2889 if (rdev->flags & RADEON_IS_AGP) { 2890 fixed20_12 agpmode_ff; 2891 agpmode_ff.full = dfixed_const(radeon_agpmode); 2892 temp_ff.full = dfixed_const_666(16); 2893 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); 2894 } 2895 /* TODO PCIE lanes may affect this - agpmode == 16?? */ 2896 2897 if (ASIC_IS_R300(rdev)) { 2898 sclk_delay_ff.full = dfixed_const(250); 2899 } else { 2900 if ((rdev->family == CHIP_RV100) || 2901 rdev->flags & RADEON_IS_IGP) { 2902 if (rdev->mc.vram_is_ddr) 2903 sclk_delay_ff.full = dfixed_const(41); 2904 else 2905 sclk_delay_ff.full = dfixed_const(33); 2906 } else { 2907 if (rdev->mc.vram_width == 128) 2908 sclk_delay_ff.full = dfixed_const(57); 2909 else 2910 sclk_delay_ff.full = dfixed_const(41); 2911 } 2912 } 2913 2914 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); 2915 2916 if (rdev->mc.vram_is_ddr) { 2917 if (rdev->mc.vram_width == 32) { 2918 k1.full = dfixed_const(40); 2919 c = 3; 2920 } else { 2921 k1.full = dfixed_const(20); 2922 c = 1; 2923 } 2924 } else { 2925 k1.full = dfixed_const(40); 2926 c = 3; 2927 } 2928 2929 temp_ff.full = dfixed_const(2); 2930 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); 2931 temp_ff.full = dfixed_const(c); 2932 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); 2933 temp_ff.full = dfixed_const(4); 2934 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); 2935 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); 2936 mc_latency_mclk.full += k1.full; 2937 2938 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); 2939 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); 2940 2941 /* 2942 HW cursor time assuming worst case of full size colour cursor. 2943 */ 2944 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); 2945 temp_ff.full += trcd_ff.full; 2946 if (temp_ff.full < tras_ff.full) 2947 temp_ff.full = tras_ff.full; 2948 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); 2949 2950 temp_ff.full = dfixed_const(cur_size); 2951 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); 2952 /* 2953 Find the total latency for the display data. 2954 */ 2955 disp_latency_overhead.full = dfixed_const(8); 2956 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); 2957 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; 2958 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; 2959 2960 if (mc_latency_mclk.full > mc_latency_sclk.full) 2961 disp_latency.full = mc_latency_mclk.full; 2962 else 2963 disp_latency.full = mc_latency_sclk.full; 2964 2965 /* setup Max GRPH_STOP_REQ default value */ 2966 if (ASIC_IS_RV100(rdev)) 2967 max_stop_req = 0x5c; 2968 else 2969 max_stop_req = 0x7c; 2970 2971 if (mode1) { 2972 /* CRTC1 2973 Set GRPH_BUFFER_CNTL register using h/w defined optimal values. 2974 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] 2975 */ 2976 stop_req = mode1->hdisplay * pixel_bytes1 / 16; 2977 2978 if (stop_req > max_stop_req) 2979 stop_req = max_stop_req; 2980 2981 /* 2982 Find the drain rate of the display buffer. 2983 */ 2984 temp_ff.full = dfixed_const((16/pixel_bytes1)); 2985 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); 2986 2987 /* 2988 Find the critical point of the display buffer. 2989 */ 2990 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); 2991 crit_point_ff.full += dfixed_const_half(0); 2992 2993 critical_point = dfixed_trunc(crit_point_ff); 2994 2995 if (rdev->disp_priority == 2) { 2996 critical_point = 0; 2997 } 2998 2999 /* 3000 The critical point should never be above max_stop_req-4. Setting 3001 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. 3002 */ 3003 if (max_stop_req - critical_point < 4) 3004 critical_point = 0; 3005 3006 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { 3007 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ 3008 critical_point = 0x10; 3009 } 3010 3011 temp = RREG32(RADEON_GRPH_BUFFER_CNTL); 3012 temp &= ~(RADEON_GRPH_STOP_REQ_MASK); 3013 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3014 temp &= ~(RADEON_GRPH_START_REQ_MASK); 3015 if ((rdev->family == CHIP_R350) && 3016 (stop_req > 0x15)) { 3017 stop_req -= 0x10; 3018 } 3019 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3020 temp |= RADEON_GRPH_BUFFER_SIZE; 3021 temp &= ~(RADEON_GRPH_CRITICAL_CNTL | 3022 RADEON_GRPH_CRITICAL_AT_SOF | 3023 RADEON_GRPH_STOP_CNTL); 3024 /* 3025 Write the result into the register. 3026 */ 3027 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3028 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3029 3030 #if 0 3031 if ((rdev->family == CHIP_RS400) || 3032 (rdev->family == CHIP_RS480)) { 3033 /* attempt to program RS400 disp regs correctly ??? */ 3034 temp = RREG32(RS400_DISP1_REG_CNTL); 3035 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | 3036 RS400_DISP1_STOP_REQ_LEVEL_MASK); 3037 WREG32(RS400_DISP1_REQ_CNTL1, (temp | 3038 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3039 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3040 temp = RREG32(RS400_DMIF_MEM_CNTL1); 3041 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | 3042 RS400_DISP1_CRITICAL_POINT_STOP_MASK); 3043 WREG32(RS400_DMIF_MEM_CNTL1, (temp | 3044 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | 3045 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); 3046 } 3047 #endif 3048 3049 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n", 3050 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ 3051 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); 3052 } 3053 3054 if (mode2) { 3055 u32 grph2_cntl; 3056 stop_req = mode2->hdisplay * pixel_bytes2 / 16; 3057 3058 if (stop_req > max_stop_req) 3059 stop_req = max_stop_req; 3060 3061 /* 3062 Find the drain rate of the display buffer. 3063 */ 3064 temp_ff.full = dfixed_const((16/pixel_bytes2)); 3065 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); 3066 3067 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); 3068 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); 3069 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3070 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); 3071 if ((rdev->family == CHIP_R350) && 3072 (stop_req > 0x15)) { 3073 stop_req -= 0x10; 3074 } 3075 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3076 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; 3077 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | 3078 RADEON_GRPH_CRITICAL_AT_SOF | 3079 RADEON_GRPH_STOP_CNTL); 3080 3081 if ((rdev->family == CHIP_RS100) || 3082 (rdev->family == CHIP_RS200)) 3083 critical_point2 = 0; 3084 else { 3085 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; 3086 temp_ff.full = dfixed_const(temp); 3087 temp_ff.full = dfixed_mul(mclk_ff, temp_ff); 3088 if (sclk_ff.full < temp_ff.full) 3089 temp_ff.full = sclk_ff.full; 3090 3091 read_return_rate.full = temp_ff.full; 3092 3093 if (mode1) { 3094 temp_ff.full = read_return_rate.full - disp_drain_rate.full; 3095 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); 3096 } else { 3097 time_disp1_drop_priority.full = 0; 3098 } 3099 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; 3100 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); 3101 crit_point_ff.full += dfixed_const_half(0); 3102 3103 critical_point2 = dfixed_trunc(crit_point_ff); 3104 3105 if (rdev->disp_priority == 2) { 3106 critical_point2 = 0; 3107 } 3108 3109 if (max_stop_req - critical_point2 < 4) 3110 critical_point2 = 0; 3111 3112 } 3113 3114 if (critical_point2 == 0 && rdev->family == CHIP_R300) { 3115 /* some R300 cards have problem with this set to 0 */ 3116 critical_point2 = 0x10; 3117 } 3118 3119 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3120 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3121 3122 if ((rdev->family == CHIP_RS400) || 3123 (rdev->family == CHIP_RS480)) { 3124 #if 0 3125 /* attempt to program RS400 disp2 regs correctly ??? */ 3126 temp = RREG32(RS400_DISP2_REQ_CNTL1); 3127 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | 3128 RS400_DISP2_STOP_REQ_LEVEL_MASK); 3129 WREG32(RS400_DISP2_REQ_CNTL1, (temp | 3130 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3131 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3132 temp = RREG32(RS400_DISP2_REQ_CNTL2); 3133 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | 3134 RS400_DISP2_CRITICAL_POINT_STOP_MASK); 3135 WREG32(RS400_DISP2_REQ_CNTL2, (temp | 3136 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | 3137 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); 3138 #endif 3139 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); 3140 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); 3141 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); 3142 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); 3143 } 3144 3145 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n", 3146 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); 3147 } 3148 } 3149 3150 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t) 3151 { 3152 DRM_ERROR("pitch %d\n", t->pitch); 3153 DRM_ERROR("use_pitch %d\n", t->use_pitch); 3154 DRM_ERROR("width %d\n", t->width); 3155 DRM_ERROR("width_11 %d\n", t->width_11); 3156 DRM_ERROR("height %d\n", t->height); 3157 DRM_ERROR("height_11 %d\n", t->height_11); 3158 DRM_ERROR("num levels %d\n", t->num_levels); 3159 DRM_ERROR("depth %d\n", t->txdepth); 3160 DRM_ERROR("bpp %d\n", t->cpp); 3161 DRM_ERROR("coordinate type %d\n", t->tex_coord_type); 3162 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); 3163 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); 3164 DRM_ERROR("compress format %d\n", t->compress_format); 3165 } 3166 3167 static int r100_track_compress_size(int compress_format, int w, int h) 3168 { 3169 int block_width, block_height, block_bytes; 3170 int wblocks, hblocks; 3171 int min_wblocks; 3172 int sz; 3173 3174 block_width = 4; 3175 block_height = 4; 3176 3177 switch (compress_format) { 3178 case R100_TRACK_COMP_DXT1: 3179 block_bytes = 8; 3180 min_wblocks = 4; 3181 break; 3182 default: 3183 case R100_TRACK_COMP_DXT35: 3184 block_bytes = 16; 3185 min_wblocks = 2; 3186 break; 3187 } 3188 3189 hblocks = (h + block_height - 1) / block_height; 3190 wblocks = (w + block_width - 1) / block_width; 3191 if (wblocks < min_wblocks) 3192 wblocks = min_wblocks; 3193 sz = wblocks * hblocks * block_bytes; 3194 return sz; 3195 } 3196 3197 static int r100_cs_track_cube(struct radeon_device *rdev, 3198 struct r100_cs_track *track, unsigned idx) 3199 { 3200 unsigned face, w, h; 3201 struct radeon_bo *cube_robj; 3202 unsigned long size; 3203 unsigned compress_format = track->textures[idx].compress_format; 3204 3205 for (face = 0; face < 5; face++) { 3206 cube_robj = track->textures[idx].cube_info[face].robj; 3207 w = track->textures[idx].cube_info[face].width; 3208 h = track->textures[idx].cube_info[face].height; 3209 3210 if (compress_format) { 3211 size = r100_track_compress_size(compress_format, w, h); 3212 } else 3213 size = w * h; 3214 size *= track->textures[idx].cpp; 3215 3216 size += track->textures[idx].cube_info[face].offset; 3217 3218 if (size > radeon_bo_size(cube_robj)) { 3219 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", 3220 size, radeon_bo_size(cube_robj)); 3221 r100_cs_track_texture_print(&track->textures[idx]); 3222 return -1; 3223 } 3224 } 3225 return 0; 3226 } 3227 3228 static int r100_cs_track_texture_check(struct radeon_device *rdev, 3229 struct r100_cs_track *track) 3230 { 3231 struct radeon_bo *robj; 3232 unsigned long size; 3233 unsigned u, i, w, h, d; 3234 int ret; 3235 3236 for (u = 0; u < track->num_texture; u++) { 3237 if (!track->textures[u].enabled) 3238 continue; 3239 if (track->textures[u].lookup_disable) 3240 continue; 3241 robj = track->textures[u].robj; 3242 if (robj == NULL) { 3243 DRM_ERROR("No texture bound to unit %u\n", u); 3244 return -EINVAL; 3245 } 3246 size = 0; 3247 for (i = 0; i <= track->textures[u].num_levels; i++) { 3248 if (track->textures[u].use_pitch) { 3249 if (rdev->family < CHIP_R300) 3250 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); 3251 else 3252 w = track->textures[u].pitch / (1 << i); 3253 } else { 3254 w = track->textures[u].width; 3255 if (rdev->family >= CHIP_RV515) 3256 w |= track->textures[u].width_11; 3257 w = w / (1 << i); 3258 if (track->textures[u].roundup_w) 3259 w = roundup_pow_of_two(w); 3260 } 3261 h = track->textures[u].height; 3262 if (rdev->family >= CHIP_RV515) 3263 h |= track->textures[u].height_11; 3264 h = h / (1 << i); 3265 if (track->textures[u].roundup_h) 3266 h = roundup_pow_of_two(h); 3267 if (track->textures[u].tex_coord_type == 1) { 3268 d = (1 << track->textures[u].txdepth) / (1 << i); 3269 if (!d) 3270 d = 1; 3271 } else { 3272 d = 1; 3273 } 3274 if (track->textures[u].compress_format) { 3275 3276 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; 3277 /* compressed textures are block based */ 3278 } else 3279 size += w * h * d; 3280 } 3281 size *= track->textures[u].cpp; 3282 3283 switch (track->textures[u].tex_coord_type) { 3284 case 0: 3285 case 1: 3286 break; 3287 case 2: 3288 if (track->separate_cube) { 3289 ret = r100_cs_track_cube(rdev, track, u); 3290 if (ret) 3291 return ret; 3292 } else 3293 size *= 6; 3294 break; 3295 default: 3296 DRM_ERROR("Invalid texture coordinate type %u for unit " 3297 "%u\n", track->textures[u].tex_coord_type, u); 3298 return -EINVAL; 3299 } 3300 if (size > radeon_bo_size(robj)) { 3301 DRM_ERROR("Texture of unit %u needs %lu bytes but is " 3302 "%lu\n", u, size, radeon_bo_size(robj)); 3303 r100_cs_track_texture_print(&track->textures[u]); 3304 return -EINVAL; 3305 } 3306 } 3307 return 0; 3308 } 3309 3310 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) 3311 { 3312 unsigned i; 3313 unsigned long size; 3314 unsigned prim_walk; 3315 unsigned nverts; 3316 unsigned num_cb = track->cb_dirty ? track->num_cb : 0; 3317 3318 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && 3319 !track->blend_read_enable) 3320 num_cb = 0; 3321 3322 for (i = 0; i < num_cb; i++) { 3323 if (track->cb[i].robj == NULL) { 3324 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 3325 return -EINVAL; 3326 } 3327 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; 3328 size += track->cb[i].offset; 3329 if (size > radeon_bo_size(track->cb[i].robj)) { 3330 DRM_ERROR("[drm] Buffer too small for color buffer %d " 3331 "(need %lu have %lu) !\n", i, size, 3332 radeon_bo_size(track->cb[i].robj)); 3333 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", 3334 i, track->cb[i].pitch, track->cb[i].cpp, 3335 track->cb[i].offset, track->maxy); 3336 return -EINVAL; 3337 } 3338 } 3339 track->cb_dirty = false; 3340 3341 if (track->zb_dirty && track->z_enabled) { 3342 if (track->zb.robj == NULL) { 3343 DRM_ERROR("[drm] No buffer for z buffer !\n"); 3344 return -EINVAL; 3345 } 3346 size = track->zb.pitch * track->zb.cpp * track->maxy; 3347 size += track->zb.offset; 3348 if (size > radeon_bo_size(track->zb.robj)) { 3349 DRM_ERROR("[drm] Buffer too small for z buffer " 3350 "(need %lu have %lu) !\n", size, 3351 radeon_bo_size(track->zb.robj)); 3352 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", 3353 track->zb.pitch, track->zb.cpp, 3354 track->zb.offset, track->maxy); 3355 return -EINVAL; 3356 } 3357 } 3358 track->zb_dirty = false; 3359 3360 if (track->aa_dirty && track->aaresolve) { 3361 if (track->aa.robj == NULL) { 3362 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i); 3363 return -EINVAL; 3364 } 3365 /* I believe the format comes from colorbuffer0. */ 3366 size = track->aa.pitch * track->cb[0].cpp * track->maxy; 3367 size += track->aa.offset; 3368 if (size > radeon_bo_size(track->aa.robj)) { 3369 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d " 3370 "(need %lu have %lu) !\n", i, size, 3371 radeon_bo_size(track->aa.robj)); 3372 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n", 3373 i, track->aa.pitch, track->cb[0].cpp, 3374 track->aa.offset, track->maxy); 3375 return -EINVAL; 3376 } 3377 } 3378 track->aa_dirty = false; 3379 3380 prim_walk = (track->vap_vf_cntl >> 4) & 0x3; 3381 if (track->vap_vf_cntl & (1 << 14)) { 3382 nverts = track->vap_alt_nverts; 3383 } else { 3384 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; 3385 } 3386 switch (prim_walk) { 3387 case 1: 3388 for (i = 0; i < track->num_arrays; i++) { 3389 size = track->arrays[i].esize * track->max_indx * 4; 3390 if (track->arrays[i].robj == NULL) { 3391 DRM_ERROR("(PW %u) Vertex array %u no buffer " 3392 "bound\n", prim_walk, i); 3393 return -EINVAL; 3394 } 3395 if (size > radeon_bo_size(track->arrays[i].robj)) { 3396 dev_err(rdev->dev, "(PW %u) Vertex array %u " 3397 "need %lu dwords have %lu dwords\n", 3398 prim_walk, i, size >> 2, 3399 radeon_bo_size(track->arrays[i].robj) 3400 >> 2); 3401 DRM_ERROR("Max indices %u\n", track->max_indx); 3402 return -EINVAL; 3403 } 3404 } 3405 break; 3406 case 2: 3407 for (i = 0; i < track->num_arrays; i++) { 3408 size = track->arrays[i].esize * (nverts - 1) * 4; 3409 if (track->arrays[i].robj == NULL) { 3410 DRM_ERROR("(PW %u) Vertex array %u no buffer " 3411 "bound\n", prim_walk, i); 3412 return -EINVAL; 3413 } 3414 if (size > radeon_bo_size(track->arrays[i].robj)) { 3415 dev_err(rdev->dev, "(PW %u) Vertex array %u " 3416 "need %lu dwords have %lu dwords\n", 3417 prim_walk, i, size >> 2, 3418 radeon_bo_size(track->arrays[i].robj) 3419 >> 2); 3420 return -EINVAL; 3421 } 3422 } 3423 break; 3424 case 3: 3425 size = track->vtx_size * nverts; 3426 if (size != track->immd_dwords) { 3427 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", 3428 track->immd_dwords, size); 3429 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", 3430 nverts, track->vtx_size); 3431 return -EINVAL; 3432 } 3433 break; 3434 default: 3435 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", 3436 prim_walk); 3437 return -EINVAL; 3438 } 3439 3440 if (track->tex_dirty) { 3441 track->tex_dirty = false; 3442 return r100_cs_track_texture_check(rdev, track); 3443 } 3444 return 0; 3445 } 3446 3447 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) 3448 { 3449 unsigned i, face; 3450 3451 track->cb_dirty = true; 3452 track->zb_dirty = true; 3453 track->tex_dirty = true; 3454 track->aa_dirty = true; 3455 3456 if (rdev->family < CHIP_R300) { 3457 track->num_cb = 1; 3458 if (rdev->family <= CHIP_RS200) 3459 track->num_texture = 3; 3460 else 3461 track->num_texture = 6; 3462 track->maxy = 2048; 3463 track->separate_cube = 1; 3464 } else { 3465 track->num_cb = 4; 3466 track->num_texture = 16; 3467 track->maxy = 4096; 3468 track->separate_cube = 0; 3469 track->aaresolve = false; 3470 track->aa.robj = NULL; 3471 } 3472 3473 for (i = 0; i < track->num_cb; i++) { 3474 track->cb[i].robj = NULL; 3475 track->cb[i].pitch = 8192; 3476 track->cb[i].cpp = 16; 3477 track->cb[i].offset = 0; 3478 } 3479 track->z_enabled = true; 3480 track->zb.robj = NULL; 3481 track->zb.pitch = 8192; 3482 track->zb.cpp = 4; 3483 track->zb.offset = 0; 3484 track->vtx_size = 0x7F; 3485 track->immd_dwords = 0xFFFFFFFFUL; 3486 track->num_arrays = 11; 3487 track->max_indx = 0x00FFFFFFUL; 3488 for (i = 0; i < track->num_arrays; i++) { 3489 track->arrays[i].robj = NULL; 3490 track->arrays[i].esize = 0x7F; 3491 } 3492 for (i = 0; i < track->num_texture; i++) { 3493 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 3494 track->textures[i].pitch = 16536; 3495 track->textures[i].width = 16536; 3496 track->textures[i].height = 16536; 3497 track->textures[i].width_11 = 1 << 11; 3498 track->textures[i].height_11 = 1 << 11; 3499 track->textures[i].num_levels = 12; 3500 if (rdev->family <= CHIP_RS200) { 3501 track->textures[i].tex_coord_type = 0; 3502 track->textures[i].txdepth = 0; 3503 } else { 3504 track->textures[i].txdepth = 16; 3505 track->textures[i].tex_coord_type = 1; 3506 } 3507 track->textures[i].cpp = 64; 3508 track->textures[i].robj = NULL; 3509 /* CS IB emission code makes sure texture unit are disabled */ 3510 track->textures[i].enabled = false; 3511 track->textures[i].lookup_disable = false; 3512 track->textures[i].roundup_w = true; 3513 track->textures[i].roundup_h = true; 3514 if (track->separate_cube) 3515 for (face = 0; face < 5; face++) { 3516 track->textures[i].cube_info[face].robj = NULL; 3517 track->textures[i].cube_info[face].width = 16536; 3518 track->textures[i].cube_info[face].height = 16536; 3519 track->textures[i].cube_info[face].offset = 0; 3520 } 3521 } 3522 } 3523 3524 int r100_ring_test(struct radeon_device *rdev) 3525 { 3526 uint32_t scratch; 3527 uint32_t tmp = 0; 3528 unsigned i; 3529 int r; 3530 3531 r = radeon_scratch_get(rdev, &scratch); 3532 if (r) { 3533 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 3534 return r; 3535 } 3536 WREG32(scratch, 0xCAFEDEAD); 3537 r = radeon_ring_lock(rdev, 2); 3538 if (r) { 3539 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 3540 radeon_scratch_free(rdev, scratch); 3541 return r; 3542 } 3543 radeon_ring_write(rdev, PACKET0(scratch, 0)); 3544 radeon_ring_write(rdev, 0xDEADBEEF); 3545 radeon_ring_unlock_commit(rdev); 3546 for (i = 0; i < rdev->usec_timeout; i++) { 3547 tmp = RREG32(scratch); 3548 if (tmp == 0xDEADBEEF) { 3549 break; 3550 } 3551 DRM_UDELAY(1); 3552 } 3553 if (i < rdev->usec_timeout) { 3554 DRM_INFO("ring test succeeded in %d usecs\n", i); 3555 } else { 3556 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", 3557 scratch, tmp); 3558 r = -EINVAL; 3559 } 3560 radeon_scratch_free(rdev, scratch); 3561 return r; 3562 } 3563 3564 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3565 { 3566 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1)); 3567 radeon_ring_write(rdev, ib->gpu_addr); 3568 radeon_ring_write(rdev, ib->length_dw); 3569 } 3570 3571 int r100_ib_test(struct radeon_device *rdev) 3572 { 3573 struct radeon_ib *ib; 3574 uint32_t scratch; 3575 uint32_t tmp = 0; 3576 unsigned i; 3577 int r; 3578 3579 r = radeon_scratch_get(rdev, &scratch); 3580 if (r) { 3581 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3582 return r; 3583 } 3584 WREG32(scratch, 0xCAFEDEAD); 3585 r = radeon_ib_get(rdev, &ib); 3586 if (r) { 3587 return r; 3588 } 3589 ib->ptr[0] = PACKET0(scratch, 0); 3590 ib->ptr[1] = 0xDEADBEEF; 3591 ib->ptr[2] = PACKET2(0); 3592 ib->ptr[3] = PACKET2(0); 3593 ib->ptr[4] = PACKET2(0); 3594 ib->ptr[5] = PACKET2(0); 3595 ib->ptr[6] = PACKET2(0); 3596 ib->ptr[7] = PACKET2(0); 3597 ib->length_dw = 8; 3598 r = radeon_ib_schedule(rdev, ib); 3599 if (r) { 3600 radeon_scratch_free(rdev, scratch); 3601 radeon_ib_free(rdev, &ib); 3602 return r; 3603 } 3604 r = radeon_fence_wait(ib->fence, false); 3605 if (r) { 3606 return r; 3607 } 3608 for (i = 0; i < rdev->usec_timeout; i++) { 3609 tmp = RREG32(scratch); 3610 if (tmp == 0xDEADBEEF) { 3611 break; 3612 } 3613 DRM_UDELAY(1); 3614 } 3615 if (i < rdev->usec_timeout) { 3616 DRM_INFO("ib test succeeded in %u usecs\n", i); 3617 } else { 3618 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3619 scratch, tmp); 3620 r = -EINVAL; 3621 } 3622 radeon_scratch_free(rdev, scratch); 3623 radeon_ib_free(rdev, &ib); 3624 return r; 3625 } 3626 3627 void r100_ib_fini(struct radeon_device *rdev) 3628 { 3629 radeon_ib_pool_fini(rdev); 3630 } 3631 3632 int r100_ib_init(struct radeon_device *rdev) 3633 { 3634 int r; 3635 3636 r = radeon_ib_pool_init(rdev); 3637 if (r) { 3638 dev_err(rdev->dev, "failed initializing IB pool (%d).\n", r); 3639 r100_ib_fini(rdev); 3640 return r; 3641 } 3642 r = r100_ib_test(rdev); 3643 if (r) { 3644 dev_err(rdev->dev, "failed testing IB (%d).\n", r); 3645 r100_ib_fini(rdev); 3646 return r; 3647 } 3648 return 0; 3649 } 3650 3651 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) 3652 { 3653 /* Shutdown CP we shouldn't need to do that but better be safe than 3654 * sorry 3655 */ 3656 rdev->cp.ready = false; 3657 WREG32(R_000740_CP_CSQ_CNTL, 0); 3658 3659 /* Save few CRTC registers */ 3660 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); 3661 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); 3662 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); 3663 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); 3664 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3665 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); 3666 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); 3667 } 3668 3669 /* Disable VGA aperture access */ 3670 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); 3671 /* Disable cursor, overlay, crtc */ 3672 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); 3673 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | 3674 S_000054_CRTC_DISPLAY_DIS(1)); 3675 WREG32(R_000050_CRTC_GEN_CNTL, 3676 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | 3677 S_000050_CRTC_DISP_REQ_EN_B(1)); 3678 WREG32(R_000420_OV0_SCALE_CNTL, 3679 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); 3680 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); 3681 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3682 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | 3683 S_000360_CUR2_LOCK(1)); 3684 WREG32(R_0003F8_CRTC2_GEN_CNTL, 3685 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | 3686 S_0003F8_CRTC2_DISPLAY_DIS(1) | 3687 S_0003F8_CRTC2_DISP_REQ_EN_B(1)); 3688 WREG32(R_000360_CUR2_OFFSET, 3689 C_000360_CUR2_LOCK & save->CUR2_OFFSET); 3690 } 3691 } 3692 3693 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) 3694 { 3695 /* Update base address for crtc */ 3696 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3697 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3698 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3699 } 3700 /* Restore CRTC registers */ 3701 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); 3702 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); 3703 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); 3704 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3705 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); 3706 } 3707 } 3708 3709 void r100_vga_render_disable(struct radeon_device *rdev) 3710 { 3711 u32 tmp; 3712 3713 tmp = RREG8(R_0003C2_GENMO_WT); 3714 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); 3715 } 3716 3717 static void r100_debugfs(struct radeon_device *rdev) 3718 { 3719 int r; 3720 3721 r = r100_debugfs_mc_info_init(rdev); 3722 if (r) 3723 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 3724 } 3725 3726 static void r100_mc_program(struct radeon_device *rdev) 3727 { 3728 struct r100_mc_save save; 3729 3730 /* Stops all mc clients */ 3731 r100_mc_stop(rdev, &save); 3732 if (rdev->flags & RADEON_IS_AGP) { 3733 WREG32(R_00014C_MC_AGP_LOCATION, 3734 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 3735 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 3736 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 3737 if (rdev->family > CHIP_RV200) 3738 WREG32(R_00015C_AGP_BASE_2, 3739 upper_32_bits(rdev->mc.agp_base) & 0xff); 3740 } else { 3741 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 3742 WREG32(R_000170_AGP_BASE, 0); 3743 if (rdev->family > CHIP_RV200) 3744 WREG32(R_00015C_AGP_BASE_2, 0); 3745 } 3746 /* Wait for mc idle */ 3747 if (r100_mc_wait_for_idle(rdev)) 3748 dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); 3749 /* Program MC, should be a 32bits limited address space */ 3750 WREG32(R_000148_MC_FB_LOCATION, 3751 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 3752 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 3753 r100_mc_resume(rdev, &save); 3754 } 3755 3756 void r100_clock_startup(struct radeon_device *rdev) 3757 { 3758 u32 tmp; 3759 3760 if (radeon_dynclks != -1 && radeon_dynclks) 3761 radeon_legacy_set_clock_gating(rdev, 1); 3762 /* We need to force on some of the block */ 3763 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 3764 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 3765 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) 3766 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); 3767 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 3768 } 3769 3770 static int r100_startup(struct radeon_device *rdev) 3771 { 3772 int r; 3773 3774 /* set common regs */ 3775 r100_set_common_regs(rdev); 3776 /* program mc */ 3777 r100_mc_program(rdev); 3778 /* Resume clock */ 3779 r100_clock_startup(rdev); 3780 /* Initialize GART (initialize after TTM so we can allocate 3781 * memory through TTM but finalize after TTM) */ 3782 r100_enable_bm(rdev); 3783 if (rdev->flags & RADEON_IS_PCI) { 3784 r = r100_pci_gart_enable(rdev); 3785 if (r) 3786 return r; 3787 } 3788 3789 /* allocate wb buffer */ 3790 r = radeon_wb_init(rdev); 3791 if (r) 3792 return r; 3793 3794 /* Enable IRQ */ 3795 r100_irq_set(rdev); 3796 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 3797 /* 1M ring buffer */ 3798 r = r100_cp_init(rdev, 1024 * 1024); 3799 if (r) { 3800 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 3801 return r; 3802 } 3803 r = r100_ib_init(rdev); 3804 if (r) { 3805 dev_err(rdev->dev, "failed initializing IB (%d).\n", r); 3806 return r; 3807 } 3808 return 0; 3809 } 3810 3811 int r100_resume(struct radeon_device *rdev) 3812 { 3813 /* Make sur GART are not working */ 3814 if (rdev->flags & RADEON_IS_PCI) 3815 r100_pci_gart_disable(rdev); 3816 /* Resume clock before doing reset */ 3817 r100_clock_startup(rdev); 3818 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3819 if (radeon_asic_reset(rdev)) { 3820 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3821 RREG32(R_000E40_RBBM_STATUS), 3822 RREG32(R_0007C0_CP_STAT)); 3823 } 3824 /* post */ 3825 radeon_combios_asic_init(rdev->ddev); 3826 /* Resume clock after posting */ 3827 r100_clock_startup(rdev); 3828 /* Initialize surface registers */ 3829 radeon_surface_init(rdev); 3830 return r100_startup(rdev); 3831 } 3832 3833 int r100_suspend(struct radeon_device *rdev) 3834 { 3835 r100_cp_disable(rdev); 3836 radeon_wb_disable(rdev); 3837 r100_irq_disable(rdev); 3838 if (rdev->flags & RADEON_IS_PCI) 3839 r100_pci_gart_disable(rdev); 3840 return 0; 3841 } 3842 3843 void r100_fini(struct radeon_device *rdev) 3844 { 3845 r100_cp_fini(rdev); 3846 radeon_wb_fini(rdev); 3847 r100_ib_fini(rdev); 3848 radeon_gem_fini(rdev); 3849 if (rdev->flags & RADEON_IS_PCI) 3850 r100_pci_gart_fini(rdev); 3851 radeon_agp_fini(rdev); 3852 radeon_irq_kms_fini(rdev); 3853 radeon_fence_driver_fini(rdev); 3854 radeon_bo_fini(rdev); 3855 radeon_atombios_fini(rdev); 3856 kfree(rdev->bios); 3857 rdev->bios = NULL; 3858 } 3859 3860 /* 3861 * Due to how kexec works, it can leave the hw fully initialised when it 3862 * boots the new kernel. However doing our init sequence with the CP and 3863 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup 3864 * do some quick sanity checks and restore sane values to avoid this 3865 * problem. 3866 */ 3867 void r100_restore_sanity(struct radeon_device *rdev) 3868 { 3869 u32 tmp; 3870 3871 tmp = RREG32(RADEON_CP_CSQ_CNTL); 3872 if (tmp) { 3873 WREG32(RADEON_CP_CSQ_CNTL, 0); 3874 } 3875 tmp = RREG32(RADEON_CP_RB_CNTL); 3876 if (tmp) { 3877 WREG32(RADEON_CP_RB_CNTL, 0); 3878 } 3879 tmp = RREG32(RADEON_SCRATCH_UMSK); 3880 if (tmp) { 3881 WREG32(RADEON_SCRATCH_UMSK, 0); 3882 } 3883 } 3884 3885 int r100_init(struct radeon_device *rdev) 3886 { 3887 int r; 3888 3889 /* Register debugfs file specific to this group of asics */ 3890 r100_debugfs(rdev); 3891 /* Disable VGA */ 3892 r100_vga_render_disable(rdev); 3893 /* Initialize scratch registers */ 3894 radeon_scratch_init(rdev); 3895 /* Initialize surface registers */ 3896 radeon_surface_init(rdev); 3897 /* sanity check some register to avoid hangs like after kexec */ 3898 r100_restore_sanity(rdev); 3899 /* TODO: disable VGA need to use VGA request */ 3900 /* BIOS*/ 3901 if (!radeon_get_bios(rdev)) { 3902 if (ASIC_IS_AVIVO(rdev)) 3903 return -EINVAL; 3904 } 3905 if (rdev->is_atom_bios) { 3906 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 3907 return -EINVAL; 3908 } else { 3909 r = radeon_combios_init(rdev); 3910 if (r) 3911 return r; 3912 } 3913 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3914 if (radeon_asic_reset(rdev)) { 3915 dev_warn(rdev->dev, 3916 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3917 RREG32(R_000E40_RBBM_STATUS), 3918 RREG32(R_0007C0_CP_STAT)); 3919 } 3920 /* check if cards are posted or not */ 3921 if (radeon_boot_test_post_card(rdev) == false) 3922 return -EINVAL; 3923 /* Set asic errata */ 3924 r100_errata(rdev); 3925 /* Initialize clocks */ 3926 radeon_get_clock_info(rdev->ddev); 3927 /* initialize AGP */ 3928 if (rdev->flags & RADEON_IS_AGP) { 3929 r = radeon_agp_init(rdev); 3930 if (r) { 3931 radeon_agp_disable(rdev); 3932 } 3933 } 3934 /* initialize VRAM */ 3935 r100_mc_init(rdev); 3936 /* Fence driver */ 3937 r = radeon_fence_driver_init(rdev); 3938 if (r) 3939 return r; 3940 r = radeon_irq_kms_init(rdev); 3941 if (r) 3942 return r; 3943 /* Memory manager */ 3944 r = radeon_bo_init(rdev); 3945 if (r) 3946 return r; 3947 if (rdev->flags & RADEON_IS_PCI) { 3948 r = r100_pci_gart_init(rdev); 3949 if (r) 3950 return r; 3951 } 3952 r100_set_safe_registers(rdev); 3953 rdev->accel_working = true; 3954 r = r100_startup(rdev); 3955 if (r) { 3956 /* Somethings want wront with the accel init stop accel */ 3957 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 3958 r100_cp_fini(rdev); 3959 radeon_wb_fini(rdev); 3960 r100_ib_fini(rdev); 3961 radeon_irq_kms_fini(rdev); 3962 if (rdev->flags & RADEON_IS_PCI) 3963 r100_pci_gart_fini(rdev); 3964 rdev->accel_working = false; 3965 } 3966 return 0; 3967 } 3968